74LVQ541 OCTAL BUS BUFFER WITH 3 STATE OUTPUTS (NON INVERTED) ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: tPD =5.8 ns (TYP.) at VCC = 3.3 V COMPATIBLE WITH TTL OUTPUTS LOW POWER DISSIPATION: ICC = 4 µA (MAX.) at TA=25°C LOW NOISE: VOLP = 0.4V (TYP.) at VCC = 3.3V 75Ω TRANSMISSION LINE DRIVING CAPABILITY SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 12mA (MIN) at VCC = 3.0 V PCI BUS LEVELS GUARANTEED AT 24 mA BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL OPERATING VOLTAGE RANGE: VCC(OPR) = 2V to 3.6V (1.2V Data Retention) PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 541 IMPROVED LATCH-UP IMMUNITY DESCRIPTION The 74LVQ541 is a low voltage CMOS OCTAL BUS BUFFER with 3 STATE OUTPUTS NON INVERTED fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power and low noise 3.3V applications. SOP TSSOP ORDER CODES PACKAGE TUBE T&R SOP TSSOP 74LVQ541M 74LVQ541MTR 74LVQ541TTR The 3-STATE control gate operates as two input and such that if either G1 and G2 are high, all eight outputs are in the high impedance state. In order to enhance PC board layout, the 74AC541 offers a pinout having inputs and outputs on opposite side of the package. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS July 2001 1/9 74LVQ541 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL 1, 19 2, 3, 4, 5, 6, 7, 8, 9 18, 17, 16, 15, 14, 13, 12, 11 10 20 G1, G2 A1 to A8 Output Enable Inputs Data Inputs Y1 to Y8 Data Outputs GND VCC NAME AND FUNCTION Ground (0V) Positive Supply Voltage TRUTH TABLE INPUTS OUTPUT G1 G2 An Yn H X L L X H L L X X L H Z Z L H X : Don’t Care Z : High Impedance ABSOLUTE MAXIMUM RATINGS Symbol V CC Parameter Supply Voltage Value Unit -0.5 to +7 V -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 V DC Input Diode Current ± 20 mA IOK DC Output Diode Current ± 20 mA IO DC Output Current VI DC Input Voltage VO DC Output Voltage IIK ICC or IGND DC VCC or Ground Current Storage Temperature Tstg TL Lead Temperature (10 sec) V ± 50 mA ± 400 mA -65 to +150 °C 300 °C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied RECOMMENDED OPERATING CONDITIONS Symbol Parameter Unit Supply Voltage (note 1) 2 to 3.6 V VI Input Voltage 0 to VCC V VO Output Voltage 0 to VCC V Top Operating Temperature V CC dt/dv Input Rise and Fall Time VCC = 3.0V (note 2) 1) Truth Table guaranteed: 1.2V to 3.6V 2) VIN from 0.8V to 2V 2/9 Value -55 to 125 °C 0 to 10 ns/V 74LVQ541 DC SPECIFICATIONS Test Condition Symbol VIH V IL VOH Parameter High Level Input Voltage Low Level Input Voltage High Level Output Voltage TA = 25°C VCC (V) Min. Typ. Max. 2.0 3.0 to 3.6 3.0 Value Low Level Output Voltage 3.0 -55 to 125°C Min. Min. 0.8 IO=-50 µA 2.9 IO =-12 mA 2.58 2.99 2.9 2.9 2.48 2.2 I OZ ICC IOLD IOHD Input Leakage Current High Impedance Output Leakage Current Quiescent Supply Current Dynamic Output Current (note 1, 2) V 0.8 2.48 Unit Max. 2.0 0.8 V V 2.2 IO=50 µA 0.002 0.1 0.1 0.1 IO =12 mA 0 0.36 0.44 0.44 0.55 0.55 IO =24 mA II Max. 2.0 IO =-24 mA VOL -40 to 85°C V 3.6 VI = VCC or GND ± 0.1 ±1 ±1 µA 3.6 VI = VIH or VIL VO = VCC or GND ±0.25 ± 2.5 ± 5.0 µA 3.6 VI = VCC or GND 4 40 40 µA 3.6 VOLD = 0.8 V max 36 25 mA VOHD = 2 V min -25 -25 mA 1) Maximum test duration 2ms, one output loaded at time 2) Incident wave switching is guaranteed on transmission lines with impedances as low as 75Ω DYNAMIC SWITCHING CHARACTERISTICS Test Condition Symbol VOLP V OLV V IHD VILD Parameter Dynamic Low Voltage Quiet Output (note 1, 2) Dynamic High Voltage Input (note 1, 3) Dynamic Low Voltage Input (note 1, 3) Value TA = 25°C VCC (V) Min. 3.3 -0.8 3.3 Typ. Max. 0.5 0.8 -40 to 85°C -55 to 125°C Min. Min. Max. Unit Max. V -0.6 2 V C L = 50 pF 3.3 0.8 V 1) Worst case package. 2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V, (n-1) outputs switching and one output at GND. 3) Max number of data inputs (n) switching. (n-1) switching 0V to 3.3V. Inputs under test switching: 3.3V to threshold (VILD), 0V to threshold (VIHD), f=1MHz. 3/9 74LVQ541 AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, RL = 500 Ω, Input tr = tf = 3ns) Test Condition Symbol Parameter tPLH tPHL Propagation Delay Time tPZL tPZH Output Enable Time tPLZ tPHZ Output Disable Time tOSLH tOSHL Output To Output Skew Time (note1, 2) Value TA = 25°C VCC (V) Min. 2.7 Typ. Max. -40 to 85°C -55 to 125°C Min. Min. Max. Max. 6.6 11 12.5 14 (*) 3.3 2.7 5.8 9 10.5 12 9.2 13.5 15 18 3.3 (*) 2.7 7.6 10 11.5 13 9.0 12 13.5 15 3.3 (*) 2.7 7.3 9.0 10.5 12 0.5 0.5 1.0 1.0 1.0 1.0 1.0 1.0 3.3 (*) Unit ns ns ns ns 1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switching in the same direction, either HIGH or LOW (tOSLH = |tPLHm - tPLHn|, tOSHL = |tPHLm - tPHLn|) 2) Parameter guaranteed by design (*) Voltage range is 3.3V ± 0.3V CAPACITIVE CHARACTERISTICS Test Condition Symbol Parameter CIN Input Capacitance C OUT Output Capacitance Power Dissipation Capacitance (note 1) C PD Value TA = 25°C VCC (V) Min. Typ. Max. -40 to 85°C -55 to 125°C Min. Min. Max. Unit Max. 3.3 4 pF 3.3 8 pF 10 pF 3.3 fIN = 10MHz 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/8 (per Gate) 4/9 74LVQ541 TEST CIRCUIT TEST tPLH, tPHL SWITCH Open tPZL, tPLZ 2V CC tPZH, tPHZ Open C L = 50pF or equivalent (includes jig and probe capacitance) R L = R1 = 500Ω or equivalent R T = ZOUT of pulse generator (typically 50Ω) WAVEFORM 1 : PROPAGATION DELAYS (f=1MHz; 50% duty cycle) 5/9 74LVQ541 WAVEFORM 2 : OUTPUT ENABLE AND DISABLE TIMES (f=1MHz; 50% duty cycle) 6/9 74LVQ541 SO-20 MECHANICAL DATA mm. inch DIM. MIN. TYP A a1 MAX. MIN. TYP. 2.65 0.1 0.104 0.2 a2 MAX. 0.004 0.008 2.45 0.096 b 0.35 0.49 0.014 0.019 b1 0.23 0.32 0.009 0.012 C 0.5 0.020 c1 45° (typ.) D 12.60 13.00 0.496 0.512 E 10.00 10.65 0.393 0.419 e 1.27 0.050 e3 11.43 0.450 F 7.40 7.60 0.291 0.300 L 0.50 1.27 0.020 0.050 M S 0.75 0.029 8° (max.) PO13L 7/9 74LVQ541 TSSOP20 MECHANICAL DATA mm. inch DIM. MIN. TYP MAX. A MIN. TYP. MAX. 1.2 A1 0.05 A2 0.8 b 0.047 0.15 0.002 0.004 0.006 1.05 0.031 0.039 0.041 0.19 0.30 0.007 0.012 c 0.09 0.20 0.004 0.0089 D 6.4 6.5 6.6 0.252 0.256 0.260 E 6.2 6.4 6.6 0.244 0.252 0.260 E1 4.3 4.4 4.48 0.169 0.173 0.176 1 e 0.65 BSC K 0° L 0.45 A 0.0256 BSC 0.60 8° 0° 0.75 0.018 8° 0.024 0.030 A2 A1 b K e L E c D E1 PIN 1 IDENTIFICATION 1 0087225C 8/9 74LVQ541 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringe ment of patents or other righ ts of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this pub lication are subject to change without notice. Thi s pub lication supersedes and replaces all information previously supplied. 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