74LVQ299 8 BIT PIPO SHIFT REGISTER WITH ASYNCHRONOUS CLEAR ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: tPD = 8.3 ns (TYP.) at VCC = 3.3 V COMPATIBLE WITH TTL OUTPUTS LOW POWER DISSIPATION: ICC = 4 µA (MAX.) at TA=25°C LOW NOISE: VOLP = 0.5V (TYP.) at VCC = 3.3V 75Ω TRANSMISSION LINE DRIVING CAPABILITY SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 12mA (MIN) at VCC = 3.0 V PCI BUS LEVELS GUARANTEED AT 24 mA BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL OPERATING VOLTAGE RANGE: VCC(OPR) = 2V to 3.6V (1.2V Data Retention) PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 299 IMPROVED LATCH-UP IMMUNITY DESCRIPTION The 74LVQ299 is a low voltage CMOS 8 BIT PIPO SHIFT REGISTER (3-STATE) fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power and low noise 3.3V applications. SOP TSSOP ORDER CODES PACKAGE TUBE T&R SOP TSSOP 74LVQ299M 74LVQ299MTR 74LVQ299TTR These devices have four modes (HOLD, SHIFT LEFT, SHIFT RIGHT and LOAD DATA). Each mode is chosen by two function select inputs (S0, S1) as shown in the Truth Table. When one or both enable inputs, (G1, G2) are high, the eight input/output terminals are in the high impedance state; however sequential operation or clearing of the register is not affected. Clear function is asynchronous to clock. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS July 2001 1/12 74LVQ299 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL 1, 19 2, 3 7, 13, 6, 14, 5, 15, 4, 16 8, 17 9 11 12 18 10 20 S0, S1 G1, G2 A/QA to H/QH QA’,QH’ CLEAR SR CLOCK SL GND VCC NAME AND FUNCTION Mode Select Inputs 3-State Output Enable Inputs (Active LOW) Parallel Data Inputs or 3-State Parallel Outputs (Bus Driver) Serial Outputs (Standard Output) Asynchronous Master Reset Input (Active LOW) Serial Data Shift Right Input Clock Input (LOW to HIGH, Edge-triggered) Serial Data Shift Left Input Ground (0V) Positive Supply Voltage TRUTH TABLE INPUTS MODE CLEAR FUNCTION SELECTED INPUTS/OUTPUTS OUTPUT CONTROL SERIAL CLOCK A/QA H/QH QA’ QH’ X X X X Z L L QA0 Z L L QH0 L L L QA0 L L L QH0 H H QGn H QGn L L QGn L QGn X QBn H QBn H QBn L QBn L a h a h S1 S0 G1* G2* L L L H H L X L H X L L X L L L X L L L SHIFT RIGHT H L H L L H L H L L X SHIFT LEFT H H L L L H H H L L L L X LOAD H H H X X X X Z CLEAR HOLD OUTPUTS X X X X SL SR X X X X X * When one or both controls are high, the eight input/output terminals are the high impedance state: however sequential operation or cleaning of the register is not affected. Z : High Impedance Qn0 : The level of An before the indicated steady state input conditions were established. Qnn : The level of Qn before the most recent active transition indicated by OR a, h : The level of the steady state inputs A, H, respectively. X : Don’t Care 2/12 74LVQ299 LOGIC DIAGRAM 3/12 74LVQ299 TIMING CHART ABSOLUTE MAXIMUM RATINGS Symbol VCC Parameter Supply Voltage Value Unit -0.5 to +7 V VI DC Input Voltage -0.5 to VCC + 0.5 V VO DC Output Voltage IIK DC Input Diode Current -0.5 to VCC + 0.5 ± 20 mA IOK DC Output Diode Current ± 20 mA IO DC Output Current ± 50 mA ICC or IGND DC VCC or Ground Current Tstg Storage Temperature TL Lead Temperature (10 sec) V ± 400 mA -65 to +150 °C 300 °C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied RECOMMENDED OPERATING CONDITIONS Symbol VCC Parameter Unit 2 to 3.6 V VI Input Voltage 0 to VCC V VO Output Voltage 0 to VCC V Top Operating Temperature -55 to 125 °C 0 to 10 ns/V dt/dv Input Rise and Fall Time VCC = 3.0V (note 2) 1) Truth Table guaranteed: 1.2V to 3.6V 2) VIN from 0.8V to 2V 4/12 Value Supply Voltage (note 1) 74LVQ299 DC SPECIFICATIONS Test Condition Symbol VIH VIL VOH Parameter High Level Input Voltage Low Level Input Voltage High Level Output Voltage TA = 25°C VCC (V) Min. Typ. Max. 2.0 3.0 to 3.6 3.0 Value Low Level Output Voltage 3.0 -55 to 125°C Min. Min. 0.8 IO=-50 µA 2.9 IO=-12 mA 2.58 2.99 IOZ ICC IOLD IOHD Input Leakage Current High Impedance Output Leakage Current Quiescent Supply Current Dynamic Output Current (note 1, 2) V 0.8 2.9 2.9 2.48 2.48 2.2 2.2 Unit Max. 2.0 0.8 V V IO=50 µA 0.002 0.1 0.1 0.1 IO=12 mA 0 0.36 0.44 0.44 0.55 0.55 IO=24 mA II Max. 2.0 IO=-24 mA VOL -40 to 85°C V 3.6 VI = VCC or GND ± 0.1 ±1 ±1 µA 3.6 VI = VIH or VIL VO = VCC or GND ±0.25 ± 2.5 ± 5.0 µA 3.6 VI = VCC or GND 4 40 40 µA 3.6 VOLD = 0.8 V max 36 25 mA VOHD = 2 V min -25 -25 mA 1) Maximum test duration 2ms, one output loaded at time 2) Incident wave switching is guaranteed on transmission lines with impedances as low as 75Ω DYNAMIC SWITCHING CHARACTERISTICS Test Condition Symbol VOLP VOLV VIHD VILD Parameter Dynamic Low Voltage Quiet Output (note 1, 2) Dynamic High Voltage Input (note 1, 3) Dynamic Low Voltage Input (note 1, 3) Value TA = 25°C VCC (V) Min. 3.3 -0.8 3.3 Typ. Max. 0.5 0.8 -40 to 85°C -55 to 125°C Min. Min. Max. Unit Max. V -0.6 2 V CL = 50 pF 3.3 0.8 V 1) Worst case package. 2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V, (n-1) outputs switching and one output at GND. 3) Max number of data inputs (n) switching. (n-1) switching 0V to 3.3V. Inputs under test switching: 3.3V to threshold (VILD), 0V to threshold (VIHD), f=1MHz. 5/12 74LVQ299 AC ELECTRICAL CHARACTERISTICS(CL = 50 pF, R L = 500 Ω, Input tr = tf = 3ns) Test Condition Symbol Parameter tPLH tPHL Propagation Delay Time CLOCK to Q’A or Q’H tPLH tPHL Propagation Delay Time CLOCK to A/QA, H/QH tPHL Propagation Delay Time CLEAR to Q’A or Q’H tPHL Propagation Delay Time CLEAR to A/QA, H/QH tPZL tPZH Output Enable Time G1 or G2 to A/QA, H/QH tPLZ tPHZ Output Disable Time G1 or G2 to A/QA, H/QH tW CLEAR Pulse Width LOW tW ts th ts th ts th tREM fMAX tOSLH tOSHL CLOCK Pulse Width LOW Setup Time HIGH or LOW (A/QA, H/ QH to CLOCK) Hold Time HIGH or LOW (A/QA, H/QH to CLOCK) Setup Time HIGH or LOW (S0 or S1 to CLOCK) Hold Time HIGH or LOW (S0 or S1 to CLOCK) Setup Time HIGH or LOW (SR or SL to CLOCK) Hold Time HIGH or LOW (SR or SL to CLOCK) Recovery Time CLEAR to CLOCK Maximum Clock Frequency Output To Output Skew Time (note1, 2) VCC (V) Value TA = 25°C Min. -40 to 85°C -55 to 125°C Min. Min. Typ. Max. 9.7 15.0 17.5 20.0 8.2 12.0 14.0 16.5 2.7 9.8 15.0 17.5 20.0 3.3(*) 8.3 12.0 14.0 16.5 2.7 3.3 (*) Max. Max. 2.7 8.4 14.0 16.5 19.0 3.3(*) 7.1 11.0 13.0 15.0 2.7 8.9 15.0 17.5 20.0 7.4 12.0 14.0 16.5 9.9 15.0 17.5 20.0 8.0 12.0 14.0 16.5 2.7 9.8 15.0 17.5 20.0 3.3(*) 8.0 12.0 14.0 16.5 3.3 (*) 2.7 3.3 (*) 2.7 5.0 2.1 5.0 5.0 4.0 2.0 4.0 4.0 5.0 2.1 5.0 5.0 4.0 2.0 4.0 4.0 4.0 1.4 4.0 4.0 3.0 1.1 3.0 3.0 2.7 1.0 -1.3 1.0 1.0 3.3(*) 1.0 -1.0 1.0 1.0 2.7 6.0 3.1 6.0 6.0 5.0 2.5 5.0 5.0 1.0 -3.1 1.0 1.0 1.0 -2.6 1.0 1.0 (*) 3.3 2.7 (*) 3.3 2.7 3.3 3.3 (*) (*) 2.7 3.3 (*) 2.7 4.0 1.5 4.0 4.0 3.3(*) 3.0 1.1 3.0 3.0 2.7 1.0 -1.5 1.0 1.0 3.3(*) 1.0 -1.1 1.0 1.0 2.7 1.0 -0.7 1.0 1.0 3.3(*) 1.0 -0.5 1.0 1.0 2.7 100 150 80 60 3.3(*) 2.7 120 180 100 80 3.3 (*) 0.5 0.5 1.0 1.0 1.0 1.0 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1.0 1.0 ns 1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switching in the same direction, either HIGH or LOW (tOSLH = |tPLHm - tPLHn|, t OSHL = |tPHLm - t PHLn|) 2) Parameter guaranteed by design (*) Voltage range is 3.3V ± 0.3V 6/12 74LVQ299 CAPACITIVE CHARACTERISTICS Test Condition Symbol Parameter CIN Input Capacitance CI/O Bus Input Capacitance Power Dissipation Capacitance (note 1) CPD Value TA = 25°C VCC (V) Min. 3.3 Typ. Max. -40 to 85°C -55 to 125°C Min. Min. Max. Unit Max. 4 pF pF 3.3 fIN = 10MHz 10 pF 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x f IN + ICC/n (per circuit) TEST CIRCUIT TEST SWITCH tPLH, tPHL Open tPZL, tPLZ 2VCC tPZH, tPHZ Open CL = 50pF or equivalent (includes jig and probe capacitance) RL = R1 = 500Ω or equivalent RT = ZOUT of pulse generator (typically 50Ω) 7/12 74LVQ299 WAVEFORM 1 : PROPAGATION DELAYS (f=1MHz; 50% duty cycle) WAVEFORM 2 : PROPAGATION DELAYS (f=1MHz; 50% duty cycle) 8/12 74LVQ299 WAVEFORM 3 : PROPAGATION DELAYS (f=1MHz; 50% duty cycle) WAVEFORM 4 : PROPAGATION DELAYS (f=1MHz; 50% duty cycle) 9/12 74LVQ299 SO-20 MECHANICAL DATA mm. inch DIM. MIN. TYP A a1 MAX. MIN. TYP. 2.65 0.1 0.104 0.2 a2 MAX. 0.004 0.008 2.45 0.096 b 0.35 0.49 0.014 0.019 b1 0.23 0.32 0.009 0.012 C 0.5 0.020 c1 45° (typ.) D 12.60 13.00 0.496 0.512 E 10.00 10.65 0.393 0.419 e 1.27 0.050 e3 11.43 0.450 F 7.40 7.60 0.291 0.300 L 0.50 1.27 0.020 0.050 M S 0.75 0.029 8° (max.) PO13L 10/12 74LVQ299 TSSOP20 MECHANICAL DATA mm. inch DIM. MIN. TYP MAX. A MIN. TYP. MAX. 1.2 A1 0.05 A2 0.8 b 0.047 0.15 0.002 0.004 0.006 1.05 0.031 0.039 0.041 0.19 0.30 0.007 0.012 c 0.09 0.20 0.004 0.0089 D 6.4 6.5 6.6 0.252 0.256 0.260 E 6.2 6.4 6.6 0.244 0.252 0.260 E1 4.3 4.4 4.48 0.169 0.173 0.176 1 e 0.65 BSC K 0° L 0.45 A 0.0256 BSC 0.60 8° 0° 0.75 0.018 8° 0.024 0.030 A2 A1 b K e L E c D E1 PIN 1 IDENTIFICATION 1 0087225C 11/12 74LVQ299 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. 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