ETC AM79R70-1SC

Am79R70
Ringing Subscriber Line Interface Circuit
DISTINCTIVE CHARACTERISTICS
Ideal for ISDN-TA and set top applications
On-chip ringing with on-chip ring-trip detector
Low standby state power
Battery operation:
— VBAT1: –40 V to –67 V
— VBAT2: –19 V to VBAT1
On-chip battery switching and feed selection
On-hook transmission
Polarity reversal option
Programmable constant-current feed
Programmable Open Circuit voltage
Programmable loop-detect threshold
Current gain = 1000
Two-wire impedance set by single component
Ground-key detector
Tip Open state for ground-start lines
Internal VEE regulator
(no external –5 V power supply required)
Two on-chip relay drivers and snubber circuits
BLOCK DIAGRAM
Relay
Driver
RTRIP1
RTRIP2
RYOUT2
RYE
Relay
Driver
A(TIP)
Ring-Trip
Detector
Input Decoder
and Control
Ground-Key
Detector
HPA
Two-Wire
Interface
D1
D2
C1
C2
C3
Off-Hook
Detector
E1
DET
Signal
Transmission
RD
VTX
RSN
HPB
B(RING)
RYOUT1
Power-Feed
Controller
RINGIN
RDC
RDCR
VBAT2
VBAT1
RSGL
RSGH
B2EN
Switch
Driver
VCC VNEG BGND AGND/DGND
Publication# 080211 Rev: D Amendment: /0
Issue Date: October 1999
GENERAL DESCRIPTION
The Legerity family of subscriber line interface circuit
(SLIC) products provide the telephone interface functions required throughout the worldwide market. Legerity SLIC devices address all major telephony markets
including central office (CO), private branch exchange
(PBX), digital loop carrier (DLC), fiber-in-the-loop
(FITL), radio-in-the-loop (RITL), hybrid fiber coax
(HFC), and video telephony applications.
The Legerity SLIC devices offer support of BORSHT
(battery feed, overvoltage protection, ringing, supervision, hybrid, and test) functions with features including
current limiting, on-hook transmission, polarity reversal,
tip-open, and loop-current detection. These features allow reduction of linecard cost by minimizing component
count, conserving board space, and supporting automated manufacturing.
The Legerity SLIC devices provide the two- to four-wire
hybrid function, DC loop feed, and two-wire supervision.
Two-wire termination is programmed by a scaled impedance network. Transhybrid balance can be achieved with
an external balance circuit or simply programmed using
a companion Legerity codec device, the Am79C02/03/
031 DSLAC™ device, the Am79Q02/021/031 Programmable Quad SLAC (QSLAC™) device, or the
Am79Q5457/4457 Nonprogrammable QSLAC device.
2
The Am79R70 Ringing SLIC device is a bipolar monolithic SLIC that offers on-chip ringing. Now designers
can achieve significant cost reductions at the system
level for short-loop applications by integrating the ringing function on chip. Examples of such applications
would be ISDN Terminal Adaptors and set top boxes.
Using a CMOS-compatible input waveform and wave
shaping R-C network, the Am79R70 Ringing SLIC can
provide trapezoidal wave ringing to meet various design requirements.
In order to further enhance the suitability of this device
in short-loop, distributed switching applications, Legerity has maximized power savings by incorporating battery switching on chip. The Am79R70 Ringing SLIC
device switches between two battery supplies such that
in the Off-hook (active) state, a low battery is used to
save power. In order to meet the Open Circuit voltage
requirements of fax machines and maintenance termination units (MTU), the SLIC automatically switches to
a higher voltage in the On-hook (standby) state.
Like all of the Legerity SLIC devices, the Am79R70
Ringing SLIC device supports on-hook transmission,
ring-trip detection and programmable loop-detect
threshold. The Am79R70 Ringing SLIC device is a programmable constant-current feed device with two onchip relay drivers to operate external relays. This unique
device is available in the proven Legerity 75 V bipolar
process in 32-pin PLCC packages.
Am79R70 Data Sheet
ORDERING INFORMATION
Standard Products
Legerity standard products are available in several packages and operating ranges. The order number (Valid Combination) is
formed by a combination of the elements below.
Am79R70
J
C
TEMPERATURE RANGE
C = Commercial (0°C to 70°C)*
PACKAGE TYPE
J = 32-pin Plastic Leaded Chip Carrier (PL 032)
S = 28-pin Small Outline Integrated Circuit (SOW 028)
POLARITY REVERSAL OPTION
Blank = No Polarity Reversal
–1 = Polarity Reversal
DEVICE NUMBER/DESCRIPTION
Am79R70
Subscriber Line Interface Circuit
Valid Combinations
Valid Combinations
Am79R70
–1
JC
SC
Valid Combinations list configurations planned to
be supported in volume for this device. Consult
the local Legerity sales office to confirm availability of specific valid combinations, to check on
newly released combinations, and to obtain additional data on Legerity’s standard military–grade
products.
Note:
* Functionality of the device from 0°C to +70°C is guaranteed by production testing.
Am79R70 Data Sheet
3
CONNECTION DIAGRAMS
Top View
VCC
VBAT2
BGND
B(RING)
A(TIP)
4
3
2
1
32
31 30
RD
RYOUT2
32-Pin PLCC
RYOUT1
6
28
RTRIP2
B2EN
7
27
HPB
VBAT1
8
26
HPA
D1
9
25
RINGIN
E1
10
24
RDCR
C3
11
23
VTX
C2
12
22
VNEG
DET
13
21
RSN
18
19 20
AGND/DGND
16 17
RDC
15
NC
14
RSGL
RTRIP1
RSGH
29
D2
5
C1
RYE
28-Pin SOIC
Notes:
1. Pin 1 is marked for orientation.
RSVD
1
28
VBAT1
E1
2
27
B2EN
C3
3
26
RSVD
C2
4
25
VBAT2
DET
5
24
VCC
C1
6
23
BGND
RSGH
7
22
B(RING)
RSGL
8
21
A(TIP)
RDC
9
20
RD
AGND
10
19
RTRIP1
RSN
11
18
RTRIP2
VNEG
12
17
HPB
VTX
13
16
HPA
RDCR
14
15
RINGIN
2. NC = No connect
3. RSVD = Reserved. Do not connect to this pin.
4
Am79R70 Data Sheet
PIN DESCRIPTIONS
Pin Names
Type
Description
AGND/DGND
Gnd
Analog and digital ground are connected internally to a single pin.
A(TIP)
Output
Output of A(TIP) power amplifier.
B2EN
Input
VBAT2 enable. Logic Low enables operation from VBAT2. Logic High enables operation from
VBAT1. TTL compatible.
BGND
Gnd
Battery (power) ground
B(RING)
Output
Output of B(RING) power amplifier.
C3–C1
Input
Decoder. TTL compatible. C3 is MSB and C1 is LSB.
D1
Input
Relay1 control. TTL compatible. Logic Low activates the Relay1 relay driver.
D2
Input
(Option) Relay2 control. TTL compatible. Logic Low activates the Relay2 relay driver.
DET
Output
Detector. Logic Low indicates that the selected detector is tripped. Logic inputs C3–C1 and E1
select the detector. Open-collector with a built-in 15 kΩ pull-up resistor.
E1
Input
(Option) A logic High selects the off-hook detector. A logic Low selects the ground-key detector.
TTL compatible.
HPA
Capacitor
High-pass filter capacitor. A(TIP) side of high-pass filter capacitor.
HPB
Capacitor
High-pass filter capacitor. B(RING) side of high-pass filter capacitor.
RD
Resistor
Detect resistor. Threshold modification and filter point for the off-hook detector.
RDC
Resistor
DC feed resistor. Connection point for the DC-feed current programming network, which also
connects to the receiver summing node (RSN). VRDC is negative for normal polarity and positive
for reverse polarity.
RDCR
—
Connection point for feedback during ringing.
RINGIN
Input
Ring Signal Input. Pin for ring signal input. Square-wave shaped by external RC filter. Requires
50% duty cycle. CMOS-compatible input.
RSGH
Input
Saturation Guard High. Pin for resistor to adjust Open Circuit voltage when operating from
VBAT1.
RSGL
Input
Saturation Guard Low. Pin for resistor to adjust the anti-saturation cut-in voltage when operating
from both VBAT1 and VBAT2.
RSN
Input
The metallic current (AC and DC) between A(TIP) and B(RING) is equal to 1000 x the current
into this pin. The networks that program receive gain, two-wire impedance, and feed resistance
all connect to this node.
RTRIP1
Input
Ring-trip detector. Ring-trip detector threshold set and filter pin.
RTRIP2
Input
Ring-trip detector threshold offset (switch to VBAT1). For power conservation in any nonringing
state, this switch is open.
RYE
Output
Common Emitter of RYOUT1/RYOUT2. Emitter output of RYOUT1 and RYOUT2. Normally
connected to relay ground.
RYOUT1
Output
Relay/switch driver. Open-collector driver with emitter internally connected to RYE.
RYOUT2
Output
(Option) Relay/switch driver. Open-collector driver with emitter internally connected to RYE.
VBAT1
Battery
Battery supply and connection to substrate.
VBAT2
Battery
Power supply to output amplifiers. Connect to off-hook battery through a diode.
VCC
Power
Positive analog power supply.
VNEG
Power
Negative analog power supply. This pin is the return for the internal VEE regulator.
VTX
Output
Transmit Audio. This output is a 0.5066 gain version of the A(TIP) and B(RING) metallic AC voltage. VTX also sources the two-wire input impedance programming network.
Am79r70 Data Sheet
5
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage temperature ......................... –55°C to +150°C
Commercial (C) Devices
VCC with respect to AGND/DGND .......... 0.4 V to +7 V
Ambient temperature ............................. 0°C to +70°C*
VNEG with respect to AGND/DGND ...... 0.4 V to VBAT2
VCC ..................................................... 4.75 V to 5.25 V
VBAT2 ....................................................VBAT1 to GND
VNEG ..................................................–4.75 V to VBAT2
VBAT1 with respect to AGND/DGND:
Continuous..................................... +0.4 V to –80 V
10 ms ............................................. +0.4 V to –85 V
VBAT1 .................................................... –40 V to –67 V
BGND with respect to AGND/DGND........ +3 V to –3 V
A(TIP) or B(RING) to BGND:
Continuous ...............................VBAT1 –5 V to +1 V
10 ms (f = 0.1 Hz) ..................VBAT1 –10 V to +5 V
1 µs (f = 0.1 Hz) .....................VBAT1 –15 V to +8 V
250 ns (f = 0.1 Hz) ...............VBAT1 –20 V to +12 V
Current from A(TIP) or B(RING).....................±150 mA
VBAT2 ....................................................–19 V to VBAT1
AGND/DGND.......................................................... 0 V
BGND with respect to
AGND/DGND ........................ –100 mV to +100 mV
Load resistance on VTX to ground .............. 20 kΩ min
The Operating Ranges define those limits between which the
functionality of the device is guaranteed.
* Functionality of the device from 0°C to +70°C is guaranteed
by production testing.
RYOUT1, RYOUT2 current................................75 mA
RYOUT1, RYOUT2 voltage ..................... RYE to +7 V
RYOUT1, RYOUT2 transient ................. RYE to +10 V
RYE voltage ........................................ BGND to VBAT1
C3–C1, D2–D1, E1, B2EN, and RINGIN
Input voltage .........................–0.4 V to VCC + 0.4 V
Maximum power dissipation, continuous,
TA = 70°C, No heat sink (See note):
In 32-pin PLCC package..............................1.67 W
In 28-pin SOIC package ..............................1.25 W
Thermal Data:................................................................ θJA
In 32-pin PLCC package....................... 45°C/W typ
In 28-pin SOIC package ........................ 60°C/W typ
Note: Thermal limiting circuitry on chip will shut down the
circuit at a junction temperature of about 165°C. The device
should never see this temperature and operation above 145°C
junction temperature may degrade device reliability. See the
SLIC Packaging Considerations for more information.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent device failure. Functionality at or above
these limits is not implied. Exposure to Absolute Maximum
Ratings for extended periods may affect device reliability.
6
Am79R70 Data Sheet
ELECTRICAL CHARACTERISTICS
Description
Test Conditions (See Note 1)
Min
Typ
Max
200 Hz to 3.4 kHz (Test Circuit D)
26
Unit
Note
dB
1, 4, 6
3
20
Ω
4
+50
mV
20
Ω
4
2.5
Vpk
2a
0.88
Vrms
2b
dB
5
Transmission Performance
2-wire return loss
ZVTX, analog output impedance
VVTX, analog output offset voltage
–50
ZRSN, analog input impedance
1
Overload level, 2-wire and 4-wire, off hook Active state
Overload level, 2-wire
On hook, RLAC = 600 Ω
THD (Total Harmonic Distortion)
+3 dBm, BAT2 = –24 V
THD, on hook, OHT state
0 dBm, RLAC = 600 Ω,
BAT1 = –67 V
–64
–50
–40
Longitudinal Performance (See Test Circuit C)
Longitudinal to metallic L-T, L-4 balance
200 Hz to 3.4 kHz
40
Longitudinal signal generation 4-L
200 Hz to 800 Hz, Normal polarity
40
Longitudinal current per pin (A or B)
Active or OHT state
12
Longitudinal impedance at A or B
0 to 100 Hz, TA = +25°C
dB
28
mArms
25
Ω/pin
4
Idle Channel Noise
C-message weighted noise
+7
+14
dBrnC
Psophometric weighted noise
–83
–76
dBmp
4
Insertion Loss and Four- to Four-Wire Balance Return Signal (See Test Circuits A and B)
Gain accuracy
4- to 2-wire
0 dBm, 1 kHz
–0.20
0
+0.20
Gain accuracy
2- to 4-wire and
4- to 4-wire
0 dBm, 1 kHz
–6.22
–6.02
–5.82
Gain accuracy
4- to 2-wire
OHT state, on hook
–0.35
0
+0.35
Gain accuracy
2- to 4-wire and
4- to 4-wire
OHT state, on hook
–6.37
–6.02
–5.77
Gain accuracy over frequency
300 to 3400 Hz
relative to 1 kHz
–0.10
+0.10
Gain tracking
+3 dBm to –55 dBm
relative to 0 dBm
–0.10
+0.10
3, 4
Gain tracking
OHT state, on hook
0 dBm to –37 dBm
+3 dBm to 0 dBm
–0.10
–0.35
+0.10
+0.35
3, 4
3
Group delay
0 dBm, 1 kHz
3
dB
Am79r70 Data Sheet
3
µs
1, 4, 6
7
ELECTRICAL CHARACTERISTICS (CONTINUED)
Description
Test Conditions (See Note 1)
Min
Typ
Max
1.1IL
Unit
Note
Line Characteristics
IL, Loop-current accuracy
IL in constant-current region,
B2EN = 0
0.9IL
IL
IL, Long loops, Active state
RLDC = 600 Ω, RSGL = open
RLDC = 750 Ω, RSGL = short
20
20
21.7
0.8IL
IL
IL, Accuracy, Standby state
V BAT1 – 10 V
I L = -------------------------------------R L + 400
mA
IL = constant-current region
TA = 25°C
ILLIM
1.2IL
18
Active, A and B to ground
OHT, A and B to ground
27
39
55
55
110
4
IL, Loop current, Open Circuit state
RL = 0
100
IA, Pin A leakage, Tip Open state
RL = 0
100
IB, Pin B current, Tip Open state
B to ground
VA, Standby, ground-start signaling
A to –48 V = 7 kΩ,
B to ground = 100 Ω
34
–7.5
µA
mA
–5
4
V
VAB, Open Circuit voltage
42
7
Power Supply Rejection Ratio (VRIPPLE = 100 mVrms), Active Normal State
VCC
50 Hz to 3400 Hz
33
50
VNEG
50 Hz to 3400 Hz
30
40
VBAT1
50 Hz to 3400 Hz
30
50
VBAT2
50 Hz to 3400 Hz
30
50
dB
5
Power Dissipation
On hook, Open Circuit state
VBAT1
48
100
On hook, Standby state
VBAT2
55
80
On hook, OHT state
VBAT1
200
300
On hook, Active state
VBAT1
220
350
Off hook, Standby state
VBAT1 or VBAT2
RL = 300 Ω
2000
2800
Off hook, OHT state
VBAT1
RL = 300 Ω
2000
2200
Off hook, Active state
VBAT2
RL = 300 Ω
550
750
9
mW
9
Supply Currents
ICC, On-hook VCC supply current
Open Circuit state
Standby state
OHT state
Active state–normal
3.0
3.2
6.2
6.5
4.5
5.5
8.0
9.0
INEG, On-hook VNEG supply current
Open Circuit state
Standby state
OHT state
Active state–normal
0.1
0.1
0.7
0.7
0.2
0.2
1.1
1.1
Open Circuit state
Standby state
OHT state
Active state–normal
0.45
0.6
2.0
2.7
1.0
1.5
4.0
5.0
IBAT, On-hook VBAT supply current
8
Am79R70 Data Sheet
mA
ELECTRICAL CHARACTERISTICS (continued)
Description
Test Conditions (See Note 1)
Min
Typ
Max
Unit
Note
Logic Inputs (C3–C1, D2–D1, E1, and B2EN)
VIH, Input High voltage
2.0
VIL, Input Low voltage
0.8
IIH, Input High current
–75
40
IIL, Input Low current
–400
V
µA
Logic Output DET
VOL, Output Low voltage
IOUT = 0.8 mA, 15 kΩ to VCC
0.40
VOH, Output High voltage
IOUT = –0.1 mA, 15 kΩ to VCC
2.4
BAT1 – 1
IRTD = æè ---------------------------- + 24 µAöø • 335
RRT1
–10
VAB, Ringing
Bat1 = –67 V, ringload = 1570 Ω
57
VAB Ringing offset
VRINGIN = 2.5 V
V
Ring-Trip Detector Input
Ring detect accuracy
+10
%
Ring Signal
∆VAB/∆VRINGIN (RINGIN gain)
61
Vpk
0
V
180
—
Ground-Key Detector Thresholds
Ground-key resistive threshold
B to ground
Ground-key current threshold
B to ground
2
5
10
11
kΩ
mA
Loop Detector
RLTH, Loop-resistance detect threshold
Active, VBAT1
Active, VBAT2
Standby
–20
–20
–12
20
20
12
%
8
Relay Driver Output (RELAY1 and 2)
VOL, On voltage (each output)
IOL = 30 mA
+0.25
+0.4
VOL, On voltage (each output)
IOL = 40 mA
+0.30
+0.8
IOH, Off leakage (each output)
VOH = +5 V
Zener breakover (each output)
IZ = 100 µA
Zener on voltage (each output)
IZ = 30 mA
100
6.6
7.9
11
V
4
µA
V
RELAY DRIVER SCHEMATIC
RYOUT2
RYOUT1
RYE
BGND
BGND
Am79R70 Data Sheet
9
Notes:
1. Unless otherwise noted, test conditions are BAT1 = –67 V, BAT2 = –24 V, VCC = +5 V, VNEG = –5 V, RL = 600 Ω,
RDC1 = 80 kΩ, RDC2 = 20 kΩ, RD = 75 kΩ, no fuse resistors, CHP = 0.018 µF, CDC = 1.2 µF, D1 = D2 = 1N400x,
two-wire AC input impedance (ZSL) is a 600 Ω resistance synthesized by the programming network shown below.
RSGL = open, RSGH = open, RDCR = 2 kΩ, RRT1 = 430 kΩ, RRT2 = 12 kΩ, CRT = 1.5 µF, RSLEW = 150 kΩ, CSLEW = 0.33 µF.
VTX
RT1 = 150 kΩ
RT2 = 150 kΩ
CT1 = 60 pF
RSN
RRX = 300 kΩ
~
VRX
2. a. Overload level is defined when THD = 1%.
b. Overload level is defined when THD = 1.5%.
3. Balance return signal is the signal generated at VTX by VRX. This specification assumes that the two-wire AC load impedance
matches the programmed impedance.
4. Not tested in production. This parameter is guaranteed by characterization or correlation to other tests.
5. This parameter is tested at 1 kHz in production. Performance at other frequencies is guaranteed by characterization.
6. Group delay can be greatly reduced by using a ZT network such as that shown in Note 1 above. The network reduces the
group delay to less than 2 µs and increases 2WRL. The effect of group delay on linecard performance may also be compensated
for by synthesizing complex impedance with the QSLAC or DSLAC device.
7. Open Circuit VAB can be modified using RSGH.
8. RD must be greater than 56 kΩ. Refer to Table 2 for typical value of RLTH.
9. Lower power is achieved by switching into low-battery state in standby. Standby loop current is returned to VBAT1 regardless
of the battery selected.
Table 1. SLIC Decoding
(DET) Output
State
C3 C2 C1
2-Wire Status
E1 = 1
E1 = 0
0
0
0
0
Open Circuit
Ring trip
Ring trip
1
0
0
1
Ringing
Ring trip
Ring trip
2
0
1
0
Active
Loop detector
Ground key
3
0
1
1
On-hook TX (OHT)
Loop detector
Ground key
4
1
0
0
Tip Open
Loop detector
Ground key
B2EN = 1**
5
1
0
1
Standby
Loop detector
Ground key
VBAT1
6*
1
1
0
Active Polarity Reversal
Loop detector
Ground key
7*
1
1
1
OHT Polarity Reversal
Loop detector
Ground key
Notes:
* Only –1 performance grade devices support polarity reversal.
** For correct ground-start operation using Tip Open, VBAT1 on-hook battery must be used.
10
Battery Selection
Am79R70 Data Sheet
B2EN
B2EN
Table 2. User-Programmable Components
Z T = 500 ( Z 2WIN – 2RF )
ZT is connected between the VTX and RSN pins. The fuse resistors are
RF, and Z2WIN is the desired 2-wire AC input impedance. When computing ZT, the internal current amplifier pole and any external stray capacitance between VTX and RSN must be taken into account.
ZL
1000 • ZT
Z RX = ------------ • -------------------------------------------------G42L ZT + 500 ( ZL + 2R F )
ZRX is connected from VRX to RSN. ZT is defined above, and G42L is the
desired receive gain.
2500
R DC1 + R DC2 = --------------I LOOP
RDC1, RDC2, and CDC form the network connected to the RDC pin.
ILOOP is the desired loop current in the constant-current region.
3000
R DCR1 + RDCR2 = ---------------------Iringlim
RDCR1, RDCR2, and CDCR form the network connected to the RDCR pin.
See Applications Circuit for these components.
R DC1 + R DC2
C DC = 19 ms • --------------------------------RDC1 R DC2
C DCR
R DCR1 + R DCR2
= ---------------------------------------- • 150 µs
R DCR1 R DCR2
R D = R LTH • 12.67 for high battery state
CDCR sets the ringing time constant, which can be between 15 µs and
150 µs.
RD is the resistor connected from the RD pin to GND and RLTH is the
loop-resistance threshold between on-hook and off-hook detection. RD
should be greater than 56 kΩ to guarantee detection will occur in the
Standby state. Choose the value of RD for high battery state; then use
the equation for RLTH to find where the threshold is for low battery.
Loop-Threshold Detect Equations
RD
R LTH = ------------ for high battery
12.67
This is the same equation as for RD in the preceding equation, except
solved for RLTH.
RD
R LTH = ------------ for low battery
11.37
For low battery, the detect threshold is slightly higher, which will avoid
oscillating between states.
V BAT1 – 10
R LTH = ----------------------------- • R D – 400 – 2R F
915
RLTH standby < RLTH active VBAT1 < RLTH active VBAT2, which will guarantee no unstable states under all operating conditions. This equation
will show at what resistance the standby threshold will be; it is actually
a current threshold rather than a resistance threshold, which is shown
by the Vbat dependency.
Am79R70 Data Sheet
11
DC FEED CHARACTERISTICS
50
5) VAPPH
High Battery Anti-Sat
4) VASH
40
VAB
(Volts)
30
1) Constant-Current Region
20
3) VAPPL
Low Battery Anti-Sat
2) VASL
10
0
30
IL (mA)
Figure 1. Typical VAB vs. IL DC Feed Characteristics
R DC = R DC1 + R DC2 = 20 kΩ + 80 kΩ = 100 kΩ
( V BAT1 = – 67 V , V BAT2 = – 24 V )
Notes:
1. Constant-current region:
2500
V AB = IL R L = ------------- R L ; where R L = R L + 2RF
RDC
2. Low battery
1000 • ( 104 • 10 + R SGL )
V ASL = ------------------------------------------------------------------- ; where RSGL = resistor to GND, B2EN = logic Low.
3
6720 • 10 + ( 80 • R SGL )
3
3
Anti-sat region:
1000 • ( R SGL – 56 • 10 )
V ASL = --------------------------------------------------------------- ; where RSGL = resistor to VCC, B2EN = logic Low.
3
6720 • 10 + ( 80 • R SGL )
RSGL to VCC must be greater than 100 kΩ.
3.
V APPL = 4.17 + V ASL
V APPL
I LOOPL = -----------------------------------------------------------------------------( RDC1 + R DC2 )
-------------------------------------- + 2R F + R LOOP
600
4. High battery
V ASH = V ASHH + V ASL
3
Anti-sat region:
1000 • ( 70 • 10 + R SGH )
V ASHH = ----------------------------------------------------------------------- ; where RSGH = resistor to GND, B2EN = logic High.
3
1934 • 10 + ( 31.75 • RSGH )
3
1000 • ( R SGH + 2.75 • 10 )
V ASHH = ----------------------------------------------------------------------- ; where RSGH = resistor to VCC, B2EN = logic High.
3
1934 • 10 + ( 31.75 • RSGH )
RSGH to VCC must be greater than 100 kΩ.
5.
V APPH = 4.17 + VASH
V APPH
I LOOPH = -----------------------------------------------------------------------------( R DC1 + R DC2 )
-------------------------------------- + 2RF + R LOOP
600
12
Am79R70 Data Sheet
RING-TRIP COMPONENTS
R RT2 = 12 kΩ
C RT = 1.5 µF
V BAT1
R RT1 = 320 • CF • ------------------------------------------------------------------------------------------------------------------------------------------ • ( R LRT + 150 + 2RF )
VBAT1 – 5 – ( 24 µA • 320 • CF • ( R LRT + 150 + 2R F ) )
where RLRT = Loop-detection threshold resistance for ring trip and CF = Crest factor of ringing signal (≈ 1.25)
RSLEW, CSLEW
Ring waveform rise time ≈ 0.214 • (RSLEW • CSLEW) ≈ tr.
For a 1.25 crest factor @ 20 Hz, tr ≈ 10 mS.
∴ (RSLEW = 150 kΩ, CSLEW = 0.33 µF.)
CSLEW should be changed if a different crest factor is desired.
Ringing Reference
(Input to RSLEW)
0
B(RING)
A(TIP)
Battery
This is the best time for
switching between RINGING
and other states for minimizing
detect switching transients.
Figure 2. Ringing Waveforms
A
a
RL
IL
SLIC
RSN
RDC2
b
RDC1
B
CDC
RDC
Feed current programmed by RDC1 and RDC2
Figure 3. Feed Programming
Am79R70 Data Sheet
13
TEST CIRCUITS
A(TIP)
VTX
RL
2
SLIC
VAB
VL
AGND
RL
RT
RRX
2
B(RING) RSN
IL2-4 = 20 log (VTX / VAB)
A. Two- to Four-Wire Insertion Loss
A(TIP)
VTX
SLIC
VAB
RL
AGND
RT
RRX
B(RING) RSN
VRX
IL4-2 = 20 log (VAB / VRX)
BRS = 20 log (VTX / VRX)
B. Four- to Two-Wire Insertion Loss and Four- to Four-Wire Balance Return Signal
1
ωC
A(TIP)
<< RL
RL
S1
C
SLIC
2
VL
VL
VTX
VAB
AGND
RT
RL
S2
2
B(RING) RSN
S2 Open, S1 Closed
L-T Long. Bal. = 20 log (VAB / VL)
S2 Closed, S1 Open
4-L Long. Sig. Gen. = 20 log (VL / VRX)
L-4 Long. Bal. = 20 log (VTX / VL)
C. Longitudinal Balance
14
Am79R70 Data Sheet
RRX
VRX
TEST CIRCUITS (continued)
ZD
A(TIP)
R
VTX
RT1
SLIC
VS
VM
AGND
R
ZIN
CT1
RT2
B(RING)
RSN
RRX
ZD: The desired impedance;
e.g., the characteristic impedance of the line
Return loss = –20 log (2 VM / VS)
D. Two-Wire Return Loss Test Circuit
VCC
6.2 kΩ
A(TIP)
A(TIP)
DET
RL = 600 Ω
B(RING)
15 pF
RG
B(RING)
E1
F. Ground-Key Switching
E. Loop-Detector Switching
L1
200 Ω
C1
RF1
50 Ω
A
RF2
50 Ω
200 Ω
HF
GEN
1.5 Vrms
80% Amplitude
Modulated
100 kHz to 30 MHz
CAX
33 nF
B
50 Ω
L2
C2
CBX
33 nF
VTX
SLIC
under test
G. RFI Test Circuit
Am79R70 Data Sheet
15
TEST CIRCUITS (continued)
+5 V –5 V
CRT
1.5 µF
RRT2
12 kΩ
RRT1
430 kΩ
RTRIP1
RTRIP2
CAX
2.2 nF
A(TIP)
HPA
A(TIP)
CHP
VCC
VNEG
RD
RSGH
RSGL
VTX
HPB
B(RING)
VTX
RRX
300 kΩ
VRX
RDC
RYOUT1
RSGL
open
RSN
RDC1
80 kΩ
CBX
2.2 nF
RSGH
open
RT
300 kΩ
18 nF
B(RING)
RD
75 kΩ
RDC2
20 kΩ
RDCR
RDCR
2.0 kΩ
RYOUT2
CDC 1.2 µF
RYE
D1
BAT1
VBAT1
D2
0.1 µF
VBAT2
BAT2
0.1 µF
BGND
B2EN
C1
C2
C3
D1
D2
E1
DET
RSLEW
100 kΩ
RINGIN
AGND/
DGND
See Note.
CSLEW
0.33 µF
BATTERY
GROUND
ANALOG
GROUND
Note:
The input should be 50% duty cycle CMOS-compatible input.
DIGITAL
GROUND
H. Am79R70 Test Circuit
16
Am79R70 Data Sheet
APPLICATION CIRCUIT
+5 V –5 V
CRT
1.5 µF
K1
Bat1
RRT1
515 kΩ
A(TIP)
K1
G TISP A
61089 A
RING
RFB = 50 Ω
RTRIP2
CAX = 2.2 nF
RFA = 50 Ω
TIP
RTRIP1
RRT2
12 kΩ
K2
CHP
18 nF
K2
VCC
VNEG
RD
RSGH
RSGL
VTX
RD
66 kΩ
RSGH
open
RT1
125 kΩ
HPA
HPB
RSN
RT2
CBX = 2.2 nF
VRX
RDC2
50 kΩ
RDC
RYOUT1
CDC
820 nF
CDCR
RDCR1
RDCR
15 kΩ
RYOUT2
RYE
D1
BAT1
VBAT1
D2
0.1 µF
BAT2
VBAT2
0.1 µF
B2EN
C1
C2
C3
D1
D2
E1
RSLEW
150 kΩ
See Note.
RINGIN
AGND/
DGND
Assumptions:
1. 1.25 CF
2. 25 mA ILOOP
3. 100 mA Ringing Current Limit
RDCR2
15 kΩ
10 nF
DET
BGND
VTX
RRX
125 kΩ 250 kΩ
CT
RDC1
50 kΩ
B(RING)
RSGL
open
CSLEW
0.33 µF
4. 5.2 kΩ High Battery Loop Threshold
5. 925 Ω Ringing Loop Threshold
6. 600 Ω Two-wire Impedance,
600 Ω ZL
Note:
7. G42L = 1
8. –67 V Vbat1, –24 V Vbat2
BATTERY
GROUND
ANALOG
GROUND
DIGITAL
GROUND
The input should be 50% duty cycle CMOS-compatible input.
I. Application Circuit
Am79R70 Data Sheet
17
PHYSICAL DIMENSIONS
PL032
.485
.495
.447
.453
.009
.015
.585
.595
.042
.056
.125
.140
Pin 1 I.D.
.080
.095
.547
.553
SEATING
PLANE
.400
REF.
.490
.530
.013
.021
.050 REF.
.026
.032
TOP VIEW
16-038FPO-5
PL 032
DA79
6-28-94 ae
SIDE VIEW
SOW28
28
15
.453
.500
.324
.350
0°
8°
1
.016
.050
14
.050 BSC
DETAIL A
.697
.728
0.86
0.90
.080
.100
.006
.0125
.002
.014
0.14
0.20
.014
.024
0.045 MIN.
16-038-SO28-2_AC
SOW28
DF87
9-3-97 lv
DETAIL A
18
Am79R70 Data Sheet
REVISION SUMMARY
Revision A to Revision B
•
Minor changes were made to the data sheet style and format to conform to Legerity standards.
Revision B to Revision C
•
The 28-pin SOIC information and package was added to the Ordering Information and the Connection Diagrams sections.
•
The physical dimensions (PL032 and SOW28) were added to the Physical Dimensions section.
•
Updated the Pin Description table to correct inconsistencies.
Revision C to Revision D
•
Changed Ring-Trip Components equation from:
V BAT1
R RT1 = 300 • CF • ------------------------------------------------------------------------------------------------------------------------------------------ • ( R LRT + 150 + 2RF )
Vbat – 3.5 – ( 15 µA • 300 • CF • ( R LRT + 150 + 2R F ) )
To:
V BAT1
R RT1 = 320 • CF • ------------------------------------------------------------------------------------------------------------------------------------- • ( R LRT + 150 + 2R F )
Vbat – 5 – ( 24 µA • 320 • CF • ( R LRT + 150 + 2R F ) )
Am79r70 Data Sheet
19
Notes:
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Notes:
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