September 2001 AS6WA5128 ® 3.0V to 3.6V 512K × 8 Intelliwatt™ low-power CMOS SRAM Features • AS6WA5128 • Intelliwatt™ active power circuitry • Industrial and commercial temperature ranges available • Organization: 524,288 words × 8 bits • 3.0V to 3.6V at 55 ns • Low power consumption: ACTIVE - 144 mW at 3.6V and 55 ns • 1.5V data retention • Equal access and cycle times • Easy memory expansion with CS, OE inputs • Smallest footprint packages - 36(48)-ball FBGA • ESD protection ≥ 2000 volts • Latch-up current ≥ 200 mA • Low power consumption: STANDBY - 72 µW max at 3.6V 36(48)-CSP/BGA Package (shading indicates no ball) Logic block diagram VCC GND 1 2 3 4 5 6 A A0 A1 NC A3 A6 A8 B I/O5 A2 WE A4 A7 I/O1 C I/O6 NC A5 D VSS VCC E VCC VSS F I/O7 G I/O8 H A9 512K × 8 Array (4,194,304) I/O8 Sense amp A0 A1 A2 A3 A4 A5 A6 A7 A8 Row decoder Input buffer I/O1 A9 A10 A11 A12 A13 A14 A15 A16 Column decoder Control circuit WE OE CS I/O2 A18 A17 I/O3 OE CS A16 A15 I/O4 A10 A11 A12 A13 A14 Selection guide VCC Range Product AS6WA5128 9/21/01; v.1.2 Min (V) 3.0 Typ2 (V) 3.3 Max (V) 3.6 Speed (ns) 55 Alliance Semiconductor Power Dissipation Standby (ISB1) Operating (ICC) Max (mA) Max (µA) 2 20 P. 1 of 9 Copyright © Alliance Semiconductor. All rights reserved. AS6WA5128 ® Functional description The AS6WA5128 is a low-power CMOS 4,194,304-bit Static Random Access Memory (SRAM) device organized as 524,288 words × 8 bits. It is designed for memory applications where slow data access, low power, and simple interfacing are desired. Equal address access and cycle times (tAA, tRC, tWC) of 55 ns are ideal for low-power applications. Active high and low chip selects (CS) permit easy memory expansion with multiple-bank memory systems. When CS is high, the device enters standby mode: the AS6WA5128 is guaranteed not to exceed 72 µW power consumption at 3.6V and 55ns. The device also returns data when VCC is reduced to 1.5V for even lower power consumption. A write cycle is accomplished by asserting write enable (WE) and chip select (CS) low. Data on the input pins I/O1–I/O8 is written on the rising edge of WE (write cycle 1) or CS (write cycle 2). To avoid bus contention, external devices should drive I/ O pins only after outputs have been disabled with output enable (OE) or write enable (WE). A read cycle is accomplished by asserting output enable (OE), chip select (CS), with write enable (WE) High. The chip drives I/ O pins with the data word referenced by the input address. When either chip select or output enable is inactive, or write enable is active, output drivers stay in high-impedance mode. All chip inputs and outputs are CMOS-compatible, and operation is from a single 3.0 to 3.6V supply. The device is available in the JEDEC standard 36(48)-ball FBGA package. Absolute maximum ratings Parameter Device Symbol Min Max Unit Voltage on VCC relative to VSS VtIN –0.5 VCC + 0.5 V Voltage on any I/O pin relative to GND VtI/O –0.5 Power dissipation PD – 1.0 W Storage temperature (plastic) Tstg –65 +150 °C Temperature with VCC applied Tbias –55 +125 °C DC output current (low) IOUT – 20 mA V Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Truth table CS WE OE Supply Current I/O1–I/O8 Mode H X X ISB High Z Standby (ISB) L X X ISB High Z Standby (ISB) L H H ICC High Z Output disable (ICC) L H L ICC DOUT Read (ICC) L L X ICC DIN Write (ICC) Key: X = Don’t care, L = Low, H = High. 9/21/01; v.1.2 Alliance Semiconductor P. 2 of 9 AS6WA5128 ® Recommended operating condition (over the operating range) Parameter Description Test Conditions Min VOH Output HIGH Voltage IOH = –2.1mA VCC = 3.0 - 3.6V VOL Output LOW Voltage IOL = 2.1mA VCC = 3.0 - 3.6V VIH Input HIGH Voltage VCC = 3.0 - 3.6V VIL Input LOW Voltage VCC = 3.0 - 3.6V IIX Input Load Current IOZ Output Load Current ICC VCC Operating Supply Current Max 2.4 Unit V 0.4 V 2.2 VCC + 0.5 V –0.5 0.8 V GND < VIN < VCC –1 +1 µA GND < VO < VCC; Outputs High Z –1 +1 µA VCC = 3.6V 2 mA CS = VIL, IOUT = 0mA, f = 0, VIN = VIL or VIH ICC1 @ 1 MHz CS < 0.2V, VIN < 0.2V, Average VCC Operating or VIN > VCC – 0.2V, Supply Current at 1 MHz f = 1 mS VCC = 3.6V 5 mA ICC2 Average VCC Operating CS ≠ VIL, VIN = VIL or Supply Current VIH, f = fMax VCC = 3.6V 40 mA ISB CS Power Down Current; CS > VIH, other inputs TTL Inputs = 0V – VCC VCC = 3.6V 150 µA ISB1 CS > VCC – 0.2V, CS Power Down Current; other inputs = 0V – CMOS Inputs VCC, f = fMax VCC = 3.6V 20 µA Capacitance (f = 1 MHz, Ta = Room temperature, VCC = NOMINAL) Parameter Symbol Signals Test conditions Max Unit Input capacitance CIN A, CS, WE, OE VIN = 0V 5 pF I/O capacitance CI/O I/O VIN = VOUT = 0V 7 pF 9/21/01; v.1.2 Alliance Semiconductor P. 3 of 9 AS6WA5128 ® Read cycle (over the operating range) Parameter Symbol Min Max Unit Notes Read cycle time tRC 55 – ns Address access time tAA – 55 ns 3 Chip select (CS) access time tACS – 55 ns 3 Output enable (OE) access time tOE – 25 ns Output hold from address change tOH 10 – ns 5 CS low to output in low Z tCLZ 10 – ns 4, 5 CS high to output in high Z tCHZ 0 20 ns 4, 5 OE low to output in low Z tOLZ 5 – ns 4, 5 OE high to output in high Z tOHZ 0 20 ns 4, 5 Power up time tPU 0 – ns 4, 5 Power down time tPD – 55 ns 4, 5 Key to switching waveforms Rising input Falling input Undefined/don’t care Read waveform 1 (address controlled) tRC Address tOH DOUT tAA tOH Previous data valid Data valid Read waveform 2 (CS, OE controlled) tRC1 CS tOE OE tOLZ tOHZ tACE tCHZ DOUT Data valid tCLZ Supply current 9/21/01; v.1.2 tPU tPD 50% Alliance Semiconductor ICC ISB 50% P. 4 of 9 AS6WA5128 ® Write cycle (over the operating range) Parameter Symbol Min Max Unit Notes Write cycle time tWC 55 – ns Chip select to write end tCW 40 – ns Address setup to write end tAW 40 – ns Address setup time tAS 0 – ns Write pulse width tWP 35 – ns Write recovery time tWR 0 – ns Address hold from end of write tAH 0 – ns Data valid to write end tDW 25 – ns Data hold time tDH 0 – ns 4, 5 Write enable to output in high Z tWZ 0 20 ns 4, 5 Output active from write end tOW 5 – ns 4, 5 12 12 Write waveform 1 (WE controlled) tWC tWR tAH tAW Address tWP WE tAS tDW DIN tDH Data valid tWZ tOW DOUT Write waveform 2 (CS controlled) tAW tWC tAH tWR Address tAS tCW CS tWP WE tWZ DIN tDW tDH Data valid DOUT 9/21/01; v.1.2 Alliance Semiconductor P. 5 of 9 AS6WA5128 ® Data retention characteristics (over the operating range) Parameter Symbol VCC for data retention VDR Data retention current ICCDR Chip deselect to data retention time tCDR Operation recovery time Test conditions VCC = 1.5V CS ≥ VCC – 0.1V or VIN ≥ VCC – 0.1V or VIN ≤ 0.1V tR Min Max Unit 1.5V - V – 10 µA 0 – tRC – ns Data retention waveform Data retention mode VCC VDR ≥ 1.5V VCC VCC tCDR tR VDR VIH CS VIH AC test loads and waveforms Thevenin equivalent: R1 VCC OUTPUT R1 VCC OUTPUT 30 pF RTH 5 pF ALL INPUT PULSES R2 INCLUDING JIG AND SCOPE (a) VTH OUTPUT R2 INCLUDING JIG AND SCOPE VCC Typ GND 90% 10% (b) 90% < 5 ns 10% (c) Parameters VCC = 3.6V Unit R1 1523 Ohms R2 1142 Ohms RTH 476 Ohms VTH 1.4V Volts Notes 1 2 3 4 5 6 7 8 9 10 11 12 13 14 During VCC power-up, a pull-up resistor to VCC on CS is required to meet ISB specification. This parameter is sampled, but not 100% tested. For test conditions, see AC Test Conditions. tCLZ and tCHZ are specified with CL = 5pF as in Figure C. Transition is measured ±500 mV from steady-state voltage. This parameter is guaranteed, but not tested. WE is HIGH for read cycle. CS and OE are LOW for read cycle. Address valid prior to or coincident with CS transition LOW. All read cycle timings are referenced from the last valid address to the first transitioning address. CS or WE must be HIGH during address transitions. Either CS or WE asserting high terminates a write cycle. All write cycle timings are referenced from the last valid address to the first transitioning address. N/A. 1.5V data retention applies to commercial and industrial temperature range operations. C = 30pF, except at high Z and low Z parameters, where C = 5pF. 9/21/01; v.1.2 Alliance Semiconductor P. 6 of 9 AS6WA5128 ® Typical DC and AC characteristics Normalized supply current vs. supply voltage Normalized access time vs. supply voltage 1.4 Normalized standby current vs. ambient temperature 1.0 3.0 2.5 0.8 VIN = VCC typ TA = 25° C 0.6 0.4 0.75 Normalized ISB2 1.0 Normalized TAA Normalized ICC 1.2 TA = 25° C 0.5 1.5 1.0 0.5 0.0 0.25 0.2 VCC = VCC typ VIN = VCC typ 2.0 –0.5 0.0 1.7 2.2 2.7 3.2 3.7 Supply voltage (V) 0.0 1.7 2.2 2.7 3.2 3.7 –55 Supply Voltage (V) Normalized standby current vs. supply voltage Normalized ICC vs. Cycle Time 1.4 1.0 Normalized ICC Normalized ISB 1.5 ISB2 1.2 0.8 0.6 VIN = VCC typ TA = 25° C 0.4 0.2 25 105 Ambient temperature (°C) VIN = 3.6V TA = 25° C 1.0 0.50 0.10 0.0 1 9/21/01; v.1.2 2.8 1.9 Supply voltage (V) 3.7 Alliance Semiconductor 1 5 10 Supply voltage (V) P. 7 of 9 15 AS6WA5128 ® Package diagrams and dimensions 36(48)-ball FBGA Bottom View 6 5 4 3 Top View 2 Ball #A1 index Ball #A1 1 A B C D SRAM Die C1 C E F A1 G H Elastomer A B B1 Detail View Side View A E2 D E E2 Y E Die Die E1 0.3/Typ Minimum Typical Maximum A – 0.75 – B 6.90 7.00 7.10 1. Bump counts: 36(48) (8 row × 6 column). B1 – 3.75 – 2. Pitch: (x,y) = 0.75 mm × 0.75 mm (typ). C 10.90 11.00 11.10 C1 – 5.25 – D 0.30 0.35 0.40 5. Typ: typical. E – – 1.20 6. Y is coplanarity: 0.08 (max). E1 – 0.68 – E2 0.22 0.25 0.27 Y – – 0.08 9/21/01; v.1.2 Notes 3. Units: millimeters. 4. All tolerance are ±0.050 unless otherwise specified. Alliance Semiconductor P. 8 of 9 AS6WA5128 ® Ordering codes Speed (ns) Ordering Code Package Type Operating Range 55 AS6WA5128-BC 48-ball fine pitch BGA Commercial 55 AS6WA5128-BI 48-ball fine pitch BGA Industrial Part numbering system AS6WA 5128 B C, I SRAM Intelliwatt™ prefix Device number Package: B: CSP/BGA Temperature range: C: Commercial: 0° C to 70° C I: Industrial: –40°C to 85° C 9/21/01; v.1.2 Alliance Semiconductor P. 9 of 9 © Copyright Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. 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