Features • Incorporates the ARM7TDMI™ ARM® Thumb® Processor Core • • • • • • • • • • • • – High-performance 32-bit RISC Architecture – High-density 16-bit Instruction Set – Leader in MIPS/Watt – Embedded ICE (In-Circuit Emulation) 4K Bytes Internal RAM Fully-programmable External Bus Interface (EBI) – Maximum External Address Space of 64M Bytes – Up to Eight Chip Selects – Software Programmable 8/16-bit External Data Bus Eight-level Priority, Individually Maskable, Vectored Interrupt Controller – 4 External Interrupts, Including a High-priority Low-latency Interrupt Request 32 Programmable I/O Lines Three-channel 16-bit Timer/Counter – Three External Clock Inputs – Two Multi-purpose I/O Pins per Channel Two USARTs – Two Dedicated Peripheral Data Controller (PDC) Channels per USART Programmable Watchdog Timer Low-power Idle Mode Fully Static Operation: 0 Hz to 33 MHz 2.7V to 3.6V Operating Range -40°C to 85°C Operating Temperature Range Available in a 100-lead TQFP Package Description AT91 ARM® Thumb® 16/32-bit Microcontroller AT91M40400 Electrical and Mechanical Characteristics The AT91M40400 is a member of the Atmel AT91 16/32-bit microcontroller family which is based on the ARM7TDMI processor core. This processor has a high-performance 32-bit RISC architecture with a high-density 16-bit instruction set and very low power consumption. In addition, a large number of internally banked registers result in very fast exception handling, making the device ideal for real-time control applications. The AT91 ARM-based microcontroller unit family also features Atmel’s highdensity, nonvolatile memory technology. The on-chip Flash program memory is insystem programmable. The AT91M40400 has a direct connection to off-chip memory, including Flash, through the External Bus Interface (EBI). The device is manufactured using Atmel’s high-density CMOS technology. By combining the ARM7TDMI processor core with an on-chip RAM and a wide range of peripheral functions on a monolithic chip, the AT91M40400 is a powerful microcontroller that offers a flexible, cost-effective solution to many compute-intensive embedded control applications. Rev. 1078C–12/00 1 Pin Configuration P21/TXD1/NTRI P20/SCK1 P19 P18 P17 P16 P15/RXD0 P14/TXD0 P13/SCK0 P12/FIQ GND P11/IRQ2 P10/IRQ1 VDD VDD P9/IRQ0 P8/TIOB2 P7/TIOA2 P6/TCLK2 P5/TIOB1 P4/TIOA1 P3/TCLK1 GND GND P2/TIOB0 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 Figure 1. AT91M40400 Pinout (Top View) P27/NCS3 100 26 P29/A21/CS6 P26/NCS2 99 27 VDD NCS1 98 28 VDD NCS0 97 29 P30/A22/CS5 NWAIT 96 30 P31/A23/CS4 VDD 95 31 D0 VDD 94 32 D1 NWR0/NWE 93 33 D2 NRD/NOE 92 34 D3 TCK 91 35 D4 TDO 90 36 GND TDI 89 37 D5 38 D6 AT91M40400 100-lead TQFP TMS 88 GND 87 39 D7 GND 86 40 D8 P25/MCKO 85 41 D9 P24/BMS 84 42 D10 P23 83 43 D11 MCKI 82 44 VDD VDD 81 45 D12 NWDOVF 80 46 D13 NRST 79 47 D14 2 17 18 19 20 21 22 23 24 25 A14 GND A15 A16 A17 A18 A19 P28/A20/CS7 16 GND 15 A13 11 A8 A12 10 VDD 14 9 A7 A11 8 A6 13 7 A5 12 6 A4 A9 5 A3 AT91M40400 A10 4 P1/TIOA0 A2 50 3 P0/TCLK0 76 2 49 P22/RXD1 A1 D15 GND 48 77 1 78 A0/NLB GND NWR1/NUB AT91M40400 Table 1. AT91M40400 Pin Description Type Active Level Output – I/O – Chip Select Output Low CS4 - CS7 Chip Select Output High A23 - A20 after reset NWR0 Lower Byte 0 Write Signal Output Low Used in Byte Write Option NWR1 Upper Byte 1 Write Signal Output Low Used in Byte Write Option NRD Read Signal Output Low Used in Byte Write Option NWE Write Enable Output Low Used in Byte Select Option NOE Output Enable Output Low Used in Byte Select Option NUB Upper Byte Select Output Low Used in Byte Select Option NLB Lower Byte Select Output Low Used in Byte Select Option NWAIT Wait Input Input Low BMS Boot Mode Select Input – Sampled during reset FIQ Fast Interrupt Request Input – PIO - controlled after reset IRQ0-IRQ2 External Interrupt Request Input – PIO - controlled after reset TCLK0-TCLK2 Timer External Clock Input – PIO - controlled after reset TIOA0-TIOA2 Multipurpose Timer I/O Pin A I/O – PIO - controlled after reset TIOB0-TIOB2 Multipurpose Timer I/O Pin B I/O – PIO - controlled after reset SCK0-SCK1 External Serial Clock I/O – PIO - controlled after reset TXD0-TXD1 Transmit Data Output Output – PIO - controlled after reset RXD0-RXD1 Receive Data Input Input – PIO - controlled after reset PIO P0-P31 Parallel IO Line I/O – WD NWDOVF Watchdog Overflow Output Low MCKI Master Clock Input Input – MCKO Master Clock Output Output – NRST Hardware Reset Input Input Low Schmidt trigger, internal pull-up NTRI Tri-state Mode Select Input Low Sampled during reset TMS Test Mode Select Input – Schmidt trigger, internal pull-up TDI Test Data Input Input – Schmidt trigger, internal pull-up TDO Test Data Output Output – TCK Test Clock Input – VDD Power GND Ground Module EBI Name Function A0 - A23 Address Bus D0 - D15 Data Bus NCS0 - NCS3 Comments All valid after reset AIC Timer USART Open drain Schmidt trigger Clock Reset ICE Schmidt trigger, internal pull-up Power 3 Absolute Maximum Ratings* Operating Temperature (Commercial) ........0 to +70°C *NOTICE: Operating Temperature (Industrial) .....-40°C to +85°C Voltage on any input Pin with respect to Ground ........................-0.5V to +5.5V Maximum Operating Voltage ................................4.6V Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC Output Current ..............................................2 mA DC Characteristics TA = -40°C to 85°C, VDD = 2.7V to 3.6V unless otherwise specified. All pads are 5V tolerant. Table 2. DC Characteristics Symbol Parameter Condition VIL Input Low Voltage VDD = 2.7V to 3.6V VIH Input High Voltage VDD = 2.7V to 3.6V VOL Output Low Voltage IOL = 0.8 mA, VDD = 3.0V VOH Output High Voltage IOH = 0.8 mA, VDD = 3.0V IOH Output Source Current VDD = 3.0V, VOH = 2.4V 2 mA IOL Output Sink Current VDD = 3.0V, VOL = 0.4V 2 mA ILEAK Input Leakage Current 100 nA IPULL Input Pull-up Current -80 µA ICAP Input Capacitance for all Pins 12 pF ISC Static Current 4 AT91M40400 VDD = 3.3V, VIN = 0 VDD = 3.6V, MCKI = 0 Hz All inputs driven, TMS, TDI, TCK, NRST = 1 Min Typ Max Units -0.5 0.3 x VDD V 0.7 x VDD VDD + 0.5 or 5.5 V 0.1 V VDD - 0.1 V -400 30 µA AT91M40400 Power Supply Current The following table shows results of measurements peformed at typical conditions (VDD = 3.3V and TA = 25°C). Table 3. Power Consumption Mode Conditions Typ Unit Reset NRST = 0 1.08 mW/MHz Normal Fetch in Internal SRAM 1.42 mW/MHz Idle – 0.63 mW/MHz Conditions Environment Constraints The output delays are valid for a capacitive load of 50 pF as shown in Figure 2. Figure 2. Output/Bi-directional Pad Capacitive Load CL = 50 pF PAD Timing Results The output delays are for a capacitive load of 50 pF as shown in Figure 2 above. In order to obtain the timing for other capacitance values, the following equation should be used: t = t datasheet + ""factor × ( C load – 50 pF ) Table 4. Derating Factor Due to Capacitive Load Variation Parameter Factor Commercial Industrial Units 0.052 0.058 ns/pF 5 Clock Waveforms Table 5. Clock Waveform Parameters Minimum 25 MHz Maximum Symbol Parameter 33 MHz 25 MHz 33 MHz Units 1/tCP Oscillator Frequency 25 33 MHz tCP Main Clock Period 40 30 ns tCH High Time 17 12 ns tCL Low Time 17 12 ns tr Rising Edge TBD TBD ns tf Falling Edge TBD TBD ns Table 6. Clock Propagation Times Maximum Symbol Parameter 25 MHz 33 MHz Units tCDLH Rising Edge Propagation Time 12 9 ns tCDHL Falling Edge Propagation Time 12 9 ns Figure 3. Clock Waveform tr tCH MCKI tf 0.7 VDDIO 0.3 VDDIO tCL MCKO tCDLH 6 AT91M40400 tCDHL tCP AT91M40400 AC Characteristics The following tables refer to Figure 4. Table 7. General-purpose EBI Signals Minimum Symbol Parameter EBI1 Maximum 25 MHz 33 MHz 25 MHz 33 MHz Units MCKI Falling to NUB Valid 4 4 16 11 ns EBI2 MCKI Falling to NLB/A0 Valid 6 6 22 14 ns EBI3 MCKI Falling to A7 - A1 Valid 6 6 22 15 ns EBI4 MCKI Falling to A23 - A8 Valid 6 6 21 14 ns EBI5 MCKI Falling to Chip Select 5 5 21 14 ns EBI6 NWAIT Setup before MCKI Rising 4 4 8 6 ns EBI7 NWAIT Hold after MCKI Rising 1 1 5 4 ns Table 8. EBI Write Signals Minimum Symbol Parameter EBI8 Maximum 25 MHz 33 MHz 25 MHz 33 MHz Units MCKI Rising to NWR Active (No Wait States) 3 3 14 10 ns EBI9 MCKI Rising to NWR Active (Wait States) 3 3 14 10 ns EBI10 MCKI Falling to NWR Inactive (No Wait States) 4 4 16 11 ns EBI11 MCKI Rising to NWR Inactive (Wait States) 4 4 16 11 ns EBI12 MCKI Rising to D0 - D15 Out Valid 5 5 20 14 ns EBI19 NWR High to A23 - A1, NUB/NLB/A0, NCS, CS changes (No Wait States) TBD TBD ns EB20 NWR High to A23 - A1, NCS, CS Changes (Wait States) tCP/2 tCP/2 ns EBI21 Data Out Valid before NWR High TBD TBD ns EBI22 Data Out Valid after NWR High (No Wait States) TBD TBD ns EBI23 Data Out Valid after NWR High (Wait States) tCP/2 tCP/2 ns 7 Table 9. EBI Read Signals Minimum Symbol Parameter EBI13 EBI14 MCKI Rising to NRD Valid EBI15 Maximum 25 MHz 33 MHz 25 MHz 33 MHz Units MCKI Falling to NRD Valid(1) 4 4 15 10 ns (2) 4 4 15 10 ns D0 - D15 in Setup before MCKI Falling 2 2 3 3 ns EBI16 D0 - D15 in Hold after MCKI Falling 1 1 2 2 ns EBI17 NRD High to A23 - A1, NCS, CS Changes TBD TBD ns Data Hold after NRD High TBD TBD ns EBI18 Notes: 8 1. Early Read Protocol 2. Standard Read Protocol AT91M40400 AT91M40400 Figure 4. EBI Signals Relative to MCKI MCKI EBI5 EBI5 NCS CS EBI3/EBI4 No Wait Wait A1 - A23 EBI6 EBI7 NWAIT EBI1/EBI2 NUB/NLB/A0 EBI13 EBI13 EBI17 NRD(1) EBI14 EBI18 NRD(2) EBI15 EBI16 D0 - D15 read EBI8 EBI10 EBI19 NWR (No Wait States) EBI9 EBI20 EBI11 NWR (Wait States) EBI12 EBI21 EBI22 EBI22 D0 - D15 to Write No Wait Notes: Wait 1. Early Read Protocol 2. Standard Read Protocol 9 Peripheral Signals USART Signals The inputs have to meet the minimum pulse width and period constraints shown in Table 10 and Table 11, and represented in Figure 5. Table 10. USART Input Minimum Pulse Width Symbol Parameter US1 SCK/RXD Minimum Pulse Width Minimum Pulse Width Units 3(tCP/2) ns Minimum Input Period Units 5(tCP/2) ns Table 11. USART Minimum Input Period Symbol Parameter US2 SCK Minimum Input Period Figure 5. USART Signals US1 RXD US2 US1 SCK 10 AT91M40400 AT91M40400 Timer/Counter Signals Due to internal synchronization of input signals, there is a delay between an input event and a corresponding output event. This delay is 3(tCP) in Waveform Event Detection mode and 4(tCP) in Waveform Total Count Detection mode. The inputs have to meet the minimum pulse width and minimum input period shown in Tables 12 and 13, and as represented in Figure 6. Table 12. Timer Input Minimum Pulse Width Symbol Parameter TC1 TCLK/TIOA/TIOB Minimum Pulse-Width Minimum Pulse Width Units 3(tCP/2) ns Minimum Input Period Units 5(tCP/2) ns Table 13. Timer Input Minimum Period Symbol Parameter TC2 TCLK/TIOA/TIOB Minimum Input Period Figure 6. Timer Input 3(tCP/2) TC2 1(tCP) MCKI TC1 TIOA/TIOB/TCLK 11 Watchdog Timer Signals Table 14. Watchdog Timer Outputs Minimum Symbol Parameter WD1 WD2 Maximum 25 MHz 33 MHz 25 MHz 33 MHz MCKI Rising to NWDOVF Rising 3 3 13 9 MCKI Rising to NWDOVF Falling 4 4 14 10 Units ns Figure 7. Watchdog Signals Relative to MCKI MCKI WD1 NWDOVF Output WD2 Z Z Reset Signals A minimum pulse width is necessary, as shown in Table 15 and as represented in Figure 8. Table 15. Reset Minimum Pulse Width Symbol Parameter RST1 NRST Minimum Pulse Width Minimum Pulse Width Units 10(tCP) ns Figure 8. Reset Signal RST1 NRST Only the NRST rising edge is synchronized with MCKI. The falling edge is asynchronous. 12 AT91M40400 AT91M40400 Advanced Interrupt Controller Signals Inputs have to meet the minimum pulse width and mimimum input period shown in Table 16 and Table 17 and represented in Figure 9. Table 16. AIC Input Minimum Pulse Width Symbol Parameter AIC1 FIQ/IRQ0/IRQ1/IRQ2/IRQ3 Minimum Pulse Width Minimum Pulse Width Units 3(tCP/2) ns Minimum Input Period Units 5(tCP/2) ns Table 17. AIC Input Minimum Period Symbol Parameter AIC2 AIC Minimum Input Period Figure 9. AIC Signals AIC2 MCKI AIC1 FIQ/IRQ0/IRQ1/IRQ2/IRQ3 Input 13 Parallel I/O Signals The inputs have to meet the minimum pulse width shown in Table 18 and represented in Figure 10. Table 18. PIO Input Minimum Pulse Width Symbol Parameter PIO1 PIO Input Minimum Pulse Width Figure 10. PIO Signal PIO1 PIO Inputs 14 AT91M40400 Minimum Pulse Width Units 3(tCP/2) ns AT91M40400 ICE Interface Signals Table 19. ICE Interface Timing Specifications Minimum Symbol Parameter ICE1 Maximum 25 MHz 33 MHz TCK Low Period TBD TBD ICE2 TCK High Period TBD TBD ICE3 TDI, TMS Setup to TCK ICE4 TDI, TMS Hold from TCK TBD TBD ICE5 TDO Hold Time TBD TBD ICE6 TCK to TDO Valid TBD TBD 25 MHz 33 MHz TBD TBD Units ns TBD TBD Figure 11. ICE Interface Signal TCK ICE1 ICE2 TMS/TDI ICE3 ICE4 TDO ICE5 ICE6 15 Package Outline TQFP 100 100-lead Thin (1.4 mm) Quad Flat Pack Table 20. Common Dimensions (mm) Symbol Min Nom Max c 0.09 0.2 c1 0.09 0.16 L 0.45 0.6 L1 0.75 1.00 REF R2 0.08 R1 0.08 S 0.2 q 0° θ1 0° θ2 θ3 0.2 3.5° 7° 11° 12° 13° 11° 12° 13° A 1.6 A1 0.05 A2 1.35 0.15 1.4 1.45 Tolerances of form and position aaa 0.2 bbb 0.2 Table 21. Lead Count Dimensions b b1 Pin Count D/E BSC D1/E1 BSC Min Nom Max Min Nom Max e BSC ccc ddd 100 16.0 14.0 0.17 0.22 0.27 0.17 0.2 0.23 0.50 0.10 0.06 Thermal resistance of package: 40°C/W. 16 AT91M40400 AT91M40400 Figure 12. 100-lead TQFP Package Drawing aaa bbb PIN 1 θ2 S ccc θ3 ddd R1 θ1 R2 0.25 θ c c1 L1 17 Ordering Information Speed (MHz) Power Supply Ordering Code 25 2.7V to 3.6V AT91M40400-25AI 33 2.7V to 3.6V AT91M40400-33AC Package Operation Range Industrial (-40°C to 85°C) TQFP 100 18 AT91M40400 Commercial (0°C to 70°C) Atmel Headquarters Atmel Operations Corporate Headquarters Atmel Colorado Springs 2325 Orchard Parkway San Jose, CA 95131 TEL (408) 441-0311 FAX (408) 487-2600 Europe Atmel SarL Route des Arsenaux 41 Casa Postale 80 CH-1705 Fribourg Switzerland TEL (41) 26-426-5555 FAX (41) 26-426-5500 Asia Atmel Asia, Ltd. Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimhatsui East Kowloon Hong Kong TEL (852) 2721-9778 FAX (852) 2722-1369 Japan 1150 E. Cheyenne Mtn. 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The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life suppor t devices or systems. ARM, Thumb and ARM Powered are registered trademarks of ARM Limited. ARM7TDMI is a trademark of ARM Limited. Marks bearing ® and/or ™ are registered trademarks and trademarks of Atmel Corporation. Terms and product names in this document may be trademarks of others. Printed on recycled paper. 1078C–12/00/0M