[ /Title (CD40 70B, CD407 7B) /Subject (CMO S Quad ExclusiveOR and ExclusiveNOR Gate) /Autho r () /Keywords (Harris Semiconductor, CD400 0, metal gate, CMOS , pdip, cerdip, mil, CD4070B, CD4077B Data sheet acquired from Harris Semiconductor SCHS055A CMOS Quad Exclusive-OR and Exclusive-NOR Gate January 1998 - Revised March 2002 Features Description • High-Voltage Types (20V Rating) The Harris CD4070B contains four independent ExclusiveOR gates. The Harris CD4077B contains four independent Exclusive-NOR gates. • CD4070B - Quad Exclusive-OR Gate • CD4077B - Quad Exclusive-NOR Gate The CD4070B and CD4077B provide the system designer with a means for direct implementation of the Exclusive-OR and Exclusive-NOR functions, respectively. • Medium Speed Operation - tPHL, tPLH = 65ns (Typ) at VDD = 10V, CL = 50pF • 100% Tested for Quiescent Current at 20V Ordering Information • Standardized Symmetrical Output Characteristics • 5V, 10V and 15V Parametric Ratings PART NUMBER • Maximum Input Current of 1µA at 18V Over Full Package Temperature Range - 100nA at 18V and 25oC TEMP. RANGE (oC) PACKAGE PKG. NO. CD4070BE -55 to 125 14 Ld PDIP E14.3 CD4077BE -55 to 125 14 Ld PDIP E14.3 CD4070BF -55 to 125 14 Ld CERDIP F14.3 CD4077BF -55 to 125 14 Ld CERDIP F14.3 CD4070BM -55 to 125 14 Ld SOIC M14.15 Applications CD4077BM -55 to 125 14 Ld SOIC M14.15 • Logical Comparators CD4070BNSR -55 to 125 14 Ld SOP NSR CD4077BNSR -55 to 125 14 Ld SOP NSR • Noise Margin (Over Full Package Temperature Range) - 1V at VDD = 5V, 2V at VDD = 10V, 2.5V at VDD = 15V • Meets All Requirements of JEDEC Standard No. 13B, “Standard Specifications for Description of ‘B’ Series CMOS Devices • Adders/Subtractors • Parity Generators and Checkers Pinouts CD4070B (PDIP, CERDIP, SOIC, SOP) TOP VIEW CD4077B (PDIP, CERDIP, SOIC, SOP) TOP VIEW A 1 14 VDD A 1 14 VDD B 2 13 H B 2 13 H J=A⊕B 3 12 G J=A⊕B 3 12 G K=C⊕D 4 11 M = G ⊕ H K=C⊕D 4 11 M = G ⊕ H C 5 10 L = E ⊕ F C 5 10 L = E ⊕ F D 6 9 F D 6 9 F VSS 7 8 E VSS 7 8 E CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2002, Texas Instruments Incorporated 1 File Number 910.1 CD4070B, CD4077B Functional Diagrams CD4070B 1 A J=A⊕B K=C⊕D M=G⊕ H L=E⊕F VSS = 7 VDD = 14 5 C 4 6 D 8 E 10 9 F H 3 2 B G CD4077B 12 11 13 A J B J =A K=C K L ⊕B ⊕D ⊕H =E⊕F C D M=G E L F G M H 1 3 2 5 4 6 8 10 9 12 11 13 J K L M VDD VDD VDD p VDD B† p 2(5,9,12) n p 1(6,8,13) n p n J p n 3(4,10,11) n VDD n p p J VDD p VSS † n VSS VDD A† 2(5,9,12) n VSS p B† p A† p 1(6,8,13) n n VSS VSS † INPUTS PROTECTED BY CMOS PROTECTION NETWORK 3(4,10,11) n VSS VDD INPUTS PROTECTED BY CMOS PROTECTION NETWORK VSS VSS FIGURE 1. SCHEMATIC DIAGRAM FOR CD4070B (1 OF 4 IDENTICAL GATES) FIGURE 2. SCHEMATIC DIAGRAM FOR CD4077B (1 OF 4 IDENTICAL GATES) CD4070B TRUTH TABLE (1 OF 4 GATES) CD4077B TRUTH TABLE (1 OF 4 GATES) A B J A B J 0 0 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 0 1 1 0 1 1 1 NOTE: 1 = High Level 0 = Low Level J=A⊕B NOTE: 1 = High Level 0 = Low Level J=A⊕B 2 CD4070B, CD4077B Absolute Maximum Ratings Thermal Information DC Supply Voltage Range (VDD) . . . . . . . . . . . . . . . . . -0.5V to 20V Input Voltage Range, All Inputs . . . . . . . . . . . . . . -0.5V to VDD 0.5V DC Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .± 10mA Package Thermal Impedance, θJA (see Note 1): PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80oC/W SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86oC/W SOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76oC/W Maximum Junction Temperature (Hermetic Package or Die) . 175oC Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Operating Conditions Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range (Typical) . . . . . . . . . . . . . . . . . . . . 3V to 18V CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. The package thermal impedance is calculated in accordance with JESD 51-7. DC Electrical Specifications LIMITS AT INDICATED TEMPERATURES (oC) CONDITIONS PARAMETER Quiescent Device Current IDD Max Output Low (Sink) Current IOL Min Output High (Source) Current IOH Min Output Voltage: Low Level, VOL Max Output Voltage: High Level, VOH Min Input Low Voltage, VIL Max Input High Voltage, VIH Min Input Current, IIN Max 25 VO (V) VIN (V) VDD (V) -55 -40 85 125 MIN TYP MAX UNITS - 0, 5 5 0.25 0.25 7.5 7.5 - 0.01 0.25 µA - 0, 10 10 0.5 0.5 15 15 - 0.01 0.5 µA - 0, 15 15 1 1 30 30 - 0.01 1 µA - 0, 20 20 5 5 150 150 - 0.02 5 µA 0.4 0, 5 5 0.64 0.61 0.42 0.36 0.51 1 - mA 0.5 0, 10 10 1.6 1.5 1.1 0.9 1.3 2.6 - mA 1.5 0, 15 15 4.2 4 2.8 2.4 3.4 6.8 - mA 4.6 0, 5 5 -0.64 -0.61 -0.42 -0.36 -0.51 -1 - mA 2.5 0, 5 5 -2 -1.8 -1.3 -1.15 -1.6 -3.2 - mA 9.5 0, 10 10 -1.6 -1.5 -1.1 -0.9 -1.3 -2.6 - mA 13.5 0, 15 15 -4.2 -4 -2.8 -2.4 -3.4 -6.8 - mA - 0, 5 5 0.05 0.05 0.05 0.05 - 0 0.05 V - 0, 10 10 0.05 0.05 0.05 0.05 - 0 0.05 V - 0, 15 15 0.05 0.05 0.05 0.05 - 0 0.05 V - 0, 5 5 4.95 4.95 4.95 4.95 4.95 5 - V - 0, 10 10 9.95 9.95 9.95 9.95 9.95 10 - V - 0, 15 15 14.95 14.95 14.95 14.95 14.95 15 - V 0.5, 4.5 - 5 1.5 1.5 1.5 1.5 - - 1.5 V 1, 9 - 10 3 3 3 3 - - 3 V 1.5, 13.5 - 15 4 4 4 4 - - 4 V 0.5, 4.5 - 5 3.5 3.5 3.5 3.5 3.5 - - V 1, 9 - 10 7 7 7 7 7 - - V 1.5, 13.5 - 15 11 11 11 11 11 - - V - 0, 18 18 ±0.1 ±0.1 ±1 ±1 - ±10-5 ±0.1 µA 3 CD4070B, CD4077B AC Electrical Specifications TA = 25oC, Input tr, tf = 20ns, CL = 50pF, RL = 200kΩ TEST CONDITIONS PARAMETER Propagation Delay Time Transition Time SYMBOL VDD (V) TYP MAX UNITS tPHL, tPLH 5 140 280 ns 10 65 130 ns 15 50 100 ns 5 100 200 ns 10 50 100 ns 15 40 80 ns Any Input 5 7.5 pF tTHL, tTLH Input Capacitance LIMITS ON ALL TYPES CIN TA = 25oC IOL, OUTPUT LOW (SINK) CURRENT (mA) GATE TO SOURCE VOLTAGE (VGS) = 15V 30 25 20 10V 15 10 5V 5 0 0 5 10 15 TA = 25oC 15 GATE TO SOURCE VOLTAGE (VGS) = 15V 12.5 10 10V 7.5 5 5V 2.5 0 0 5 VDS, DRAIN TO SOURCE VOLTAGE (V) 10 15 VDS, DRAIN TO SOURCE VOLTAGE (V) FIGURE 4. MINIMUM OUTPUT LOW (SINK) CURRENT CHARACTERISTICS VDS, DRAIN TO SOURCE VOLTAGE (V) VDS, DRAIN TO SOURCE VOLTAGE (V) -15 -10 -5 TA = 25oC GATE TO SOURCE VOLTAGE (VGS) = -5V 0 0 -5 -10 -15 -10V -20 -25 -15V -30 IOH, OUTPUT HIGH (SOURCE) CURRENT (mA) FIGURE 3. TYPICAL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS -15 -10 -5 0 0 TA = 25oC GATE TO SOURCE VOLTAGE (VGS) = -5V -5 -10V -15V FIGURE 5. TYPICAL OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS -10 -15 FIGURE 6. MINIMUM OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS 4 IOH, OUTPUT HIGH (SINK) CURRENT (mA) IOL, OUTPUT LOW (SINK) CURRENT (mA) Typical Performance Curves CD4070B, CD4077B (Continued) tPHL, tPLH, PROPAGATION DELAY TIME (ns) tTHL, tTLH, TRANSITION TIME (ns) Typical Performance Curves TA = 25oC 200 SUPPLY VOLTAGE (VDD) = 5V 150 100 10V 50 15V 0 0 20 40 60 80 100 TA = 25oC 300 200 SUPPLY VOLTAGE (VDD) = 5V 100 10V 15V 0 0 110 20 105 TA = 25oC LOAD CAPACITANCE CL = 50pF 300 200 100 0 5 10 15 60 80 100 FIGURE 8. TYPICAL PROPAGATION DELAY TIME AS A FUNCTION OF LOAD CAPACITANCE PD, POWER DISSIPATION (µW) tPHL, tPLH, PROPAGATION DELAY TIME (ns) FIGURE 7. TYPICAL TRANSITION TIME AS A FUNCTION OF LOAD CAPACITANCE 0 40 CL, LOAD CAPACITANCE (pF) CL, LOAD CAPACITANCE (pF) VDD, SUPPLY VOLTAGE (V) FIGURE 9. TYPICAL PROPAGATION DELAY TIME AS A FUNCTION OF SUPPLY VOLTAGE V 104 )= 15 D E AG LT O YV PL 103 102 (V D P SU 10 10V CL = 50pF 10V CL = 15pF 5V 1 10-1 10-1 20 TA = 25oC 1 102 103 10 fI, INPUT FREQUENCY (kHz) 104 FIGURE 10. TYPICAL DYNAMIC POWER DISSIPATION AS A FUNCTION OF INPUT FREQUENCY 5 CD4070B, CD4077B Dual-In-Line Plastic Packages (PDIP) E14.3 (JEDEC MS-001-AA ISSUE D) N 14 LEAD DUAL-IN-LINE PLASTIC PACKAGE E1 INDEX AREA 1 2 3 INCHES N/2 MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A - 0.210 - 5.33 4 A1 0.015 - 0.39 - 4 A2 0.115 0.195 2.93 4.95 - -B-AE D BASE PLANE A2 -C- SEATING PLANE A L D1 e B1 D1 B 0.010 (0.25) M A1 eC C A B S B 0.014 0.022 0.356 0.558 - C L B1 0.045 0.070 1.15 1.77 8 eA C 0.008 0.014 D 0.735 0.775 18.66 D1 0.005 - 0.13 - 5 E 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5 C eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 1.14mm). 6 e 0.100 BSC eA 0.300 BSC eB - L 0.115 N 0.204 14 0.355 19.68 2.54 BSC 7.62 BSC 0.430 - 0.150 2.93 10.92 3.81 14 5 6 7 4 9 Rev. 0 12/93 CD4070B, CD4077B Ceramic Dual-In-Line Frit Seal Packages (CERDIP) c1 F14.3 MIL-STD-1835 GDIP1-T14 (D-1, CONFIGURATION A) LEAD FINISH 14 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE -D- -A- BASE METAL INCHES (c) SYMBOL E M -Bbbb S C A-B S Q -C- SEATING PLANE S1 - 0.200 - 5.08 - 0.014 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - eA b2 b ccc M C A-B S e D S eA/2 NOTES b α A A MAX A A L MIN M (b) D BASE PLANE MILLIMETERS MAX b1 SECTION A-A D S MIN c b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 D - 0.785 - 19.94 5 E 0.220 0.310 5.59 7.87 5 e aaa M C A - B S D S NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH. 0.100 BSC 2.54 BSC - eA 0.300 BSC 7.62 BSC - eA/2 0.150 BSC 3.81 BSC - L 0.125 0.200 3.18 5.08 - Q 0.015 0.060 0.38 1.52 6 S1 0.005 - 0.13 - 7 α 90o 105o 90o 105o - aaa - 0.015 - 0.38 - bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - M - 0.0015 - 0.038 2, 3 N 14 14 8 Rev. 0 4/94 7 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. 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