Revised January 1999 CD4514BC• CD4515BC 4-Bit Latched/4-to-16 Line Decoders General Description Features The CD4514BC and CD4515BC are 4-to-16 line decoders with latched inputs implemented with complementary MOS (CMOS) circuits constructed with N- and P-channel enhancement mode transistors. These circuits are primarily used in decoding applications where low power dissipation and/or high noise immunity is required. ■ Wide supply voltage range: The CD4514BC (output active high option) presents a logical “1” at the selected output, whereas the CD4515BC presents a logical “0” at the selected output. The input latches are R–S type flip-flops, which hold the last input data presented prior to the strobe transition from “1” to “0”. This input data is decoded and the corresponding output is activated. An output inhibit line is also available. ■ High noise immunity: 3.0V to 15V 0.45 VDD (typ.) ■ Low power TTL: fan out of 2 compatibility: driving 74L ■ Low quiescent power dissipation: 0.025 µW/package @ 5.0 VDC ■ Single supply operation ■ Input impedance = 1012Ω typically ■ Plug-in replacement for MC14514, MC14515 Ordering Code: Order Number CD4514BCWM Package Number Package Diagram M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide CD4514BCN N24A 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.600” Wide CD4515BCWM M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide CD4515BCN N24A 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.600” Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Connection Diagram Pin Assignments for SOIC and DIP Top View © 1999 Fairchild Semiconductor Corporation DS005994.prf www.fairchildsemi.com CD4514BC• CD4515BC 4-Bit Latched/4-to-16 Line Decoders October 1987 CD4514BC• CD4515BC Truth Table Decode Truth Table (Strobe = 1) Data Inputs Selected Output CD4514 = Logic “1” Inhibit D C B A 0 0 0 0 0 S0 0 0 0 0 1 S1 0 0 0 1 0 S2 0 0 0 1 1 S3 0 0 1 0 0 S4 0 0 1 0 1 S5 0 0 1 1 0 S6 0 0 1 1 1 S7 0 1 0 0 0 S8 0 1 0 0 1 S9 0 1 0 1 0 S10 0 1 0 1 1 S11 0 1 1 0 0 S12 0 1 1 0 1 S13 0 1 1 1 0 S14 0 1 1 1 1 1 X X X X CD4515 = Logic “0” S15 All Outputs = 0, CD4514 All Outputs = 1, CD4515 X = Don’t Care Logic Diagram www.fairchildsemi.com 2 Recommended Operating Conditions (Note 2) −0.5V to +18V DC Supply Voltage (VDD) Input Voltage (VIN) −0.5V to VDD + 0.5V −65°C to +150°C Storage Temperature Range (TS) DC Supply Voltage (VDD) 3V to 15V Input Voltage (VIN) 0V to VDD Operating Temperature Range (TA) Power Dissipation (PD) −40°C to +85°C CD4514BC, CD4515BC Dual-In-Line 700 mW Small Outline 500 mW Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. Except for “Operating Temperature Range” they are not meant to imply that the devices should be operated at these limits. The tables of “Recommended Operating Conditions” and “Electrical Characteristics” provide conditions for actual device operation. Lead Temperature (TL) (Soldering, 10 seconds) 260°C Note 2: VSS = 0V unless otherwise specified. DC Electrical Characteristics (Note 2) CD4514BC, CD4515BC Symbol IDD VOL Parameter VIH IOL IOH IIN Max +25°C Min +85°C Typ Max Min Max Units VDD = 5V, VIN = VDD or V SS 20 0.005 20 150 µA Current VDD = 10V, VIN = VDD or V SS 40 0.010 40 300 µA VDD = 15V, VIN = VDD or V SS 80 0.015 80 600 µA VDD = 5V 0.05 0 0.05 0.05 V VDD = 10V 0.05 0 0.05 0.05 V VDD = 15V 0.05 0 0.05 0.05 V LOW Level HIGH Level Output Voltage VIL Min Quiescent Device Output Voltage VOH −40°C Conditions VIL = 0V, VIH = VDD, |IO| < 1 µA VIL = 0V, VIH = VDD, |IO| < 1 µA VDD = 5V 4.95 4.95 5.0 4.95 VDD = 10V 9.95 9.95 10.0 9.95 V VDD = 15V 14.95 14.95 15.0 14.95 V V LOW Level |IO| < 1 µA Input Voltage VDD = 5V, VO = 0.5V or 4.5V 1.5 2.25 1.5 1.5 VDD = 10V, VO = 1.0V or 9.0V 3.0 4.50 3.0 3.0 V VDD = 15V, VO = 1.5V or 13.5V 4.0 6.75 4.0 4.0 V V HIGH Level |IO| < 1 µA Input Voltage VDD = 5V, VO = 0.5V or 4.5V 3.5 3.5 2.75 3.5 VDD = 10V, VO = 1.0V or 9.0V 7.0 7.0 5.50 7.0 V VDD = 15V, VO = 1.5V or 13.5V 11.0 11.0 8.25 11.0 V LOW Level Output VDD = 5V, VO = 0.4V 0.52 0.44 0.88 0.36 mA Current (Note 3) VDD = 10V, VO = 0.5V 1.3 1.1 2.25 0.90 mA VDD = 15V, VO = 1.5V 3.6 3.0 8.8 2.4 mA HIGH Level Output VDD = 5V, VO = 4.6V −0.52 −0.44 −0.88 −0.36 mA Current (Note 3) VDD = 10V, VO = 9.5V −1.3 −1.1 −2.25 −0.90 mA VDD = 15V, VO = 13.5V −3.6 −3.0 −8.8 −2.4 Input Current V mA VDD = 15V, VIN = 0V −0.3 −10−5 −0.3 −1.0 µA VDD = 15V, VIN = 15V 0.3 10−5 0.3 1.0 µA Note 3: IOH and IOL are tested one output at a time. 3 www.fairchildsemi.com CD4514BC• CD4515BC Absolute Maximum Ratings(Note 1) (Note 2) CD4514BC• CD4515BC AC Electrical Characteristics (Note 4) All types CL = 50 pF, TA = 25°C, tr = tf = 20 ns unless otherwise specified Symbol tTHL, tTLH tPLH, tPHL tPLH, tPHL Parameter Transition Times Propagation Delay Times Inhibit Propagation Delay Times tSU tWH Setup Time Strobe Pulse Width Typ Max Units VDD = 5V Conditions Min 100 200 ns VDD = 10V 50 100 ns VDD = 15V 40 80 ns VDD = 5V 550 1100 ns VDD = 10V 225 450 ns VDD = 15V 150 300 ns VDD = 5V 400 800 ns ns VDD = 10V 150 300 VDD = 15V 100 200 ns VDD = 5V 125 250 ns VDD = 10V 50 100 ns VDD = 15V 38 75 ns VDD = 5V 175 350 ns VDD = 10V 50 100 ns VDD = 15V 38 75 ns 150 CPD Power Dissipation Capacitance Per Package (Note 5) CIN Input Capacitance Any Input (Note 6) 5 pF 7.5 pF Note 4: AC Parameters are guaranteed by DC correlated testing. Note 5: CPD determines the no load AC power consumption of any CMOS device. For complete explanation, see Family Characteristics application note, AN-90. Note 6: Capacitance is guaranteed by periodic testing. www.fairchildsemi.com 4 CD4514BC• CD4515BC AC Test Circuit and Switching Time Waveforms FIGURE 1. 5 www.fairchildsemi.com CD4514BC• CD4515BC Applications times faster than the shift frequency of the input registers, the most significant bit (MSB) from each register could be selected for transfer to the data bus. Therefore, all of the most significant bits from all of the registers can be transferred to the data bus before the next most significant bit is presented for transfer by the input registers. Two CD4512 8-channel data selectors are used here with the CD4514B 4-bit latch/decoder to effect a complex data routing system. A total of 16 inputs from data registers are selected and transferred via a 3-STATE data bus to a data distributor for rearrangement and entry into 16 output registers. In this way sequential data can be re-routed or intermixed according to patterns determined by data select and distribution inputs. Information from the 3-STATE bus is redistributed by the CD4514B 4-bit latch/decoder. Using the 4-bit address, INA–IND, the information on the inhibit line can be transferred to the addressed output line to the desired output registers, A–P. This distribution of data bits to the output registers can be made in many complex patterns. For example, all of the most significant bits from the input registers can be routed into output register A, all of the next most significant bits into register B, etc. In this way horizontal, vertical, or other methods of data slicing can be implemented. Data is placed into the routing scheme via the 8 inputs on both CD4512 data selectors. One register is assigned to each input. The signals on A0, A1 and A2 choose 1-of-8 inputs for transfer out to the 3-STATE data bus. A fourth signal, labelled Dis, disables one of the CD4512 selectors, assuring transfer of data from only one register. In addition to a choice of input registers, 1–16, the rate of transfer of the sequential information can also be varied. That is, if the CD4512 were addressed at a rate that is 8 www.fairchildsemi.com 6 CD4514BC• CD4515BC Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Package Number M24B 7 www.fairchildsemi.com CD4514BC• CD4515BC 4-Bit Latched/4-to-16 Line Decoders Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.600” Wide Package Number N24A LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.