ETC CLC405AJE

CLC405
Low Cost, Low Power, 110MHz Op Amp with Disable
General Description
The CLC405 is a low cost, wideband (110MHz) op amp
featuring a TTL-compatible disable which quickly switches
off in 18ns and back on in 40ns. While disabled, the CLC405
has a very high input/output impedance and its total power
consumption drops to a mere 8mW. When enabled, the
CLC405 consumes only 35mW and can source or sink an
output current of 60mA. These features make the CLC405 a
versatile, high speed solution for demanding applications
that are sensitive to both power and cost.
Utilizing National’s proven architectures, this current
feedback amplifier surpasses the performance of alternative
solutions and sets new standards for low power at a low
price. This power conserving op amp achieves low distortion
with −72dBc and −70dBc for second and third harmonics
respectively. Many high source impedance applications will
benefit from the CLC405’s 6MΩ input impedance And finally,
designers will have a bipolar part with an exceptionally low
100nA non-inverting bias current.
With 0.1dB flatness to 50MHz and low differential gain and
phase errors, the CLC405 is an ideal part for professional
video processing and distribution. However, the 110MHz
−3dB bandwidth (AV = +2) coupled with a 350V/µs slew rate
also make the CLC405 a perfect choice in cost sensitive
applications such as video monitors, fax machines, copiers,
and CATV systems.
n Ultra fast enable/disable times
n High output current: 60mA
Applications
n
n
n
n
n
n
n
n
n
Desktop video systems
Multiplexers
Video distribution
Flash A/D driver
High speed switch/driver
High source impedance applications
Peak detector circuits
Professional video processing
High resolution monitors
Frequency Response (AV = +2V/V)
Features
n
n
n
n
n
Low cost
Very low input bias current:100nA
High input impedance: 6MΩ
110MHz −3dB bandwidth (Av =+2)
Low power: Icc =3.5mA
DS012703-1
Connection Diagram
DS012703-33
Pinout
DIP & SOIC
© 2001 National Semiconductor Corporation
DS012703
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CLC405 Low Cost, Low Power, 110MHz Op Amp with Disable
February 2001
CLC405
Typical Application
DS012703-3
Wideband Digitally Controlled Programmable Gain Amplifier
DS012703-2
Channel Switching
Ordering Information
Package
Temperature Range
Industrial
Part Number
Package Marking
8-pin plastic DIP
−40˚C to +85˚C
CLC405AJP
CLC405AJP
N08E
8-pin plastic SOIC
−40˚C to +85˚C
CLC405AJE
CLC405AJE
M08A
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2
NSC Drawing
Storage Temperature Range
Lead Temperature (soldering 10 sec)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Operating Ratings
± 7V
Supply Voltage (VCC)
IOUT
is short circuit protected to ground
Common Mode Input Voltage
Junction Temperature
−65˚C to +150˚C
+300˚C
Thermal Resistance
Package
MDIP
SOIC
± VCC
+150˚C
(θJC)
75˚C/W
130˚C/W
(θJA)
130˚C/W
150˚C/W
Electrical Characteristics
AV = +2, Rf = 348Ω: VCC = ± 5V, RL = 100Ω unless specified
Notes
Parameter
Conditions
Ambient Temperature
CLC405AJ
Typ
Min/Max
(Note 2)
Units
+25˚C
+25˚C
0 to
70˚C
−40 to
85˚C
110
75
50
45
Frequency Domain Response
−3dB Bandwidth
VOUT < 1.0VPP
VOUT < 5.0VPP
42
31
27
26
MHz
−3dB Bandwidth
AV = +1
VOUT < 0.5VPP (Rf = 2K)
135
–
–
–
MHz
± 0.1dB Bandwidth
VOUT < 1.0VPP
50
15
–
–
MHz
Gain Flatness
VOUT < 1.0VPP
dB
(Note 3)
MHz
Peaking
DC to 200MHz
0
0.6
0.8
1.0
Rolloff
< 30MHz
< 20MHz
0.05
0.3
0.4
.5
dB
0.3
0.6
0.7
0.7
deg
0.03
0.04
0.05
%
0.4
0.5
0.55
deg
Linear Phase Deviation
Differential Gain
(Note 4)
Differential Phase
(Note 4)
NTSC, RL = 150Ω
0.01
NTSC, RL = 150Ω
0.01
NTSC, RL =150Ω
0.25
NTSC, RL = 150Ω
0.08
%
deg
Time Domain Response
Rise and Fall Time
2V Step
5
7.5
8.2
8.4
ns
Settling Time to 0.05%
2V Step
18
27
36
39
ns
Overshoot
Slew Rate
2V Step
3
12
12
12
%
AV = +2
2V Step
350
260
225
215
V/µs
AV = −1
1V Step
650
–
–
–
V/µs
Distortion And Noise Response
(Note 5)
2nd Harmonic Distortion
2VPP, 1MHz/10MHz
−72/−52
−46
−45
−44
dBc
(Note 5)
3rd Harmonic Distortion
2VPP, 1MHz/10MHz
−70/−57
−50
−47
−46
dBc
Equivalent Input Noise
Non-Inverting Voltage
> 1MHz
5
6.3
6.6
6.7
nV/
Inverting Current
> 1MHz
12
15
16
17
pA/
Non-Inverting Current
> 1MHz
3
3.8
4
4.2
pA/
7
Static DC Performance
(Note 6)
Input Offset Voltage
Average Drift
(Note 6)
Input Bias Current
Non-Inverting
Average Drift
(Note 6)
Input Bias Current
1
5
30
50
100
900
3
Inverting
1
Average Drift
17
3
5
8
mV
50
µV/˚C
1600
2800
nA
8
11
nA/˚C
7
10
µA
40
45
nA/˚C
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CLC405
Absolute Maximum Ratings (Note 1)
CLC405
Electrical Characteristics
(Continued)
AV = +2, Rf = 348Ω: VCC = ± 5V, RL = 100Ω unless specified
Notes
Parameter
Conditions
Typ
Min/Max
(Note 2)
Units
Static DC Performance
(Note 6)
Power Supply Rejection Ratio
DC
52
47
46
45
Common Mode Rejection Ratio
DC
50
45
44
43
dB
Supply Current
RL = ∞
3.5
4.0
4.1
4.4
mA
RL = ∞
0.8
0.9
0.95
1
mA
40
55
58
58
ns
Turn Off Time
to > 50dB attn. @
10MHz
18
26
30
32
ns
Off Isolation
10MHz
59
55
55
55
dB
High Input Voltage
VIH
2
2
2
V
Low Input Voltage
VIL
0.8
0.8
0.8
V
3
2.4
1
MΩ
1
2
2
2
pF
± 2.2
1.8
1.7
1.5
V
(Note 6)
Disabled
dB
Switching DC Performance
Turn On Time
Miscellaneous Performance
Input Resistance
Non- Inverting
Input Resistance
Inverting
Input Capacitance
Non- Inverting
Common Mode Input Range
Output Voltage Range
Output Voltage Range
6
Ω
182
RL = 100Ω
RL = ∞
+3.5,−2.8 +3.1,−2.7 +2.9,−2.6 +2.4,−1.6
+4.0,−3.3 +3.9,−3.2 +3.8,−3.1 +3.7,−2.8
Output Current
Output Resistance, Closed Loop
V
V
40
40
38
20
mA
0.06
0.2
0.25
0.4
Ω
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.
Note 2: Max/min ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined
from tested parameters.
Note 3: At temps
< 0˚C, spec is guaranteed for RL 500Ω.
Note 4: An 825Ω=pull-down resistor is connected between VO and − VCC
Note 5: Guaranteed at 10MHz
Note 6: AJ-level: spec. is 100% tested at +25˚C.
Typical Performance Characteristics
(AV = +2, Rf = 348Ω: VCC = ± 5V, RL = 100Ω Unless
Specified).
Non-Inverting Frequency Response
Inverting Frequency Response
DS012703-4
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DS012703-5
4
(AV = +2, Rf = 348Ω: VCC = ± 5V, RL = 100Ω Unless
Specified). (Continued)
Frequency Response for Various RLS
Frequency Response vs. VOUT
DS012703-6
Frequency Response vs. Capacitive Load
DS012703-7
Gain Flatness & Linear Phase Deviation
DS012703-23
DS012703-8
Maximum Output Voltage vs. RL
Open Loop Transimpedance Gain, Z(s)
DS012703-9
DS012703-24
5
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CLC405
Typical Performance Characteristics
CLC405
Typical Performance Characteristics
(AV = +2, Rf = 348Ω: VCC = ± 5V, RL = 100Ω Unless
Specified). (Continued)
Equivalent Input Noise
2nd & 3rd Harmonic Distortion
DS012703-10
2nd Harmonic Distortion vs. POUT
DS012703-11
3rd Harmonic Distortion vs. POUT
DS012703-12
Output Resistance vs. Frequency
DS012703-13
Forward and Reverse Gain During Disable
DS012703-14
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DS012703-15
6
(AV = +2, Rf = 348Ω: VCC = ± 5V, RL = 100Ω Unless
Specified). (Continued)
Differential Gain and Phase
Small Signal Pulse Response
DS012703-31
DS012703-16
Large Signal Pulse Response
Settling Time vs. Capacitive Load
DS012703-32
DS012703-25
Short Term Settling Time
PSRR and CMRR
DS012703-26
DS012703-19
7
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CLC405
Typical Performance Characteristics
CLC405
Typical Performance Characteristics
(AV = +2, Rf = 348Ω: VCC = ± 5V, RL = 100Ω Unless
Specified). (Continued)
IBI, IBN, VIO vs. Temperature
DS012703-27
Application Division
Feedback Resistor
The feedback resistor, Rf, determines the loop gain and
frequency response for a current feedback amplifier. Unless
otherwise stated, the performance plots and data sheet
specify CLC405 operation with Rf of 348Ω at a gain of +2V/V.
Optimize frequency response for different gains by changing
Rf. Decrease to peak frequency response and extend
bandwidth. Increase Rf to roll off the frequency response and
decrease bandwidth. Use a 2kΩ Rf for unity gain, voltage
follower circuits.
Use application note OA-13 to optimize your Rf selection.
The equations in this note are a good starting point for
selecting Rf. The value for the inverting input impedance for
OA-13 is approximately 182Ω.
Enable/Disable Operation Using ± 5V Supplies
DS012703-20
FIGURE 1. Enable/Disable Operation for Single or
Unbalanced Supply Operation
The CLC405 has a TTL & CMOS logic compatible disable
function. Apply a logic low (i.e. < 0.8V) to pin 8, and the
CLC405 is guaranteed disabled across its temperature
range. Apply a logic high to pin 8, (i.e. > 2.0V) and the
CLC405 is guaranteed enabled. Voltage, not current, at pin 8
determines the enable/disable state of the CLC405.
Disable the CLC405 and its inputs and output become high
impedances. While, disabled, the CLC405’s quiescent
power drops to 8mW.
Use the CLC405’s disable to create analog switches or
multiplexers. Implement a single analog switch with one
CLC405 positioned between an input and output. Create an
analog multiplexer with several CLC405s. Tie the outputs
together and put a different signal on each CLC405 input.
Operate the CLC405 without connecting pin 8. An internal
20kΩ pull-up resistor guarantees the CLC405 is enabled
when pin 8 is floating.
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Figure 1 illustrates the internal enable/disable operation of
the CLC405. When pin 8 is left floating or is tied to +VCC, Q1
is on and pulls tail current through the CLC405 bias circuitry.
When pin 8 is less than 0.8V above the supply midpoint, Q1
stops tail current from flowing in the CLC405 circuitry. The
CLC405 is now disabled.
Disable Limitations
The feedback resistor, Rf, limits off isolation in inverting gain
configurations. Do not apply voltages greater than +VCC or
less than -VEE to pin 8 or any other pin.
8
Video Performance vs. IEX
Improve the video performance of the CLC405 by drawing
extra current from the amplifier output stage. Using a single
external resistor as shown in Figure 3, you can adjust the
differential phase. Video performance vs. IEX is illustrated
below in Graph 1. This graph represents positive video
performance with negative synchronization pulses.
(Continued)
Input - Bias Current, Impedance,
Termination Considerations
and
Source
The CLC405 has:
• a 6MΩ non-inverting input impedance.
• a 100nA non-inverting input bias current.
If a large source impedance application is considered,
remove all parasitic capacitance around the non-inverting
input source traces. Parasitic capacitances near the input
and source act as a low-pass filter and reduce bandwidth
Current feedback op amps have uncorrelated input bias
currents. These uncorrelated bias currents prevent source
impedance matching on each input from canceling offsets.
Refer to application note OA-07 of the data book to find
specific circuits to correct DC offsets.
Layout Considerations
Whenever questions about layout arise, USE THE
EVALUATION BOARD AS A TEMPLATE.
Use the CLC730013 and CLC730027 evaluation boards for
the DIP and SOIC respectively. These board layouts were
optimized to produce the typical performance of the CLC405
shown in the data sheet. To reduce parasitic capacitances,
the ground plane was removed near pins 2,3, and 6. To
reduce series inductance, trace lengths of components and
nodes were minimized.
Parasitics on traces degrade performance. Minimize
coupling from traces to both power and ground planes. Use
low inductive resistors for leaded components.
Do not use dip sockets for the CLC405 DIP amplifiers. These
sockets can peak the frequency domain response or create
overshoot in the time domain response. Use flush-mount
socket pins when socketing is necessary. The 730013 circuit
board device holes are sized for Cambion P/N 450-2598
socket pins or their functional equivalent.
Insert the back matching resistor (ROUT) shown in Figure 2
when driving coaxial cable or a capacitive load. Use the plot
in the typical performance section labeled “Settling Time vs.
Capacitive Load” to determine the optimum resistor value for
ROUT for different capacitive loads. This optimal resistance
improves settling time for pulse-type applications and
increases stability.
DS012703-28
Graph 1. Differential Gain & Phase vs. IEX
DS012703-29
FIGURE 3.
The value for Rpd in Figure 3 is determined by: at ± 5V
supplies.
at ± 5V supplies.
Wideband Digital PGA
As shown on the front page, the CLC405 is easily configured
as a digitally controlled programmable gain amplifier. Make a
PGA by configuring several amplifiers at required gains.
Keep Rf near 348Ω and change Rg for each different gain.
Use a TTL decoder that has enough outputs to control the
selection of different gains and the buffer stage. Connect the
buffer stage like the buffer on the front page. The buffer
isolates each gain stage from the load and can produce a
gain of zero for a gain selection of zero. Use of an inverter
(7404) on the buffer disable pin to keep the buffer
operational at all gains except zero. Or float the buffer
disable pin for a continuous enable state.
DS012703-18
FIGURE 2.
Use power-supply bypassing capacitors when operating this
amplifier. Choose quality 0.1µF ceramics for C1 and C2.
Choose quality 6.8µF tantalum capacitors for C3 and C4.
Place 0.1µF capacitors within 0.1 inches from the power
pins. Place the 6.8µF capacitors within 3/4 inches from the
power pins.
9
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CLC405
Application Division
CLC405
Application Division
(Continued)
Amplitude Equalization
Sending signals over coaxial cable greater than 50 meters in
length will attenuate high frequency signal components.
Equalizers restore the attenuated components of this signal.
The circuit in Figure 3, is an op amp equalizer. The RC
networks peak the response of the CLC405 at higher
frequencies. This peaking restores cable-attenuated
frequencies. Graph 2 shows how the equalizer actually
restores a digital word through 150 meters of coaxial cable.
DS012703-30
Graph 2. Digital Word Amplitude Equalization
The values used to produce Graph 2 are:
Rg = 348Ω
R1 = 450Ω
C1 = 470pF
R2 = 90Ω
C2 = 70pF
Amplitude Equalizer
Place the first zero (fz1) at some low frequency (540 khz for
Graph 2). R1 & C1 produce a pole (fp1 @ 750khz) that
cancels fz1. Place a second zero at a higher frequency (fz2 @
12Mhz). R2 & C2 provide a canceling pole (of fp2 = 25Mhz).
Graph 3 shows the closed loop response of the op amp
equalizer with equations for the poles, zeros, and gains.
DS012703-21
FIGURE 4.
DS012703-22
Graph 3. Closed Loop Equalizer Frequency Response
Note: For very high frequency equalization, us a higher
bandwidth part (i.e., CLC44X).
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10
CLC405
Physical Dimensions
inches (millimeters) unless otherwise noted
NS Product Number M08A
NS Product Number N08E
11
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CLC405 Low Cost, Low Power, 110MHz Op Amp with Disable
Notes
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