NSC PC8374T

August 2004
Revision 1.1
PC8374T
SafeKeeper Desktop TrustedI/O
General Description
Outstanding Features
The National Semiconductor PC8374T Advanced I/O product is a member of the PC837x SuperI/O family. All PC837x
devices are highly integrated and are pin and software compatible, thus providing drop-in interchangeability and enabling a variety of assembly options using only a single
motherboard and BIOS.
■
TCG 1.1b based Trusted Platform Module (TPM)
— Integrated non-volatile secure storage
— Hardware and software protection schemes
— Tamper resistance schemes
— Pin compatible to integrated TPM 1.2 device
PC8374T integration allows for a reduced system board size
and saves on total system cost.
■
The PC8374T includes legacy SuperI/O functions, Trusted
Platform Module (TPM), system glue functions, health monitoring and control, commonly used functions such as GPIO,
and ACPI-compliant Power Management support.
Legacy modules: Parallel Port, Floppy Disk Controller
(FDC), two Serial Ports, Serial InfraRed Port and a Keyboard and Mouse Controller (KBC)
■
Glue functions to complement the South Bridge functionality
■
System health support, including SensorPath sensor
interface, and fan monitor and control
■
VSB3-powered Power Management with 19 wake-up
sources
■
Controls three LED indicators
■
16 GPIO pins with a variety of wake-up options
■
I/O-mapped and memory-mapped registers
■
128-pin PQFP package
The Trusted Platform Module provides a solution for PC security, based on the TCG standard. The complete security
solution includes hardware, software, and firmware.
The PC8374T integrates miscellaneous analog and digital
system glue functions to reduce the number of discrete
components required. The host communicates with the
functions integrated in the PC8374T through an LPC Bus
Interface.
The PC8374T supports both I/O and memory mapping of
module registers and enables building legacy-free systems.
PC8374T System Block Diagram
South Bridge
Power Management
LPC Bus
PC8374T
System
BIOS
TPM
VBAT
Serial Interface x 2
Parallel Port Interface
Floppy Drive Interface
PS/2 Interfaces
KBC Ports
Infrared Interface
GPIO
SuperI/O
SMBus I/F
Wake-Up
Events
Physical
Presence
SensorPathTM I/F
LMxx Sensors
LEDs
Tacho
PWM
Reset
Logic
Power
Supply
Drv
Drv
Drv
National Semiconductor and TRI-STATE are registered trademarks of National Semiconductor Corporation.
SensorPath and SafeKeeper are trademarks of National Semiconductor Corporation.
All other brand or product names are trademarks or registered trademarks of their respective holders.
© 2004 National Semiconductor Corporation
www.national.com
PC8374T SafeKeeper  Desktop TrustedI/O
PRODUCT BRIEF
PC8374T
Features
■
Trusted Platform Module (TPM)
■
TCG 1.1b compliant
■
Processing Unit
— 16-bit embedded RISC processor core
■
Internal Memory
— On-chip Non-Volatile memory for secure storage
— On-chip data RAM
■
■
■
TPM Firmware
— VSB3 RAM-based storage for loadable keys
■
Tamper Resistance
— Clock Jitter protection
❏ Protection on reference clock
❏
■
Each pin individually configured as input or output
■
Programmable features for each output pin:
■
Programmable option for internal pull-up resistor on
each input pin (some with internal pull-down resistor option)
■
Lock option for the configuration and data of each output
pin
■
15 GPIO pins generate IRQ/SIOPME/SMI for wake-up
events; each GPIO has separate:
— Enable control of event status routing to IRQ
— Enable control of event status routing to SIOPME
— Polarity and edge/level selection
❏ Programmable debouncing
Protection of security functions from LPC clock
jitter
Glue Functions
■
Generates the power-related signals:
— Main Power good
— Power distribution control (for switching between
Main and Standby regulators)
— Resume reset (Master Reset) according to the 5V
standby supply status
— Main power supply turn on (PS_ON)
■
Voltage translation between 2.5V or 3.3V levels (DDC) and
5V levels (VGA) for the SMBus serial clock and data signals
■
Isolation circuitry for the SMBus serial clock and data signals
■
Buffers PCI_RESET to generate three reset output signals
■
Generates “highest active supply” reference voltage
— Based on 3.3V and 5V Main supplies
— Based on 3.3V and 5V Standby supplies
■
High-current LED driver control for Hard Disk Drive
activity indication
■
Software selectable alternative functionality, through pin
multiplexing
Glitch and brownout detector
SensorPath interface to sensors optimizes digital/analog
partitioning
— Simplifies board design and routing
— Supports distributed sensors and centralized control
— Health monitoring is self-contained and requires
minimal host attention
— Faster boot time
— Off loads SMBus, and enables ASF compliance
Fan Monitor and Control
— Three PWM-based fan controls
— Four 16-bit resolution tachometer inputs
— Software or local temperature feedback control
www.national.com
LM96010
All 16 GPIO pins powered by VSB3
System Health Support
■
❏
■
— Secure storage contents protection
— Permanent disable of all TPM test mechanisms
when locked
■
LM96012
— Drive type (open-drain, push-pull or TRI-STATE)
— TRI-STATE on detection of falling VDD3 for
VSB3-powered pins driving VDD-supplied devices
— Power analysis resistance
— Low and High Frequency monitor
— Voltage attack detector
❏ Low Voltage
❏
LM96011 and LM95010
❏
General-Purpose Modules
Secured General-Purpose I/O (GPIO)
— Internal processor controlled
— Three GPIO pins, one used for Physical Presence
— I/O pins individually configured as input or output
— Configurable internal pull-up resistors
— Owner authorization control
Power Management Controller (PMC); power modes,
switched by software or hardware
❏
— Simultaneous read support via LPC interface and SMBus
Host Interface
— Using LPC Bus
— Command/Data/Status standard interface
■
Heceta6-compatible register set accessible via the LPC
interface and SMBus
— Supports the following combinations of LMxx devices:
❏ LM96011
2
Revision 1.1
Bus Interface
■
LPC Bus Interface
— Based on Intel’s LPC Interface Specification Revision 1.1, August 2002
— I/O, Memory and 8-bit Firmware Memory read and
write cycles, Firmware Memory writes may insert
wait cycles
— Up to four 8-bit DMA channels
— Serial IRQ (SERIRQ)
— Supports SuperI/O register memory and I/O mapping
■
Configuration Control
— PnP Configuration Register structure
— Compliant with PC01 Specification Revision 1.0,
1999-2000
— Base Address strap (BADDR) to setup the address
of the Index-Data register pair (defaults to 2Eh/2Fh)
❏ TPM Index-Data register pair Base Address set
by the TPM (defaults to 7Eh/7Fh) or via SuperI/O
Configuration registers
■
Floppy Disk Controller (FDC)
— Software compatible with the PC8477 (the PC8477
contains a superset of the FDC functions in the
µDP8473, NEC µPD765A/B and N82077 devices)
— Error-free handling of data overrun and underrun
— Programmable write protect
— Supports FM and MFM modes
— Supports Enhanced mode command for three-mode
Floppy Disk Drive (FDD)
— Perpendicular recording drive support for 2.88 MBytes
— Burst (16-byte FIFO) and Non-Burst modes
— Full support for IBM Tape Drive Register (TDR)
implementation of AT and PS/2 drive types
— High-performance digital separator
— Supports fast tape drives (2 Mbps) and standard
tape drives (1 Mbps, 500 Kbps and 250 Kbps)
■
Keyboard and Mouse Controller (KBC)
— 8-bit microcontroller, software compatible with
8042AH and PC87911
— Standard interface (60h, 64h, IRQ1 and IRQ12)
— Supports two external swapable PS/2 interfaces for
keyboard and mouse
— Programmable, dedicated quasi-bidirectional I/O
lines (GA20/P21, KBRST/P20)
— Flexible resource allocation for all logical devices:
❏ Relocatable base address
❏
15 IRQ routing options to serial IRQ
❏
Up to four optional 8-bit DMA channels
— Configurable feature sets:
❏ VSB3-powered pin multiplexing
Power Management
Legacy Modules
■
Serial Ports 1 and 2
— Software compatible with the NS16550A and NS16450
— Support shadow register for write-only bit monitoring
— Data rates up to 1.5 Mbaud
■
Serial Infrared Port (SIR)
— Software compatible with the 16550A and the 16450
— Shadow register support for write-only bit monitoring
— HP-SIR
— ASK-IR option of SHARP-IR
— DASK-IR option of SHARP-IR
— Consumer Remote Control supports RC-5, RC-6,
NEC, RCA and RECS 80
■
Supports ACPI Specification Revision 2.0b, July 27, 2000
■
System Wake-Up Control (SWC)
— Optional routing of events to generate SCI
(SIOPME) on detection of:
❏ Keyboard or Mouse events
❏
Ring Indication RI on each of the two serial ports
❏
General-Purpose Input Events from 15 GPIO pins
❏
IRQs of the Keyboard and Mouse Controller
❏
IRQs of the other internal modules
— Optional routing of the SCI (SIOPME) to generate
IRQ (SERIRQ)
— Implements the GPE1_BLK of the ACPI General Purpose (Generic) Register blocks with “child” events
— VSB3-powered event detection and event-logic configuration
IEEE 1284-compliant Parallel Port
— ECP, with Level 2 (14 mA sink and source output
buffers)
— Software or hardware control
— Enhanced Parallel Port (EPP) compatible with EPP
1.7 and EPP 1.9
— Supports EPP as mode 4 of the Extended Control
Register (ECR)
— Selection of internal pull-up or pull-down resistor for
Paper End (PE) pin
— Supports a demand DMA mode mechanism and a
DMA fairness mechanism for improved bus utilization
— Protection circuit that prevents damage to the
parallel port when a printer connected to it is powered up or is operated at high voltages (in both
cases, even if the PC8374T is in power-down state)
Revision 1.1
■
■
Enhanced Power Management (PM), including:
— Special configuration registers for power down
— Low-leakage pins
— Low-power CMOS technology
— Ability to disable all modules
— High-current LED drivers control (two LEDs) for
power status indication with:
❏ Standard blinking, controlled by software
❏
Advanced blinking, controlled by power supply
status, sleep state or software
❏
Special blinking, controlled by power supply
status, sleep state and software bit
— VBAT-powered indication of the Main power supply
state before an AC power failure
3
www.national.com
PC8374T
Features (Continued)
PC8374T
Features (Continued)
■
Clocking, Supply, and Package Information
■
Clocks
— On-chip Low-Frequency Clock Generator:
❏ Generates 32.768 KHz internal clock
❏
— On-chip SuperI/O Clock Generator:
❏ Generates 48 MHz
❏
■
Selected at power-up by strap input (TEST)
— TRI-STATE device pins, selected at power-up by
strap input (TRIS)
VDD3 powered
■
Protection
— All device pins are 5V tolerant and back-drive protected (except LPC bus pins)
— High ESD protection of all the device pins
— Pin multiplexing selection lock
— Configuration register lock
Power Supply
— 3.3V supply operation
— Separate pin pairs for main (VDD3) and standby
(VSB3) power supplies
— Backup battery input (VBAT) for SWC indications
— Low standby power consumption
— Very low power consumption from backup battery
(less than 1 µA)
■
www.national.com
Testability
— XOR tree structure
❏ Includes all the device pins (except the supply
and the analog pins)
4
Package
— 128-pin PQFP
Revision 1.1
PC8374T
1.0
Signal/Pin Connection and Description
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
IDE_RSTDRV
PCI_RESET
LAD0
LAD1
VDD3
LAD2
VSS
LAD3
LFRAME
PCI_CLK
LDRQ
SER_IRQ
SMI
STB_WRITE
AFD_DSTRB
VDD3
INIT
SLIN_ASTRB
VSS
ERR
PD0
PD1
PD2
PD3
PD4
PD5
1.1 CONNECTION DIAGRAM
VSB5
REF5V_STBY
PCIRST_OUT
PCIRST_OUT2/GPIOE12
GPIOE13
VSB3
BKFD_CUT
VSS
LATCHED_BF_CUT
GPIOE17
PS_ON
PWRGD_PS
CPU_PRESENT
PWRGD_3V
SLP_S3
SLP_S5
SMB1_SCL
HMSCL/SMB2_SCL
SMB1_SDA
HMSDA/SMB2_SDA
IOPA1/CLOCKI32/GPIO15
38
37
36
35
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
34
33
32
PC8374T
128-Pin PQFP
(Top View)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
PD6
PD7
ACK
BUSY_WAIT
PE
SLCT
RI1
VDD3
DTR_BOUT1/XOR_OUT/BADDR
VSS
CTS1
SOUT1/TEST
RTS1/TRIS
SIN1
DSR1
DCD1
DENSEL
DRATE0
INDEX
MTR0
DR0
DIR
STEP
WDATA
WGATE
TRK0
WP
RDATA
HDSEL
DSKCHG
VSS
KBRST
VDD3
GA20
KBDAT
KBCLK
MDAT
MCLK
GPIOE00/SWD
GPIOE01/FANTACH3
GPIOE02/FANTACH4
GPIOE03/FANPWM1
VSB3
GPIOE04/FANPWM2
GPIOE05/FANPWM3
VSS
GPIOE06/FANTACH1
GPIOE07/FANTACH2
CC_DDCSCL/GPIOE13
5V_DDCSCL/GPIOE11
CC_DDCSDA/GPIOE12
5V_DDCSDA/GPIOE10
GPO11/VsbStrap1/
GPIOE00/RI2/IRTX
GPIOE01/SIN2/RI2
GPIOE02/SOUT2/IRRX
GPIOE03/DSR2/SIN2
GPO12/RTS2/SOUT2/VddStrap1
TPM_PP/IOPA6
GPIOE04/CTS2/DSR2
GPO13/DTR_BOUTPC8374T2/RTS2/Vdd
GPIOE05/DCD2/CTS2
GPIOE06/IRRX/DTR_BOUT2
GPIOE07/IRTX/DCD2
RSMRST
VSB3
GRN_LED
YLW_LED
VSS
VCORF
VBAT
SIOPME
GPIOE16
IOPA0/GPIOE14
VCORF2
65
66
67
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
CLOCKI14
HD_LED
PRIMARY_HD
SECONDARY_HD
SCSI
REF5V
Plastic Quad Flatpack (PQFP), JEDEC
Order Number PC8374T0xxx/VLA
Package Number VLA128A
Revision 1.1
5
Note: ’xxx’ stands for the following Keyboard
Controller Microcodes:
IBW - for AMI
IBU - for Intel
IBM - for IBM
ICG - for Dell
ICK - for Phoenix
www.national.com
PC8374T
1.0 Signal/Pin Connection and Description
(Continued)
Pin
Pin Name
Pin
Pin Name
Pin
Pin Name
Pin
Pin Name
1
MCLK
33
SLCT
65
CLOCKI14
97
VCORF
2
MDAT
34
PE
66
HD_LED
98
VBAT
3
KBCLK
35
BUSY_WAIT
67
PRIMARY_HD
99
SIOPME
4
KBDAT
36
ACK
68
SECONDARY_HD
100
GPIOE16
5
GA20
37
PD7
69
SCSI
101
IOPA0/GPIOE14
6
VDD3
38
PD6
70
REF5V
102
VCORF2
7
KBRST
39
PD5
71
VSB5
103
GPIOE00/SWD
8
VSS
40
PD4
72
REF5V_STBY
104
GPIOE01/FANTACH3
9
DSKCHG
41
PD3
73
PCIRST_OUT
105
FANTACH4/GPIOE02
10
HDSEL
42
PD2
74
PCIRST_OUT2/GPIOE12
106
GPIOE03/FANPWM1
11
RDATA
43
PD1
75
GPIOE13
107
VSB3
12
WP
44
PD0
76
VSB3
108
GPIOE04/FANPWM2
13
TRK0
45
ERR
77
BKFD_CUT
109
GPIOE05/FANPWM3
14
WGATE
46
VSS
78
VSS
110
VSS
15
WDATA
47
SLIN_ASTRB
79
LATCHED_BF_CUT
111
GPIOE06/FANTACH1
16
STEP
48
INIT
80
GPIOE17
112
GPIOE07/FANTACH2
17
DIR
49
VDD3
81
PS_ON
113
CC_DDCSCL/GPIOE13
18
DR0
50
AFD_DSTRB
82
PWRGD_PS
114
5V_DDCSCL/GPIOE11
19
MTR0
51
STB_WRITE
83
CPU_PRESENT
115
CC_DDCSDA/GPIOE12
20
INDEX
52
SMI
84
PWRGD_3V
116
5V_DDCSDA/GPIOE10
21
DRATE0
53
SER_IRQ
85
SLP_S3
117
GPO11/VsbStrap1
22
DENSEL
54
LDRQ
86
SLP_S5
118
GPIOE00/RI2/IRTX
23
DCD1
55
PCI_CLK
87
SMB1_SCL
119
GPIOE01/SIN2/RI2
24
DSR1
56
LFRAME
88
SMB2_SCL/HMSCL
120
GPIOE02/SOUT2/IRRX
25
SIN1
57
LAD3
89
SMB1_SDA
121
GPIOE03/DSR2/SIN2
26
RTS1/TRIS
58
VSS
90
SMB2_SDA/HMSDA
122
GPO12/RTS2/SOUT2/
VddStrap1
27
SOUT1/TEST
59
LAD2
91
IOPA1/CLOCKI32/GPIO15
123
TPM_PP/IOPA6
28
CTS1
60
VDD3
92
RSMRST
124
GPIOE04/CTS2/DSR2
29
VSS
61
LAD1
93
VSB3
125
GPO13/DTR_BOUT2/
RTS2/VddStrap2
30
DTR_BOUT1/BADDR/
XOR_OUT
62
LAD0
94
GRN_LED
126
GPIOE05/DCD2/CTS2
31
VDD3
63
PCI_RESET
95
YLW_LED
127
GPIOE06/IRRX/
DTR_BOUT2
32
RI1
64
IDE_RSTDRV
96
VSS
128
GPIOE07/IRTX/DCD2
www.national.com
6
Revision 1.1
PC8374T
1.0 Signal/Pin Connection and Description
(Continued)
1.2 BUFFER TYPES AND SIGNAL/PIN DIRECTORY
The signal DC characteristics of the pins described in Section 1.4 on page 10 are denoted by buffer type symbols, which are
defined in Table 1 and described in further detail in Section 2.2 on page 22.
Table 1. Buffer Types
Symbol
Revision 1.1
Description
INT
Input, TTL compatible
INTS
Input, TTL compatible, with 250 mV Schmitt Trigger
INTS2
Input, TTL compatible, with 200 mV Schmitt Trigger
INTS4
Input, TTL compatible, with 400 mV Schmitt Trigger
INPCI
Input, PCI 3.3V compatible
INSM
Input, SMBus compatible
INULR
Input, power, resistor protected (not characterized)
AI
Input, analog (0-5.5V tolerant)
Op/n
Output, TTL/CMOS compatible, push-pull buffer capable of sourcing p mA
and sinking n mA
ODn
Output, TTL/CMOS compatible, open-drain buffer capable of sinking n mA
OPCI
Output, PCI 3.3V compatible,
AO
Output, analog (0-5.5V tolerant)
SWSM
Input/Output switch, SMBus compatible
PWR
Power pin
GND
Ground pin
7
www.national.com
www.national.com
8
Revision 1.1
GPIOE13
GPIO15
75
91
GPIO
GPIO
Glue
117 GPO11
GPIO
GPIOE10
GPIOE11
114 5V_DDCSCL
116 5V_DDCSDA
GPIOE13
113 CC_DDCSCL
GPIOE12
FANTACH2
112 GPIOE07
115 CC_DDCSDA
FANTACH1
111 GPIOE06
Glue
FANPWM3
FANPWM2
108 GPIOE04
109 GPIOE05
FANPWM1
106 GPIOE03
GPIO
FANTACH4
FANTACH3
GPIOE00
IOPA0
CLOCKI32
GPIOE12
XOR_OUT
Alternate
Signal
105 GPIOE02
104 GPIOE01
HM
PCIRST_OUT2
74
103 SWD
DTR_BOUT1
30
GPIO
SOUT1
27
Serial
Port 1
Function
Block
101 GPIOE14
RTS1
Default
Signal
26
Pin
GPIO
HM
GPIO
TPM
TPM
GPIO
Config
Function
Block
IOPA1
Alternate
Signal
TPM
Function
Block
Configuration Select
SIOCF2.GPIO03EN
SIOCF2.TACH2EN
SIOCF2.TACH1EN
SIOCF3.PWM3EN
SIOCF3.PWM2EN
SIOCF3.PWM1EN
SIOCF2.TACH4EN
SIOCF2.TACH3EN
SIOCF4.nSWD
TPM Firmware Controlled
TPM Firmware Controlled
SIOCF4.nPCIRSTO2
TEST (strap)
Table 2. Pin Multiplexing Configuration
VsbStrap11
GPIOE10
GPIOE12
GPIOE11
GPIOE13
GPIOE07
GPIOE06
GPIOE05
GPIOE04
GPIOE03
GPIOE02
GPIOE01
GPIOE00
GPIOE14
GPIOE13
GPIOE12
BADDR
TEST
TRIS
Strap or
Wake-Up
Strap
SWC
SWC
SWC
Config
(Straps)
Function
Block
Table 2 shows only multiplexed pins, their associated functional blocks and the configuration bits for the selection of the multiplexed options used in the PC8374T.
1.3 PIN MULTIPLEXING
PC8374T
9
IRTX
IOPA6
128 GPIOE07
123 TPM_PP
1. VSB strap input. Reserved for National use.
2. VDD strap input. Reserved for National use.
IRRX
127 GPIOE06
TPM
DCD2
DTR_BOUT2
125 GPO13
126 GPIOE05
CTS2
124 GPIOE04
RTS2
DSR2
121 GPIOE03
GPIO
SOUT2
120 GPIOE02
122 GPO12
SIN2
Alternate
Signal
119 GPIOE01
Function
Block
RI2
Default
Signal
118 GPIOE00
Pin
TPM
InfraRed
Serial
Port 2
Function
Block
DCD2
DTR_BOUT
2
CTS2
RTS2
DSR2
SOUT2
SIN2
IRRX
RI2
IRTX
Alternate
Signal
Serial
Port 2
TPM Firmware controlled
SIOCF3.373COMP AND
SIOCF3.SP2EN AND
SIOCF3.IREN
SIOCF3.373COMP AND
SIOCF3.SP2EN
SIOCF3.373COMP AND
SIOCF3.SP2EN AND
SIOCF3.IREN
SIOCF3.373COMP AND
SIOCF3.SP2EN
Serial
Port 2
InfraRed
SIOCF3.373COMP AND
SIOCF3.SP2EN AND
SIOCF3.IREN
Configuration Select
InfraRed
Function
Block
Table 2. Pin Multiplexing Configuration (Continued)
VddStrap2
VddStrap12
RI2
RI2
Strap or
Wake-Up
Config
(Straps)
Config
(Straps)
SWC
Function
Block
PC8374T
Revision 1.1
www.national.com
PC8374T
1.0 Signal/Pin Connection and Description
(Continued)
1.4 DETAILED SIGNAL/PIN DESCRIPTIONS
This section describes all signals of the PC8374T device. The signals are organized by functional group.
1.4.1
LPC Interface
Signal
Pin(s) I/O Buffer Type Power Well
LAD3-0
57, 59, I/O
61-62
PCI_CLK
55
LFRAME
Description
INPCI/OPCI
VDD3
LPC Address-Data. Multiplexed command, address bi-directional
data and cycle status.
I
INPCI
VDD3
LPC Clock. PCI clock used for the LPC bus (up to 33 MHz).
56
I
INPCI
VDD3
LPC Frame. Low pulse indicates the beginning of a new LPC cycle
or termination of a broken cycle.
LDRQ
54
O
OPCI
VDD3
LPC DMA Request. Encoded DMA request for LPC interface.
PCI_RESET
63
I
INPCI
VDD3
LPC Reset. PCI system reset used for the LPC bus (Hardware Reset).
SER_IRQ
53
I/O
INPCI/OPCI
VDD3
Serial IRQ. The interrupt requests are serialized over a single pin,
where each IRQ level is delivered during a designated time slot.
SMI
52
O
OD6
VDD3
System Management Interrupt. Active (low) level indicates that
an SMI occurred. External pull-up resistor to VDD3 is required.
1.4.2
Serial Port 1 and Serial Port 2 (UART1 and UART2)
Signal
Pin(s) I/O Buffer Type Power Well
CTS1
28
I
INTS
VDD3
CTS2
124 or
126
I
INTS
VDD3
DCD1
23
I
INTS
VDD3
DCD2
126 or
128
I
INTS
VDD3
DSR1
24
I
INTS
VDD3
DSR2
121 or
124
I
INTS
VDD3
DTR_BOUT1 30
O
O4/8
VDD3
DTR_BOUT2 125 or
127
O
O4/8
VDD3
RI1
32
I
INTS
VDD3
RI2
118 or
119
I
INTS
VDD3
RTS1
26
O
O4/8
VDD3
RTS2
122 or
125
O
O4/8
VDD3
SIN1
25
I
INTS
VDD3
SIN2
119 or
121
I
INTS
VDD3
www.national.com
Description
Clear to Send. When low, indicates that the modem or other data
transfer device is ready to exchange data.
Data Carrier Detected. When low, indicates that the modem or
other data transfer device has detected the data carrier.
Data Set Ready. When low, indicates that the data transfer
device, e.g., modem, is ready to establish a communications link.
Data Terminal Ready. When low, indicates to the modem or
other data transfer device that the corresponding UART is ready
to establish a communications link. After a system reset, these
pins provide the DTR function and set these signals to inactive
high.
Baud Output. Provides the associated serial channel baud rate
generator output signal if test mode is selected, i.e., bit 7 of
EXCR1 register is set.
Ring Indicator. When low, indicates that a telephone ring signal
was received by the modem. These pins are monitored during
VDD power-off for wake-up event detection.
Request to Send. When low, indicates to the modem or other
data transfer device that the corresponding UART device is ready
to exchange data. A system reset sets these signals to inactive
high.
Serial Input. Receives composite serial data from the
communications link (peripheral device, modem or other data
transfer device).
10
Revision 1.1
Signal
27
O
O4/8
VDD3
SOUT2
120 or
122
O
O4/8
VDD3
1.4.3
(Continued)
Pin(s) I/O Buffer Type Power Well
SOUT1
Description
Serial Output. Sends composite serial data to the
communications link (peripheral device, modem or other data
transfer device). These signals are set active high after a system
reset.
InfraRed Port
Signal
Pin(s) I/O Buffer Type Power Well
Description
IRRX
127 or
120
I
INTS
VDD3
InfraRed Receive. InfraRed serial input data.
IRTX
128 or
118
O
O6/12
VDD3
InfraRed Transmit. InfraRed serial output data.
1.4.4
PC8374T
1.0 Signal/Pin Connection and Description
Parallel Port
Signal
Pin(s)
I/O Buffer Type Power Well
Description
36
I
INT
VDD3
Acknowledge. Pulsed low by the printer to indicate that it has
received data from the parallel port.
AFD_DSTRB 50
O
OD14, O14/14
VDD3
AFD - Automatic Feed. When low, instructs the printer to
automatically feed a line after printing each line. This pin is in
TRI-STATE after a 0 is loaded into the corresponding control
register bit. An external 4.7 KΩ pull-up resistor must be
connected to this pin.
DSTRB - Data Strobe (EPP). Active low; used in EPP mode
to denote a data cycle. When the cycle is aborted, DSTRB
becomes inactive (high).
BUSY_WAIT 35
I
INT
VDD3
Busy. Set high by the printer when it cannot accept another
character.
Wait. In EPP mode, the parallel port device uses this active
low signal to extend its access cycle.
ERR
45
I
INT
VDD3
Error. Set active low by the printer when it detects an error.
INIT
48
O
OD14, O14/14
VDD3
Initialize. When low, initializes the printer. This signal is in
TRI-STATE after a 1 is loaded into the corresponding control
register bit. An external 4.7 KΩ pull-up resistor must be
connected to this pin.
PD7-0
37-44
I/O
INT/O14/14
VDD3
Parallel Port Data. Transfers data to and from the peripheral
data bus and the appropriate parallel port data register. These
signals have a high current drive capability.
PE
34
I
INT
VDD3
Paper End. Set high by the printer when it is out of paper.
This pin has an internal weak pull-up or pull-down resistor.
SLCT
33
I
INT
VDD3
Select. Set active high by the printer when the printer is
selected.
SLIN_ASTRB 47
O
OD14, O14/14
VDD3
SLIN - Select Input. When low, selects the printer. This signal
is in TRI-STATE after a 0 is loaded into the corresponding
control register bit. An external 4.7 KΩ pull-up resistor must be
connected to this pin.
ASTRB - Address Strobe (EPP). Active low, used in EPP
mode to denote an address cycle. When the cycle is aborted,
ASTRB becomes inactive (high).
ACK
Revision 1.1
11
www.national.com
PC8374T
1.0 Signal/Pin Connection and Description
Signal
Pin(s)
I/O Buffer Type Power Well
STB_WRITE 51
1.4.5
(Continued)
O
OD14, O14/14
VDD3
Description
STB - Data Strobe. When low, Indicates to the printer that
valid data is available at the printer port. This signal is in TRISTATE after a 0 is loaded into the corresponding control
register bit. An external 4.7 KΩ pull-up resistor must be
connected to this pin.
WRITE - Write Strobe. Active low, used in EPP mode to
denote an address or data write cycle. When the cycle is
aborted, WRITE becomes inactive (high).
Floppy Disk Controller (FDC)
Signal
Pin(s)
I/O Buffer Type Power Well
Description
DENSEL
22
O
OD12 O6/12
VDD3
Density Select. Indicates that a high FDC density data rate (500
Kbps, 1 Mbps or 2 Mbps) or a low density data rate (250 or 300
Kbps) is selected.
DIR
17
O
OD12 O6/12
VDD3
Direction. Determines the direction of the Floppy Disk Drive
(FDD) head movement (active = step in; inactive = step out)
during a seek operation.
DR0
18
O
OD12 O6/12
VDD3
Drive Select. Active low signal controlled by bit 0 of the Digital
Output Register (DOR).
DRATE0
21
O
OD12 O6/12
VDD3
Data Rate. Reflects the value of bit 0 of either Configuration
Control Register (CCR) or Data Rate Select Register (DSR),
whichever was written to last.
DSKCHG
9
I
INTS
VDD3
Disk Change. Indicates that the drive door was opened.
HDSEL
10
O
OD12 O6/12
VDD3
Head Select. Selects which side of the FDD is accessed. Active
(low) selects side 1; inactive selects side 0.
INDEX
20
I
INTS
VDD3
Index. Indicates the beginning of an FDD track.
MTR0
19
O
OD12 O6/12
VDD3
Motor Select. Active low motor enable signal for drive 0, controlled
by bit D4 of the Digital Output Register (DOR).
RDATA
11
I
INTS
VDD3
Read Data. Raw serial input data stream read from the FDD.
STEP
16
O
OD12 O6/12
VDD3
Step. Issues pulses to the disk drive at a software programmable
rate to move the head during a seek operation.
TRK0
13
I
INTS
VDD3
Track 0. Indicates to the controller that the head of the selected
floppy disk drive is at track 0.
WDATA
15
O
OD12 O6/12
VDD3
Write Data. Carries out the pre-compensated serial data that is
written to the FDD. Pre-compensation is software selectable.
WGATE
14
O
OD12 O6/12
VDD3
Write Gate. Enables the write circuitry of the selected FDD.
WGATE is designed to prevent glitches during power-up and
power-down. This prevents writing to the disk when power is
cycled.
WP
12
I
INTS
VDD3
Write Protected. Indicates that the disk in the selected drive is
write protected.
www.national.com
12
Revision 1.1
1.4.6
PC8374T
1.0 Signal/Pin Connection and Description
(Continued)
Keyboard and Mouse Controller (KBC)
Signal
Pin(s)
I/O Buffer Type Power Well
KBCLK
3
I/O
INTS/OD14
VDD3
Keyboard Clock. Keyboard clock signal. External pull-up resistor
is required for PS/2 compliance. This pin is monitored during
VDD3 power-off for wake-up event detection.
KBDAT
4
I/O
INTS/OD14
VDD3
Keyboard Data. Keyboard data signal. External pull-up resistor is
required for PS/2 compliance. This pin is monitored during VDD3
power-off for wake-up event detection.
MCLK
1
I/O
INTS/OD14
VDD3
Mouse Clock. Mouse clock signal. External pull-up resistor is
required for PS/2 compliance. This pin is monitored during VDD3
power-off for wake-up event detection.
MDAT
2
I/O
INTS/OD14
VDD3
Mouse Data. Mouse data signal. External pull-up resistor is
required for PS/2 compliance. This pin is monitored during VDD3
power-off for wake-up event detection.
KBRST
7
I/O
INT/OD8,
O4/8
VDD3
KBD Reset. Keyboard reset (P20) quasi-bidirectional output.
GA20
5
I/O
INT/OD8,
O4/8
VDD3
Gate A20. KBC gate A20 (P21) quasi-bidirectional output.
1.4.7
General-Purpose I/O (GPIO)
Signal
GPIOE00
Pin(s)
I/O Buffer Type Power Well
103
INTS/
OD8, O4/8
VSB3
118
INTS/
OD12, O6/12
VDD3
GPIOE01-06 104-106,
108-109,
111
VSB3
INTS/
OD8, O4/8
119-121,
124,
126-127
GPIOE07
112
128
GPIOE10-13 116, 114,
115, 113
GPO11
117
GPO12-13
122, 125
INTS/
OD8, O4/8
VSB3
INTS/
OD12, O6/12
VDD3
INTS/
OD8, O4/8
GPIOE14,
101,
GPIOE16-17 100, 80
91
General-Purpose I/O Ports. Each pin is configured
independently as input or I/O, with or without static pull-up (and
some also with or without static pull-down) and with either opendrain or push-pull output type. These pins have event detection
capability to generate a wake-up event or an interrupt.
Note: If GPIOE12 is configured (on pin 74) make sure
that the pin’s default function does not interfere with
the circuit connected to the GPIO. Failure to do so may
result in irreversible damage to the chip.
INTS2/
OD6, O3/6
GPIOE12-13 74-75
GPIO15
Description
VDD3
I/O
Revision 1.1
Description
O
VSB3
INTS/
OD8, O4/8
General-Purpose I/O Port. This pin is configured
independently as input or I/O with or without static pull-up and
with either open-drain or push-pull output type.
OD8, O4/8
General-Purpose Output Port. This pin is configured
independently as output, with or without static pull-up and with
either open-drain or push-pull output type.
VDD3
13
www.national.com
PC8374T
1.0 Signal/Pin Connection and Description
1.4.8
(Continued)
Health Management (HM)
Signal
Pin(s)
I/O Buffer Type Power Well
Description
SWD
103
I/O
INSM/OD6
VSB3
SensorPath Data. Bidirectional, SensorPath Data interface
signal to LMxx sensor device(s). An internal pull-up for this pin
is optional.
HMSCL
88
I/O
INSM/OD6
VSB3
Health Management SMBus Serial Clock. Serial clock
signal. External pull-up resistor is required.
HMSDA
90
I/O
INSM/OD6
VSB3
Health Management SMBus Serial Data. Serial data signal.
External pull-up resistor is required.
FANTACH1-4 111-112,
104-105
I
INTS
VDD3
Fan Inputs. Used to feed the fan’s tachometer pulse to the
Fan Speed Monitor.
FANPWM1-3 106,
108-109
O
OD12,O6/12
VDD3
Fan Outputs. Pulse Width Modulation (PWM) signals, used to
control the speed of cooling fans by controlling the voltage
supplied to the fan motors.
1.4.9
Trusted Platform Module (TPM)
Signal
Pin(s)
I/O Buffer Type Power Well
Description
TPM_PP
123
I
INTS
VSB3
Physical Presence Input. Indicates owner’s physical presence.
IOPA0,
IOPA1,
IOPA6
101,
91,
123
I/O
INTS/
OD8, O4/8
VSB3
General-Purpose I/O Ports. Each pin is configured
independently as input or I/O, with or without static pull-up and
with either open-drain or push-pull output type. These pins
have event detection capability to generate a wake-up event
or an interrupt.
1.4.10 System Wake-Up Control (SWC)
Signal
GPIOE00-07
Pin(s)
I/O Buffer Type Power Well
103-106,
108-109,
111-112
118-121,
124,
126-128
GPIOE10-13
116, 114,
115, 113
GPIOE12-13
74-75
VSB3
INTS
Description
Wake-Up Inputs. Generates a wake-up event. These pins
have programmable debouncing. When the pin is not used,
the internal pull-up resistor must be enabled to allow the pin
to be left not connected.
VDD3
I
INTS2
VSB3
INTS
GPIOE14,
GPIOE16-17
101,
100, 80
RI1
RI2
32,
118 or
119
I
INTS
VSB3
Ring Indicator Wake-Up. When low, generates a wake-up
event, indicating that a telephone ring signal was received by
the modem.
KBCLK
3
I
INTS
VSB3
Keyboard Clock Wake-Up. Generates a wake-up event when
a specific keyboard sequence is detected.
KBDAT
4
I
INTS
VSB3
Keyboard Data Wake-Up. Generates a wake-up event when
a specific keyboard sequence is detected.
MCLK
1
I
INTS
VSB3
Mouse Clock Wake-Up. Generates a wake-up event when a
specific mouse action is detected.
www.national.com
14
Revision 1.1
Signal
Pin(s)
PC8374T
1.0 Signal/Pin Connection and Description
(Continued)
I/O Buffer Type Power Well
Description
MDAT
2
I
INTS
VSB3
Mouse Data Wake-Up. Generates a wake-up event when a
specific mouse action is detected.
SIOPME
99
O
OD8, O4/8
VSB3
Power Management Event (SCI). Active level indicates that a
wake-up event occurred, causing the system to exit its current
sleep state. This signal has programmable polarity (default is
active low).
SLP_S3,
SLP_S5
85,
86
I
INTS4
VSB3
Sleep States 3 to 5. Active (low) level indicates the system is in
one of the sleep states S3 or S5. These signals are generated
by an external ACPI controller.
YLW_LED,
GRN_LED
95,
94
O
OD24
VSB3
Power LEDs. Yellow and green LED drivers. Each indicates
the Main power status or blinks under software control.
1.4.11 Clocks
Signal
Pin(s)
I/O Buffer Type Power Well
Description
CLOCKI32
91
I
INTS
VSB3
Low-Frequency Clock Input. 32.768 KHz clock for the TPM timing.
CLOCKI14
65
I
INTS
VDD3
High-Frequency Clock Input. 14.31818 MHz clock for the onchip, 48 MHz Clock Generator (for the Legacy modules).
1.4.12 Glue Functions
Signal
Pin(s) I/O Buffer Type Power Well
Description
REF5V
70
O
AO
VSB3
Main Highest Active Supply, Reference Output.
Reference voltage equal to the highest voltage between
VDD5 and VDD3. External pull-up resistor to VDD5 is required.
REF5V_STBY
72
O
AO
VSB3
Standby Highest Active Supply, Reference Output.
Reference voltage equal to the highest voltage between
VSB5 and VSB3. External pull-up resistor to VSB5 is required.
PS_ON
81
O
OD6
VSB3
Main Power Supply On/Off Control. Active (low) level turns
the main power supply (VDD) on. External pull-up resistor to
VSB5 is required.
PWRGD_PS
82
I
INTS4
VSB3
Power Good Signal from the Power Supply. Active level
indicates the Main power supply voltage is valid.
PWRGD_3V
84
O
O3/6
VSB3
Power Good Output. Active level indicates: Main supply
voltage is valid and the system is in a higher than S3 sleep
state.
CPU_PRESENT
83
I
INTS4
VSB3
CPU Present. Active (low) level indicates a processor is
currently plugged in.
BKFD_CUT
77
O
OD6
VSB3
Backfeed-Cut Control. Power distribution control (when
switching between main and standby regulators) for system
transition into and out of the S3 sleep state. External pull-up
resistor to VSB5 is required.
LATCHED_BF_
CUT
79
O
O14/14
VSB3
Latched Backfeed-Cut. Power distribution control (when
switching between main and standby regulators) for system
transition into and out of the S5 sleep state.
VSB5
71
I
AI
VSB3
Standby 5V Power Supply. Used for Resume Reset
generation (Range: 0-5.5V, Backdrive protected).
RSMRST
92
O
O3/6
VSB3
Resume Reset. Power-Up reset signal based on the VSB5
supply voltage.
Revision 1.1
15
www.national.com
PC8374T
1.0 Signal/Pin Connection and Description
Signal
PRIMARY_HD
(Continued)
Pin(s) I/O Buffer Type Power Well
Description
67
I
INTS4
VDD3
Primary Drive. Active (low) level indicates that the primary
IDE drive is active.
SECONDARY_HD 68
I
INTS4
VDD3
Secondary Drive. Active (low) level indicates that the
secondary IDE drive is active.
SCSI
69
I
INTS4
VDD3
SCSI Drive. Active (low) level indicates that the SCSI drive
is active.
HD_LED
66
O
OD12
VDD3
Hard Drive LED. Red LED driver. When low, indicates that
at least one drive is active.
VSB3
Chipset Cluster (2.5V or 3.3V) Level DDC Serial Clock.
SMBus serial clock signal with 2.5V or 3.3V logic levels for
Data Display Channel (DDC) interface. External pull-up
resistor to VDD3 or 2.5V is required.
VSB3
5V Level DDC Serial Clock. SMBus serial clock signal with
5V logic levels for VGA monitor interface. External pull-up
resistor to VDD5 is required.
CC_DDCSCL
113
I/O
SWSM
5V_DDCSCL
114
I/O
SWSM
CC_DDCSDA
115
I/O
SWSM
VSB3
Chipset Cluster (2.5V or 3.3V) Level DDC Serial Data.
SMBus serial data signal with 2.5V or 3.3V logic levels for
DDC interface. External pull-up resistor to VDD3 or 2.5V is
required.
5V_DDCSDA
116
I/O
SWSM
VSB3
5V Level DDC Serial Data. SMBus serial data signal with
5V logic levels for VGA monitor interface. External pull-up
resistor to VDD5 is required.
SMB1_SCL
87
I/O
SWSM
VSB3
Bus 1 Serial Clock. Serial clock signal of SMBus 1 (3.3V logic
levels). External pull-up resistor to the 3.3V supply is required.
SMB2_SCL
88
I/O
SWSM
VSB3
Bus 2 Serial Clock. Serial clock signal of SMBus 2 (3.3V logic
levels). External pull-up resistor to the 3.3V supply is required.
SMB1_SDA
89
I/O
SWSM
VSB3
Bus 1 Serial Data. Serial data signal of SMBus 1 (3.3V logic
levels). External pull-up resistor to the 3.3V supply is required.
SMB2_SDA
90
I/O
SWSM
VSB3
Bus 2 Serial Data. Serial data signal of SMBus 2 (3.3V logic
levels). External pull-up resistor to the 3.3V supply is required.
PCIRST_OUT
73
O
O14/14
VSB3
PCI Reset Output. PCI system reset. PCIRST_OUT is a
buffered copy of PCI_RESET when VDD3 is on, and it is held
at low level when VDD3 is off.
PCIRST_OUT2
74
O
O14/14
VSB3
PCI Reset Output 2. PCI system reset (same behavior as
PCIRST_OUT above).
IDE_RSTDRV
64
O
OD6
VDD3
IDE Reset Output. IDE drive reset. IDE_RSTDRV is a
buffered copy of PCI_RESET when VDD3 is on, and it is
floating when VDD3 is off.
www.national.com
16
Revision 1.1
PC8374T
1.0 Signal/Pin Connection and Description
(Continued)
1.4.13 Configuration Straps and Testing
Signal
Pin(s)
I/O Buffer Type Power Well
Description
BADDR
30
I
INTS
VDD3
Base Address. Sampled at VDD Power-Up reset to determine
the base address of the configuration Index-Data register pair,
as follows:
– No pull-down resistor (default)
- 2Eh-2Fh
– 10 KΩ1 external pull-down resistor - 4Eh-4Fh
The external pull-down resistor must be connected to VSS.
VsbStrap1
117
I
INTS
VSB3
Vsb Strap 1. Reserved strap input function for National use.
VddStrap1
122
I
INTS
VDD3
Vdd Strap 1. Reserved strap input function for National use.
VddStrap2
125
I
INTS
VDD3
Vdd Strap 2. General-Purpose strap input function.
TRIS
26
I
INTS
VDD3
TRI-STATE Device. Sampled at VDD Power-Up reset to force
the device to float all its output and I/O pins, as follows:
– No pull-down resistor (default)
- normal pin operation
– 10 KΩ1 external pull-down resistor - floating device pins
The external pull-down resistor must be connected to VSS.
When TRIS is set to 0 (by an external pull-down resistor), TEST
must be 1 (left unconnected).
TEST
27
I
INTS
VDD3
XOR Tree Test Mode. Sampled at VDD Power-Up reset to force
the device pins into a XOR tree configuration, as follows:
– No pull-down resistor (default)
- normal device operation
– 10 KΩ1 external pull-down resistor - pins configured as XOR
tree.
When TEST is set to 0 (by an external pull-down resistor), TRIS
must be 1 (left unconnected).
XOR_OUT
30
O
O4/8
VDD3
XOR Tree Output. All the device pins (except power type and
analog type pins) are internally connected in a XOR tree structure.
1. Because the strap function is multiplexed with the Serial Port pins, a CMOS transceiver device is recommended
for Serial Port functionality; in this case, the value of the external pull-down resistor is 10 KΩ. If, however, a TTL
transceiver device is used, the value of the external pull-down resistor must be 470Ω, and since the Serial Port
pins are not able to drive this load, the external pull-down resistor must be disconnected tEPLV after VDD3
power-up (see “VDD Power-Up Reset” on page 30).
1.4.14 Power and Ground
Signal
Pin(s)
I/O Buffer Type
Power
Well
Description
VSS
8, 29, 46, 58,
78, 96, 110
I
GND
Ground. Ground connection for both core logic and I/O buffers,
for the Main, Standby and Battery power supplies.
VDD3
6, 31, 49, 60
I
PWR
Main 3.3V Power Supply. Powers the I/O buffers of the legacy
peripherals and the LPC interface.
VSB3
76, 93, 107
I
PWR
Standby 3.3V Power Supply. Powers the I/O buffers of the
GPIO ports, SWC, Glue Functions, TPM Health Management
and the on-chip Core power converter.
VCORF
97
I/O
PWR
On-Chip Core Power Converter Filter. On-chip Core power
converter output. An external 1 µF ceramic filter capacitor must
be connected between this pin and VSS.
VCORF2
102
I/O
PWR
On-Chip Core Power Converter Filter. On-chip Core power
converter output. An external 1 µF ceramic filter capacitor must
be connected between this pin and VSS.
Revision 1.1
17
www.national.com
PC8374T
1.0 Signal/Pin Connection and Description
Signal
VBAT
Pin(s)
98
I/O Buffer Type
I
INULR
(Continued)
Power
Well
Description
Battery Power Supply. When VSB3 is off, this supply provides
battery back-up to some of the SWC registers. When the
functions powered by VBAT are not used, the VBAT pin must be
connected to VSB3.
The pin is connected to the internal logic through a series
resistor and diode for UL-compliant protection.
VSB5
www.national.com
71
I
PWR
Standby 5V Power Supply. Used for Resume Reset generation
in the Glue Logic.
18
Revision 1.1
PC8374T
1.0 Signal/Pin Connection and Description
(Continued)
1.5 INTERNAL PULL-UP AND PULL-DOWN RESISTORS
The signals listed in Table 3 have internal pull-up (PU) and/or pull-down (PD) resistors. The internal resistors are optional
for those signals indicated as “Programmable”. See Section 2.3 on page 27 for the values of each resistor type.
Table 3. Internal Pull-Up and Pull-Down Resistors
Signal
Pin(s)
Power Well
Type
Comments
Health Management (HM)
SWD
PU1K25
VSB
103
Programmable1
Parallel Port
ACK
36
VDD3
PU220
AFD_DSTRB
50
VDD3
PU440
BUSY_WAIT
35
VDD3
PD120
ERR
45
VDD3
PU220
INIT
48
VDD3
PU440
PE
34
VDD3
SLCT
33
VDD3
PD120
SLIN_ASTRB
47
VDD3
PU440
STB_WRITE
51
VDD3
PU440
PU220/PD120 Programmable
Keyboard and Mouse Controller (KBC)
KBRST
7
VDD3
PU30
GA20
5
VDD3
PU30
System Wake-Up Control (SWC)
SIOPME
VSB3
99
PU30
Programmable2
General-Purpose Input/Output (GPIO) Ports
103
VSB
PU1K25
Programmable3
118
VDD3
PU30/PD30
Programmable4
104-106, 108-109, 111
VSB3
PU30
119-121, 124, 126-127
VDD3
112
VSB3
PU30
Programmable5
128
VDD3
PU30/PD30
Programmable4
GPIOE10-11
116, 114
VSB3
PU30
Programmable6
GPIOE12
115
VSB3
PU30
Programmable6
VSB3
PU30
Programmable6
PU90
Programmable1
GPIOE00
GPIOE01-06
GPIOE07
Programmable1
74
GPIOE13
113
75
Revision 1.1
GPIOE14
101
VSB3
PU30/PD30
Programmable4
GPIO15, GPIOE16
91, 100
VSB3
PU30
Programmable5
GPIOE17
80
VSB3
PU30
Programmable1
19
www.national.com
PC8374T
1.0 Signal/Pin Connection and Description
(Continued)
Table 3. Internal Pull-Up and Pull-Down Resistors (Continued)
Signal
Pin(s)
Power Well
Type
Comments
GPO11
117
VSB3
PU30
Programmable1
GPO12-13
122, 125
VDD3
PU30
Programmable1
Glue Functions
PWRGD_PS
82
VSB3
PU90
CPU_PRESENT
83
VSB3
PU90
PRIMARY_HD
67
VDD3
PU90
SECONDARY_HD
68
VDD3
PU90
SCSI
69
VDD3
PU90
Trusted Platform Module (TPM)
TPM_PP
123
VSB3
PD30
Programmable7
IOPA6
123
VSB3
PU30/PD30
Programmable8
IOPA0, IOPA1
101, 91
VSB3
PU30
Programmable8
Strap Configuration
BADDR
30
VDD3
PU30
Strap9
TRIS
26
VDD3
PU30
Strap9
TEST
27
VDD3
PU30
Strap9
VsbStrap1
117
VSB3
PU30
Strap10
VddStrap1
122
VDD3
PU30
Strap9
VddStrap2
125
VDD3
PU30
Strap9
1. Default at reset: enabled.
2. Enabled only when the OD6 buffer type is selected (OD6 is the default at reset).
3. Alternate function at reset: enabled.
4. Default at reset: PD enabled.
5. Default at reset: disabled.
6. Alternate function at reset: disabled.
7. Controlled by TPM. Default at reset: enabled.
8. Controlled by TPM. Default at reset: disabled.
9. Active only during VDD Power-Up reset.
10. Active only during VSB Power-Up reset.
www.national.com
20
Revision 1.1
Device Characteristics
2.1
GENERAL DC ELECTRICAL CHARACTERISTICS
2.1.1
PC8374T
2.0
Recommended Operating Conditions
Symbol
Parameter
Min
Typ
Max
Unit
VDD3
Main 3V Supply Voltage
3.0
3.3
3.6
V
VSB3
Standby 3V Supply Voltage
3.0
3.3
3.6
V
VBAT
Battery Backup Supply Voltage
2.4
3.0
3.6
V
+70
°C
TA
2.1.2
Operating Temperature
0
Absolute Maximum Ratings
Absolute maximum ratings are values beyond which damage to the device may occur. Unless otherwise specified, all voltages are relative to ground (VSS).
Symbol
VSUP
Parameter
Conditions
Min
Max
Unit
−0.5
+4.1
V
All other pins
−0.5
5.5
V
LAD3-0, LFRAME, SERIRQ
−0.5
VDD3 + 0.5
V
All other pins
−0.5
5.5
V
LAD3-0, LDRQ, SERIRQ
−0.5
VDD3 + 0.5
V
−65
+165
°C
1
W
+260
°C
Supply Voltage1
VI
Input Voltage
VO
Output Voltage
TSTG
Storage Temperature
PD
Power Dissipation
TL
Lead Temperature Soldering (10 s)
ESD Tolerance
CZAP = 100 pF
2000
RZAP = 1.5 KΩ2
V
1. VSUP is VDD3, VSB3.
2. Value based on test complying with RAI-5-048-RA human body model ESD testing.
2.1.3
Capacitance
Symbol
Parameter
Conditions
Min2
Typ1
Max2
Unit
4
5
pF
8
12
pF
8
10
pF
CIN
Input Pin Capacitance
CINC
LPC Clock Input Capacitance
CPCI
LPC Pin Capacitance
CIO
I/O Pin Capacitance
8
10
pF
CO
Output Pin Capacitance
6
8
pF
PCI_CLK
LAD3-0, LFRAME, PCI_RESET,
SERIRQ, LDRQ
5
1. TA = 25°C; f = 1 MHz.
2. Not tested. Guaranteed by characterization.
Revision 1.1
21
www.national.com
PC8374T
2.0 Device Characteristics
2.1.4
(Continued)
Power Consumption under Recommended Operating Conditions
Symbol
IDD3
VDD3 Average Supply Current
IDD3LP
ISB3
VDD3 Quiescent Supply Current in
Low Power Mode3
VSB3 Average Supply Current
ISB3LP
IBAT
Conditions1
Typ
Max2
Unit
VIL = 0.5V, VIH = 2.4V, No Load
14
20
mA
VIL = VSS, VIH = VDD3, No Load
0.5
0.8
mA
VIL = 0.5V, VIH = 2.4V, No Load
25
100
mA
VIL = VSS, VIH = VSB3, No Load
5
TBD
mA
VDD3, VSB3 = 0V, VBAT = 3V
0.4
0.9
µA
Parameter
VSB3 Quiescent Supply Current in
Low Power Mode3
VBAT Battery Supply Current
1. All parameters specified for 0°C ≤ TA ≤ 70°C; VDD3 and VSB3 = 3.3V ±10% unless otherwise specified.
2. Not tested. Guaranteed by characterization.
3. All the modules disabled; no LPC bus activity.
2.1.5
Voltage Thresholds
Parameter1
Symbol
Min2
Typ
Max2
Unit
VDD3ON
VDD3 Detected as Power-on
2.3
2.6
2.9
V
VDD3OFF
VDD3 Detected as Power-off
2.1
2.5
2.8
V
VSB3ON
VSB3 Detected as Power-on
2.3
2.6
2.9
V
VSB3OFF
VSB3 Detected as Power-off
2.1
2.5
2.8
V
VPPSW
VPP Switching between VSB3 and VBAT
2.0
2.3
2.6
V
VBATLOW
VBAT Detected as “Low”
2.3
V
1. All parameters specified for 0°C ≤ TA ≤ 70°C.
2. Not tested. Guaranteed by characterization.
2.2
DC CHARACTERISTICS OF PINS, BY I/O BUFFER TYPES
The following tables summarize the DC characteristics of all device pins described in Section 1.2 on page 7. The characteristics
describe the general I/O buffer types defined in Table 1 on page 7. For exceptions, refer to Section 2.2.13 on page 26. The DC
characteristics of the LPC interface meet the PCI Local Bus Specification (Rev 2.2 December 18, 1998) for 3.3V DC signaling.
2.2.1
Input, TTL Compatible
Symbol: INT
Symbol
Parameter
Conditions
Min
Max
Unit
VIH
Input High Voltage
2.0
5.51
V
VIL
Input Low Voltage
−0.51
0.8
V
IIL2
Input Leakage Current
±1
µA
0 < VIN < VSUP3
1. Not tested. Guaranteed by design.
2. Input leakage current includes the output leakage of the bi-directional buffers with TRI-STATE outputs.
3. VSUP is VDD3 or VSB3 according to the input power well.
www.national.com
22
Revision 1.1
2.2.2
PC8374T
2.0 Device Characteristics
(Continued)
Input, TTL Compatible, with Schmitt Trigger
Symbol: INTS
Symbol
Parameter
Conditions
Min
Max
Unit
VIH
Input High Voltage
2.0
5.51
V
VIL
Input Low Voltage
−0.51
0.8
V
VHY
Input Hysteresis
2502
IIL3
Input Leakage Current
mV
±1
0 < VIN < VSUP4
µA
1. Not tested. Guaranteed by design.
2. Not tested. Guaranteed by characterization.
3. Input leakage current includes the output leakage of the bi-directional buffers with TRI-STATE outputs.
4. VSUP is VDD3 or VSB3 according to the input power well.
2.2.3
Input, TTL Compatible, with 200 mV Schmitt Trigger
Symbol: INTS2
Symbol
Parameter
Conditions
Min
Max
Unit
VIH
Input High Voltage
2.0
5.51
V
VIL
Input Low Voltage
−0.51
0.8
V
VHY
Input Hysteresis
2002
IIL3
Input Leakage Current
mV
±1
0 < VIN < VSUP4
µA
1. Not tested. Guaranteed by design.
2. Not tested. Guaranteed by characterization.
3. Input leakage current includes the output leakage of the bi-directional buffers with TRI-STATE outputs.
4. VSUP is VDD3 or VSB3 according to the input power well.
2.2.4
Input, TTL Compatible, with 400 mV Schmitt Trigger
Symbol: INTS4
Symbol
Parameter
Conditions
Min
Max
Unit
VIH
Input High Voltage
2.0
5.51
V
VIL
Input Low Voltage
−0.51
0.8
V
VHY
Input Hysteresis
4002
IIL3
Input Leakage Current
0 < VIN < VSUP4
mV
±1
µA
1. Not tested. Guaranteed by design.
2. Not tested. Guaranteed by characterization.
3. Input leakage current includes the output leakage of the bi-directional buffers with TRI-STATE outputs.
4. VSUP is VDD3 or VSB3 according to the input power well.
Revision 1.1
23
www.national.com
PC8374T
2.0 Device Characteristics
2.2.5
(Continued)
Input, PCI 3.3V Compatible
Symbol: INPCI
Symbol
Parameter
Conditions
Min
Max
Unit
VIH
Input High Voltage
0.5 VDD
VDD + 0.51
V
VIL
Input Low Voltage
−0.51
0.3 VDD
V
lIL2
Input Leakage Current
±1
µA
0 < VIN < VDD3
1. Not tested. Guaranteed by design.
2. Input leakage current includes the output leakage of the bi-directional buffers with TRI-STATE outputs.
2.2.6
Input, SMBus Compatible
Symbol: INSM
Symbol
Parameter
Conditions
Min
Max
Unit
VIH
Input High Voltage
1.4
5.51
V
VIL
Input Low Voltage
−0.51
0.8
V
IIL2
Input Leakage Current
±1
µA
0 < VIN < VSB
1. Not tested. Guaranteed by design.
2. Input leakage current includes the output leakage of the bidirectional buffers with TRI-STATE outputs.
2.2.7
Analog Input
Symbol: AI
Symbol
Parameter
VIR
Input Voltage Range
lIL
Input Leakage Current
Conditions
Min
Max
Unit
0
5.51
V
300
µA
VIN = VIR
1. Not tested. Guaranteed by characterization.
2.2.8
Output, TTL/CMOS Compatible, Push-Pull Buffer
Symbol: Op/n
Output, TTL/CMOS Compatible, rail-to-rail push-pull buffer that is capable of sourcing p mA and sinking n mA
Symbol
VOH
VOL
Parameter
Output High Voltage
Output Low Voltage
Conditions
Min
Max
Unit
IOH = −p mA
2.4
V
IOH = −50 µA
VSUP − 0.21
V
IOL = n mA
0.4
V
IOL = 50 µA
0.2
V
1. VSUP is VDD3 or VSB3 according to the output power well.
www.national.com
24
Revision 1.1
2.2.9
(Continued)
Output, TTL/CMOS Compatible, Open-Drain Buffer
Symbol: ODn
Output, TTL/CMOS-compatible open-drain output buffer capable of sinking n mA. Output from these signals is opendrain and is never forced high.
Symbol
VOL
2.2.10
Parameter
Conditions
Output Low Voltage
Min
Max
Unit
IOL = n mA
0.4
V
IOL = 50 µA
0.2
V
Max
Unit
Output, PCI 3.3V Compatible
Symbol: OPCI
Symbol
Parameter
Conditions
Min
0.9 VDD3
VOH
Output High Voltage
lout = −500 µA
VOL
Output Low Voltage
lout = 1500 µA
2.2.11
V
0.1 VDD3
V
Min
Max
Unit
0
5.51
V
20
µA
Analog Output
Symbol: AO
Symbol
Parameter
VOR
Output Voltage Range
VOD
Output Drive Voltage
lOL
Output Leakage Current
Conditions
lout = −3.6 mA
VSUP2 − 150 mV
VOUT = VOR, VSUP < VOUT
1. Not tested. Guaranteed by characterization.
2. VSUP is VDD3 or VSB3 according to the pin power well.
2.2.12
Input/Output Switch, SMBus Compatible
Symbol: SWSM
Symbol
Parameter
Conditions
Min
ISW = ±3 mA, Switch Closed
Max
Unit
1501
mV
VDRP
Pin-to-Pin Voltage Drop
VISC
Input Voltage for Switch Closed
ISW = ±3 mA
VISO
Input Voltage for Switch Open
ISW = ±20 µA
2.25
V
VISO < VIN < 5.5V
±201
µA
IIL
Input Leakage Current
V
1.51
1. Not tested. Guaranteed by characterization.
Revision 1.1
25
www.national.com
PC8374T
2.0 Device Characteristics
PC8374T
2.0 Device Characteristics
2.2.13
(Continued)
Exceptions
1. All pins are 5V tolerant except for the output pins with PCI (OPCI) buffer types.
2. All pins are back-drive protected except for the output pins with PCI (OPCI) buffer types.
3. The following pins have an internal static pull-up resistor (when enabled) and therefore may have leakage current from
VSUP (when VIN = 0): SWD, ACK, AFD_DSTRB, ERR, INIT, PE, SLIN_ASTRB, STB_WRITE, KBRST, GA20, SIOPME,
GPIOE00-07, GPIOE10-17, GPO11-13 PWRGD_PS, CPU_PRESENT, PRIMARY_HD, SECONDARY_HD, SCSI,
IOPA0, IOPA1, IOPA6.
4. The following pins have an internal static pull-down resistor (when enabled) and therefore may have leakage current to
VSS (when VIN = VSUP): BUSY_WAIT, PE and SLCT, GPIOE14, GPIOE00 (on pin 118), GPIOE07 (on pin 128), TPM_PP,.
5. The following strap pins have an internal static pull-up resistor enabled during Power-Up reset and therefore may have
leakage current to VSUP (when VIN = 0): BADDR, TRIS, TEST, VsbStrap1, VddStrap1, VddStrap2.
6. When VDD3 = 0V, the following pins present a DC load to VSS of 30 KΩ minimum (not tested, guaranteed by design) for
a pin voltage of 0V to 3.6V: CTS1, CTS2, DCD1, DCD2, DSR1, DSR2, DTR_BOUT1, DTR_BOUT2, RI1, RI2, RTS1,
RTS2, SIN1, SIN2, SOUT1, SOUT2.
7. Output from SLCT, BUSY_WAIT (and PE if bit 2 of PP Confg0 register is 0) is open-drain in all SPP modes except in
SPP-Compatible mode when the setup mode is ECP-based FIFO and bit 4 of the Control2 parallel port register is 1. Otherwise, output from these signals is level 2. External 4.7 KΩ pull-up resistors should be used.
8. Output from ACK, ERR (and PE if bit 2 of PP Confg0 register is set to 1) is open-drain in all SPP modes except in SPPCompatible mode when the setup mode is ECP-based FIFO and bit 4 of the Control2 parallel port register is set to 1.
Otherwise, output from these signals is level 2. External 4.7 KΩ pull-up resistors should be used.
9. Output from STB, AFD, INIT and SLIN is open-drain in all SPP modes, except in SPP-Compatible mode when the setup
mode is ECP-based (FIFO). Otherwise, output from these signals is level 2. External 4.7 KΩ pull-up resistors should be
used.
10. IOH is valid for a GPIO pin only when it is not configured as open-drain.
11. In XOR Tree mode, the buffer type of the input pins participating in the XOR Tree is INT (Input, TTL compatible), regardless of the buffer type of these pins in normal device operation mode (see Section 1.4 on page 10).
2.2.14
Terminology
Back-Drive Protection. A pin that is back-drive protected does not sink current into the supply when an input voltage higher
than the supply, but below the pin’s maximum input voltage, is applied to the pin. This is true even when the supply is inactive. Note that active pull-up resistors and active output buffers are typically not back-drive protected.
5-Volt Tolerance. An input signal that is 5V tolerant can operate with input voltage of up to 5V even though the supply to the
device is only 3.3V. The actual maximum input voltage allowed to be supplied to the pin is indicated by the maximum high
voltage allowed for the input buffer. Note that some pins have multiple buffers, not all of which are 5V tolerant. In such cases,
there is a note that indicates at what conditions a 5V input may be applied to the pin; if there is no note, the low maximum
voltage among the buffers is the maximum voltage allowed for the pin.
www.national.com
26
Revision 1.1
2.3
PC8374T
2.0 Device Characteristics
(Continued)
INTERNAL RESISTORS
DC Test Conditions
Pull-Up Resistor Test Circuit
Pull-Down Resistor Test Circuit
VSUP
VSUP
Device
Under
Test
RPU
VSUP
Device
Under
Test
IPU
Pin
IPD
Pin
A
A
RPD
V
VPIN
V
VPIN
Figure 1. Internal Resistor Test Conditions, TA = 0°C to 70°C, VSUP = 3.3V
VSUP
Device
Under
Test
VSUP
VPIN > VIH
Device
Under
Test
IPU
RPU
Pin
10µA
RPU
IPU
Pin
A
VPIN
V
VSUP
VPIN < VIL
A
10µA
VPIN
V
10 KΩ
Figure 2. Internal Pull-Down Resistor for Straps, TA = 0°C to 70°C, VSUP = 3.3V
Notes for Figures 1 and 2:
1. VSUP is VDD3 or VSB3 according to the pin power well.
2. The equivalent resistance of the pull-up resistor is calculated by RPU = (VSUP − VPIN) / IPU.
3. The equivalent resistance of the pull-down resistor is calculated by RPD = VPIN / IPD.
2.3.1
Pull-Up Resistor
Symbol: PUnn
Symbol
RPU
Parameter
Pull-up equivalent resistance
Conditions1
Min2
Typical
Max2
Unit
VPIN = 0V
nn − 30%
nn
nn + 30%
KΩ
nn − 38%
KΩ
VPIN = 0.8 VSUP3
VPIN = 0.17 VSUP3
nn − 35%
Conditions1
Min2
Typical
Max2
Unit
VPIN = VSUP
nn − 30%
nn
nn + 30%
KΩ
KΩ
1. TA = 0°C to 70°C, VSUP = 3.3V.
2. Not tested. Guaranteed by characterization.
3. For strap pins only.
2.3.2
Pull-Down Resistor
Symbol: PDnn
Symbol
RPD
Parameter
Pull-down equivalent resistance
1. TA = 0°C to 70°C, VSUP = 3.3V.
2. Not tested. Guaranteed by characterization.
Revision 1.1
27
www.national.com
PC8374T
2.0 Device Characteristics
2.4
(Continued)
AC ELECTRICAL CHARACTERISTICS
2.4.1
AC Test Conditions
Load Circuit
AC Testing Input, Output Waveform
VSUP
(unless otherwise specified)
S1
2.4
0.1 µf
0.4
2.0
0.8
Test Points
2.0
0.8
RL
Device
Under
Test
Input
Output
CL
Figure 3. AC Test Conditions, TA = 0°C to 70°C, VSUP = 3.3V ±10%
Notes:
1. VSUP is either VDD3 or VSB3, according to the pin power well.
2. CL = 50 pF for all output pins except the following pin groups:
− CL = 100 pF for Serial Port 1 and 2 pins (see Section 1.4.2 on page 10), Parallel Port pins
(see Section 1.4.4 on page 11) and Floppy Disk Controller pins (see Section 1.4.5 on page 12).
− CL = 40 pF for IDE_RSTDRV pin.
− CL = 400 pF for SMBus pins (see “SMBus Voltage Translation and Isolation Timing” on page 44).
These values include both jig and oscilloscope capacitance.
3. S1 = Open
S1 = VSUP
S1 = GND
RL = 1.0 KΩ
−
−
−
−
for push-pull output pins.
for high impedance to active low and active low to high-impedance transition measurements.
for high impedance to active high and active high to high-impedance transition measurements.
for all the pins
4. For the FDC open-drain interface pins, S1 = VDD3 and RL = 150Ω.
2.4.2
Reset Timing
VSB Power-Up Reset
Symbol Figure
Description
4
Internal Power-Up Reset
Time
tIRST
Reference Conditions
VSB3 power-up to
end of internal reset
5
Min1
Max1
Ended by
32 KHz
Clock Domain
t32KW + t32KVAL2 +
17 * tCP
Ended by
PCI_RESET
tLRST
tLRST
5
PCI_RESET active time
VSB3 power-up to end of PCI_RESET
tIPLV
5
Internal VsbStrap1 strap pullBefore end of internal reset
up resistor, valid time3
tIRST
tEPLV
5
External VsbStrap1 strap pullBefore end of internal reset
down resistor, valid time
tIRST
10 ms
1. Not tested. Guaranteed by design.
2. t32KW + t32KVAL from VSB3 power-up to 32 KHz domain toggling; see “Low-Frequency Clock Timing” on page 32.
3. Active only during VSB3 Power-Up reset.
www.national.com
28
Revision 1.1
VSB3 (Power)
VSB3ONmin
PC8374T
2.0 Device Characteristics
(Continued)
tCP
t32KW + t32KVAL
32 KHz Domain
(Internal)
tIRST
VSB Power-Up Reset
(Internal)
PCI_RESET
tEPLV
Internal VsbStrap1 Strap
(Pull-Up)
tIPLV
External VsbStrap1 Strap
(Pull-Down)
Figure 4. Internal VSB Power-Up Reset - Ended by 32 KHz Clock
VSB3 (Power)
VSB3ONmin
32 KHz Domain
(Internal)
VSB Power-Up Reset
(Internal)
t32KW + t32KVAL
tCP
tIRST
tLRST
PCI_RESET
tEPLV
Internal VsbStrap1 Strap
(Pull-Up)
External VsbStrap1 Strap
(Pull-Down)
tIPLV
Figure 5. Internal VSB Power-Up Reset - Ended by PCI_RESET
Revision 1.1
29
www.national.com
PC8374T
2.0 Device Characteristics
(Continued)
VDD Power-Up Reset
Symbol Figure
Description
Min1
Reference Conditions
tIRST
6
Internal Power-Up reset time
VDD3 power-up to end of internal reset
tLRST
6
PCI_RESET active time
VDD3 power-up to end of PCI_RESET
tIPLV
6
Internal strap pull-up resistor,
valid time2
Before end of internal reset
tIRST
tEPLV
6
External strap pull-down
resistor, valid time
Before end of internal reset
tIRST
Max1
tLRST
10 ms
2.5 s
1. Not tested. Guaranteed by design.
2. Active only during VDD3 Power-Up reset.
VDDONmin
VDD3 (Power)
tIRST
VDD Power-Up Reset
(Internal)
tLRST
PCI_RESET
tIPLV
Internal Straps
(Pull-up)
tEPLV
External Straps
(Pull-Down)
Figure 6. Internal VDD Power-Up Reset
Hardware Reset
Symbol
Figure
tWRST
7
Description
Reference Conditions
PCI_RESET pulse width
Min
Max
100 ns
Internal Clock
tWRST
PCI_RESET
Figure 7. Hardware Reset
www.national.com
30
Revision 1.1
2.4.3
PC8374T
2.0 Device Characteristics
(Continued)
Clock Timing
High-Frequency Clock Timing
Symbol Figure
Reference
Conditions
Clock Input Parameters
CLOCKI14
Min
Typ
Max
Units
tCH
8
Clock High Pulse Width1
20
ns
tCL
8
Clock Low Pulse Width1
20
ns
tCP
8
Clock Period (50%-50%)
FCK
−
Clock Frequency
tCR
8
tCF
tCE
1
69.14
FCKTYP − 1%
69.84
70.54
ns
14.31818
FCKTYP + 1%
MHz
Clock Rise Time (VIL to VIH)
2
5
ns
8
Clock Fall Time1 (VIH to VIL)
52
ns
9
Clock Generator Enable
80
µs
1
RE PCI_RESET
to Clock Generator
enabled
1. Not tested. Guaranteed by design.
2. Recommended value.
Sym. Fig.
Internal Clock Parameter
tCP
8
Clock Period1 (50%-50%)
FCK
−
Clock Frequency
t48MD
9
Clock Wake-Up Time1
INT48M
Reference
Conditions
Min
Typ
Max
Units
20.83
ns
48
MHz
After Clock
Generator enabled
µs
500
1. Not tested. Guaranteed by characterization.
tCP
tCH
VIH
VIH
VIH
VIL
VIL
VIL
tCL
tCR
tCF
Figure 8. High-Frequency Clock Waveform Timing
VDD3 (Power)
VDD3ONmin
tCP (CLOCKI14)
CLOCKI14
(14.31818 MHz)
tCE
PCI_RESET
Enable Clock Generator
(Internal)
48 MHz Clock
t48MD
CKVALID bit
(Internal)
tCP (48 MHz)
(Internal)
Figure 9. CLOCKI14 and Internal 48 MHz Clock Timing
Revision 1.1
31
www.national.com
PC8374T
2.0 Device Characteristics
(Continued)
Low-Frequency Clock Timing
INT32K
Symbol Figure Internal Clock Parameters Reference Conditions
tCP
tCPL
10
Clock Period1
(50%-50%)
10
Clock Period1
(50%-50%)
FCK
Clock Frequency
−
FCKL
Units
Min
Typ
Max
After VSB3 power-up
21.3623
30.517578
39.6728
After CLOCKI14 valid
30.2124
30.517578
30.8227
When VDD3 does not
exist
27.465820
30.517578
33.569336
After VSB3 power-up
F32TYP − 30%
32.768
(F32TYP)
F32TYP + 30%
After CLOCKI14 valid
F32TYP − 1%
32.768
(F32TYP)
F32TYP + 1%
When VDD3 does not
exist
F32TYP − 10%
32.768
(F32TYP)
F32TYP + 10%
Clock Frequency
µs
KHz
t32KW
10
Clock wake-up time1
VSB3 stable to clock
start toggling
5
ms
t32KVAL
10
Clock valid time1
Clock start toggling to
clock valid
1
ms
1. Not tested. Guaranteed by characterization.
VSB3 (Power)
Internal
32.768 KHz
VSB3ONmin
tCP
t32KW
t32KVAL
32 KHz Domain
(Internal)
Figure 10. Internal 32 KHz (INT32K) and CLOCKO32 Timing
www.national.com
32
Revision 1.1
2.4.4
(Continued)
LPC Interface Timing
The AC characteristics of the LPC interface meet the PCI Local Bus Specification (Rev 2.2 December 18, 1998) for 3.3V DC
signaling.
PCI_CLK and PCI_RESET
Symbol
Parameter
Min
Max
Units
tCYC1
PCI_CLK Cycle Time
30
ns
tHIGH
PCI_CLK High Time2
11
ns
tLOW
PCI_CLK Low Time2
11
ns
−
PCI_CLK Slew Rate2,3
1
−
PCI_RESET Slew Rate2,4
50
4
V/ns
mV/ns
1. The PCI may have any clock frequency between nominal DC and 33 MHz. Device operational
parameters at frequencies under 16 MHz are guaranteed by design rather than by testing. The
clock frequency may be changed at any time during the operation of the system as long as the
clock edges remain “clean” (monotonic) and the minimum cycle high and low times are not violated. The clock may only be stopped in a low state.
2. Not tested. Guaranteed by characterization.
3. Rise and fall times are specified in terms of the edge rate measured in V/ns. This slew rate must
be met across the minimum peak-to-peak portion of the clock wavering (0.2 * VDD3 to 0.6 *
VDD3) as shown below.
4. The minimum PCI_RESET slew rate applies only to the rising (de-assertion) edge of the reset
signal and ensures that system noise cannot make an otherwise monotonic signal appear to
bounce in the switching range.
VDD3 = 3.3V ±10%
tHIGH
tLOW
0.6 VDD
0.5 VDD
0.4 VDD3 p-to-p
(minimum)
0.4 VDD
0.3 VDD
0.2 VDD
tCYC
Revision 1.1
33
www.national.com
PC8374T
2.0 Device Characteristics
PC8374T
2.0 Device Characteristics
(Continued)
LPC Signals
Symbol
Figure
Description
tVAL
Outputs
Output Valid Delay
tON
Outputs
tOFF
Outputs
tSU
tHL
Reference Conditions
Min
Max
Unit
After RE of CLK
2
11
ns
Float to Active Delay
After RE of CLK
2
Active to Float Delay
After RE of CLK
Inputs
Input Setup Time
Before RE of CLK
7
ns
Inputs
Input Hold Time
After RE of CLK
0
ns
ns
28
ns
Outputs
VDD3 = 3.3V ±10%
PCI_CLK
0.4 VDD3
0.4 VDD3
tVAL
tVAL
LAD3−LAD0,
LDRQ, SERIRQ
0.615 VDD3
0.285 VDD3
tON
LAD3−LAD0,
SERIRQ
tOFF
Leakage Only
Output Enabled
Leakage Only
Inputs
VDD3 = 3.3V ±10%
PCI_CLK
0.4 VDD3
tSU
LAD3−LAD0, LFRAME
SERIRQ
www.national.com
tHL
0.4 VDD3
34
Revision 1.1
2.4.5
PC8374T
2.0 Device Characteristics
(Continued)
FDC Timing
FDC Write Data Timing
Symbol
Parameter
Min
Max
Unit
tHDH
HDSEL Hold from WGATE Inactive1
100
µs
tHDS
HDSEL Setup to WGATE Active1
100
µs
tWDW
Write Data Pulse Width1
See tDRP, tICP and tWDW values in table below
1. Not tested. Guaranteed by design.
HDSEL
WGATE
tHDS
tHDH
tWDW
WDATA
tDRP, tICP, tWDW Values
Data Rate
tDRP
tICP
tICP Nominal
tWDW
tWDW Minimum
Unit
1 Mbps
1000
6 x tCP1
125
2 x tICP
250
ns
500 Kbps
2000
6 x tCP1
125
2 x tICP
250
ns
300 Kbps
3333
10 x tCP1
208
2 x tICP
375
ns
250 Kbps
4000
12 x tCP1
250
2 x tICP
500
ns
1. tCP is the clock period defined for CLOCKI in “Clock Timing” on page 31.
FDC Drive Control Timing
Symbol
Parameter
Min
Max
Unit
6
µs
Index Pulse Width
100
ns
tSTD
DIR Hold from STEP Inactive
tSTR
ms
tSTP
STEP Active (Low) Pulse Width1
8
µs
tSTR
STEP Rate Time1
0.5
ms
tDST
DIR Setup to STEP Active1
tIW
1. Not tested. Guaranteed by design.
Revision 1.1
35
www.national.com
PC8374T
2.0 Device Characteristics
(Continued)
DIR
tSTD
tDST
STEP
tSTP
tSTR
INDEX
tIW
FDC Read Data Timing
Symbol
tRDW
Parameter
Min
Read Data Pulse Width
50
Max
Unit
ns
tRDW
RDATA
www.national.com
36
Revision 1.1
2.4.6
PC8374T
2.0 Device Characteristics
(Continued)
Parallel Port Timing
Standard Parallel Port Timing
Symbol
Parameter
Conditions
Min
Max
Unit
tPDH
Port Data Hold
SPP Mode 0 and Mode 1, ECP Mode 0 and Mode1:
system dependent; ECP Mode 2: device dependent.
750
ns
tPDS
Port Data Setup
SPP Mode 0 and Mode 1, ECP Mode 0 and Mode1:
system dependent; ECP Mode 2: device dependent.
750
ns
tSW
Strobe Width
SPP Mode 0 and Mode 1, ECP Mode 0 and Mode1:
system dependent; ECP Mode 2: device dependent.
750
ns
BUSY
ACK
tPDH
tPDS
PD7−0
tSW
STB
Enhanced Parallel Port Timing
Symbol
Parameter
Min
Max
EPP 1.71 EPP 1.91
Unit
tWW19a
WRITE Active from WAIT Low
45
✔
ns
tWW19ia
WRITE Inactive from WAIT Low
45
✔
ns
tWST19a
DSTRB or ASTRB Active from WAIT Low
65
✔
ns
tWEST
DSTRB or ASTRB Active after WRITE Active
10
✔
✔
ns
tWPDH
PD7−0 Hold after WRITE Inactive
0
✔
✔
ns
tWPDS
PD7−0 Valid after WRITE Active
✔
✔
ns
tEPDW
PD7−0 Valid Width
80
✔
✔
ns
tEPDH
PD7−0 Hold after DSTRB or ASTRB Inactive
0
✔
✔
ns
15
1. Also in ECP Mode 4.
tWW19a
WRITE
DSTRB
or
ASTRB
tWST19a
tWEST
tWPDH
PD7−0
tWPDS
tWW19ia
tWST19a
tEPDH
Valid
tEPDW
WAIT
Revision 1.1
37
www.national.com
PC8374T
2.0 Device Characteristics
(Continued)
Extended Capabilities Port (ECP) Timing
Forward Mode
Symbol
Parameter
Min
Max
Unit
tECDSF
Data Setup before STB Active
0
ns
tECDHF
Data Hold after BUSY Inactive
0
ns
tECLHF
BUSY Active after STB Active
75
ns
tECHHF
STB Inactive after BUSY Active1
0
1
s
tECHLF
BUSY Inactive after STB Inactive1
0
35
ms
tECLLF
STB Active after BUSY Inactive
0
ns
1. Not tested. Guaranteed by design.
tECDHF
PD7−0
AFD
tECDSF
tECLLF
STB
tECHLF
tECLHF
BUSY
tECHHF
Reverse Mode
Symbol
Parameter
Min
Max
Unit
tECDSR
Data Setup before ACK Active
0
ns
tECDHR
Data Hold after AFD Active
0
ns
tECLHR
AFD Inactive after ACK Active
75
ns
tECHHR
ACK Inactive after AFD Inactive1
0
35
ms
tECHLR
AFD Active after ACK Inactive1
0
1
s
tECLLR
ACK Active after AFD Active
0
ns
1. Not tested. Guaranteed by design.
tECDHR
PD7−0
BUSY
tECDSR
ACK
tECLLR
tECLHR
AFD
www.national.com
tECHLR
tECHHR
38
Revision 1.1
2.4.7
PC8374T
2.0 Device Characteristics
(Continued)
Serial Ports 1 and 2 Timing
Serial Port Data Timing
See Section 2.4.8 on page 40.
Modem Control Timing
Symbol
Parameter
Min
Max
Unit
tL
RI1,2 Low Time1,2
10
ns
tH
RI1,2 High Time1,2
10
ns
tSIM
Delay to Set IRQ from Modem Input
40
ns
1. Not tested. Guaranteed by characterization.
2. The value also applies to RI1,2 wake-up detection in the SWC module.
CTS, DSR, DCD
tSIM
tSIM
INTERRUPT
(Read MSR)
(Read MSR)
tSIM
tL
tH
RI
Revision 1.1
39
www.national.com
PC8374T
2.0 Device Characteristics
2.4.8
(Continued)
Serial Port, Sharp-IR, SIR and Consumer Remote Control Timing
Symbol
Parameter
Single Bit Time in Serial Port and Sharp-IR
tBT
tCMW
tCMP
tSPW
SDRT
tSJT
Modulation Signal Pulse Width in Sharp-IR
and Consumer Remote Control
Modulation Signal Period in Sharp-IR and
Consumer Remote Control
SIR Signal Pulse Width
Conditions
Min1
Max1
Unit
Transmitter
tBTN − 252
tBTN + 25
ns
Receiver
tBTN − 2%
tBTN + 2%
ns
Transmitter
tCWN − 253
tCWN + 25
ns
Receiver
500
Transmitter
tCPN − 254
tCPN + 25
ns
Receiver
tMMIN5
tMMAX5
ns
Transmitter,
Variable
(3/16) x tBTN − 152
(3/16) x tBTN + 152
ns
Transmitter,
Fixed
1.48
1.78
µs
Receiver
1
ns
µs
SIR Data Rate Tolerance.
% of Nominal Data Rate.
Transmitter
± 0.87%
Receiver
± 2.0%
SIR Leading Edge Jitter.
% of Nominal Bit Duration.
Transmitter
± 2.5%
Receiver
± 6.5%
1. Not tested. Guaranteed by design.
2. tBTN is the nominal bit time in Serial Port, Sharp-IR, SIR and Consumer Remote Control modes. It is determined by the setting of the Baud Generator Divisor registers.
3. tCWN is the nominal pulse width of the modulation signal for Sharp-IR and Consumer Remote Control modes. It
is determined by MCPW field (bits 7-5) of IRTXMC register and TXHSC bit (bit 2) of RCCFG register.
4. tCPN is the nominal period of the modulation signal for Sharp-IR and Consumer Remote Control modes. It is
determined by MCFR field (bits 4-0) of IRTXMC register and the TXHSC bit (bit 2) of RCCFG register.
5. tMMIN and tMMAX define the time range within which the period of the incoming subcarrier signal has to fall in
order for the signal to be accepted by the receiver. These time values are determined by the contents of the
IRRXDC register and the setting of RXHSC bit (bit 5) of RCCFG register.
tBT
Serial Port
tCMW
tCMP
Sharp-IR
Consumer Remote Control
tSPW
SIR
www.national.com
40
Revision 1.1
2.4.9
PC8374T
2.0 Device Characteristics
(Continued)
Glue Function Timing
Highest Active Main and Standby Supply Reference
Symbol Figure
Description
Reference Conditions
Min
Max
Main
tPD
11
VDD3 to REF5V Propagation Delay1
VDD5 = 0; VDD3 slew rate > 10 V/ms
1 ms
VSB5 = 0; VSB3 slew rate > 10 V/ms
1 ms
Standby
tPD
11
VSB3 to REF5V_STBY Propagation Delay1
1. Not tested. Guaranteed by design.
tPD
tPD
3.3V
1.5V
VDD3, VSB3
REF5V, REF5V_STBY
0V
Figure 11. REF5V and REF5V_STBY (AC Characteristics)
Resume Reset
Symbol Figure
Description
Reference Conditions
Min
Max
Units
20
100
ms
tRD
12
Rising Supply Delay1 (typ. 32 ms)
VSB5 > VTRIP and VSB3 > VSB3ON
tFD5
12
Falling VSB5 Supply Delay1
VSB5 < VTRIP and VSB3 > VSB3ON
100
ns
tGA
12
VSB5 and VSB3 Glitch Allowance1
VSB5 < VTRIP or VSB3 < VSB3OFF
100
ns
tFD3
12
Falling VSB3 Supply Delay1
VSB3 < VSB3OFF and VSB5 > VTRIP
100
ns
tR
12
Rise Time2
VSB3 > VSB3ON
100
ns
tF
12
Fall Time2
VSB3 > VSB3ON
100
ns
1. Not tested. Guaranteed by characterization.
2. Not tested. Guaranteed by design.
Revision 1.1
41
www.national.com
PC8374T
2.0 Device Characteristics
VSB3
(Continued)
VSB3ON
VSB3OFF
tGA
VSB5
VTRIP
2.0V
1.4V
0.8V
RSMRST
tFD5
tRD
tFD3
tRD
2.0V
1.4V
0.8V
1.4V
tR
tF
Figure 12. RSMRST (AC Characteristics)
PCI Reset Buffering
Symbol
Figure
Description
Reference Conditions
tPDR
13
Rise Propagation Delay
tR
13
tPDF
tF
Min
Max
Units
From RE of PCI_RESET to RE of
PCIRST_OUT, PCIRST_OUT2
30
ns
Rise Time
PCIRST_OUT, PCIRST_OUT2
50
ns
13
Fall Propagation Delay
From FE of PCI_RESET to FE of
IDE_RSTDRV
20
ns
13
Fall Time
IDE_RSTDRV
15
ns
VDD3 = 3.3V ±10%
PCI_RESET
tPDF
IDE_RSTDRV
tF
2.0V
1.4V
0.8V
tPDR
PCIRST_OUT,
PCIRST_OUT2
2.0V
1.4V
0.8V
tR
Figure 13. Reset Outputs
www.national.com
42
Revision 1.1
PC8374T
2.0 Device Characteristics
(Continued)
Main Power Good
Symbol Figure
Description
Reference Conditions
Min
Max
Units
100
120
ms
tPSD
−
Low-to-High Delay1
After RE of PWRGD_PS
tS3D
−
High-to-Low Delay1
After FE of SLP_S3
20
ns
tR
−
PWRGD_3V Rise Time1
0.8V to 2.0V
50
ns
tF
−
PWRGD_3V Fall Time1
2.0V to 0.8V
50
ns
1. Not tested. Guaranteed by design.
Power Distribution Control
Symbol Figure
Description
Reference Conditions
Min
Max
Units
tPB
−
BKFD_CUT Propagation Delay1
PWRGD_PS or SLP_S3 to BKFD_CUT
1
µs
tTB
−
BKFD_CUT Transition Time1
0.8V to 2.0V
50
ns
tPL
14
LATCHED_BF_CUT Propagation
Delay1
BKFD_CUT or SLP_S5 to
LATCHED_BF_CUT
1
µs
tTL
14
LATCHED_BF_CUT Transition Time1 0.8V to 2.0V
50
ns
1. Not tested. Guaranteed by design.
SLP_S5
BKFD_CUT
2.0V
LATCHED_BF_CUT 1.4V
0.8V
tPL
tPL
tPL
tPL
tTL
tTL
2.0V
1.4V
0.8V
Figure 14. BKFD_CUT and LATCHED_BF_CUT (AC Characteristics)
Revision 1.1
43
www.national.com
PC8374T
2.0 Device Characteristics
(Continued)
Main Power Supply Control
Symbol Figure
Description
Reference Conditions
Min
Max
Units
(CPU_PRESENT = 1) or (SLP_S3 = 0) or
(ETC event occurred) to RE of PS_ON
1
µs
From whichever occurs last:
(CPU_PRESENT = 0), (SLP_S3 = 1), (No
ETC event and RE on SLP_S3)
to FE of PS_ON
1
µs
tPR
−
tPF
−
Fall Propagation
tR
−
Rise Time1,2
0.8V to 2.0V
50
ns
tF
−
Fall Time1
2.0V to 0.8V
50
ns
Rise Propagation Delay1,2
Delay1
1. Not tested. Guaranteed by design.
2. Test conditions: CL = 50 pF and 1 KΩ external resistor to VSB5.
SMBus Voltage Translation and Isolation Timing
Symbol
Figure
tSMBR
−
Rise Time (all signals)
tSMBF
−
Fall Time (all signals)
tSMBD
−
Type of
Requirement1
Description
Propagation Delay (each signal pair, in both
directions)
Min
Max
Unit
Input
10002,3
ns
Input
2503
ns
Output
3002,4
ns
Output
5002,4
ns
1. An “Input” type is a value the PC8374T device expects from the system; an “Output” type is a value the
PC8374T device provides to the system.
2. Test conditions: RL = 1 KΩ to VDD3 = 2.25V or 3.3V, or RL = 1.5 KΩ to VDD5 = 5V and CL = 400 pF to GND.
3. Not tested. Guaranteed by design.
4. Not tested. Guaranteed by characterization.
www.national.com
44
Revision 1.1
2.4.10
PC8374T
2.0 Device Characteristics
(Continued)
SWC Timing
Wake-Up Inputs at VSB3 Power Switching
Symbol
Figure
tEWIV
15
Description
Reference Conditions
External Wake-Up Inputs Valid1
At VSB3 power on, after the
32 KHz Domain is toggling
Min
Max
24576 * tCP2
32768 * tCP
1. Not tested. Guaranteed by characterization.
2. tCP is the cycle time of the 32 KHz clock domain (see “Low-Frequency Clock Timing” on page 32).
VSB3ON
VSB3OFF
VSB3 (Power)
tIRST
VSB Power-Up Reset
(Internal)
t32KW + t32KVAL
32 KHz Domain
(Internal)
tEWIV
GPIOE17-16,
GPIOE14-10,
GPIOE07-00,
RI
KBCLK, MCLK
KBDAT, MDAT
Figure 15. Inputs at VSB3 Power Switching
Wake-Up Inputs at VDD3 Power Switching
Symbol
Figure
tEWIV
16
Description
Reference Conditions
External Wake-Up Inputs Valid1 After VDD3 power on2
Min
Max
24576 * tCP3
32768 * tCP
1. Not tested. Guaranteed by characterization.
2. The 32 KHz clock domain is assumed to be toggling at VDD3 power stable.
3. tCP is the cycle time of the 32 KHz clock domain (see “Low-Frequency Clock Timing” on page 32).
VDD3 (Power)
VDD3ON
VDD3OFF
tEWIV
GPIOE17-16,
GPIOE14 -10,
GPIOE07-00
(VDDLOAD = 1)
Figure 16. Wake-Up Inputs at VDD3 Power Switching
Revision 1.1
45
www.national.com
PC8374T
2.0 Device Characteristics
2.4.11
(Continued)
SMBus Timing
Type of
Requirement1
Symbol
Figure
Description
tSMBR
17
Rise time (HMSCL and HMSDA)
tSMBF
17
Fall time (HMSCL and HMSDA)
Min
Max
Unit
Input2
10003
ns
Input
3003
ns
Output2
2504
ns
tSMBCKL
17
Clock low period (HMSCL)
Input
4.7
µs
tSMBCKH
17
Clock high period (HMSCL)
Input
4
µs
tSMBCY
18
Clock cycle (HMSCL)
Input
10
µs
tSMBDS
18
Data setup time (before clock rising edge)
Input
250
ns
Output
250
ns
Input
0
ns
Output2
300
ns
2
tSMBDH
18
Data hold time (after clock falling edge)
tSMBPS
19
Stop condition setup time (clock before data)
Input
4
µs
tSMBSH
19
Start condition hold time (clock after data)
Input
4
µs
tSMBBUF
19
Bus free time between Stop and Start
conditions (HMSDA)
Input
4.7
µs
tSMBRS
20
Restart condition setup time (clock before
data)
Input
4.7
µs
tSMBRH
20
Restart condition hold time (clock after data)
Input
4
µs
tSMBLEX
-
Cumulative clock low extend time from Start
to Stop (HMSCL)
Output
tSMBTO
-
Clock low time-out (HMSCL)
Input
ms
253
ms
253,5
Output
ms
353,6
1. An “Input” type is a value the PC8374T expects from the system; an “Output” type is a value the PC8374T
provides to the system.
2. Test conditions: RL = 1 KΩ to VSB = 3.3V, CL = 400 pF to GND.
3. Not tested. Guaranteed by design.
4. Not tested. Guaranteed by characterization.
5. The PC8374T detects a time-out condition if HMSCL is held low for more than tSMBTO.
6. On detection of a time-out condition, the PC8374T resets the SMBus Interface no later than tSMBTO.
tSMBCKH
3.0V
2.5V
2.5V
0.4V
0.4V
tSMBR
0.4V
tSMBCKL
0.4V
tSMBF
Figure 17. SMBus Signals (HMSCL and HMSDA) Rising Time and Falling Time
www.national.com
46
Revision 1.1
PC8374T
2.0 Device Characteristics
(Continued)
HMSDA
tSMBDH
tSMBDS
HMSCL
tSMBCY
Figure 18. SMBus Data Bit Timing
Start Condition
Stop Condition
HMSDA
tSMBDS
HMSCL
tSMBPS
tBUF
tSMBSH
Figure 19. SMBus Start and Stop Condition Timing
Restart Condition
HMSDA
HMSCL
tSMBDS
tSMBRS
tSMBRH
Figure 20. SMBus Restart Condition TIming
2.5
PACKAGE THERMAL INFORMATION
Thermal resistance (degrees C/W) ThetaJC and ThetaJA values for the PC8374T package are as follows:
Table 4. Theta (Θ) J Values
Package Type
128-PQFP
[email protected] lfpm [email protected] lfpm [email protected] lfpm [email protected] lfpm
41.5
33.7
30.1
27.7
ThetaJC
16.8
Note: Airflow for ThetaJA values is measured in linear feet per minute (lfpm).
Revision 1.1
47
www.national.com
PC8374T SafeKeeper  Desktop TrustedI/O
Physical Dimensions
All dimensions are in millimeters
Plastic Quad Flatpack (PQFP), JEDEC
Order Number PC8374T-xxx/VLA
NS Package Number VLA128A
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body, or
(b) support or sustain life, and whose failure to perform,
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in a significant injury to the user.
2. A critical component is any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
BANNED SUBSTANCE COMPLIANCE
National Semiconductor certifies that the products and packing materials meet the provisions of the Customer Products
Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification
(CSP-9-111S2) and contain no ‘‘Banned Substances’’ as defined in CSP-9-111S2.
National Semiconductor
Corporation
Americas
Email:
[email protected]
www.national.com
National Semiconductor
Europe
Fax: +49 (0) 180-530 85 86
Email: [email protected]
Deutsch Tel: +49 (0) 69 9508 6208
English Tel: +44 (0) 870 24 0 2171
Français Tel: +33 (0) 1 41 91 87 90
National Semiconductor
Asia Pacific Customer
Response Group
Tel: 65-2544466
Fax: 65-2504466
Email: [email protected]
National Semiconductor
Japan Ltd.
Tel: 81-3-5639-7560
Fax: 81-3-5639-7507
Email: [email protected]
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.