ETC CS5332/D

CS5332
Two-Phase Buck Controller
with Integrated Gate
Drivers for VRM 9.0
The CS5332 is a two–phase step down controller which
incorporates all control functions required to power high performance
processors and high current power supplies. Proprietary multi–phase
architecture guarantees balanced load current distribution and reduces
overall solution cost in high current applications. Enhanced V2
control architecture provides the fastest possible transient response,
excellent overall regulation, and ease of use.
The CS5332 multi–phase architecture reduces output voltage and
input current ripple, allowing for a significant reduction in inductor
values and a corresponding increase in inductor current slew rate. This
approach allows a considerable reduction in input and output capacitor
requirements, as well as reducing overall solution size and cost.
Features
• Enhanced V2 Control Method
• VRM 9.0 Compatible 5–Bit DAC with 1.0% Accuracy
• Adjustable Output Voltage Positioning
• 4 On–Board GATE Drivers
• 200 kHz to 800 kHz Operation Set by Resistor
• Current Sensed through Buck Inductors, or Sense Resistors
• Hiccup Mode Current Limit
• Individual Current Limits for Each Phase
• On–Board Current Sense Amplifiers
• 3.3 V, 1.0 mA Reference Output
• 5.0 V and/or 12 V Operation
• On/Off Control (through Soft Start Pin)
• Power Good Output with Internal Delay
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SO–28L
DW SUFFIX
CASE 751F
28
1
MARKING DIAGRAM
28
CS5332
AWLYYWW
1
A
WL, L
YY, Y
WW, W
= Assembly Location
= Wafer Lot
= Year
= Work Week
PIN CONNECTIONS
1
28
ROSC
VCCL
VCCL1
GATE(L)1
GND1
GATE(H)1
VCCH1
LGND
SS
VCCL2
GATE(L)2
GND2
GATE(H)2
VCCH2
COMP
VFB
VDRP
CS1
CS2
CSREF
PWRGD
VID0
VID1
VID2
VID3
VID4
ILIM
REF
ORDERING INFORMATION
Device
 Semiconductor Components Industries, LLC, 2001
May, 2001 – Rev. 10
1
Package
Shipping
CS5332GDW28
SO–28L
27 Units/Rail
CS5332GDWR28
SO–28L
1000 Tape & Reel
Publication Order Number:
CS5332/D
CS5332
300 nH
+12 V
+ 3 × 16SP270M
+5 V
1.0 µF
1.0 µF
1.0 µF
ENABLE
1.0 nF
2.74 k
COMP
VFB
VDRP
CS1
CS2
CSREF
PWRGD
VID0
VID1
VID2
VID3
VID4
ILIM
REF
25.4 k
10 k
PWRGD
VID0
VID1
600 nH
56.2 k
1.0 nF
ROSC
VCCL
VCCL1
GATE(L)1
GND1
GATE(H)1
VCCH1
LGND
SS
VCCL2
GATE(L)2
GND2
GATE(H)2
VCCH2
+
8 × 4SP560M
VOUT
CS5332
1.0 nF
12 × 10 µF
0.1 µF
VID2
VID3
1.0 µF
4.87 k
0.1 µF
VID4
1.0 k
25.5 k
.01 µF
.01 µF
600 nH
25.5 k
.01 µF
Figure 1. Application Diagram, Pentium 4 Converter
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2
CS5332
ABSOLUTE MAXIMUM RATINGS*
Rating
Operating Junction Temperature
Lead Temperature Soldering:
Reflow: (SMD styles only) (Note NO TAG)
Storage Temperature Range
ESD Susceptibility (Human Body Model)
Value
Unit
150
°C
230 peak
°C
–65 to +150
°C
2.0
kV
1. 60 second maximum above 183°C.
*The maximum package power dissipation must be observed.
ABSOLUTE MAXIMUM RATINGS
Pin Name
Pin Symbol
VMAX
VMIN
ISOURCE
ISINK
Power for Logic
VCCL
16 V
–0.3 V
N/A
50 mA
Power for GATE(L)1
VCCL1
16 V
–0.3 V
N/A
1.5 A, 1.0 µs 200 mA DC
Power for GATE(L)2
VCCL2
16 V
–0.3 V
N/A
1.5 A, 1.0 µs 200 mA DC
Power for GATE(H)1
VCCH1
20 V
–0.3 V
N/A
1.5 A, 1.0 µs 200 mA DC
Power for GATE(H)2
VCCH2
20 V
–0.3 V
N/A
1.5 A, 1.0 µs 200 mA DC
Power Good Output
PWRGD
6.0 V
–0.3 V
1.0 mA
20 mA
Soft Start Capacitor
SS
6.0 V
–0.3 V
1.0 mA
1.0 mA
Voltage Feedback Compensation
Network
COMP
6.0 V
–0.3 V
1.0 mA
1.0 mA
Voltage Feedback Input
VFB
6.0 V
–0.3 V
1.0 mA
1.0 mA
Output for Adjusting Adaptive
Voltage Positioning
VDRP
6.0 V
–0.3 V
1.0 mA
1.0 mA
Frequency Resistor
ROSC
6.0 V
–0.3 V
1.0 mA
1.0 mA
Reference Output
REF
6.0 V
–0.3 V
1.0 mA
50 mA
High–Side FET Drivers
GATE(H)1–2
20 V
–0.3 V DC
–2.0 V for 100 nS
1.5 A, 1.0 µs 200 mA DC
1.5 A, 1 µs 200 mA DC
Low–Side FET Drivers
GATE(L)1–2
16 V
–0.3 V DC
–2.0 V for 100 nS
1.5 A, 1.0 µs 200 mA DC
1.5 A, 1.0 µs 200 mA DC
Return for Logic
LGND
N/A
N/A
50 mA
N/A
Return for #1 Driver
GND1
0.3 V
–0.3 V
2.0 A, 1.0 µs 200 mA DC
N/A
Return for #2 Driver
GND2
0.3 V
–0.3 V
2.0 A, 1.0 µs 200 mA DC
N/A
Current Sense for Phases 1 – 2
CS1–CS2
6.0 V
–0.3 V
1.0 mA
1.0 mA
Current Limit Set Point
ILIM
6.0 V
–0.3 V
1.0 mA
1.0 mA
Current Sense Reference
CSREF
6.0 V
–0.3 V
1.0 mA
1.0 mA
Voltage ID DAC Inputs
VID0–4
6.0 V
–0.3 V
1.0 mA
1.0 mA
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3
CS5332
ELECTRICAL CHARACTERISTICS (0°C < TA < 70°C; 0°C < TJ < 125°C; 4.7 V < VCCL < 14 V; 8.0 V < VCCH < 20 V;
CGATE(H) = 3.3 nF, CGATE(L) = 3.3 nF, RR(OSC) = 32.4 k, CCOMP = 1.0 nF, CSS = 0.1 µF, CREF = 0.1 µF, DAC Code 10000, CVCC = 1.0 µF,
ILIM ≥ 1.0 V; unless otherwise specified.)
Test Conditions
Characteristic
Min
Typ
Max
Unit
± 1.0
%
Voltage Identification DAC (0 = Connected to VSS; 1 = Open or Pull–up to 3.3 V)
Measure VFB = COMP
Accuracy (all codes)
VID4
VID3
VID2
VID1
VID0
1
1
1
1
1
–
1.064
1.075
1.086
V
1
1
1
1
0
–
1.089
1.100
1.111
V
1
1
1
0
1
–
1.114
1.125
1.136
V
1
1
1
0
0
–
1.139
1.150
1.162
V
1
1
0
1
1
–
1.163
1.175
1.187
V
1
1
0
1
0
–
1.188
1.200
1.212
V
1
1
0
0
1
–
1.213
1.225
1.237
V
1
1
0
0
0
–
1.238
1.250
1.263
V
1
0
1
1
1
–
1.262
1.275
1.288
V
1
0
1
1
0
–
1.287
1.300
1.313
V
1
0
1
0
1
–
1.312
1.325
1.338
V
1
0
1
0
0
–
1.337
1.350
1.364
V
1
0
0
1
1
–
1.361
1.375
1.389
V
1
0
0
1
0
–
1.386
1.400
1.414
V
1
0
0
0
1
–
1.411
1.425
1.439
V
1
0
0
0
0
–
1.436
1.450
1.465
V
0
1
1
1
1
–
1.460
1.475
1.490
V
0
1
1
1
0
–
1.485
1.500
1.515
V
0
1
1
0
1
–
1.510
1.525
1.540
V
0
1
1
0
0
–
1.535
1.550
1.566
V
0
1
0
1
1
–
1.559
1.575
1.591
V
0
1
0
1
0
–
1.584
1.600
1.616
V
0
1
0
0
1
–
1.609
1.625
1.641
V
0
1
0
0
0
–
1.634
1.650
1.667
V
0
0
1
1
1
–
1.658
1.675
1.692
V
0
0
1
1
0
–
1.683
1.700
1.717
V
0
0
1
0
1
–
1.708
1.725
1.742
V
0
0
1
0
0
–
1.733
1.750
1.768
V
0
0
0
1
1
–
1.757
1.775
1.793
V
0
0
0
1
0
–
1.782
1.800
1.818
V
0
0
0
0
1
–
1.807
1.825
1.843
V
0
0
0
0
0
–
1.832
1.850
1.869
V
Input Threshold
VID4, VID3, VID2, VID1, VID0
1.00
1.25
1.50
V
Input Pull–up Resistance
VID4, VID3, VID2, VID1, VID0
25
50
100
kΩ
3.15
3.30
3.45
V
Pull–up Voltage
–
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4
CS5332
ELECTRICAL CHARACTERISTICS (continued) (0°C < TA < 70°C; 0°C < TJ < 125°C; 4.7 V < VCCL < 14 V; 8.0 V < VCCH < 20 V;
CGATE(H) = 3.3 nF, CGATE(L) = 3.3 nF, RR(OSC) = 32.4 k, CCOMP = 1.0 nF, CSS = 0.1 µF, CREF = 0.1 µF, DAC Code 10000, CVCC = 1.0 µF,
ILIM ≥ 1.0 V; unless otherwise specified.)
Characteristic
Test Conditions
Min
Typ
Max
Unit
Power–Good Output
Power Good Fault Delay
CSREF = VDAC to VDAC ± 15%
25
50
125
µs
Output Low Voltage
CSREF = 1.0 V, IPWRGD = 4.0 mA
–
0.25
0.40
V
Output Leakage Current
CSREF = 1.45 V, PWRGD = 5.5 V
–
0.1
10.0
µA
Lower Threshold
% of Nominal VID Code
–18
–14
–10
%
Upper Threshold
–
1.9
2.0
2.1
V
28.5
31
33.5
µA
Voltage Feedback Error Amplifier
VFB Bias Current (Note 2.)
1.0 V < VFB < 1.9 V
COMP Source Current
COMP = 0.5 V to 2.0 V;
VFB = 1.8 V; DAC = 00000
15
30
60
µA
COMP Sink Current
COMP = 0.5 V to 2.0 V;
VFB = 1.9 V; DAC = 00000
15
30
60
µA
COMP Max Voltage
VFB = 1.8 V COMP Open; DAC = 00000
2.4
2.7
–
V
COMP Min Voltage
VFB = 1.9 V COMP Open; DAC = 00000
–
0.1
0.2
V
Transconductance
–10 µA < ICOMP < +10 µA
–
32
–
mmho
–
2.5
–
MΩ
Output Impedance
–
Open Loop DC Gain
Note 3.
60
90
–
dB
Unity Gain Bandwidth
0.01 µF COMP Capacitor
–
400
–
kHz
–
70
–
dB
–
PSRR @ 1.0 kHz
Soft Start
Soft Start Charge Current
0.2 V ≤ SS ≤ 3.0 V
15
30
50
µA
Soft Start DisCharge Current
0.2 V ≤ SS ≤ 3.0 V
4.0
7.5
13.0
µA
Hiccup Mode Charge/Discharge Ratio
–
3.0
4.0
–
–
Peak Soft Start Charge Voltage
–
3.3
4.0
4.2
V
Soft Start DisCharge Threshold Voltage
–
0.20
0.27
0.34
V
Minimum Pulse Width
Measured from CSx to GATE(H)x
V(VFB) = V(CSREF) = 1.0 V, V(COMP) = 1.5 V
60 mV step applied between VCSX and
VCREF
–
350
515
ns
Channel Start Up Offset
V(CS1) = V(CS2) = V(VFB) = V(CSREF) = 0 V;
Measure V(COMP) when GATE(H)1,
GATE(H)2, switch high
0.3
0.4
0.5
V
PWM Comparators
2. The VFB Bias Current changes with the value of ROSC per Figure 4.
3. Guaranteed by design. Not tested in production.
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CS5332
ELECTRICAL CHARACTERISTICS (continued) (0°C < TA < 70°C; 0°C < TJ < 125°C; 4.7 V < VCCL < 14 V; 8.0 V < VCCH < 20 V;
CGATE(H) = 3.3 nF, CGATE(L) = 3.3 nF, RR(OSC) = 32.4 k, CCOMP = 1.0 nF, CSS = 0.1 µF, CREF = 0.1 µF, DAC Code 10000, CVCC = 1.0 µF,
ILIM ≥ 1.0 V; unless otherwise specified.)
Characteristic
Test Conditions
Min
Typ
Max
Unit
GATE(H) and GATE(L)
High Voltage (AC)
Note 4. Measure VCCLX – GATE(L)X or
VCCHX – GATE(H)X
–
0
1.0
V
Low Voltage (AC)
Note 4. Measure GATE(L)X or GATE(H)X
–
0
0.5
V
Rise Time GATE(H)X
1.0 V < GATE < 8.0 V; VCCHX = 10 V
–
35
80
ns
Rise Time GATE(L)X
1.0 V < GATE < 8.0 V; VCCLX = 10 V
–
35
80
ns
Fall Time GATE(H)X
8.0 V > GATE > 1.0 V; VCCHX = 10 V
–
35
80
ns
Fall Time GATE(L)X
8.0 V > GATE > 1.0 V; VCCLX = 10 V
–
35
80
ns
GATE(H) to GATE(L) Delay
GATE(H)X < 2.0 V, GATE(L)X > 2.0 V
30
65
110
ns
GATE(L) to GATE(H) Delay
GATE(L)X < 2.0 V, GATE(H)X > 2.0 V
30
65
110
ns
GATE Pull–down
Force 100 µA into GATE Driver with no power
applied to VCCHX and VCCLX = 2.0 V.
–
1.2
1.6
V
Oscillator
Switching Frequency
Measure any phase (ROSC = 32.4k)
300
400
500
kHz
Switching Frequency
Note 4. Measure any phase (ROSC = 63.4 k)
150
200
250
kHz
Switching Frequency
Note 4. Measure any phase (ROSC = 16.2 k)
600
800
1000
kHz
–
1.00
–
V
Rising Edge Only
165
180
195
deg
VDRP Output Voltage to DACOUT
Offset
CS1 = CS2 = CSREF, VFB = COMP
Measure VDRP – COMP
–15
–
15
mV
Maximum VDRP Voltage
(CS1 = CS2) – CREF = 50 mV,
VFB = COMP, Measure VDRP – COMP
240
310
380
mV
2.75
3.15
3.65
V/V
ROSC Voltage
Phase Delay
–
Adaptive Voltage Positioning
Current Sense Amp to VDRP Gain
–
Current Sensing and Sharing
CSREF Input Bias Current
V(CSx) = V(CSREF) = 0 V
–
0.5
4.0
µA
CS1–CS2 Input Bias Current
V(CSx) = V(CSREF) = 0 V
–
0.2
2.0
µA
2.80
3.15
3.53
V/V
–5.0
–
5.0
mV
0
–
VCCL – 2
V
Current Sense Amplifiers Gain
–
Current Sense Amp Mismatch
Note 4. 0 ≤ (CSx – CSREF) ≤ 50 mV
Current Sense Amplifiers Input
Common Mode Range Limit
Note 4.
Current Sense Input to ILIM Gain
0.25 V < ILIM < 1.20 V
5.00
6.25
8.00
V/V
Current Limit Filter Slew Rate
Note 4.
4.0
10
26
mV/µs
ILIM Bias Current
0 < ILIM < 1.0 V
–
0.1
1.0
µA
90
105
135
mV
1.0
–
–
mHz
Single Phase Pulse by Pulse
Current Limit: V(CSx) – V(CSREF)
Current Share Amplifier Bandwidth
–
Note 4.
4. Guaranteed by design. Not tested in production.
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CS5332
ELECTRICAL CHARACTERISTICS (continued) (0°C < TA < 70°C; 0°C < TJ < 125°C; 4.7 V < VCCL < 14 V; 8.0 V < VCCH < 20 V;
CGATE(H) = 3.3 nF, CGATE(L) = 3.3 nF, RR(OSC) = 32.4 k, CCOMP = 1.0 nF, CSS = 0.1 µF, CREF = 0.1 µF, DAC Code 10000, CVCC = 1.0 µF,
ILIM ≥ 1.0 V; unless otherwise specified.)
Characteristic
Test Conditions
Min
Typ
Max
Unit
3.2
3.3
3.4
V
Reference Output
VREF Output Voltage
0 mA < I(VREF) < 1.0 mA
General Electrical Specifications
VCCL Operating Current
VFB = COMP (no switching)
–
20.0
24.5
mA
VCCL1 Operating Current
VFB = COMP (no switching)
–
4.0
5.5
mA
VCCL2 Operating Current
VFB = COMP (no switching)
–
4.0
5.5
mA
VCCH1 Operating Current
VFB = COMP (no switching)
–
2.8
4.0
mA
VCCH2 Operating Current
VFB = COMP (no switching)
–
2.5
3.5
mA
VCCL Start Threshold
GATEs switching, Soft Start charging
4.05
4.40
4.70
V
VCCL Stop Threshold
GATEs stop switching, Soft Start discharging
3.75
4.20
4.60
V
VCCL Hysteresis
GATEs not switching, Soft Start not charging
100
200
300
mV
VCCH1 Start Threshold
GATEs switching, Soft Start charging
1.8
2.0
2.2
V
VCCH1 Stop Threshold
GATEs stop switching, Soft Start discharging
1.55
1.75
1.90
V
VCCH1 Hysteresis
GATEs not switching, Soft Start not charging
100
200
300
mV
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7
CS5332
PACKAGE PIN DESCRIPTION
PACKAGE PIN #
28 Lead SO Wide
PIN SYMBOL
1
COMP
2
VFB
Voltage Feedback Pin. To use Adaptive Voltage Positioning
(AVP) select an offset voltage at light load and connect a
resistor between VFB and VOUT. The input current of the VFB
pin and the resistor value determine output voltage offset for
zero output current. Short VFB to VOUT for no AVP.
3
VDRP
Current sense output for AVP. The offset of this pin above the
DAC voltage is proportional to the output current. Connect a
resistor from this pin to VFB to set amount AVP or leave this
pin open for no AVP.
4–5
CS1–CS2
Current sense inputs. Connect current sense network for the
corresponding phase to each input.
6
CSREF
Reference for current sense amplifiers and input for Power
Good comparators. To balance input offset voltages between
the inverting and non–inverting inputs of the current sense
amplifiers, connect a resistor between CSREF and the output
voltage. The value should be 2/5 of the value of the resistors
connected to the CSx pins.
7
PWRGD
Power–Good Output. Open collector output goes low when
the CSREF is out of regulation.
8–12
VID4–VID0
Voltage ID DAC inputs. These pins are internally pulled up to
3.3 V if left open.
13
ILIM
Sets threshold for current limit. Connect to reference through
a resistive divider.
14
REF
Reference output. Decouple with 0.1 µF to LGND
15
VCCH2
16
GATE(H)2
17
GND2
18
GATE(L)2
19
VCCL2
20
SS
Soft Start capacitor pin. The Soft Start capacitor controls both
Soft Start time and hiccup mode frequency. The COMP pin is
clamped below Soft Start during start up and hiccup mode.
21
LGND
Return for internal control circuits and IC substrate connection.
22
VCCH1
Power for GATE(H)1. UVLO Sense for High Side Driver supply connects to this pin.
23
GATE(H)1
24
GND1
25
GATE(L)1
26
VCCL1
Power for GATE(L)1.
27
VCCL
Power for internal control circuits. UVLO Sense for Logic
connects to this pin.
28
ROSC
A resistor from this pin to ground sets operating frequency
and VFB bias current.
FUNCTION
Output of the error amplifier and input for the PWM
comparators.
Power for GATE(H)2.
High side driver #2.
Return for #2 drivers.
Low side driver #2.
Power for GATE(L)2.
High side driver #1.
Return for #1 drivers.
Low side driver #1.
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CS5332
−
VCCL
Start
+Stop
−
−
+
DAC
PH 1
2.0 V
1.8 V
S
Reset
Dominant
+
DACOUT
VID1
VID2
VCCH1
Start
Stop
+
−
+
VID0
4.4 V
4.2 V
−
3.3 V
REF
REF
PWRGD
PWMC1
VID3
Delay
CO1
VID4
GATE(H)1
Gate
Nonoverlap
VCCL1
R
GATE(L)1
+
GND1
MAXC1
+
LGN
D
−
CO1
0.33 V
FAULT
VCCH2
−
PH 2
+
−
S
2.0 V
AVPA
Reset
Dominant
VDRP
−
−
+
+
PWMC2
CSA1
−
CO1
–14%
CO2
+
CO2
CSA2
−
× 2.0
+
ILIM
Filter
−
CS2
CO2
+
+
CS1
−
+
−
CSREF
GND2
FAULT
0.33 V
Offset
Current
Source
Gen
EA
DACOUT
PH 1
SS
Discharge
Current
OSC
+
−
R
−
+
Set
Dominant
S
+
FAULT
FAULT
+
−
SS
Discharge
Current
GATE(L)2
+
MAXC2
−
+
SS
Charge
Current
VCCL2
R
−
ILIM
GATE(H)2
Gate
Nonoverlap
−
COMP
SS
Figure 2. Block Diagram
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9
VFB ROSC
PH 2
BIAS
CS5332
TYPICAL PERFORMANCE CHARACTERISTICS
80
900
VFB Bias Current, µA
800
Frequency, kHz
700
600
500
400
300
60
40
20
200
100
10
20
30
40
50
ROSC Value, kΩ
60
0
10
70
Figure 3. Oscillator Frequency
30
100
100
80
80
Time, ns
120
60
60
70
80
60
40
40
20
20
0
0
0
2
4
6
8
10
12
14
16
0
2
4
Load Capacitance, nF
6
8
10
12
14
16
Load Capacitance, nF
Figure 5. GATE(H) Rise–time vs. Load Capacitance
measured from 1.0 V to 4.0 V with VCC at 5.0 V.
Figure 6. GATE(H) Fall–time vs. Load Capacitance
measured from 4.0 V to 1.0 V with VCC at 5.0 V.
120
120
100
100
80
80
Time, ns
Time, ns
40
50
ROSC Value, kΩ
Figure 4. VFB Bias Current vs. ROSC Value
120
Time, ns
20
60
60
40
40
20
20
0
0
0
2
4
6
8
10
12
14
16
0
Load Capacitance, nF
2
4
6
8
10
12
14
16
Load Capacitance, nF
Figure 7. GATE(L) Rise–time vs. Load Capacitance
measured from 4.0 V to 1.0 V with VCC at 5.0 V.
Figure 8. GATE(L) Fall–time vs. Load Capacitance
measured from 4.0 V to 1.0 V with VCC at 5.0 V.
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CS5332
APPLICATIONS INFORMATION
FIXED FREQUENCY MULTI–PHASE CONTROL
comparator rises and terminates the PWM cycle. If the
inductor starts the cycle with a higher current, the PWM
cycle will terminate earlier providing negative feedback.
The CS5332 provides a CX input for each phase, but the
CSREF, VFB and COMP inputs are common to all phases.
Current sharing is accomplished by referencing all phases to
the same VFB and COMP pins, so that a phase with a larger
current signal will turn off earlier than phases with a smaller
current signal.
Including both current and voltage information in the
feedback signal allows the open loop output impedance of
the power stage to be controlled. If the COMP pin is held
steady and the inductor current changes, there must also be
a change in the output voltage. Or, in a closed loop
configuration when the output current changes, the COMP
pin must move to keep the same output voltage. The required
change in the output voltage or COMP pin depends on the
scaling of the current feedback signal and is calculated as
In a multi–phase converter, multiple converters are
connected in parallel and are switched on at different times.
This reduces output current from the individual converters
and increases the apparent ripple frequency. Because several
converters are connected in parallel, output current can ramp
up or down faster than a single converter (with the same
value output inductor) and heat is spread among multiple
components.
The CS5332 uses a two–phase, fixed frequency,
Enhanced V2 architecture. Each phase is delayed 180° from
the previous phase. Normally GATE(H) transitions high at
the beginning of each oscillator cycle. Inductor current
ramps up until the combination of the current sense signal
and the output ripple trip the PWM comparator and bring
GATE(H) low. Once GATE(H) goes low, it will remain low
until the beginning of the next oscillator cycle. While
GATE(H) is high, the Enhanced V2 loop will respond to line
and load transients. Once GATE(H) is low, the loop will not
respond again until the beginning of the next cycle.
Therefore, constant frequency Enhanced V2 will typically
respond within the off–time of the converter.
The Enhanced V2 architecture measures and adjusts
current in each phase. An additional input (CX) for inductor
current information has been added to the V2 loop for each
phase as shown in Figure 9.
SWNODE
L
RL
CSX
+
CSA
RS
OFFSET
CSREF
The single–phase power stage output impedance is;
Single Stage Impedance VI RS CSA Gain.
The multi–phase power stage output impedance is the
single–phase output impedance divided by the number of
phases. The output impedance of the power stage determines
how the converter will respond during the first few µs of a
transient before the feedback loop has repositioned the
COMP pin.
The peak output current of each phase can also be
calculated from;
+
V
VFB VOFFSET
Ipkout (per phase) COMP
RS CSA Gain
+
+
VOUT
V RS CSA Gain I
PWM
COMP
Figure 10 shows the step response of a single phase with
the COMP pin at a fixed level. Before T1 the converter is in
normal steady state operation. The inductor current provides
the PWM ramp through the Current Sense Amplifier. The
PWM cycle ends when the sum of the current signal, voltage
signal and OFFSET exceed the level of the COMP pin. At
T1 the output current increases and the output voltage sags.
The next PWM cycle begins and the cycle continues longer
than previously while the current signal increases enough to
make up for the lower voltage at the VFB pin and the cycle
ends at T2. After T2 the output voltage remains lower than
at light load and the current signal level is raised so that the
sum of the current and voltage signal is the same as with the
original load. In a closed loop system the COMP pin would
move higher to restore the output voltage to the original level.
+
VFB
+
DACOUT
+
E.A.
+
COMP
Figure 9. Enhanced V2 Current Sense Scheme
The inductor current is measured across RS, amplified by
CSA and summed with the OFFSET and Output Voltage at
the non–inverting input of the PWM comparator. The
inductor current provides the PWM ramp and as inductor
current increases the voltage on the positive pin of the PWM
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CS5332
considered when setting the ILIM threshold. If a more
accurate current sense is required than inductive sensing can
provide, current can be sensed through a resistor as shown
in Figure 9.
SWNODE
Current Sharing Accuracy
PCB traces that carry inductor current can be used as part
of the current sense resistance depending on where the
current sense signal is picked off. For accurate current
sharing, the current sense inputs should sense the current at
the same point for each phase and the connection to the
CSREF should be made so that no phase is favored. (In some
cases, especially with inductive sensing, resistance of the
pcb can be useful for increasing the current sense
resistance.) The total current sense resistance used for
calculations must include any pcb trace between the CS
inputs and the CSREF input that carries inductor current.
Current Sense Amplifier Input Mismatch and the value of
the current sense element will determine the accuracy of
current sharing between phases. The worst case Current
Sense Amplifier Input Mismatch is 5.0 mV and will typically
be within 3.0 mV. The difference in peak currents between
phases will be the CSA Input Mismatch divided by the current
sense resistance. If all current sense elements are of equal
resistance, a 3.0 mV mismatch with a 2.0 mΩ sense resistance
will produce a 1.5 A difference in current between phases.
VFB (VOUT)
CSA Out
COMP – Offset
CSA Out + VFB
T1
T2
Figure 10. Open Loop Operation
Inductive Current Sensing
For lossless sensing current can be sensed across the
inductor as shown in Figure 11. In the diagram, L is the
output inductance and RL is the inherent inductor resistance.
To compensate the current sense signal the values of R1 and
C1 are chosen so that L/RL = R1 × C1. If this criteria is met
the current sense signal will be the same shape as the
inductor current, the voltage signal at Cx will represent the
instantaneous value of inductor current and the circuit can be
analyzed as if a sense resistor of value RL was used as a sense
resistor (RS).
Operation at > 50% Duty Cycle
For operation at duty cycles above 50% Enhanced V2
will exhibit subharmonic oscillation unless a compensation
ramp is added to each phase. A circuit like the one on the left
side of Figure 12 can be added to each current sense network
to implement slope compensation. The value of R1 can be
varied to adjust the ramp size.
R1
SWNODE
CSX
L
C1
RL
VOUT
+
CSA
OFFSET
CSREF
+
+
+
+
PWM
COMP
Switch Node
GATE(L)X
VFB
DACOUT
E.A.
+
R1
3.0 k
COMP
25 k
CSX
Figure 11. Lossless Inductive Current Sensing with
Enhanced V2
1.0 nF
0.1 µF
When choosing or designing inductors for use with
inductive sensing, tolerances and temperature effects should
be considered. Cores with a low permeability material or a
large gap will usually have minimal inductance change with
temperature and load. Copper magnet wire has a
temperature coefficient of 0.39% per °C. The increase in
winding resistance at higher temperatures should be
.01 µF
CSREF
MMBT2222LT1
Slope Comp
Circuit
Existing Current
Sense Circuit
Figure 12. External Slope Compensation Circuit
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CS5332
Ramp Size and Current Sensing
Because the current ramp is used for both the PWM ramp
and to sense current, the inductor and sense resistor values
will be constrained. A small ramp will provide a quick
transient response by minimizing the difference over which
the COMP pin must travel between light and heavy loads,
but a steady state ramp of 25 mVP–P or greater is typically
required to prevent pulse skipping and minimize pulse width
jitter. For resistive current sensing, the combination of the
inductor and sense resistor values must be chosen to provide
a large enough steady state ramp. For large inductor values
the sense resistor value must also be increased.
For inductive current sensing the RC network must meet
the requirement of L/RL = R × C to accurately sense the AC
and DC components of the current the signal. Again the
values for L and RL will be constrained in order to provide
a large enough steady state ramp with a compensated current
sense signal. A smaller L, or a larger RL than optimum might
be required. But unlike resistive sensing, with inductive
sensing small adjustments can be made easily with the
values of R and C to increase the ramp size if needed.
If RC is chosen to be smaller (faster) than L/RL, the AC
portion of the current sensing signal will be scaled larger
than the DC portion. This will provide a larger steady state
ramp, but circuit performance will be affected and must be
evaluated carefully. The current signal will overshoot during
transients and settle at the rate determined by R × C. It will
eventually settle to the correct DC level, but the error will
decay with the time constant of R × C. If this error is
excessive it will effect transient response, adaptive
positioning and current limit. During transients, the COMP
pin will be required to overshoot along with the current
signal in order to maintain the output voltage. The VDRP pin
will also overshoot during transients and possibly slow the
response. Single phase overcurrent will trip earlier than it
would if compensated correctly and hiccup mode current
limit will have a lower threshold for fast rise step loads than
for slowly rising output currents.
The waveforms in Figure 13 show a simulation of the
current sense signal and the actual inductor current during
a positive step in load current with values of L = 500 nH,
RL = 1.6 mΩ, R1 = 20 k and C1 = .01 µF. For ideal current
signal compensation the value of R1 should be 31 kΩ. Due
to the faster than ideal RC time constant there is an
overshoot of 50% and the overshoot decays with a 200 µs
time constant. With this compensation the ILIM pin
threshold must be set more than 50% above the full load
current to avoid triggering hiccup mode during a large
output load step.
Figure 13. Inductive Sensing waveform during a
Load Step with Fast RC Time Constant (50 µs/div)
Current Limit
Two levels of overcurrent protection are provided. Any
time the voltage on a Current Sense pin exceeds CSREF by
more than the Single Phase Pulse by Pulse Current Limit, the
PWM comparator for that phase is turned off. This provides
fast peak current protection for individual phases. The
outputs of all the currents are also summed and filtered to
compare an averaged current signal to the voltage on the
ILIM pin. If this voltage is exceeded, the fault latch trips and
the Soft Start capacitor is discharged by a 7.5 µA source until
the COMP pin reaches 0.2 V. Then Soft–Start begins. The
converter will continue to operate in this mode until the fault
condition is corrected.
Overvoltage Protection
Overvoltage protection (OVP) is provided as a result of
the normal operation of the Enhanced V2 control topology
with synchronous rectifiers. The control loop responds to an
overvoltage condition within 400 ns, causing the top
MOSFET’s to shut off, and the synchronous MOSFET’s to
turn on. This results in a “crowbar” action to clamp the
output voltage and prevent damage to the load. The regulator
will remain in this state until the overvoltage condition
ceases or the input voltage is pulled low.
Transient Response and Adaptive Positioning
For applications with fast transient currents the output
filter is frequently sized larger than ripple currents require in
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CS5332
to the final voltage after a transient. This will be most
apparent with lower capacitance output filters.
Note: Large levels of adaptive positioning can cause pulse
width jitter.
order to reduce voltage excursions during transients.
Adaptive voltage positioning can reduce peak–peak output
voltage deviations during load transients and allow for a
smaller output filter. The output voltage can be set higher
than nominal at light loads to reduce output voltage sag
when the load current is stepped up and set lower than
nominal during heavy loads to reduce overshoot when the
load current is stepped up. For low current applications a
droop resistor can provide fast accurate adaptive
positioning. However at high currents, the loss in a droop
resistor becomes excessive. For example, in a 50 A
converter a 1.0 mΩ resistor to provide a 50 mV change in
output voltage between no load and full load would dissipate
2.5 Watts.
Lossless adaptive positioning is an alternative to using a
droop resistor, but must respond quickly to changes in load
current. Figure 14 shows how adaptive positioning works.
The waveform labeled normal shows a converter without
adaptive positioning. On the left, the output voltage sags
when the output current is stepped down and later
overshoots when current is stepped back down. With fast
(ideal) adaptive positioning the peak to peak excursions are
cut in half. In the slow adaptive positioning waveform the
output voltage is not repositioned quickly enough after
current is stepped up and the upper limit is exceeded.
Error Amp Compensation
The transconductance error amplifier requires a capacitor
between the COMP pin and GND. Use of values less than 1.0
nF may result in error amp oscillation of several MHz.
The capacitor between the COMP pin and the inverting
error amplifier input and the parallel resistance of the VFB
resistor and the VDRP resistor are used to roll off the error
amp gain. The gain is rolled off at a high enough frequency
to give a quick transient response, but low enough to cross
zero dB well below the switching frequency to minimize
ripple and noise on the COMP pin.
UVLO
The CS5332 has undervoltage lockout functions
connected to two pins. One, intended for the logic and
low–side drivers, with a 4.4 V turn–on threshold is
connected to the VCCL pin. A second, for the high side
drivers, has a 2.0 V threshold and is connected to the VCCH1
pin.
The UVLO threshold for the high side drivers was chosen
at a low value to allow for flexibility in the part and an input
voltage as low as 3.3 V. In many applications this will be
disabled or will only check that the applicable supply is on
– not that it is at a high enough voltage to run the converter.
For the 12 VIN converter in Figure 1. the UVLO pin for the
high side driver is pulled up by the 5.0 V supply (through two
diode drops) and the function is not used. The diode between
the Soft Start pin and the 12 V supply holds the Soft Start pin
near GND and prevents start–up while the 12 V supply is off.
In an application where a higher UVLO threshold is
necessary a circuit like the one in Figure 15 will lock out the
converter until the 12 V supply exceeds 9.0 V.
Normal
Fast Adaptive Positioning
Slow Adaptive Positioning
Limits
Figure 14. Adaptive Positioning
The CS5332 can be configured to adjust the output
voltage based on the output current of the converter. (Refer
to Figure 1.)
To set the no–load positioning, a resistor is placed
between the output voltage and VFB pin. The VFB bias
current will develop a voltage across the resistor to decrease
the output voltage. The VFB bias current is dependent on the
value of ROSC. See Figure 4 on the datasheet.
During no load conditions the VDRP pin is at the same
voltage as the VFB pin, so none of the VFB bias current flows
through the VDRP resistor. When output current increases
the VDRP pin increases proportionally and the VDRP pin
current offsets the VFB bias current and causes the output
voltage to decrease.
The VFB and VDRP pins take care of the slower and DC
voltage positioning. The first few µs are controlled primarily
by the ESR and ESL of the output filter. The transition
between fast and slow positioning is controlled by the ramp
size and the error amp compensation. If the ramp size is too
large or the error amp too slow there will be a long transition
+12 V
+5.0 V
50 k
Soft Start
100 k
100 k
Figure 15. External UVLO Circuit
Remote Sense
In some applications that require remote output voltage
sensing, there are conditions when the path of the feedback
signal can be broken. In a voltage regulator module (VRM)
the remote voltage feedback sense point is typically off the
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CS5332
considered when laying out the power, filter and feedback
signal sections of the board. Typically, a multi–layer board
with at least one ground plane is recommended. If the layout
is such that high currents can exist in the ground plane
underneath the controller or control circuitry, the ground
plane can be slotted to reroute the currents away from the
controller. The slots should typically not be placed between
the controller and the output voltage or in the return path of
the gate drive. Additional power and ground planes or
islands can be added as required for a particular layout.
Gate drives experience high di/dt during switching and the
inductance of gate drive traces should be minimized. Gate
drive traces should be kept as short and wide as practical and
should have a return path directly below the gate trace.
Output filter components should be placed on wide planes
connected directly to the load to minimize resistive drops
during heavy loads and inductive drops and ringing during
transients. If required, the planes for the output voltage and
return can be interleaved to minimize inductance between
the filter and load.
Voltage feedback should be taken from a point of the
output or the output filter that doesn’t favor any one phase.
If the feedback connection is closer to one inductor than the
others the ripple associated with that phase may appear
larger than the ripple associated with the other phases and
poor current sharing can result.
The current sense signal is typically tens of milli–volts.
Noise pick–up should be avoided wherever possible.
Current feedback traces should be routed away from noisy
areas such as switch nodes and gate drive signals. The paths
should be matched as well as possible. It is especially
important that all current sense signals be picked off at
similar points for accurate current sharing. If the current
signal is taken from a place other than directly at the inductor
any additional resistance between the pick–off point and the
inductor appears as part of the inherent inductor resistance
and should be considered in design calculations. Capacitors
for the current feedback networks should be placed as close
to the current sense pins as practical.
module. If the module is powered apart from the intended
application, the feedback will be left open. On a
motherboard, the feedback path might be broken when the
processor socket is left open. Without the feedback
connection the output voltage is likely to exceed the
intended voltage. To protect the circuit from overvoltage
conditions, a resistor can be connected between the local
output voltage and the remote sense line as shown in Figure 16.
Local VOUT
Remote VOUT
100 Ω
CSREF Network
Remote
Sense
Line
VFB Network
Figure 16. Remote Sense Connection
Soft Start Enable, and Hiccup Mode
A capacitor between the Soft Start pin and GND controls
Soft Start and hiccup mode slopes. A 0.1 µF capacitor with
30 µA charge current will allow the output to ramp up at 0.3
V/ms or 1.5 V in 5.0 ms at start–up.
When a fault is detected due to overcurrent or UVLO the
converter will enter a low duty cycle hiccup mode. During
hiccup mode the converter will not switch from the time a
fault is detected until the Soft Start capacitor has discharged
below the Soft Start Discharge Threshold and then charged
back up above the Channel Start Up Offset.
The Soft Start pin will disable the converter when pulled
below 0.3 V.
Layout Guidelines
With the fast rise, high output currents of microprocessor
applications, parasitic inductance and resistance should be
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CS5332
DESIGN PROCEDURE
Multiply the converterZ by the output current step size
to calculate where the output voltage should recover to
within the first switching cycle after a transient. If the
ConverterZ is higher than the value required to recover
to where the adaptive positioning is set, the remainder
of the recovery will be controlled by the error amp
compensation and will typically recover in 10 – 20 µs.
Current Sensing, Power Stage and
Output Filter Components
1. Choose the output filter components to meet peak
transient requirements. The formula below can be
used to provide an approximate starting point for
capacitor choice, but will be inadequate to calculate
actual values.
VR IOUT ConverterZ
Make sure that ∆VR is less than the expected peak
transient for a good transient response.
5. Adjust L and RL or RS as required to meet the best
combination of transient response, steady state output
voltage ripple and pulse width jitter.
VPEAK (IT) ESL I ESR
Ideally the output filter should be simulated with
models including ESR, ESL, circuit board parasitics
and delays due to switching frequency and converter
response. Typically both bulk capacitance
(electrolytic, Oscon, etc,) and low impedance
capacitance (ceramic chip) will be required. The bulk
capacitance provides “hold up” during the converter
response. The low impedance capacitance reduces
steady state ripple and bypasses the bulk capacitance
during slewing of output current.
2. For inductive current sensing (only) choose the
current sense network RC to provide a 25 mV
minimum ramp during steady state operation.
R (VIN VOUT) Current Limit
When the sum of the Current Sense amplifiers (VITOTAL)
exceeds the voltage on the ILIM pin the part will enter hiccup
mode. For inductive sensing the ILIM pin voltage should be
set based on the inductor resistance (or current sense
resistor) at max temperature and max current. To set the level
of the ILIM pin:
6. VI(LIM) R IOUT(LIM) CS to ILIM Gain
where:
R is RL or RS;
IOUT(LIM) is the current limit threshold.
For the overcurrent to work properly the inductor time
constant (L/R) should be ≤ the Current sense RC. If the
RC is too fast, during step loads the current waveform
will appear larger than it is (typically for a few hundred
µs) and may trip the current limit at a level lower than
the DC limit.
VOUTVIN
F C 25 mV
Then choose the inductor value and inherent resistance
to satisfy L/RL = R × C.
For ideal current sense compensation the ratio of L and
RL is fixed, so the values of L and RL will be a
compromise typically with the maximum value RL
limited by conduction losses or inductor temperature
rise and the minimum value of L limited by ripple
current.
3. For resistive current sensing choose L and RS to
provide a steady state ramp greater than 25 mV.
Adaptive Positioning
7. To set the amount of voltage positioning below the
DAC setting at no load, connect a resistor (RV(FB))
between the output voltage and the VFB pin. Choose
RV(FB) as;
LRS (VIN VOUT) TON25 mV
RV(FB) NL PositionVFB Bias Current
Again the ratio of L and RL is fixed and the values of
L and RS will be a compromise.
4. Calculate the high frequency output impedance
(ConverterZ) of the converter during transients. This
is the impedance of the Output filter ESR in parallel
with the power stage output impedance (PwrstgZ)
and will indicate how far from the original level
(∆VR) the output voltage will typically recover to
within one switching cycle. For a good transient
response ∆VR should be less than the peak output
voltage overshoot or undershoot.
See Figure 4 for VFB Bias Current.
8. To set the difference in output voltage between no
load and full load, connect a resistor (RV(DRP))
between the VDRP and VFB pins. RV(DRP) can be
calculated in two steps. First calculate the difference
between the VDRP and VFB pin at full load. (The VFB
voltage should be the same as the DAC voltage during
closed loop operation.) Then choose the RV(DRP) to
source enough current across RV(FB) for the desired
change in output voltage.
VV(DRP) IOUTFL R CS to VDRP Gain
VR ConverterZ ESR
ConverterZ where:
R = RL or RS for one phase;
IOUTFL is the full load output current.
PwrstgZ ESR
PwrstgZ ESR
where:
RV(DRP) VDRP RV(FB)VOUT
PwrstgZ RS CSA Gain2.0
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CS5332
Calculate Input Filter Capacitor Current Ripple
Current Sensing, Power Stage and
Output Filter Components
The procedure below assumes that phases do not overlap
and output inductor ripple current (P–P) is less than the
average output current of one phase.
9. Calculate Input Current
1.Assume 1.5 mΩ of output filter ESR.
2. R (VIN VOUT) (VOUTVIN)(F C 25 mV)
(12 1.55) (1.5512)(240 k .01F 25mV)
22.5 k
LRL .01 F 22.5 k 225 s
VOUT IOUT
IIN (Efficiency VIN)
Choose RL 2.0 m
L 2.0 m 225 s 450 nH
10. Calculate Duty Cycle (per phase).
Duty Cycle VOUT
(Efficiency VIN)
3. n/a
4. PwrstgZ RL CSA Gain2.0
11. Calculate Apparent Duty Cycle.
2.0 m 3.152 3.1 m
Apparent Duty Cycle Duty Cycle # of Phases
12. Calculate Input Filter Capacitor Ripple Current. Use
the chart in Figure 17 to calculate the normalized
ripple current (KRMS) based on the reciprocal of
Apparent Duty Cycle. Then multiply the input current
by KRMS to obtain the Input Filter Capacitor Ripple
Current.
ConverterZ
Ripple (RMS) IIN KRMS
Current Limit
6.VI(LIM) RL IOUT(LIM) CS to ILIM Gain
2.0 m 50 A 6.25 625 mV
3.50
Frequency, kHz
PwrstgZ ESR
PwrstgZ ESR
3.1 m 1.5 m 1.0 m
3.1 m 1.5 m
VR 1.0 m 41 A 41 mV
5. n/a
4.00
3.00
Adaptive Positioning
2.50
7. RV(FB) NL PositionVFB Bias Current
2.00
50 mV18 A 2.78 k
1.50
8. VDRP RL IOUT Current Sense to VDRP Gain
1.00
2.0 m 41 A 3.1 254 mV
0.50
0.00
0
RV(DRP) VDRP RV(FB)VOUT
254 mV 2.78 k50 mV 25.4 k
15
10
5
1/ Apparent Duty Cycle
9. IIN 1.52 V 41 A 6.1 A
(0.85 12VIN)
Figure 17. Normalized Input Filter Capacitor
Ripple Current
1.52 V
10. Duty Cycle (0.85 12 V ) 0.15
IN
DESIGN EXAMPLE
Choose the component values for a 240 kHz, 12 V to 1.525
V, 41 A converter with lossless current sensing, adaptive
positioning and a 50 A current limit. The adaptive
positioning is chosen 50 mV below the DAC setting at no
load and 50 mV below the no–load position with 41 A out.
The peak output voltage transient is 70 mV max during a 41
A step current.
11. Apparent Duty Cycle 0.15 2.0 0.3
12. RMS ripple is 6.1 A 1.5 9.2 A
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CS5332
300 nH
VIN
+
1.0 µF
1.0 µF
1.0 µF
ENABLE
10 k
1 nF
1.2 µH
56.2 k
1 nF
1 nF
ROSC
COMP
VCCL
VFB
VCCL1
VDRP
GATE(L)1
CS1
GND1
CS2
GATE(H)1
CSREF
VCCH1
PWRGD
LGND
VID0
SS
VID1
VCCL2
VID2
GATE(L)2
VID3
GND2
VID4
GATE(H)2
ILIM
VCCH2
REF
2.74 k
3 × 4SP560M
VOUT
CS5332
25.4 k
12.7 k
PWRGD
0.1 µF
2.8 k
3 × 10 µF
0.1 µF
1.0 µF
1.2 µH
1.0 k
0.1 µF
25.5 k
25.5 k
0.1 µF
0.1 µF
GL1
GL2
Figure 18. Additional Application Diagram, 5.0 V only to 2.5 V
300 nH
+5 V
+
+12 V
1.0 µF
3 × 16SP270M
ENABLE
470 nH
56.2 k
1.0 nF
1.0 nF
1.0 nF
2.74 k
25.4 k
12.7 k
PWRGD
VID0
VID1
ROSC
VCCL
VCCL1
GATE(L)1
GND1
GATE(H)1
VCCH1
LGND
SS
VCCL2
GATE(L)2
GND2
GATE(H)2
VCCH2
+
8 × 4SP560M
CS5332
COMP
VFB
VDRP
CS1
CS2
CSREF
PWRGD
VID0
VID1
VID2
VID3
VID4
ILIM
REF
VOUT
12 × 1.0 µF
0.1 µF
VID2
VID3
1.0 µF
4.87 k
0.1 µF
VID4
1.0 k
.01 µF
.01 µF
25.5 k
470 nH
25.5 k
.01 µF
Figure 19. Additional Application Diagram, 5.0 V to 1.6 V with 12 V Bias
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18
CS5332
300 nH
+5 V
+
1.0 µF
3 × 6SP680M
ENABLE
1.0 nF
470 nH
56.2 k
1.0 nF
COMP
VFB
VDRP
CS1
CS2
CSREF
PWRGD
VID0
VID1
VID2
VID3
VID4
ILIM
REF
2.74 k
25.4 k
12.7 k
PWRGD
VID0
VID1
CS5332
1.0 nF
+
8 × 4SP560M
ROSC
VCCL
VCCL1
GATE(L)1
GND1
GATE(H)1
VCCH1
LGND
SS
VCCL2
GATE(L)2
GND2
GATE(H)2
VCCH2
VOUT
12 × 10 µF
0.1 µF
VID2
VID3
4.87 k
0.1 µF
VID4
1.0 µF
470 nH
1.0 k
.01 µF
.01 µF
25.5 k
25.5 k
.01 µF
Figure 20. Additional Application Diagram, 5.0 V only to 1.6 V
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19
CS5332
PACKAGE DIMENSIONS
SO–28
DW SUFFIX
CASE 751F–05
ISSUE F
D
A
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSIONS.
4. MAXIMUM MOLD PROTRUSION 0.015 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS
OF B DIMENSION AT MAXIMUM MATERIAL
CONDITION.
15
0.25
E
H
M
B
M
28
1
14
PIN 1 IDENT
A
B
A1
e
B
0.025
C
M
C A
S
B
L
0.10
S
C
SEATING
PLANE
DIM
A
A1
B
C
D
E
e
H
L
MILLIMETERS
MIN
MAX
2.35
2.65
0.13
0.29
0.35
0.49
0.23
0.32
17.80
18.05
7.40
7.60
1.27 BSC
10.05
10.55
0.41
0.90
0
8
PACKAGE THERMAL DATA
Parameter
SO–28L
Unit
RΘJC
Typical
15
°C/W
RΘJA
Typical
75
°C/W
V2 is a trademark of Switch Power, Inc.
Pentium is a registered trademark of Intel Corporation.
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CS5332/D