DS3647A Quad TRI-STATEÉ MOS Memory I/O Register General Description The DS3647A is a 4-bit I/O buffer register intended for use in MOS memory systems. This circuit employs a fall-through latch for data storage. This method of latching captures the data in parallel with the output, thus eliminating the delays encountered in other designs. This circuit uses Schottkyclamped transistor logic for minimum propagation delay and employs PNP input transistors so that input currents are low, allowing a large fan-out for this circuit which is needed in a memory system. Two pins per bit are provided, and data transfer is bi-directional so that the register can handle both input and output data. The direction of data flow is controlled through the input enables. The latch control, when taken low, will cause the register to hold the data present at that time and display it at the outputs. Data can be latched into the register independent of the output disables or EXPANSION input. Either or both of the outputs may be taken to the high-impedance state with the output disables. The EXPANSION pin disables both outputs to facilitate multiplexing with other I/O registers on the same data lines. The DS3647A features TRI-STATE outputs. The ‘‘B’’ port outputs are designed for use in bus organized data transmission systems and can sink 80 mA and source b5.2 mA. Data going from port ‘‘A’’ to port ‘‘B’’ and from ‘‘B’’ to port ‘‘A’’ is inverted in the DS3647A. Features Y Y Y Y Y Y Y Y PNP inputs minimize loading Fall-through latch design Propagation delay of only 15 ns TRI-STATE outputs EXPANSION control Bi-directional data flow TTL compatible Transmission line driver output Logic and Connection Diagrams Dual-In-Line Package TL/F/8354 – 2 Top View Order Number DS3647AD or DS3647AN See NS Package Number D16C or N16A TL/F/8354 – 1 TRI-STATEÉ is a registered trademark of National Semiconductor Corp. C1995 National Semiconductor Corporation TL/F/8354 RRD-B30M105/Printed in U. S. A. DS3647A Quad TRI-STATE MOS Memory I/O Register February 1986 Absolute Maximum Ratings (Note 1) Operating Conditions If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage Input Voltage Supply Voltage (VCC) Temperature (TA) DS3647A 7V Min 4.5 Max 5.5 Units V 0 a 70 §C b 1.5V to a 7V b 65§ to a 150§ C Storage Temperature Range Maximum Power Dissipation* at 25§ C Molded Package 1476 mW Lead Temperature (Soldering, 10 seconds) 300§ C *Derate molded package 10.0 mW/§ C above 25§ C. Electrical Characteristics (Notes 2 and 3) Symbol Parameter VIN(1) Logic ‘‘1’’ Input Voltage VIN(0) Logic ‘‘0’’ Input Voltage IIN(1) Logic ‘‘1’’ Input Current Conditions Logic ‘‘0’’ Input Current VCC e 5.5V, VIN e 0.5V VCLAMP Input Clamp Voltage VCC e 4.5V, IIN eb18 mA VOL(A) Logic ‘‘0’’ Output Voltage A Ports VCC e 4.5V, IOL e 20 mA VOL(B) VOH(A) VOH(B) Logic ‘‘0’’ Output Voltage Typ Max Units 0.8 V 2.0 VCC e 5.5V, VIN e 5.5V IIN(0) Min Latch, Disable Inputs 0.1 40 mA Expansion 0.2 80 mA A Ports, B Ports 0.2 100 mA Enable Inputs 0.4 200 mA Latch, Disable Inputs b 25 b 250 mA Expansion b 50 b 500 mA A Ports, B Ports b 50 b 500 mA Enable, Inputs b 0.1 b 1.25 mA b 0.6 b 1.2 V 0.4 0.5 V 0.3 0.4 V 0.4 0.5 IOL e 30 mA VCC e 4.5V V B Ports IOL e 50 mA Logic ‘‘1’’ Output Voltage VCC e 5V 3.0 3.4 V A Ports VCC e 4.5V 2.5 3.4 V Logic ‘‘1’’ Output Voltage VCC e 5V 2.9 3.3 V VCC e 4.5V 2.4 3.3 V IOH eb1 mA IOH eb5.2 mA, (Note 4) B Ports V IOS(A) Output Short-Circuit Current A Port VCC e 4.5V to 5.5V, VOUT e 0V, (Note 4) b 50 b 80 b 120 mA IOS(B) Output Short-Circuit Current B Port VCC e 4.5V to 5.5V, VOUT e 0V, (Note 4) b 70 b 120 b 180 mA ICC Power Supply Current DS3647A 100 140 mA DS3647A 70 105 mA Exp e 3V, A Ports e 0V, B Ports Open, All Other Pins e 0V Enable A, Latch e 3V, A Ports e 0V, B Ports Open, All Other Pins e 0V Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’ they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device operation. Note 2: Unless otherwise specified min/max limits apply across the 0§ C to a 70§ C range. All typicals are given for VCC e 5V and TA e 25§ C. Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. Note 4: Only one output at a time should be shorted. 2 Switching Characteristics (VCC e 5V, TA e 25§ C) Symbol Parameter Conditions Min Typ Max Units DATA TRANSFER B PORT TO A PORT tpd0 Propagation Delay to a Logic ‘‘0’’ CL e 50 pF, RL e 280X, (Figures 1 and 4) 7.5 15 ns tpd1 Propagation Delay to a Logic ‘‘1’’ CL e 50 pF, RL e 280X, (Figures 1 and 4) 6.0 12 ns A PORT CONTROL FROM OUTPUT DISABLE A INPUT tLZ Delay to High Impedance from Logic ‘‘0’’ (Figures 1 and 5) 13 20 ns tHZ Delay to High Impedance from Logic ‘‘1’’ (Figures 1 and 6) 14 20 ns tZL Delay to Logic ‘‘0’’ from High Impedance (Figures 1 and 7) 10 15 ns tZH Delay to Logic ‘‘1’’ from High Impedance (Figures 1 and 8) 25 35 ns DATA TRANSFER A PORT TO B PORT, DS3647A tpd0 Propagation Delay to a Logic ‘‘0’’ CL e 50 pF, RL e 100 X, (Figures 2 and 4) 6.5 12 ns tpd1 Propagation Delay to a Logic ‘‘1’’ CL e 50 pF, RL e 100 X, (Figures 2 and 4) 8.0 15 ns B PORT CONTROL FROM OUTPUT DISABLE B INPUT, DS3647A tLZ Delay to High Impedance from Logic ‘‘0’’ (Figures 2 and 5) 15 25 ns tHZ Delay to High Impedance from Logic ‘‘1’’ (Figures 2 and 6) 14 20 ns tZL Delay to Logic ‘‘0’’ from High Impedance (Figures 2 and 7) 10 16 ns tZH Delay to Logic ‘‘1’’ from High Impedance (Figures 2 and 8) 25 35 ns LATCH SET-UP AND HOLD TIMES, ALL DEVICES tSET-UP Set-Up Time of Data Input Before Latch Goes Low 5 0 ns tHOLD Hold Time of Data Input After Latch Goes Low 10 5 ns Product Description Device Number B Port To A Port Function A Port To B Port Function A Port Outputs B Port Outputs DS3647A Inverting Inverting TRI-STATE TRI-STATE 3 Truth Table Input Enables Latch Output Disables A Expansion A Ports A1-A4 B Ports B1-B4 Comments A B B 1 0 1 0 0 0 Hi-Z A Data in on A, output to B 0 1 1 0 0 0 B Hi-Z Data in on B, output to A 1 0 0 0 0 0 Hi-Z A Data stored which is present when latch goes low 0 1 0 0 0 0 B Hi-Z Data stored which is present when latch goes low 1 0 x 0 1 0 Hi-Z Hi-Z Both A and B in Hi-Z state, Data in on A, may be latched 0 1 x 1 0 0 Hi-Z Hi-Z Both A and B in Hi-Z state, Data in on B, may be latched x x x x x 1 Hi-Z Hi-Z Both A and B in Hi-Z state AC Test Circuits TL/F/8354–3 TL/F/8354 – 4 FIGURE 1. A Port Load FIGURE 2. B Port Load Note 1: CL includes probe and jig capacitance. Operating Waveforms Using TRI-STATE TRI-STATE Disabled TL/F/8354 – 6 TL/F/8354–5 *When the Input Enable makes a negative transition, the output will be indeterminate for a short duration. The negative transition of the Input Enable normally occurs during a don’t-care timing state at the output. 4 Switching Time Waveforms tpd0 and tpd1 TL/F/8354 – 7 Input Characteristics: f e 1 MHz, tR e tF s 5 ns (10% to 90% points), duty cycle e 50%, ZOUT e 50 X FIGURE 4 tHZ tLZ TL/F/8354 – 10 TL/F/8354 – 8 FIGURE 6 FIGURE 5 tZH tZL TL/F/8354 – 11 TL/F/8354 – 9 FIGURE 8 FIGURE 7 Schematic Diagram TL/F/8354 – 12 Note. Data pins A1–A4 and B1–B4 consist of an input and an output tied together. 5 Typical Application The diagram below shows how the DS3647A can be used as a register capable of multiplexing data lines. TL/F/8354 – 13 6 Physical Dimensions inches (millimeters) Hermetic Dual-In-Line Package (D) Order Number DS3647AD NS Package D16C 7 DS3647A Quad TRI-STATE MOS Memory I/O Register Physical Dimensions inches (millimeters) (Continued) Molded Dual-In-Line Package (N) Order Number DS3647AN NS Package N16A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation 1111 West Bardin Road Arlington, TX 76017 Tel: 1(800) 272-9959 Fax: 1(800) 737-7018 2. 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