G M 71V 65803C
G M 71V S65803C L
8,388,608 W O R D S x 8 BIT
CMOS DYNAMIC RAM
D escription
Pin Configuration
T h e GM 71V ( S)65803C/ C L i s t h e n ew
generation dynamic RA M organized 8,388,608
w o r d s by 8 b i t s. T h e G M 71V (S)65803C/ C L
utilizes advanced CM O S Silicon Gate Process
Technology as w ell as advanced circuit
t ech n i q u es f o r w i d e operating margins, both
i n t er n al l y a n d t o t h e sy s t e m u ser . Sy st e m
oriented f eatures include single pow er su p p l y o f
3.3V + / - 1 0 % t o l e r a n c e , d i r ect i n t er f a c i n g
capability w ith high performance logic families
su ch as Schottky TTL.
T h e GM 71V (S)65803C/ C L o f f e r s Extended
D ata Out (EDO) M ode as a high speed access
m o d e.
Features
* 8,388,608 W o r d s x 8 Bit
* Extended Data Out (EDO) M ode Capability
* Fast A ccess Tim e & C y cle Tim e
(Unit: ns)
t RAC
tAA
t CAC
t RC
t H PC
G M 71V (S)65803C/ CL-5
50
25
13
84
20
G M 71V (S)65803C/ CL-6
60
30
15
104
25
32 SOJ / TSOP II
VCC
1
32
VSS
IO0
2
31
IO7
IO1
3
30
IO6
IO2
4
29
IO5
IO3
5
28
IO4
NC
6
27
VSS
VCC
7
26
/CAS
/WE
8
25
/OE
/RAS
9
24
NC
A0
10
23
A11
A1
11
22
A10
A2
12
21
A9
A3
13
20
A8
A4
14
19
A7
A5
15
18
A6
VCC
16
17
VSS
*Pow er d i ssipation
- A ctive : 522m W / 486m W (M A X)
- Standby : 1.8 m W ( CM OS l ev el : M A X )
0.54m W ( L-Ver sion : M A X)
*EDO page mode capability
*A ccess tim e : 50ns/ 60ns (m ax)
*Refresh cycles
- RA S only Refresh
4096 cycles/ 64 m s (GM 71V 65803C)
4096 cycles/ 128m s (GM 71V S65803CL)(L_Ver sion)
*CBR & H i d d en Refresh
4096 cycles/ 64 m s (GM 71V 65803C)
4096 cycles/ 128 m s (GM 71V S65803CL)( L-Ver sion )
*4 v ariations of refresh
-RA S-only refresh
-CA S-before-RA S r ef r esh
-H i d d en refresh
-Sel f r efresh (L-V er sion)
*Single Pow er Supply of 3.3V+/ -10 % w i t h a built-in VBB generator
*Battery Back Up Operation ( L-Version )
Rev 0.1 / Apr’01
(Top View)
G M 71V 65803C
G M 71V S65803C L
P i n D escription
Pin
Function
Pin
A 0-A 11
A d d r ess I n p u t s
A 0-A 11
Refresh A d d r ess I n p u t s
Function
W r i t e Enable
WE
I / O0 - I/ O7
D ata Input / O u t p u t
RA S
Row A d d r ess Strobe
V CC
Pow er (+3.3V)
CAS
C o l u m n A d d r ess Strobe
V SS
Ground
OE
Output Enable
NC
N o Connection
O rdering I n f orm ation
T y p e N o.
A ccess T i m e
Pack age
G M 71V(S)65803C/ C L J-5
G M 71V(S)65803C/ C L J-6
50ns
60ns
400 M i l
32Pin
Plastic SO J
G M 71V(S)65803C/ CLT-5
G M 71V(S)65803C/ CLT-6
50ns
60ns
400 M i l
32Pin
Plastic TSOP II
A b solute M aximum Ratings*
Symbol
Param eter
T STG
Rating
Unit
-55 to 125
C
-0.5 t o V CC + 0.5
(M A X ; 4.6V)
V
V
Storage Tem p er ature (Plastic)
VT
V o l t age on any Pin Relative to V SS
V CC
V o l t age on V CC Relative to V SS
-0.5 to 4.6
I OUT
Short Circuit Output Current
50
mA
Pow er D i ssipation
1.0
W
PT
*N ote : Operation at or above A bsolute M aximum Ratings can adversely affect device reliability.
Recom m ended D C O p erating Conditions (T A = 0 ~ 70C)
Symbol
Param eter
M in
Typ
M ax
Unit
N otes
V CC
Supply Voltage
3.0
3.3
3.6
V
1,2
V SS
Supply Voltage
0
0
0
V
2
V IH
I n p u t H igh Voltage
2.0
-
V cc+0.3
V
1
V IL
I n p u t L o w V oltage
-0.3
-
0.8
V
1
TA
A m bient Temper ature under Bias
0
-
70
C
Rev 0.1 / Apr’01
G M 71V 65803C
G M 71V S65803C L
D C Electrical Characteristics: ( V C C = 3.3V + / -10%, T A = 0 ~ 70C)
Symbol
Parameter
M in
M ax
Unit
VOH
O u t p u t L ev el
O u t p u t L ev el Voltage (I O U T = -2m A )
2.4
V CC
V
V OL
O u t p u t L ev el
O u t p u t L ev el Voltage (I O U T = 2m A )
0
0.4
V
I CC1
O p er ating Current ( t RC = t RC m i n )
50ns
-
145
60ns
-
135
-
2
mA
I CC2
St a n d b y C u r r en t ( T T L i n t erface)
Pow er Su p p l y St an d b y C u r r ent
(RA S, CA S= V I H , D O U T = H i g h - Z )
N ote
1,2
mA
RA S-Only Ref r esh C u r r ent
( t RC = t RC m i n )
50ns
-
145
60ns
-
135
Extended Data Out page M o d e Cu r r ent
50ns
-
110
60ns
-
100
CM OS i n t er f ace
(RA S, CA S> = V C C -0.2V , D O U T = H i g h - Z )
-
0.5
mA
St a n d b y C u r r en t ( L _ V er sion)
-
300
uA
50ns
-
145
60ns
-
135
Battery Back Up Operating Current(Standby w ith CBR)
(tRC=31.25u s,tRA S=300ns,D o u t = H i g h - Z )
-
500
uA
4, 5
St a n d b y C u r r ent (CM O S)
Pow er Su p p l y St an d b y C u r r ent
RA S = V I H , CA S = V I L , D O U T = Enable
-
5
mA
1
I CC9
Self Refresh Current
(RA S, CA S <=0.2V ,D o u t = H i g h - Z )
-
400
uA
5
I I(L)
I n p u t L eakage Current, A n y I n p u t
(0V < = V I N < = V cc)
-5
5
uA
I O(L )
O u t p u t L eak age Current
( D O U T i s D i sabl ed , 0V < = V O U T < = V cc)
-5
5
uA
I CC3
I CC4
(RA S = V I L , C A S, A d d r ess Cycling: t H P C = t H P C m i n )
I CC5
I CC6
I CC7
I CC8
CA S-before-RA S Ref r esh C u r r en t
(t RC = t RC m i n )
mA
2
mA
1,3
4
mA
N ote: 1. I C C d ep ends on output load condition w hen the device is selected. I CC(max) i s sp eci f i ed at the
o u t p u t o p en condition.
2. A d d r ess can b e changed once or less w h i l e RA S = V I L .
3. M easu r ed w i t h o n e sequ ential address change per EDO cycle, t H PC .
4. V I H > = V CC -0.2V , 0V < = V I L <=0.2V
5. L -Version
Rev 0.1 / Apr’01
G M 71V 65803C
G M 71V S65803C L
Capacitance ( V C C = 3.3V + / -10%, T A = 25C)
Symbol
Parameter
Typ
M ax
Unit
N ote
C I1
Input Capacitance (A d d r ess)
-
5
pF
1
C I2
Input Capacitance (Clocks)
-
7
pF
1
CI/ O
Output Capacitance
-
7
pF
1, 2
(Data-in,Data-Out)
N ote: 1. Cap acitance m easu r ed w i t h B o o n t o n M eter or effective capacitance m easu r i n g m ethod.
2. RA S, C A S = V I H t o d i sable D O U T .
A C C h aracteristics ( V C C = 3.3V + / -10%, T A = 0 ~ 70C, N otes 1, 2,19)
T est Conditions
I n p u t r i se an d f al l t i m es : 2ns
Output timing reference l ev el s : V O L / V O H = 0.8/ 2.0V
I n p u t l ev el : V I L / V I H = 0.0/ 3.0V
O u t p u t l o a d : 1 TTL gate+C L (100pF)
I n p u t t i m i n g r ef er ence levels : V I L / V I H = 0.8/ 2.0V
(Including scope and jig)
Read, W rite, Read-M odify-W rite and Refresh C y cles (Com m on Param eters)
G M 71V (S)65803C/CL-5 G M 71V (S)65803C/CL-6
Param eter
Symbol
Unit
Mi
n
M ax
-
t RC
Ran d o m Read o r W r i t e Cycle Time
84
t RP
RA S Pr echarge T i m e
30
t CP
C A S Pr echarge T i m e
t RA S
-
Mi
n
M ax
104
-
ns
40
-
ns
N ote
s
8
-
10
-
ns
RA S Pu l se W i d t h
50
10000
60
10000
ns
tCAS
C A S Pu l se W i d t h
8
10000
10
10000
ns
t A SR
Row A d d r ess Set - u p T i m e
0
-
0
-
ns
t RA H
Row A d d r ess H o l d T i m e
8
-
10
-
ns
t A SC
C o l u m n A d d r ess Set-u p T i m e
0
-
0
-
ns
tC A H
C o l u m n A d d r ess H o l d T i m e
8
-
10
-
ns
tRCD
RA S to CA S D elay Time
12
37
14
45
ns
3
t RA D
RA S t o C o l u m n A d d r ess D elay Time
10
25
12
30
ns
4
t RSH
RA S H o l d T i m e
13
-
15
-
ns
t C SH
C A S H old Time
35
-
40
-
ns
t CRP
C A S to RA S Pr echarge T i m e
5
-
5
-
ns
tODD
OE to D I N D elay Time
13
-
15
-
ns
5
tDZO
OE Delay Time from D I N
0
-
0
-
ns
6
tDZC
C A S D elay Time f r o m D I N
0
-
0
-
ns
6
tT
TransitionTime (Rise and Fall)
2
50
2
50
ns
t REF
Refresh Period
Refresh Period ( L-Version )
Rev 0.1 / Apr’01
-
64
-
128
-
64
ms
128
ms
7
4096
cycles
4096
cycles
G M 71V 65803C
G M 71V S65803C L
Read Cycles
G M 71V (S)65803C/CL-5 G M 71V (S)65803C/CL-6
Param eter
Symbol
N otes
Unit
Mi
n
M ax
Mi
n
M ax
t RA C
A ccess Tim e f r o m R A S
-
50
-
60
ns
8,9
t CAC
A ccess Tim e f r o m C A S
-
13
-
15
ns
9,10,17
tAA
A ccess Tim e f r o m C o l u m n A d d r ess
-
25
-
30
ns
9,11,17
tOAC
A ccess Tim e from OE
-
13
-
15
ns
9
t RCS
Read C o m m and Set-up Time
0
-
0
-
ns
t RCH
Read C o m m and H o l d T i m e to CA S
0
-
0
-
ns
12
t RRH
Read C o m m and H o l d T i m e to RA S
0
-
0
-
ns
12
t RA L
C o l u m n A d d r ess to RA S L ead T i m e
25
-
30
-
ns
tCAL
C o l u m n A d d r ess to CA S L ead T i m e
15
-
18
-
ns
t OF
O u t p u t B u f f er Turn-off Delay Time f r o m C A S
-
13
-
15
ns
13,21
t OEZ
O u t p u t B u f f er Turn-off Delay Time from OE
-
13
-
15
ns
13
t CDD
C A S t o D I N D elay Time
13
-
15
-
ns
5
t RDD
RA S t o D I N D elay Time
13
-
15
-
ns
tWDD
W E to D I N D elay Time
13
-
15
-
ns
t OFR
O u t p u t B u f f er Turn-off Delay Time f r o m R A S
-
13
-
15
ns
13,21
t W EZ
O u t p u t B u f f er Turn-off Delay Time f r o m W E
-
13
-
15
ns
13
tOH
O u t p u t D ata H o l d T i m e
3
-
3
-
ns
21
t OHR
O u t p u t D ata H o l d T i m e from RA S
3
-
3
-
ns
21
t RCHR
Read C o m m and H o l d T i m e f r o m R A S
50
-
60
-
ns
tOHO
Output data hold time from OE
3
-
3
-
ns
t CLZ
C A S to Output in Low - Z
0
-
0
-
ns
F
Rev 0.1 / Apr’01
G M 71V 65803C
G M 71V S65803C L
W rite Cycles
G M 71V (S)65803C/CL-5
G M 71V (S)65803C/CL-6
Param eter
Symbol
Unit
M in
M ax
M in
M ax
N ote
tWCS
W r i t e Com m an d Set-up Time
0
-
0
-
ns
tW C H
W r i t e Com m an d H o l d T i m e
8
-
10
-
ns
tWP
W r i t e Com m an d Pulse W i d t h
8
-
10
-
ns
t RW L
W r i t e Com m and to RA S Lead Time
13
-
15
-
ns
tCWL
W r i t e Com m and to CA S L ead T i m e
8
-
10
-
ns
tD S
D ata-in Set - u p T i m e
0
-
0
-
ns
15
tD H
D ata-in H o l d T i m e
8
-
10
-
ns
15
14
Read-M odify-W rite Cycles
G M 71V (S)65803C/CL-5
G M 71V (S)65803C/CL-6
Param eter
Symbol
Unit
M in
M ax
M in
M ax
116
-
140
-
ns
N ote
t RW C
Read-M o d i f y - W r i t e Cycle Tim e
t RW D
RA S to W E Delay Time
67
-
79
-
ns
14
tCWD
C A S to W E Delay Time
30
-
34
-
ns
14
tA W D
C o l u m n A d d r ess to W E Delay Time
42
-
49
-
ns
14
tOEH
OE H o l d T i m e f r o m W E
13
-
15
-
ns
Refresh C y cles
cle
G M 71V (S)65803C/CL-5
Symbol
G M 71V (S)65803C/CL-6
Param eter
Unit
M in
M ax
M in
M ax
t C SR
C A S Set - u p T i m e
(CA S-before-RA S Refresh Cycle)
5
-
5
-
ns
tCHR
C A S H old Time
(CA S-before-RA S Refresh Cycle)
8
-
10
-
ns
t WRP
W E set u p t i m e
(CA S-before-RA S Refresh Cycle)
0
-
0
-
ns
tWRH
W E hold time
(CA S-before-RA S Refresh Cycle)
8
-
10
-
ns
t RPC
RA S Pr echarge to CA S H o l d T i m e
5
-
5
-
ns
Rev 0.1 / Apr’01
N ote
G M 71V 65803C
G M 71V S65803C L
Extended D ata O u t M ode Cycles
G M 71V (S)65803C/CL-5 G M 71V (S)65803C/CL-6
Param eter
Symbol
Unit
M in
t H PC
EDO Page M ode Cycle Time
t W PE
t RA SP
M ax
M in
20
-
25
-
W r i t e pulse w i d t h d u r i n g C A S Precharge
8
-
10
EDO M ode RA S Pu l se W i d t h
-
100000
-
tACP
A ccess Tim e f r o m C A S Pr echarge
t RH C P
RA S H o l d T i m e from CA S Pr ech arge
N ote
M ax
20
-
ns
ns
-
100000
ns
16
28
-
35
ns
9,17
28
-
35
-
ns
tCOL
C A S H o l d T i m e Ref er r ed O E
8
-
10
-
ns
t COP
C A S to OE set-up Time
5
-
5
-
ns
t RCH P
Read C o m m and H o l d T i m e f r o m C A S
Pr echarge
28
-
35
-
ns
tDOH
O u t p u t D ata H o l d T i m e from CA S Low
3
-
3
-
ns
t OEP
OE Precharge T i m e
8
-
10
-
ns
9,22
ED O Page M ode Read-M odify-W rite cycle
G M 71V (S)65803C/CL-5 G M 71V (S)65803C/CL-6
Param eter
Symbol
Unit
M in
M ax
M in
M ax
57
-
68
-
ns
45
-
54
-
ns
t H PRW C EDO Read-M o d i f y - W r i t e Cycle Time
tCPW
EDO Page M ode Read-M o d i f y - W rite Cycle
C A S Precharge to W E D elay Tim e
N ote
14
Sel f R efresh C y cles (L_V ersion)
G M 71V (S)65803C/CL-5
G M 71V (S)65803C/CL-6
Param eter
Symbol
Unit
M in
M ax
M in
M ax
N ote
t RA SS
RA S Pu l se W i d t h ( Self-Ref r esh)
100
-
100
-
us
26
t RPS
RA S Pr echarge T i m e(Self-Refresh)
90
-
110
-
ns
26
tCHS
C A S H o l d T i m e(Self-Ref r esh)
-50
-
-50
-
ns
Rev 0.1 / Apr’01
G M 71V 65803C
G M 71V S65803C L
Notes:
AC measurements assume tT = 2ns .
AC initial pause of 200 us is required after power up followed by a minimum of eight
initialization cycles ( any combination of cycles containing RAS-only refresh or CAS-beforeRAS refresh)
3. Operation with the t RCD(max) limit insures that tRAC(max) can be met, tRCD(max) is specified as a
reference point only: if t RCD is greater than the specified t RCD(max) limit, then access time is
controlled exclusively by tCAC.
4. Operation with the t RAD(max) limit insures that tRAC(max) can be met, tRAD(max) is specified as a
reference point only: if t RAD is greater than the specified t RAD(max) limit, then access time is
controlled exclusively by tAA.
5. Either tOED or tCDD must be satisfied.
6. Either tDZO or tDZC must be satisfied.
7. VIH (min) and V IL (max) are reference levels for measuring timing of input signals. Also,
transition times are measured between VIH(min) and VIL (max).
8. Assumes that t RCD<=tRCD(max) and t RAD<=tRAD(max). If t RCD or tRAD is greater than the maximum
recommended value shown in this table, tRAC exceeds the value shown.
9. Measured with a load circuit equivalent to 1 TTL loads and 100 pF.
10. Assumes that tRCD>=tRCD(max) and tRCD + tCAC(max) >=tRAD + tAA(max).
11. Assumes that tRAD >=tRAD (max) and tRCD + tCAC(max)<=tRAD + tAA(max).
12. Either tRCH or tRRH must be satisfied for a read cycles.
1.
2.
13. tOFF(max), tOEZ(max), t OFR(max) and t WEZ(max) define the time at which the outputs achieve the
open circuit condition and is not referenced to output voltage levels.
14. tWCS, t RWD, t CWD, t AWD, and t CPW are not restrictive operating parameters. They are included in the
data sheet as electrical characteristics only: if t WCS ≥ tWCS(min), the cycle is an early write cycle
and the data out pin will remain open circuit (high impedance) throughout the entire cycle: if
tRWD ≥ tRWD(min), t CWD ≥ tCWD(min), t AWD ≥ tAWD(min) and t CPW ≥ tCPW(min), the cycle is a readmodify-write and the data output will contain data read from the selected cell: if neither of the
above sets of conditions is satisfied, the condition of the data out (at access time) is
indeterminate.
15. tDS and t DH are referred to CAS leading edge in early write cycles and to WE leading edge in
delayed write or read-modify-write cycles.
16. tRASP defines RAS pulse width in extended data out mode cycles.
17. Access time is determined by the longest among tAA, tCAC and tCPA.
18. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying
data to the device.
19. When output buffers are enabled once, sustain the low impedance state until valid daa is
obtained. When output buffer is turned on and off within a very short time, generally it causes
large VCC/VSS line noise, which causes to degrade VIH min/VIL max level.
Rev 0.1 / Apr’01
G M 71V 65803C
G M 71V S65803C L
20.
21.
22.
23.
24.
25.
26.
27.
tHPC (min) can be achieved during a series of EDO mode early write cycles or EDO mode read
cycles. If both write and read operation are mixed in a EDO mode, RAS cycle { EDO mode mix
cycle (1),(2) } minimum value of CAS cycle t HPC (t CAS + t CP + 2t T) becomes greater than the
specified t HPC (min) value.
The value of CAS cycle time of mixed EDO page mode is
shown in EDO page mode mix cycle (1) and (2).
Data output turns off and becomes high impedance from later rising edge of RAS and CAS.
Hold time and turn off time are specified by the timing specifications of later rising edge of RAS
and CAS between tOHR and tOH, and between tOFR and tOFF.
tDOH defines the time at which the output level go cross. V OL= 0.8V, VOH =2.0V of output timing
reference level.
Before and after self refresh mode, execute CBR refresh to all refresh addresses in or within 64
ms period on the condition a and b below.
a. Enter self refresh mode within 15.6 us after either burst refresh or distributed refresh at equal
interval to all refresh addresses are completed.
b. Start burst refresh or distributed refresh at equal interval to all refresh addressed within 15.6us
after exiting from self refresh mode.
In case of entering from RAS-only-refresh, it is necessary to execute CBR refresh before and
after self refresh mode according as note 23.
For L_Version, it is available to apply each 128 ms and 31.2 us instead of 64ms and 15.6us at
note 23.
At t RASS > 100 us , self refresh mode is activated, and not active at t RASS < 10us . It is undefined
within the range of 10 us < tRASS < 100 us . for tRASS > 10 us , it is necessary to satisfy tRPS.
XXX: H or L ( H : VIH(min)<=VIN<=VIH(max), L: VIH(min)<=VIN<=VIH(max))
///////: Invalid Dout
When the address, clock and input pins are not described on timing waveforms, their pins must
be applied VIH or VIL.
Rev 0.1 / Apr’01
G M 71V 65803C
G M 71V S65803C L
S O J 32 pin PK G D i m ension
Unit: mm
0.64 M I N
21.38 M A X
1.165 M A X
0.33 M I N
1.27
0.53 M A X
0.33 M I N
0.49 M A X
0.10
2.09 M I N
3.01 M A X
11.05 MIN
11.31 MAX
9.65 MAX
9.15 MIN
10.03 MIN
MIN
3.24 MIN
3.76 MAX
20.95 M I N
Rev 0.1 / Apr’01
10.29 MAX
1.16 M A X
G M 71V 65803C
G M 71V S65803C L
T S O P I I 3 2 P I N Pack age D i m ension
0~5
10.16
1.20 MAX
N O R M A L TYPE
0.42
0.08
0.40
0.06
1.27
0.08
D i m en sion including the plating thickness
Base m aterial dimension
Rev 0.1 / Apr’01
0.05
0.125
0.04
0.80
M IN
0.18 M A X
0.10
0.145
0.68
1.15 M A X
Unit: mm
0.60 M A X
11.56 MIN
21.35 M A X
0.40 M I N
11.96 MAX
¡ £
20.95 M I N