ISL5640 Data Sheet ADV ANCE I NF O R MA T ION June 2000 3V Dual 8-Bit, 20/40/60MSPS A/D Converter with Internal Voltage Reference The ISL5640 is a monolithic, dual 8-bit analog-to-digital converter fabricated in an advanced CMOS process. It is designed for high speed applications where integration, bandwidth and accuracy are essential. The ISL5640 features a 9-stage pipeline architecture. The fully pipelined architecture and an innovative input stage enable the ISL5640 to accept a variety of input configurations, singleended or fully differential. Only one external clock is necessary to drive both converters and an internal band-gap voltage reference is provided. This allows the system designer to realize an increased level of system integration resulting in decreased cost and power dissipation. File Number 4657.3 Features • Sampling Rate . . . . . . . . . . . . . . . . . . . . . . . . . . .40MSPS • 7.4 Bits at fIN = 1MHz • Low Power at 40MSPS. . . . . . . . . . . . . . . . . . . . . 100mW • Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . <1mW • Wide Full Power Input Bandwidth. . . . . . . . . . . . . 250MHz • SFDR at fIN = 1MHz . . . . . . . . . . . . . . . . . . . . . . . . . .55dB • Excellent Channel-to-Channel Isolation . . . . . . . . . >75dB • On-Chip Sample and Hold Amplifiers • Internal Bandgap Voltage Reference . . . . . . . . . . . . 1.25V • Single Supply Voltage Operation . . . . . . . . . . . . . . . +3.0V • Offset Binary or Two’s Complement Output Format • Dual 8-Bit A/D Converters on a Monolithic Chip • Pin Compatible Upgrade to AD9288 The ISL5640 is offered in 20MSPS, 30MSPS, 40MSPS and 60MSPS sampling rates. Applications Ordering Information • PSK and QAM I&Q Demodulators • Medical Imaging Pinout -40 to 85 48 Ld LQFP Q48.7x7 30 ISL5640/4IN -40 to 85 48 Ld LQFP Q48.7x7 40 ISL5640/6IN -40 to 85 48 Ld LQFP Q48.7x7 60 Evaluation Platform GND 1 48 47 46 45 44 43 42 41 40 39 38 37 36 IIN+ 2 3 35 34 N/C 4 33 IVRIN 5 VROUT QVRIN 6 7 32 31 DVCC GND AVCC S1 8 9 3-1 GND AVCC GND DVCC 27 GND 26 N/C N/C QD0 QD1 N/C 28 11 25 12 13 14 15 16 17 18 19 20 21 22 23 24 QD3 QD2 GND 10 QD5 QD4 QIN+ QD6 S2 QIN- 30 29 QD7 IINDFS DVCC GND 25 AVCC ISL5640 EVAL 48 LEAD LQFP TOP VIEW ID0 ISL5640/3IN ID3 20 ID5 ID4 Q48.7x7 ID6 -40 to 85 48 Ld LQFP DVCC ISL5640/2IN • High Speed Data Acquisition GND ID7 PACKAGE SAMPLING RATE PKG. NO. (MSPS) AVCC I CLK TEMP. RANGE (oC) Q CLK PART NUMBER • Wireless Local Loop ID2 ID1 The ISL5640 has excellent dynamic performance while consuming less than 100mW power at 40MSPS. The A/D only requires a single +3.0V power supply. Data output latches are provided which present valid data to the output bus with a latency of 5 clock cycles. CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000 ISL5640 Functional Block Diagram I/QINI/QCLK CLOCK I/QIN+ S/H STAGE 1 2-BIT FLASH 2-BIT DAC + ∑ - X2 I/QD7 (MSB) I/QD6 DIGITAL DELAY AND DIGITAL ERROR CORRECTION STAGE 8 I/QD5 I/QD4 I/QD3 2-BIT FLASH 2-BIT DAC I/QD2 I/QD1 + I/QD0 (LSB) ∑ - X2 STAGE 9 2-BIT FLASH I OR Q CHANNEL VROUT MODE DATA FORMAT REFERENCE I/QVRIN AVCC 3-2 AGND DVCC DGND S1/S2 DFS ISL5640 Typical Application Schematic ISL5640 (2) IIN + IIN + IIN - (3) IIN - QIN + (11) QIN + QIN - (10) QIN - (LSB) ID0 (37) ID0 ID1 (38) ID1 ID2 (39) ID3 (40) ID2 ID3 ID4 (31) ID4 ID5 (42) ID5 ID6 (43) ID6 (MSB) ID7 (44) ID7 (LSB) QD0 (24) QD0 QD1 (23) QD1 QD2 (22) QD3 (21) QD2 QD3 QD4 (20) QD4 QD5 (19) QD5 QD6 (18) QD6 (MSB) QD7 (17) QD7 (5) IVRIN 0.1µF (6) QVRIN (7) VROUT CLOCK ICLK (47) QCLK (14) S1 (8) S1 S2 (9) S2 DFS (4) +3V (13,30,31,48) AVCC DV CC (15, 28, 33, 46) + 10µF DFS 0.1µF (12,29,32) AGND BNC AGND DGND 3-3 3V + 0.1µF DGND (16, 27, 34, 45) 10µF AND 0.1µF CAPS ARE PLACED AS CLOSE TO PART AS POSSIBLE 10µF ISL5640 Pin Descriptions Pin Descriptions (Continued) PIN NO. NAME Analog Ground 24 QD0 Q-Channel, Data Bit 0 Output (LSB) IIN+ I-Channel Positive Analog Input 25 N/C No Connect 3 IIN- I-Channel Negative Analog Input 26 N/C No Connect 4 DFS Data Format Select (Low for Offset Binary and High for Twos Complement Output Format) 27 DGND Digital Ground 28 DVCC Digital Supply 29 AGND Analog Ground 30 AVCC Analog Supply 31 AVCC Analog Supply Q-Channel Voltage Reference Input 32 AGND Analog Ground PIN NO. NAME 1 AGND 2 DESCRIPTION 5 IVRIN I-Channel Voltage Reference Input 6 VROUT +1.25V Reference Voltage Output (Decouple with 0.1µF Capacitor) DESCRIPTION 7 QVRIN 8 S1 Mode Select Pin 1 (See Table) 33 DVCC Digital Supply 9 S2 Mode Select Pin 2 (See Table) 34 DGND Digital Ground 10 QIN- Q-Channel Negative Analog Input 35 N/C No Connect 11 QIN+ Q-Channel Positive Analog Input 36 N/C No Connect 12 AGND Analog Ground 37 ID0 I-Channel, Data Bit 0 Output 13 AVCC Analog Supply 38 ID1 I-Channel, Data Bit 1 Output 14 QCLK Q-Channel Clock Input 39 ID2 I-Channel, Data Bit 2 Output 15 DVCC Digital Supply 40 ID3 I-Channel, Data Bit 3 Output 16 DGND Digital Ground 41 ID4 I-Channel, Data Bit 4 Output 17 QD7 Q-Channel, Data Bit 7 Output (MSB) 42 ID5 I-Channel, Data Bit 5 Output 18 QD6 Q-Channel, Data Bit 6 Output 43 ID6 I-Channel, Data Bit 6 Output 19 QD5 Q-Channel, Data Bit 5 Output 44 ID7 I-Channel, Data Bit 7 Output (MSB) 20 QD4 Q-Channel, Data Bit 4 Output 45 DGND Digital Ground 21 QD3 Q-Channel, Data Bit 3 Output 46 DVCC Digital Supply 22 QD2 Q-Channel, Data Bit 2 Output 47 ICLK I-Channel Clock Input 23 QD1 Q-Channel, Data Bit 1 Output 48 AVCC Analog Supply 3-4 ISL5640 Absolute Maximum Ratings TA = 25oC Thermal Information Supply Voltage, AVCC or DVCC to AGND or DGND . . . . . . . . . . .4V DGND to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3V Digital I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DGND to DVCC Analog I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . AGND to AVCC Operating Conditions Thermal Resistance (Typical, Note 1) θJA (oC/W) ISL5640IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC (Lead Tips Only) Temperature Range ISL5640IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Electrical Specifications AVDD = DVDD = +3.3V; VIN = 1.50V; fS = 40MSPS at 50% Duty Cycle; CL = 10pF; TA = 25oC; Unless Otherwise Specified PARAMETER TEST CONDITIONS MIN TYP MAX UNITS 8 - - Bits ACCURACY Resolution Integral Linearity Error, INL fIN = 1MHz - 0.5 - LSB Differential Linearity Error, DNL (Guaranteed No Missing Codes) fIN = 1MHz - ±0.2 ±1.0 LSB Offset Error, VOS fIN = DC -10 - +10 LSB Full Scale Error, FSE fIN = DC - 1 - LSB Minimum Conversion Rate No Missing Codes - - - MSPS Maximum Conversion Rate No Missing Codes 40 - - MSPS Effective Number of Bits, ENOB fIN = 1MHz - 7.5 - Bits Signal to Noise and Distortion Ratio, SINAD RMS Signal = -------------------------------------------------------------RMS Noise + Distortion fIN = 1MHz - 46 - dB Signal to Noise Ratio, SNR RMS Signal = ------------------------------RMS Noise fIN = 10MHz - 47 - dB Total Harmonic Distortion, THD fIN = 10MHz - -53 - dBc 2nd Harmonic Distortion fIN = 10MHz - -54 - dBc 3rd Harmonic Distortion fIN = 10MHz - -70 - dBc Spurious Free Dynamic Range, SFDR fIN = 10MHz - 54 - dBc Intermodulation Distortion, IMD f1 = 1MHz, f2 = 1.02MHz - - - dBc I/Q Channel Crosstalk - - - dBc I/Q Channel Offset Match - - - LSB I/Q Channel Full Scale Error Match - - - LSB DYNAMIC CHARACTERISTICS Transient Response (Note 2) - - - Cycle Over-Voltage Recovery 0.2V Overdrive (Note 2) - - - Cycle - 1.0 - V ANALOG INPUT Maximum Peak-to-Peak Single-Ended Analog Input Range Analog Input Resistance, RINA or RINB VINA, VINB = VREF, DC - - - MΩ Analog Input Capacitance, CINA or CINB VINA, VINB = 1.5V, DC - - - pF 3-5 ISL5640 Electrical Specifications AVDD = DVDD = +3.3V; VIN = 1.50V; fS = 40MSPS at 50% Duty Cycle; CL = 10pF; TA = 25oC; Unless Otherwise Specified (Continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Analog Input Bias Current, IBA or IBB VINA/VINB = ART/BRT, ARB/BRB, DC (Notes 2, 3) - - - µA Full Power Input Bandwidth, FPBW fS = 40MHz, (Note 2) - 250 - MHz Reference Voltage Input Range - - - V Total Reference Resistance, RRIN - 300 - Ω Reference Current, IRIN - - - mA REFERENCE VOLTAGE INPUT SAMPLING CLOCK INPUT Input Logic High Voltage, VIH CLK 2.0 - - V Input Logic Low Voltage, VIL CLK - - 0.8 V Input Logic High Current, IIH CLK, VIH = 3.3V - - - µA Input Logic Low Current, IIL CLK, VIL = 0V - - - µA Input Capacitance, CIN CLK - - - pF Output Logic High Voltage, VOH IOH = 100µA; DVDD = 3.3V - - - V Output Logic Low Voltage, VOL IOL = 1.5mA; DVDD = 3.3V - - - V Output Logic High Voltage, VOH IOH = 100µA; DVDD = 3.0V - - - V Output Logic Low Voltage, VOL IOL = 100µA; DVDD = 3.0V - - - V - - - pF Aperture Delay, tAP - 4 - ns Aperture Jitter, tAJ - 5 - psRMS Data Output Hold, tH - 10.7 - ns Data Output Delay, tOD - 11.7 - ns DIGITAL OUTPUTS Output Capacitance, COUT TIMING CHARACTERISTICS Data Latency, t LAT For a Valid Sample (Note 2) - 5 - Cycles Power-Up Initialization Data Invalid Time (Note 2) - - - Cycles Sample Clock Pulse Width (Low) (Note 2) 11.25 12.5 - ns Sample Clock Pulse Width (High) (Note 2) 11.25 12.5 - ns - ±5 - % Sample Clock Duty Cycle Variation POWER SUPPLY CHARACTERISTICS Analog Supply Voltage, AVDD (Note 2) 3.0 3.3 3.6 V Digital Supply Voltage, DVDD (Note 2) 3.0 3.3 3.6 V Supply Current, IDD fS = 40MSPS - 30.3 - mA - 100 110 mW Power Dissipation Offset Error Sensitivity, ∆VOS A VDD or DVDD = 3.3V ±5% - ±0.125 - LSB Gain Error Sensitivity, ∆FSE A VDD or DVDD = 3.3V ±5% - ±0.15 - LSB NOTES: 1. Parameter guaranteed by design or characterization and not production tested. 2. With the clock low and DC input. 3-6 ISL5640 Timing Waveforms ANALOG INPUT CLOCK INPUT SN - 1 HN - 1 SN HN SN + 1 HN + 1 SN + 2 SN + 5 HN + 5 SN + 6 HN + 6 SN + 7 HN + 7 SN + 8 HN + 8 INPUT S/H 1ST STAGE 2ND STAGE B1 , N - 1 B2 , N - 2 9TH STAGE B1 , N B2 , N - 1 B9 , N - 5 DATA OUTPUT B1 , N + 1 B1 , N + 4 B2 , N + 4 B2 , N B9 , N - 4 DN - 6 B1 , N + 5 B9 , N DN - 5 DN - 1 3. SN : N-th sampling period. 4. HN : N-th holding period. 5. BM , N : M-th stage digital output corresponding to N-th sampled input. 6. DN : Final data output corresponding to N-th sampled input. FIGURE 1. ISL5640 INTERNAL CIRCUIT TIMING ANALOG INPUT tAP tAJ 1.5V tOD tH DATA OUTPUT 2.4V DATA N-1 DATA N 0.5V FIGURE 2. ISL5640 INPUT TO OUTPUT TIMING 3-7 B1 , N + 7 B2 , N + 6 B9 , N + 2 DN NOTES: 1.5V B2 , N + 5 B9 , N + 1 tLAT CLOCK INPUT B1 , N + 6 B9 , N + 3 DN + 1 DN + 2 ISL5640 TABLE 1. A/D CODE TABLE OFFSET BINARY OUTPUT CODE DIFFERENTIAL INPUT VOLTAGE (I/QIN+ - I/QIN-) CODE CENTER DESCRIPTION MSB LSB I/QD9 I/QD8 I/QD7 I/QD6 I/QD5 I/QD4 I/QD3 I/QD2 I/QD1 I/QD0 +Full Scale (+fS) -1/4 LSB 0.499756V 1 1 1 1 1 1 1 1 1 1 +fS - 11/4 LSB 0.498779V 1 1 1 1 1 1 1 1 1 0 +3/4 LSB 732.422µV 1 0 0 0 0 0 0 0 0 0 -1/4 LSB -244.141µV 0 1 1 1 1 1 1 1 1 1 -fS + 13/4 LSB -0.498291V 0 0 0 0 0 0 0 0 0 1 -Full Scale (-fS) + 3/4 LSB -0.499268V 0 0 0 0 0 0 0 0 0 0 NOTE: 7. The voltages listed above represent the ideal center of each output code shown with VREFIN = +1.25V. Detailed Description Φ1 Theory of Operation The ISL5640 is a dual 8-bit fully differential sampling pipeline A/D converter with digital error correction logic. Figure 3 depicts the circuit for the front end differential-in-differentialout sample-and-hold (S/H) amplifiers. The switches are controlled by an internal sampling clock which is a nonoverlapping two phase signal, Φ1 and Φ2 , derived from the master sampling clock. During the sampling phase, Φ1 , the input signal is applied to the sampling capacitors, CS . At the same time the holding capacitors, CH , are discharged to analog ground. At the falling edge of Φ1 the input signal is sampled on the bottom plates of the sampling capacitors. In the next clock phase, Φ2 , the two bottom plates of the sampling capacitors are connected together and the holding capacitors are switched to the op amp output nodes. The charge then redistributes between CS and CH completing one sample-and-hold cycle. The front end sample-and-hold output is a fully-differential, sampled-data representation of the analog input. The circuit not only performs the sample-andhold function but will also convert a single-ended input to a fully-differential output for the converter core. During the sampling phase, the I/QIN pins see only the on-resistance of a switch and CS . The relatively small values of these components result in a typical full power input bandwidth of 400MHz for the converter. I/QIN+ Φ1 Φ1 Φ1 CS Φ2 I/QIN- CH -+ VOUT+ +- VOUT- CS Φ1 CH Φ1 FIGURE 3. ANALOG INPUT SAMPLE-AND-HOLD As illustrated in the Functional Block Diagram and the timing diagram in Figure 1, eight identical pipeline subconverter stages, each containing a two-bit flash converter and a twobit multiplying digital-to-analog converter, follow the S/H circuit with the ninth stage being a two bit flash converter. Each converter stage in the pipeline will be sampling in one phase and amplifying in the other clock phase. Each individual subconverter clock signal is offset by 180 degrees from the previous stage clock signal resulting in alternate stages in the pipeline performing the same operation. The output of each of the eight identical two-bit subconverter stages is a two-bit digital word containing a supplementary bit to be used by the digital error correction logic. The output of each subconverter stage is input to a digital delay line which is controlled by the internal sampling clock. The function of the digital delay line is to time align the digital outputs of the eight identical two-bit subconverter stages with the corresponding output of the ninth stage flash converter before applying the eighteen bit result to the digital error correction logic. The digital error correction logic uses the supplementary bits to correct any error that may exist before generating the final ten bit digital data output of the converter. Because of the pipeline nature of this converter, the digital data representing an analog input sample is output to the digital data bus following the 6th cycle of the clock after the 3-8 ISL5640 analog sample is taken (see the timing diagram in Figure 1). This time delay is specified as the data latency. After the data latency time, the digital data representing each succeeding analog sample is output during the following clock cycle. The digital output data is provided in offset binary format (see Table 1, A/D Code Table). Internal Reference Voltage Output, VROUT The ISL5640 is equipped with an internal 1.25V bandgap reference voltage generator, therefore, no external reference voltage is required. VROUT should be connected to VRIN when using the internal reference voltage. An external, usersupplied, 0.1µF capacitor may be connected from the VROUT output pin to filter any stray board noise. Reference Voltage Inputs, I/Q VREFIN The ISL5640 is designed to accept a 1.25V reference voltage source at the VRIN input pins for the I and Q channels. Typical operation of the converter requires VRIN to be set at 1.25V. The ISL5640 is tested with VRIN connected to VROUT yielding a fully differential analog input voltage range of ±0.5V. The user does have the option of supplying an external 1.25V reference voltage. As a result of the high input impedance presented at the VRIN input pin, MΩ typically, the external reference voltage being used is only required to source small amount of reference input current. In order to minimize overall converter noise it is recommended that adequate high frequency decoupling be provided at the reference voltage input pin, VRIN . For the AC coupled differential input (Figure 4) and with VRIN connected to VROUT, full scale is achieved when the VIN and -VIN input signals are 0.5VP-P, with -VIN being 180 degrees out of phase with VIN . The converter will be at positive full scale when the I/QIN+ input is at I/QVRIN + 0.25V and the I/QIN- input is at I/QVRIN - 0.25V (I/QIN+ - I/QIN- = +0.5V). Conversely, the converter will be at negative full scale when the I/QIN+ input is equal to I/QVRIN - 0.25V and I/QIN- is at I/QVRIN + 0.25V (I/QIN+ - I/QIN- = -0.5V). The analog input can be DC coupled (Figure 5) as long as the inputs are within the analog input common mode voltage range (0.25V ≤ VDC ≤ 2.75V). The resistors, R, in Figure 5 are not absolutely necessary but may be used as load setting resistors. A capacitor, C, connected from I/QIN+ to I/QIN- will help filter any high frequency noise on the inputs, also improving performance. Values around 20pF are sufficient and can be used on AC coupled inputs as well. Note, however, that the value of capacitor C chosen must take into account the highest frequency component of the analog input signal. VIN I/QIN+ VDC R C ISL5640 I/QVRIN -VIN R VDC I/QIN- Analog Input, Differential Connection The analog input of the ISL5640 is a differential input that can be configured in various ways depending on the signal source and the required level of performance. A fully differential connection (Figure 4 and Figure 5) will deliver the best performance from the converter. FIGURE 5. DC COUPLED DIFFERENTIAL INPUT Analog Input, Single-Ended Connection The configuration shown in Figure 6 may be used with a single ended AC coupled input. I/QIN+ VIN R ISL5640 I/QVRIN I/QIN+ VIN R VDC ISL5640 R -VIN I/QIN- I/QIN- FIGURE 4. AC COUPLED DIFFERENTIAL INPUT FIGURE 6. AC COUPLED SINGLE ENDED INPUT Since the ISL5640 is powered by a single +3V analog supply, the analog input is limited to be between ground and +3V. For the differential input connection this implies the analog input common mode voltage can range from 0.25V to 2.75V. The performance of the ADC does not change significantly with the value of the analog input common mode voltage. Again, with VRIN connected to VROUT, if VIN is a 1VP-P sinewave, then I/QIN+ is a 1.0VP-P sinewave riding on a positive voltage equal to VDC . The converter will be at positive full scale when I/QIN+ is at VDC + 0.5V (I/QIN+ I/QIN- = +0.5V) and will be at negative full scale when I/QIN+ is equal to VDC - 0.5V (I/QIN+ - I/QIN- = -0.5V). Sufficient 3-9 ISL5640 headroom must be provided such that the input voltage never goes above +3V or below AGND. In this case, VDC could range between 0.5V and 2.5V without a significant change in ADC performance. The simplest way to produce VDC is to use the I/QVRIN bias source, I/QVDC , output of the ISL5640. The single ended analog input can be DC coupled (Figure 7) as long as the input is within the analog input common mode voltage range. OPERATIONAL MODES S1 S2 MODE 0 0 Standby I and Q Channels. 0 1 I channel operates normally with Q Channel in standby mode. 1 0 I and Q Channels operating with I/Q output data in phase. 1 1 I and Q Channels operating with Q data 180 degrees out of phase. VIN I/QIN+ VDC The ISL5640 sampling clock input provides a standard highspeed interface to external TTL/CMOS logic families. R C VDC Sampling Clock Requirements ISL5640 I/QIN- FIGURE 7. DC COUPLED SINGLE ENDED INPUT The resistor, R, in Figure 7 is not absolutely necessary but may be used as a load setting resistor. A capacitor, C, connected from I/QIN+ to I/QIN- will help filter any high frequency noise on the inputs, also improving performance. Values around 20pF are sufficient and can be used on AC coupled inputs as well. Note, however, that the value of capacitor C chosen must take into account the highest frequency component of the analog input signal. A single ended source may give better overall system performance if it is first converted to differential before driving the ISL5640. Operational Mode The ISL5640 contains several operational modes including a normal two channel operation, placing one or both channels in standby and delaying the Q channel data 1/2 clock cycle. The operational mode is selected via the S1 and S2 pins and is asynchronous to either clock. When either channel is placed in standby, the output data is stalled and not high impedance. When recovering from standby, valid data is available after 20 clock cycles. In order to ensure rated performance of the ISL5640, the duty cycle of the clock should be held at 50% ±5%. It must also have low jitter and operate at standard TTL/CMOS levels. Performance of the ISL5640 will only be guaranteed at conversion rates above 1MSPS (Typ). This ensures proper performance of the internal dynamic circuits. Similarly, when power is first applied to the converter, a maximum of 20 cycles at a sample rate above 1MSPS must be performed before valid data is available. Supply and Ground Considerations The ISL5640 has separate analog and digital supply and ground pins to keep digital noise out of the analog signal path. The part should be mounted on a board that provides separate low impedance connections for the analog and digital supplies and grounds. For best performance, the supplies to the ISL5640 should be driven by clean, linear regulated supplies. The board should also have good high frequency decoupling capacitors mounted as close as possible to the converter. If the part is powered off a single supply then the analog supply can be isolated by a ferrite bead from the digital supply. Refer to the application note “Using Intersil High Speed A/D Converters” (AN9214) for additional considerations when using high speed converters. The delay mode can be used to set the Q channel 180 degrees out phase of the I channel if the same clock is driving both channels. If separate, inverted clocks are used for the I and Q channels, this feature can be used to align the data. All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site www.intersil.com 3-10