ETC HM5241605CTT-12

HM5241605C Series
4M LVTTL interface SDRAM (128-kword × 16-bit)
83 MHz/80 MHz/66 MHz/57 MHz
ADE-203-381C (Z)
Rev. 3.0
Nov. 11, 1997
Description
All inputs and outputs are referred to the rising edge of the clock input. The HM5241605C is offered in 2
banks for improved performance.
Features
• 3.3V Power supply
• Clock frequency: 80 MHz (VCC min = 3.0 V)/66 MHz/57 MHz (max)
: 83 MHz (VCC min = 3.15 V)
• LVTTL interface
• Single pulsed RAS
• 2 Banks can operates simultaneously and independently
• Burst read/write operation and burst read/single write operation capability
• Programmable burst length: 1/2/4/8/full page (256)
• Programmable burst sequence:
 Sequential
 Interleave
• Full page burst length capability
 Sequential burst
 Burst stop capability
• Programmable CAS latency: 1/2/3
• Byte control by DQMU and DQML
• 1024 refresh cycles: 16 ms
• 2 variations of refresh
 Auto refresh
 Self refresh
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HM5241605C Series
Ordering Information
Type No.
Frequency
Package
HM5241605CJ-12
HM5241605CJ-15
HM5241605CJ-17
80 (83*) MHz
66 MHz
57 MHz
400-mil 50-pin plastic SOJ (CP-50D)
HM5241605CTT-12
HM5241605CTT-15
HM5241605CTT-17
80 (83*) MHz
66 MHz
57 MHz
400-mil 50-pin plastic TSOP II (TTP-50D)
Note:
1. VCC min = 3.15 V
Pin Arrangement
HM5241605CJ Series
HM5241605CTT Series
VCC
1
50
VSS
VCC
1
50
VSS
I/O0
2
49
I/O15
I/O0
2
49
I/O15
I/O1
3
48
I/O14
I/O1
3
48
I/O14
VSSQ
4
47
VSSQ
VSSQ
4
47
VSSQ
I/O2
5
46
I/O13
I/O2
5
46
I/O13
I/O3
6
45
I/O12
I/O3
6
45
I/O12
VCCQ
7
44
VCCQ
VCCQ
7
44
VCCQ
I/O4
8
43
I/O11
I/O4
8
43
I/O11
I/O5
9
42
I/O10
I/O5
9
42
I/O10
VSSQ
10
41
VSSQ
VSSQ
10
41
VSSQ
I/O6
11
40
I/O9
I/O6
11
40
I/O9
I/O7
12
39
I/O8
VCCQ
13
38
VCCQ
I/O7
12
39
I/O8
VCCQ
13
38
VCCQ
DQML
14
37
NC
WE
15
36
DQMU
DQML
14
37
NC
WE
15
36
CAS
16
DQMU
CLK
CAS
16
35
RAS
17
34
35
CLK
CKE
RAS
17
34
CS
18
33
CKE
NC
CS
18
33
A9
19
32
NC
NC
A9
19
32
A8
20
31
NC
NC
A8
20
31
A0
21
30
NC
A7
A0
21
30
A1
22
A7
29
A6
A1
22
29
A6
A2
A3
23
28
A5
A2
23
28
A5
24
27
A4
A3
24
27
VCC
25
A4
VCC
25
26
VSS
26
(Top view)
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VSS
(Top view)
HM5241605C Series
Pin Description
Pin name
Function
A0 to A9
Address input
•
Row address
•
Column address
•
Bank select address
A0 to A8
A0 to A7
A9
I/O0 to I/O15
Data-input/output
CS
Chip select
RAS
Row address strobe command
CAS
Column address strobe command
WE
Write enable command
DQMU
Upper byte input/output mask
DQML
Lower byte input/output mask
CLK
Clock input
CKE
Clock enable
VCC
Power for internal circuit
VSS
Ground for internal circuit
VCCQ
Power for I/O circuit
VSS Q
Ground for I/O circuit
NC
No connection
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HM5241605C Series
Block Diagram
A0 to A9
A0 to A7
Column address
counter
A0 to A9
Column address
buffer
512 row X 256 column X 16 bit
Input
buffer
Sense amplifier & I/O bus
Bank 0
Row decoder
Column decoder
Sense amplifier & I/O bus
Column decoder
Row decoder
Memory array
Refresh
counter
Row address
buffer
Memory array
Bank 1
512 row X 256 column X 16 bit
Output
buffer
Control logic &
timing generator
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DQMU
WE
DQML
CAS
RAS
CS
CKE
CLK
I/O0 to I/O15
HM5241605C Series
Pin Functions
CLK (input pin): CLK is the master clock input to this pin. The other input signals are referred at CLK
rising edge.
CS (input pin): When CS is Low, the command input cycle becomes valid. When CS is High, all inputs
are ignored. However, internal operations (bank active, burst operations, etc.) are held.
RAS, CAS, and WE (input pins): Although these pin names are the same as those of conventional
DRAMs, they function in a different way. These pins define operation commands (read, write, etc.)
depending on the combination of their voltage levels. For details, refer to the command operation section.
A0 to A8 (input pins): Row address (AX0 to AX8) is determined by A0 to A8 level at the bank active
command cycle CLK rising edge. Column address (AY0 to AY7) is determined by A0 to A7 level at the
read or write command cycle CLK rising edge. And this column address becomes burst access start
address. A8 defines the precharge mode. When A8 = High at the precharge command cycle, both banks
are precharged. But when A8 = Low at the precharge command cycle, only the bank that is selected by A9
(BS) is precharged.
A9 (input pin): A9 is a bank select signal (BS). The memory array of the HM5241605C is divided into
bank 0 and bank 1, both which contain 512 row × 256 column × 16 bits. If A9 is Low, bank 0 is selected,
and if A9 is High, bank 1 is selected.
CKE (input pin): This pin determines whether or not the next CLK is valid. If CKE is High, the next
CLK rising edge is valid. If CKE is Low, the next CLK rising edge is invalid. This pin is used for powerdown and clock suspend modes.
DQMU/DQML (input pins): DQMU controls upper byte and DQML controls lower byte input/output
buffers.
Read operation: If DQMU/DQML is High, the output buffer becomes High-Z. If the DQMU/DQML is
Low, the output buffer becomes Low-Z.
Write operation: If DQMU/DQML is High, the previous data is held (the new data is not written). If
DQMU/DQML is Low, the data is written.
I/O0 to I/O15 (I/O pins): Data is input to and output from these pins. These pins are the same as those of
a conventional DRAM.
VCC and VCC Q (power supply pins): 3.3 V is applied. (VCC is for the internal circuit and VCCQ is for the
output buffer.)
VSS and VSS Q (power supply pins): Ground is connected. (VSS is for the internal circuit and V SS Q is for
the output buffer.)
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HM5241605C Series
Command Operation
Command Truth Table
The synchronous DRAM recognizes the following commands specified by the CS, RAS, CAS, WE and
address pins.
Function
Symbol
CKE
n-1 n
CS
RAS CAS WE
A9
A8
A0
to A7
Ignore command
DESL
H
H
H
×
×
×
×
×
×
No operation
NOP
H
H
L
H
H
H
×
×
×
Burst stop in full page
BST
H
H
L
H
H
L
×
×
×
Column address and read command READ
H
×
L
H
L
H
V
L
V
Read with auto-precharge
H
×
L
H
L
H
V
H
V
Column address and write command WRIT
H
×
L
H
L
L
V
L
V
Write with auto-precharge
H
×
L
H
L
L
V
H
V
Row address strobe and bank active ACTV
H
×
L
L
H
H
V
V
V
Precharge select bank
PRE
H
H
L
L
H
L
V
L
×
Precharge all bank
PALL
H
H
L
L
H
L
×
H
×
Refresh
REF/SELF H
V
L
L
L
H
×
×
×
Mode register set
MRS
H
L
L
L
L
V
V
V
READ A
WRIT A
H
Note: H: VIH. L: V IL. ×: VIH or VIL. V: Valid address input
Ignore command [DESL]: When this command is set (CS is High), the synchronous DRAM ignore
command input at the clock. However, the internal status is held.
No operation [NOP]: This command is not an execution command. However, the internal operations
continue.
Burst stop in full-page [BST]: This command stops a full-page burst operation (burst length = full-page
(256)), and is illegal otherwise. Full page burst continues until this command is input. When data
input/output is completed for a full-page of data (256), it automatically returns to the start address, and
input/output is performed repeatedly.
Column address strobe and read command [READ]: This command starts a read operation. In
addition, the start address of burst read is determined by the column address (AY0 to AY7) and the bank
select address (BS). After the read operation, the output buffer becomes High-Z.
Read with auto precharge [READ A]: This command automatically performs a precharge operation after
a burst read with a burst length of 1, 2, 4 or 8. When the burst length is full-page (256), this command is
illegal.
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HM5241605C Series
Column address strobe and write command [WRIT]: This command starts a write operation. When the
burst write mode is selected, the column address (AY0 to AY7) and the bank select address (A9) become
the burst write start address. When the single write mode is selected, data is only written to the location
specified by the column address (AY0 to AY7) and the bank select address (A9).
Write with auto precharge [WRIT A]: This command automatically performs a precharge operation
after a burst write with a length of 1, 2, 4 or 8, or after a single write operation. When the burst length is
full-page (256), this command is illegal.
Row address strobe and bank activate [ACTV]: This command activates the bank that is selected by A9
(BS) and determines the row address (AX0 to AX8). When A9 is Low, bank 0 is activated. When A9 is
High, bank 1 is activated.
Precharge selected bank [PRE]: This command starts precharge operation for the bank selected by A9.
If A9 is Low, bank 0 is selected. If A9 is High, bank 1 is selected.
Precharge all banks [PALL]: This command starts a precharge operation for all banks.
Refresh [REF/SELF]: This command starts the refresh operation. There are two types of refresh
operation, the one is auto refresh, and the other is self refresh. For details, refer to the CKE truth table
section.
Mode register set [MRS]: Synchronous DRAM has a mode register that defines how it operates. The
mode register is specified by the address pins (A0 to A9) at the mode register set cycle. For details, refer to
the mode register configuration. After power on, the contents of the mode register are undefined, execute
the mode register set command to set up the mode register.
DQM Truth Table
Function
Symbol
CKE
n-1
n
DQMU
DQML
Upper byte write enable/output enable
ENBU
H
×
L
×
Lower byte write enable/output enable
ENBL
H
×
×
L
Upper byte write inhibit/output disable
MASKU
H
×
H
×
Lower byte write inhibit/output disable
MASKL
H
×
×
H
Note: H: VIH. L: V IL. ×: VIH or VIL.
The HM5241605C series can mask input/output data by means of DQMU and DQML. DQMU masks the
upper byte and DQML masks the lower byte.
During reading, the output buffer is set to Low-Z by setting DQMU/DQML to Low, enabling data output.
On the other hand, when DQMU/DQML is set to High, the output buffer becomes High-Z, disabling data
output.
During writing, data is written by setting DQMU/DQML to Low. When DQMU/DQML is set to High, the
previous data is held (the new data is not written). Desired data can be masked during burst read or burst
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HM5241605C Series
write by setting DQMU/DQML. For details, refer to the DQM control section of the HM5241605C
operating instructions.
CKE Truth Table
Current state
Function
CKE
n-1
n
CS
RAS
CAS
WE
Address
Active
Clock suspend mode entry
H
L
H
×
×
×
×
Any
Clock suspend
L
L
×
×
×
×
×
L
H
L
H
H
H
×
L
H
H
×
×
×
×
Clock suspend Clock suspend mode exit
Idle
Auto-refresh command
REF
H
H
L
L
L
H
×
Idle
Self-refresh entry
SELF
H
L
L
L
L
H
×
Idle
Power down entry
H
L
L
H
H
H
×
H
L
H
×
×
×
×
SELFX L
H
L
H
H
H
×
L
H
H
×
×
×
×
L
H
L
H
H
H
×
L
H
H
×
×
×
×
Self refresh
Power down
Self refresh exit
Power down exit
Note: H: VIH. L: V IL. ×: VIH or VIL.
Clock suspend mode entry: The synchronous DRAM enters clock suspend mode from active mode by
setting CKE to Low. The clock suspend mode changes depending on the current status (1 clock before) as
shown below.
ACTIVE clock suspend: This suspend mode ignores inputs after the next clock by internally maintaining
the bank active status.
READ suspend and READ A suspend: The data being output is held (and continues to be output).
WRITE suspend and WRIT A suspend: In this mode, external signals are not accepted. However, the
internal state is held.
Clock suspend: During clock suspend mode, keep the CKL to Low.
Clock suspend mode exit: The synchronous DRAM exits from clock suspend mode by setting CKE to
High during the clock suspend state.
IDLE: In this state, all banks are not selected, and completed precharge operation.
Auto refresh command [REF]: When this command is input from the IDLE state, the synchronous
DRAM starts auto-refresh operation. (The auto-refresh is the same as the CBR refresh of conventional
DRAMs.) During the auto-refresh operation, refresh address and bank select address are generated inside
the synchronous DRAM. For every auto-refresh cycle, the internal address counter is updated.
Accordingly, 1,024 times are required to refresh the entire memory. Before executing the auto-refresh
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HM5241605C Series
command, all the banks must be in the IDLE state. In addition, since the precharge for all banks is
automatically performed after auto-refresh, no precharge command is required after auto refresh.
Self refresh entry [SELF]: When this command is input during the IDLE state, the synchronous DRAM
starts self refresh operation. After the execution of this command, self refresh continues while CKE is
Low. Since self refresh is performed internally and automatically, external refresh operations are
unnecessary.
Power down mode entry: When this command is executed during the IDLE state, the synchronous
DRAM enters power down mode. In power down mode, power consumption is suppressed by cutting off
the initial input circuit.
Self refresh exit: When this command is executed during self refresh mode, the synchronous DRAM can
exit from self refresh mode. After exiting from self refresh mode, the synchronous DRAM enters the IDLE
state.
Power down exit: When this command is executed at the power down mode, the synchronous DRAM can
exit from power down mode. After exiting from power down mode, the synchronous DRAM enters the
IDLE state.
Function Truth Table
The following table shows the operations that are performed when each command is issued in each mode of
the synchronous DRAM.
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HM5241605C Series
Current state CS
RAS CAS WE
Address
Command
Operation
Precharge
H
×
×
×
×
DESL
Enter IDLE after t RP
L
H
H
H
×
NOP
Enter IDLE after t RP
L
H
H
L
×
BST
ILLEGAL
L
H
L
H
BA, CA, A8 READ/READ A ILLEGAL
L
H
L
L
BA, CA, A8 WRIT/WRIT A
ILLEGAL
L
L
H
H
BA, RA
ACTV
ILLEGAL
L
L
H
L
BA, A8
PRE, PALL
ILLEGAL
L
L
L
H
×
REF, SELF
ILLEGAL
L
L
L
L
MODE
MRS
ILLEGAL
H
×
×
×
×
DESL
NOP
L
H
H
H
×
NOP
NOP
L
H
H
L
×
BST
NOP
L
H
L
H
BA, CA, A8 READ/READ A ILLEGAL
L
H
L
L
BA, CA, A8 WRIT/WRIT A
ILLEGAL
L
L
H
H
BA, RA
ACTV
Bank and row active
L
L
H
L
BA, A8
PRE, PALL
NOP
L
L
L
H
×
REF, SELF
Refresh
L
L
L
L
MODE
MRS
Mode register set
Idle
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HM5241605C Series
Current state CS
RAS CAS WE
Address
Command
Operation
Row active
H
×
×
×
×
DESL
NOP
L
H
H
H
×
NOP
NOP
L
H
H
L
×
BST
NOP
L
H
L
H
BA, CA, A8 READ/READ A Begin read
L
H
L
L
BA, CA, A8 WRIT/WRIT A
Begin write
L
L
H
H
BA, RA
ACTV
Other bank active ILLEGAL on same
bank*3
L
L
H
L
BA, A8
PRE, PALL
Precharge
L
L
L
H
×
REF, SELF
ILLEGAL
L
L
L
L
MODE
MRS
ILLEGAL
H
×
×
×
×
DESL
Continue burst to end
L
H
H
H
×
NOP
Continue burst to end
L
H
H
L
×
BST
Burst stop to full page
L
H
L
H
BA, CA, A8 READ/READ A Continue burst read to CAS latency
and New read
L
H
L
L
BA, CA, A8 WRIT/WRIT A
Term burst read/start write
L
L
H
H
BA, RA
ACTV
Other bank active ILLEGAL on same
bank*3
L
L
H
L
BA, A8
PRE, PALL
Term burst read and Precharge
L
L
L
H
×
REF, SELF
ILLEGAL
L
L
L
L
MODE
MRS
ILLEGAL
Read with auto H
precharge
X
×
×
×
DESL
Continue burst to end and precharge
L
H
H
H
×
NOP
Continue burst to end and precharge
L
H
H
L
×
BST
ILLEGAL
L
H
L
H
BA, CA, A8 READ/READ A ILLEGAL
L
H
L
L
BA, CA, A8 WRIT/WRIT A
ILLEGAL
L
L
H
H
BA, RA
ACTV
Other bank active ILLEGAL on same
bank*3
L
L
H
L
BA, A8
PRE, PALL
ILLEGAL
L
L
L
H
×
REF, SELF
ILLEGAL
L
L
L
L
MODE
MRS
ILLEGAL
Read
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HM5241605C Series
Current state CS
RAS CAS WE
Address
Command
Operation
Write
H
×
×
×
×
DESL
Continue burst to end
L
H
H
H
×
NOP
Continue burst to end
L
H
H
L
×
BST
Burst stop on full page
L
H
L
H
BA, CA, A8 READ/READ A Term burst and New read
L
H
L
L
BA, CA, A8 WRIT/WRIT A
Term burst and New write
L
L
H
H
BA, RA
ACTV
Other bank active ILLEGAL on same
bank*3
L
L
H
L
BA, A8
PRE, PALL
Term burst write and Precharge*2
L
L
L
H
×
REF, SELF
ILLEGAL
L
L
L
L
MODE
MRS
ILLEGAL
Write with auto H
precharge
×
×
×
×
DESL
Continue burst to end and precharge
L
H
H
H
×
NOP
Continue burst to end and precharge
L
H
H
L
×
BST
ILLEGAL
L
H
L
H
BA, CA, A8 READ/READ A ILLEGAL
L
H
L
L
BA, CA, A8 WRIT/WRIT A
ILLEGAL
L
L
H
H
BA, RA
ACTV
Other bank active ILLEGAL on same
bank*3
L
L
H
L
BA, A8
PRE, PALL
ILLEGAL
L
L
L
H
×
REF, SELF
ILLEGAL
L
L
L
L
MODE
MRS
ILLEGAL
H
×
×
×
×
DESL
Enter IDLE after t RC
L
H
H
H
×
NOP
Enter IDLE after t RC
L
H
H
L
×
BST
Enter IDLE after t RC
L
H
L
H
BA, CA, A8 READ/READ A ILLEGAL
L
H
L
L
BA, CA, A8 WRIT/WRIT A
ILLEGAL
L
L
H
H
BA, RA
ACTV
ILLEGAL
L
L
H
L
BA, A8
PRE, PALL
ILLEGAL
L
L
L
H
×
REF, SELF
ILLEGAL
L
L
L
L
MODE
MRS
ILLEGAL
Refresh (auto
refresh)
Notes 1. H: VIH. L: V IL. ×: VIH or VIL.
The other combinations are inhibit.
2. An interval of t RWL is required between the final valid data input and the precharge command.
3. If tRRD is not satisfied, this operation is illegal.
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HM5241605C Series
From [PRECHARGE]
To [DESL], [NOP] or [BST]: When these commands are executed, the synchronous DRAM enters the
IDLE state after tRP has elapsed from the completion of precharge.
From [IDLE]
To [DESL], [NOP], [BST], [PRE] or [PALL]: These commands result in no operation.
To [ACTV]: The bank specified by the address pins and the ROW address is activated.
To [REF], [SELF]: The synchronous DRAM enters refresh mode (auto refresh or self refresh).
To [MRS]: The synchronous DRAM enters the mode register set cycle.
From [ROW ACTIVE]
To [DESL], [NOP] or [BST]: These commands result in no operation.
To [READ], [READ A]: A read operation starts. (However, an interval of tRCD is required.)
To [WRIT], [WRIT A]: A write operation starts. (However, an interval of tRCD is required.)
To [ACTV]: This command makes the other bank active. (However, an interval of tRRD is required.)
Attempting to make the currently active bank active results in an illegal command.
To [PRE], [PALL]: These commands set the synchronous DRAM to precharge mode. (However, an
interval of t RAS is required.)
From [READ]
To [DESL], [NOP]: These commands continue read operations until the burst operation is completed.
To [BST]: This command stops a full-page burst.
To [READ], [READ A]: Data output by the previous read command continues to be output. After CAS
latency, the data output resulting from the next command will start.
To [WRIT], [WRIT A]: These commands stop a burst read, and start a write cycle.
To [ACTV]: This command makes other banks bank active. (However, an interval of tRRD is required.)
Attempting to make the currently active bank active results in an illegal command.
To [PRE], [PALL]: These commands stop a burst read, and the synchronous DRAM enters precharge
mode.
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HM5241605C Series
From [READ with AUTO-PRECHARGE]
To [DESL], [NOP]: These commands continue read operations until the burst operation is completed, and
the synchronous DRAM then enters precharge mode.
To [ACTV]: This command makes other banks bank active. (However, an interval of tRRD is required.)
Attempting to make the currently active bank active results in an illegal command.
From [WRITE]
To [DESL], [NOP]: These commands continue write operations until the burst operation is completed.
To [BST]: This command stops a full-page burst.
To [READ], [READ A]: These commands stop a burst and start a read cycle.
To [WRIT], [WRIT A]: These commands stop a burst and start the next write cycle.
To [ACTV]: This command makes the other bank active. (However, an interval of tRRD is required.)
Attempting to make the currently active bank active results in an illegal command.
To [PRE], [PALL]: These commands stop burst write and the synchronous DRAM then enters precharge
mode.
From [WRITE with AUTO PRECHARGE]
To [DESL], [NOP]: These commands continue write operations until the burst is completed, and the
synchronous DRAM enters precharge mode.
To [ACTV]: This command makes the other bank activ. (However, an interval of tRRD is required.)
Attempting to make the currently active bank active results in an illegal command.
From [REFRESH]
To [DESL], [NOP], [BST]: After an auto refresh cycle (after tRC), the synchronous DRAM automatically
enters the IDLE state.
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HM5241605C Series
Simplified State Diagram
SELF
REFRESH
SR ENTRY
SR EXIT
MRS
MODE
REGISTER
SET
REFRESH
IDLE
*1
AUTO
REFRESH
CKE
CKE_
IDLE
POWER
DOWN
ACTIVE
ACTIVE
CLOCK
SUSPEND
CKE_
CKE
ROW
ACTIVE
BST
(on full page)
BST
(on full page)
WRITE
Write
WRITE
SUSPEND
CKE_
WRITE
READ
WRITE
WITH
AP
READ
WRITE
CKE
READ
WITH AP
WRITE
WITH AP
WRITEA
CKE_
READ
CKE
CKE
POWER
ON
READ
SUSPEND
READ
WITH AP
CKE_
READA
CKE
PRECHARGE
POWER
APPLIED
WRITE
WITH AP
Read
PRECHARGE
CKE_
WRITEA
SUSPEND
READ
WITH
AP
READA
SUSPEND
PRECHARGE
PRECHARGE
PRECHARGE
Automatic transition after completion of command.
Transition resulting from command input.
Note: 1. After the auto-refresh operation, precharge operation is performed automatically and
enter the IDLE state.
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HM5241605C Series
Mode Register Configuration
The mode register is set by the input to the address pins (A0 to A9) during mode register set cycles. The
mode register consists of five sections, each of which is assigned to address pins.
A9 and A8: (OPCODE): The synchronous DRAM has two types of write modes. One is the burst write
mode, and the other is the single write mode. These bits specify write mode.
Burst read and BURST WRITE: Burst write is performed for the specified burst length starting from the
column address specified in the write cycle.
Burst read and SINGLE WRITE: Data is only written to the column address specified during the write
cycle, regardless of the burst length.
A7: Keep this bit Low at the mode register set cycle.
A6, A5, A4: (LMODE): These pins specify the CAS latency.
A3: (BT): A burst type is specified. When full-page burst is performed, only "sequential" can be selected.
A2, A1, A0: (BL): These pins specify the burst length.
A9
A8
A7
OPCODE
A6
0
A5
A4
LMODE
0
0
A2
BT
A6 A5 A4 CAS Latency
A9 A8
A3
A1
A0
BL
A3 Burst Type
A2 A1 A0
0
0
0
R
0 Sequential
0
0
1
1
1
0
1
0
2
0
1
1
3
0
1
×
×
R
0
Write mode
Burst read and burst write
R
Interleave
Burst Length
BT = 0 BT = 1
0
0
0
1
1
0
0
1
2
2
1
0
4
4
1
1
8
8
1
0
0
R
R
1
0
1
R
R
1
1
0
R
R
1
1
1
F.P.
R
0
1
1
0 Burst read and SINGLE WRITE
F.P. = Full Page (256)
1
1
R is Reserved (inhibit)
R
× = 0 or 1
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HM5241605C Series
Burst Sequence
Burst length = 2
Burst length = 4
Starting Ad. Addressing(decimal)
A0
Sequence
Interleave
Starting Ad. Addressing(decimal)
A1
A0
Sequence
Interleave
0
0, 1,
0, 1,
0
0
0, 1, 2, 3,
0, 1, 2, 3,
1
1, 0,
1, 0,
0
1
1, 2, 3, 0,
1, 0, 3, 2,
1
0
2, 3, 0, 1,
2, 3, 0, 1,
1
1
3, 0, 1, 2,
3, 2, 1, 0,
Burst length = 8
Addressing(decimal)
Starting Ad.
A2
A1
A0 Sequence
Interleave
0
0
0
0, 1, 2, 3, 4, 5, 6, 7,
0, 1, 2, 3, 4, 5, 6, 7,
0
0
1
1, 2, 3, 4, 5, 6, 7, 0,
1, 0, 3, 2, 5, 4, 7, 6,
0
1
0
2, 3, 4, 5, 6, 7, 0, 1,
2, 3, 0, 1, 6, 7, 4, 5,
0
1
1
3, 4, 5, 6, 7, 0, 1, 2,
3, 2, 1, 0, 7, 6, 5, 4,
1
0
0
4, 5, 6, 7, 0, 1, 2, 3,
4, 5, 6, 7, 0, 1, 2, 3,
1
0
1
5, 6, 7, 0, 1, 2, 3, 4,
5, 4, 7, 6, 1, 0, 3, 2,
1
1
0
6, 7, 0, 1, 2, 3, 4, 5,
6, 7, 4, 5, 2, 3, 0, 1,
1
1
1
7, 0, 1, 2, 3, 4, 5, 6,
7, 6, 5, 4, 3, 2, 1, 0,
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HM5241605C Series
Operation of HM5241605C Series
Read/Write Operations
Bank active: Before executing a read or write operation, the corresponding bank and the row address must
be activated by the bank active (ACTV) command. Either bank 0 or bank 1 is activated according to the
status of the A9 pin, and the row address (AX0 to AX8) is activated by the A0 to A8 pins at the bank active
command cycle. An interval of tRCD is required between the bank active command input and the following
read/write command input.
Read operation: A read operation starts when a read command is input. Output buffer becomes Low-Z in
the (CAS Latency - 1) cycle after read command set. HM5241605C series can perform a burst read
operation. The burst length can be set to 1,2,4,8 or full-page (256). The start address for a burst read is
specified by the column address (AY0 to AY7) and the bank select address (A9) at the read command set
cycle. In a read operation, data output starts after the number of cycles specified by the CAS Latency. The
CAS Latency can be set to 1, 2, 3. When the burst length is 1, 2, 4 or 8, the Dout buffer automatically
becomes High-Z at the next cycle after the successive burst-length data has been output. When the burst
length is full-page (256), data is repeatedly output until the burst stop command is input. The CAS latency
and burst length must be specified at the mode register.
CAS Latency
CLK
t RCD
Command
Address
ACTV
Row
READ
Column
CL = 1
Dout
CL = 2
CL = 3
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out 0
out 1
out 2
out 3
out 0
out 1
out 2
out 3
out 0
out 1
out 2
out 3
CL: CAS latency
Burst length = 4
HM5241605C Series
Burst Length
CLK
t RCD
Command
ACTV
READ
Address
Row
Column
out 0
BL = 1
out 0 out 1
BL = 2
Dout
out 0 out 1 out 2 out 3
BL = 4
out 0 out 1 out 2 out 3 out 4 out 5 out 6 out 7
BL = 8
out 0 out 1 out 2 out 3 out 4 out 5 out 6 out 7 out 8
out 255
out 0
out 1
BL = full page (256)
BL: Burst length
CAS latency = 2
Write operation: Burst write or single write mode is selected by the OPCODE (A9, A8) of the mode
register.
1. Burst write: A burst write operation is enabled by setting OPCODE (A9, A8) to (0, 0). A burst write
starts in the same cycle as a write command set. (The latency of data input is 0.) The burst length can be
set to 1, 2, 4, 8, and full-page, like burst read operations. The write start address is specified by the column
address (AY0 to AY7) and the bank select address (A9) at the write command set cycle.
Burst Write
CLK
t RCD
Command
ACTV
WRIT
Address
Row
Column
BL = 1
in 0
in 0
in 1
in 0
in 1
in 2
in 3
in 0
in 1
in 2
in 3
in 4
in 5
in 6
in 7
in 0
in 1
in 2
in 3
in 4
in 5
in 6
in 7
BL = 2
Din
BL = 4
BL = 8
BL = full page (256)
in 8
in 255
in 0
in 1
CAS latency = 1, 2, 3
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HM5241605C Series
2. Single write: A single write operation is enabled by setting OPCODE (A9, A8) to (1, 0). In a single
write operation, data is only written to the column address (AY0 to AY7) and the bank select address (A9)
specified by the write command set cycle without regard to the burst length setting. (The latency of data
input is 0).
Single Write
CLK
t RCD
Command
Address
Active
Row
Din
Write
Column
in 0
CAS latency = 1, 2, 3
Burst length = 1, 2, 4, 8, full page
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HM5241605C Series
Auto Precharge
Read with auto precharge: In this operation, since precharge is automatically performed after completing
a read operation, a precharge command need not be executed after each read operation. The command
executed for the same bank after the execution of this command must be the bank active (ACTV)
command. In addition, an interval defined by lAPR is required before execution of the next command.
CAS latency
Precharge start cycle
3
2 cycle before the final data is output
2
1 cycle before the final data is output
1
same cycle as the final data is output
CLK
CL=1 Command
READ
ACTV
out0
Dout
out1
out2
out3
lAPR
CL=2 Command
READ
ACTV
out0
Dout
out1
out2
out3
lAPR
CL=3 Command
READ
ACTV
out0
Dout
out1
out2
out3
lAPR
Note: Internal auto-precharge starts at the timing indicated by " ".
At CLK = 33 MHz (IAPR changes depending on the operating frequency.
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HM5241605C Series
Write with auto precharge: In this operation, since precharge is automatically performed after
completing a burst write or single write operation, a precharge command need not be executed after each
write operation. The command executed for the same bank after the execution of this command must be
the bank active (ACTV) command. In addition, an interval of lAPW is required between the final valid data
input and input of the next command.
Burst Write (Burst Length = 4)
CLK
Command
I/O (input)
WRIT
in0
ACTV
in1
in2
in3
lAPW
Single Write
CLK
Command
I/O (input)
WRIT
ACTV
in
lAPW
Full-page Burst Stop
Burst stop command during burst read: The burst stop (BST) command is used to stop data output
during a full-page burst. The BST command sets the output buffer to High-Z and stops the full-page burst
read. The timing from command input to the last data changes depending on the CAS latency setting.
When the CAS latency is 3, the data becomes invalid two cycles after the BST command. In addition, the
BST command is valid only during full-page burst mode, and is invalid with burst lengths of 1, 2, 4 and 8.
CAS latency
BST to valid data
BST to High impedance
1
0
1
2
1
2
3
2
3
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HM5241605C Series
CAS Latency = 1, Burst Length = full page
CLK
BST
Command
I/O (output)
out
out
out
out
out
l BSR
l BSH
0 cycle
1 cycle
CAS Latency = 2, Burst Length = full page
CLK
BST
Command
I/O (output)
out
out
out
out
out
out
l BSH = 2 cycle
l BSR = 1 cycle
CAS Latency = 3, Burst Length = full page
CLK
BST
Command
I/O (output)
out
out
out
out
out
out
l BSR = 2 cycle
out
l BSH = 3 cycle
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HM5241605C Series
Burst stop command at burst write: The burst stop command (BST command) is used to stop data input
during a full-page burst write. Data is still written in the same cycle as the BST command, but no data is
written in subsequent cycles. In addition, the BST command is only valid during full-page burst mode, and
is invalid with burst lengths of 1, 2, 4 and 8. And an interval of t RWL is required between the BST command
and the next precharge command.
Burst Length = full page
CLK
BST
Command
I/O (input)
in
in
PRE/PALL
in
l BSW = 1 cycle
t RWL
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HM5241605C Series
Command Intervals
Read command to Read command interval
1. Same bank, same ROW address: When another read command is executed at the same ROW address
of the same bank as the preceding read command execution, the second read can be performed after an
interval of no less than 1 cycle. Even when the first command is a burst read that is not yet finished, the
data read by the second command will be valid.
READ to READ Command Interval (same ROW address in same bank)
CLK
Command
ACTV
Address
(A0-A8)
Row
READ
READ
Column A Column B
BS(A9)
Dout
out A0 out B0 out B1 out B2 out B3
Bank0
Active
Column =A Column =B Column =A Column =B
Dout
Read
Read
Dout
CAS latency = 3
Burst length = 4
Bank0
2. Same bank, different ROW address: When the ROW address changes on same bank, consecutive
read commands cannot be executed; it is necessary to separate the two read commands with a precharge
command and a bank-active command.
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HM5241605C Series
3. Different bank: When the bank changes, the second read can be performed after an interval of no less
than 1 cycle, provided that the other bank is in the bank-active state. Even when the first command is a
burst read that is not yet finished, the data read by the second command will be valid.
READ to READ Command Interval (different bank)
CLK
Command
Address
(A0-A8)
ACTV
ACTV
Row 0
Row 1
READ
READ
Column A Column B
BS(A9)
Dout
out A0 out B0 out B1 out B2 out B3
Bank0
Active
Bank0 Bank1
Dout
Dout
Bank1 Bank0 Bank1
Active Read Read
CAS latency = 3
Burst length = 4
Write command to Write command interval
1. Same bank, same ROW address: When another write command is executed at the same ROW
address of the same bank as the preceding write command, the second write can be performed after an
interval of no less than 1 cycle. In the case of burst writes, the second write command has priority.
WRITE to WRITE Command Interval (same ROW address in same bank)
CLK
Command
ACTV
Address
(A0-A8)
Row
WRIT
WRIT
Column A Column B
BS(A9)
Din
in A0
Bank0
Active
in B0
in B1
Column =A Column =B
Write
Write
in B2
in B3
Burst write mode
Burst length = 4
Bank0
2. Same bank, different ROW address: When the ROW address changes, consecutive write commands
cannot be executed; it is necessary to separate the two write commands with a precharge command and a
bank-active command.
3. Different bank: When the bank changes, the second write can be performed after an interval of no less
than 1 cycle, provided that the other bank is in the bank-active state. In the case of burst write, the second
write command has priority.
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HM5241605C Series
WRITE to WRITE Command Interval (different bank)
CLK
Command
Address
(A0-A8)
ACTV
ACTV
Row 0
Row 1
WRIT
WRIT
Column A Column B
BS(A9)
Din
in A0
Bank0
Active
in B0
in B1
in B2
in B3
Burst write mode
Burst length = 4
Bank1 Bank0 Bank1
Active Write Write
Read command to Write command interval
1. Same bank, same ROW address: When the write command is executed at the same ROW address of
the same bank as the preceding read command, the write command can be performed after an interval of no
less than 1 cycle. However, DQMU/DQML must be set High so that the output buffer becomes High-Z
before data input.
READ to Write Command Interval (1)
CLK
Command
READ
WRIT
CL=1
DQMU
/DQML
CL=2
CL=3
Din
Dout
in B0
High-Z
in B1
in B2
in B3
Burst Length = 4
Burst write
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HM5241605C Series
READ to Write Command Interval (2)
CLK
Command
WRIT
READ
DQMU
/DQML
2 clock
CL=1
High-Z
Dout CL=2
High-Z
CL=3
High-Z
Din
2. Same bank, different ROW address: When the ROW address changes, consecutive write commands
cannot be executed; it is necessary to separate the two commands with a precharge command and a bankactive command.
3. Different bank: When the bank changes, the write command can be performed after an interval of no
less than 1 cycle, provided that the other bank is in the bank-active state. However, DQML/DQMU must
be set High so that the output buffer becomes High-Z before data input.
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HM5241605C Series
Write command to Read command interval
1. Same bank, same ROW address: When the read command is executed at the same ROW address of
the same bank as the preceding write command, the read command can be performed after an interval of no
less than 1 cycle. However, in the case of a burst write, data will continue to be written until one cycle
before the read command is executed.
WRITE to READ Command Interval (1)
CLK
Command
WRIT
READ
DQMU/DQML
Din
in A0
Dout
out B0
Column=A
Write
out B1
out B2
out B3
Burst write mode
CAS latency = 1
Burst length = 4
Bank0
CAS Latency
Column=B
Read
Column=B
Dout
WRITE to READ Command Interval (2)
CLK
Command
WRIT
READ
DQMU/DQML
Din
in A0
in A1
Dout
out B0
Column=A
Write
CAS Latency
Column=B
Read
Column=B
Dout
out B1
out B2
out B3
Burst write mode
CAS latency = 1
Burst length = 4
Bank0
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HM5241605C Series
2. Same bank, different ROW address: When the ROW address changes, consecutive read commands
cannot be executed; it is necessary to separate the two commands with a precharge command and a bankactive command.
3. Different bank: When the bank changes, the read command can be performed after an interval of no
less than 1 cycle, provided that the other bank is in the bank-active state. However, in the case of a burst
write, data will continue to be written until one cycle before the read command is executed (as in the case
of the same bank and the same address).
Read command to Precharge command interval (same bank): When the precharge command is
executed for the same bank as the read command that preceded it, the minimum interval between the two
commands is one cycle. However, since the output buffer then becomes High-Z after the cycles defined by
lHZP, there is a possibility that burst read data output will be interrupted, if the precharge command is input
during burst read. To read all data by burst read, the cycles defined by l EP must be assured as an interval
from the final data output to precharge command execution.
READ to PRECHARGE Command Interval (same bank): To output all data
CAS Latency = 1, Burst Length = 4
CLK
Command
READ
PRE/PALL
Dout
out A0
out A1
out A2
out A3
l EP = 0 cycle
CL=1
CAS Latency = 2, Burst Length = 4
CLK
Command
READ
PRE/PALL
Dout
out A0
CL=2
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out A1
out A2
out A3
l EP = -1 cycle
HM5241605C Series
CAS Latency = 3, Burst Length = 4
CLK
Command
READ
PRE/PALL
Dout
out A0
out A1
CL=3
out A2
out A3
l EP = -2 cycle
READ to PRECHARGE Command Interval (same bank): To stop output data
CAS Latency = 1, Burst Length = 2, 4, 8
CLK
Command
READ
PRE/PALL
High-Z
Dout
out A0
l HZP =1
CAS Latency = 2, Burst Length = 2, 4, 8
CLK
Command
READ
PRE/PALL
High-Z
Dout
out A0
l HZP =2
CAS Latency = 3, Burst Length = 2, 4, 8
CLK
Command
READ
PRE/PALL
High-Z
Dout
out A0
l HZP =3
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HM5241605C Series
Write command to Precharge command interval (same bank): When the precharge command is
executed for the same bank as the write command that preceded it, the minimum interval between the two
commands is 1 cycle. However, if the burst write operation is unfinished, the input data must be masked
by means of DQMU and DQML for assurance of the cycle defined by tRWL.
WRITE to PRECHARGE Command Interval (same bank)
Burst Length = 4 (To stop write operation)
CLK
Command
WRIT
PRE/PALL
DQMU/DQML
Din
t RWL
CLK
Command
WRIT
PRE/PALL
DQMU/DQML
Din
in A0
in A1
t RWL
Burst Length = 4 (To write all data)
CLK
Command
WRIT
PRE/PALL
DQMU/DQML
Din
in A0
in A1
in A2
in A3
t RWL
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HM5241605C Series
Bank active command interval
1. Same bank: The interval between the two bank-active commands must be no less than tRC.
Bank active to bank active for same bank
CLK
Command
ACTV
ACTV
Address
(A0-A8)
ROW
ROW
BS (A9)
t RC
Bank 0
Active
Bank 0
Active
2. In the case of different bank-active commands: The interval between the two bank-active commands
must be no less than tRRD.
Bank active to bank active for different bank
CLK
Command
ACTV
ACTV
Address
(A0-A8)
ROW:0
ROW:1
BS (A9)
t RRD
Bank 0
Active
Bank 1
Active
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HM5241605C Series
Mode register set to Bank-active command interval: The interval between setting the mode register and
executing a bank-active command must be no less than tRSA .
CLK
Command
MRS
ACTV
Address
(A0-A9)
CODE
BS & ROW
t RSA
Mode
Register Set
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Bank
Active
HM5241605C Series
DQM Control
The DQMU and DQML mask the lower and upper bytes of the I/O data, respectively. The timing of
DQMU/DQML is different during reading and writing.
Reading: When data is read, the output buffer can be controlled by DQMU/DQML. By setting
DQMU/DQML to Low, the output buffer becomes Low-Z, enabling data output. By setting
DQMU/DQML to High, the output buffer becomes High-Z, and the corresponding data is not output.
However, internal reading operations continue. The latency of DQMU/DQML during reading is 2.
CLK
DQMU
/DQML
I/O (output)
High-Z
out 0
out 1
out 3
lDOD = 2 Latency
Writing: Input data can be masked by DQMU/DQML. By setting DQMU/DQML to Low, data can be
written. In addition, when DQMU/DQML is set to High, the corresponding data is not written, and the
previous data is held. The latency of DQMU/DQML during writing is 0.
CLK
DQMU
/DQML
I/O (input)
in 0
in 3
in 1
l DID = 0 Latency
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HM5241605C Series
Refresh
Auto refresh: All the banks must be precharged before executing an auto refresh command. Since the
auto refresh command updates the internal counter every time it is executed and determines the banks and
the ROW addresses to be refreshed, external address specification is not required. The refresh cycle is
1,024 cycles/16 ms. (1,024 cycles are required to refresh all the ROW addresses.) The output buffer
becomes High-Z after auto refresh start. In addition, since a precharge has been completed by an internal
operation after the auto refresh, an additional precharge operation by the precharge command is not
required.
Self refresh: After executing a self refresh command, the self refresh operation continues while CKE is
held Low. During self refresh operation, all ROW addresses are refreshed by the internal refresh timer. A
self refresh is terminated by a self refresh exit command. If you use distributed auto-refresh mode with
15.6 µs interval in normal read/write cycle, auto-refresh should be executed within 15.6 µs immediately
after exiting from and before entering into self refresh mode. If you use address refresh or burst autorefresh mode in normal read/write cycle, 1024 cycles of distributed auto-refresh with 15.6 µs interval
should be executed within 16 ms immediately from and before entering into self refresh mode.
Others
Power down mode: The synchronous DRAM enters power down mode when CKE goes Low in the IDLE
state. In power down mode, power consumption is suppressed by deactivating the input initial circuit.
Power down mode continues while CKE is held Low. In addition, by setting CKE to High, the
synchronous DRAM exits from the power down mode, and command input is enabled from the next cycle.
In this mode, internal refresh is not performed.
Clock suspend mode: By driving CKE to Low during a bank-active or read/write operation, the
synchronous DRAM enters clock suspend mode. During clock suspend mode, external input signals are
ignored and the internal state is maintained. When CKE is driven High, the synchronous DRAM
terminates clock suspend mode, and command input is enabled from the next cycle. For details, refer to the
"CKE Truth Table".
Power up sequence: HM5241605C series has two types of power up sequence. Hitachi recommends that
the DQMU/DQML and the CKE are set to High to ensure output to be in the high impedance and to
prevent from bus contention.
1. During power up sequence, the DQMU/DQML and the CKE must be set to High. When 100 µs has
past after power on, all banks must be precharged using the precharge command. After tRP delay, set the
mode register. And after tRSA delay, execute two or more cycles of auto refresh operation as dummy, an
interval of t RC is required between two auto refresh commands.
2. During power up sequence, the DQMU/DQML and the CKE must be set to High. When 200 µs has
past after power on, all banks must be precharged using the precharge command. After tRP delay, set 8 or
more auto refresh commands. And set the mode register set command to initialize the mode register.
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HM5241605C Series
Absolute Maximum Ratings
Parameter
Symbol
Value
Unit
Notes
Voltage on any pin relative to V SS
VT
–1.0 to +5.5
V
1, 2
Supply voltage relative to VSS
VCC
–1.0 to +4.6
V
2
Short circuit output current
Iout
50
mA
Power dissipation
PT
1.0
W
Operating temperature
Topr
0 to +70
°C
Storage temperature
Tstg
–55 to +125
°C
Notes: 1. VIH (max) = 5.75 V for pulse width ≤ 5 ns.
2. Respect to V SS .
Recommended DC Operating Conditions (Ta = 0 to +70°C)
Parameter
Symbol
Min
Max
Unit
Notes
Supply voltage
VCC, VCCQ
3.0
3.6
V
1
VSS , VSS Q
0
0
V
Input high voltage
VIH
2.0
5.5
V
1, 2
Input low voltage
VIL
–0.3
0.8
V
1, 3
Notes: 1. All voltage referred to VSS
2. VIH (max) = 5.75 V for pulse width ≤ 5 ns
3. VIL (min) = –1.0 V for pulse width ≤ 5 ns
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HM5241605C Series
DC Characteristics (Ta = 0 to 70°C, VCC, VCCQ = 3.3 V ± 0.3 V, VSS, VSSQ = 0 V)
HM5241605C
-12
-15
-17
Parameter
Symbol Min
Max Min
Max Min
Max Unit Test conditions
Notes
Operating current
I CC1
—
95
—
85
—
75
mA
Burst length = 1
t RC = min
1, 2, 4
Standby current
I CC2
—
3
—
3
—
3
mA
CKE = VIL, t CK = min
5
—
2
—
2
—
2
mA
CKE = VIL
CLK = VIL or VIH Fixed
6
—
39
—
33
—
30
mA
CKE = VIH,
NOP command,
t CK = min
3
—
7
—
7
—
7
mA
CKE = VIL, t CK = min,
I/O = High-Z
1, 2
—
40
—
34
—
31
mA
CKE = VIH,
NOP command
t CK = min, I/O = High-Z
1, 2, 3
t CK = min, BL = 4
1, 2, 4
(Bank Disable)
Active standby current I CC3
(Bank active)
Burst operating
current
(CL = 1)
I CC4
—
65
—
65
—
60
mA
(CL = 2)
I CC4
—
100
—
100
—
95
mA
(CL = 3)
I CC4
—
120
—
105
—
95
mA
Auto refresh current
I CC5
—
85
—
70
—
65
mA
t RC = min
Self refresh current
I CC6
—
2
—
2
—
2
mA
VIH ≥ V CC – 0.2
VIL ≤ 0.2 V
Input leakage current
I LI
–10
10
–10
10
–10
10
µA
0 ≤ Vin ≤ V CC
Output leakage
current
I LO
–10
10
–10
10
–10
10
µA
0 ≤ Vout ≤ V CC
I/O = disable
Output high voltage
VOH
2.4
—
2.4
—
2.4
—
V
I OH = –2 mA
Output low voltage
VOL
—
0.4
—
0.4
—
0.4
V
I OL = 2 mA
7
Notes: 1. I CC depends on output load condition when the device is selected. ICC (max) is specified at the
output open condition.
2. One bank operation.
3. Input signal transition is once per two CLK cycles.
4. Input signal transition is once per one CLK cycle.
5. After power down mode set, CLK operating current.
6. After power down mode set, no CLK operating current.
7. After self refresh mode set, self refresh current.
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HM5241605C Series
Capacitance (Ta = 25°C, VCC, VCCQ = 3.3 V ± 0.3 V)
Parameter
Symbol
Typ
Max
Unit
Notes
Input capacitance (Address)
CI1
—
5
pF
1, 3
Input capacitance (Signals)
CI2
—
5
pF
1, 3
Output capacitance (I/O)
CO
—
7
pF
1, 2, 3
Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. DQMU/DQML = VIH to disable Dout.
3. This parameter is sampled and not 100% tested.
AC Characteristics (Ta = 0 to 70°C, VCC, VCCQ = 3.3 V ± 0.3 V, VSS, VSSQ = 0 V)
HM5241605C
-12
-15
-17
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Unit Notes
System clock cycle time
(CL = 1)
t CK
30
—
30
—
35
—
ns
(CL = 2)
t CK
15
—
15
—
17.5
—
ns
(CL = 3)
t CK
12.5 —
(12.0)
15
—
17.5
—
ns
CLK high pulse width
t CKH
4.5
—
6
—
7
—
ns
1
CLK low pulse width
t CKL
4.5
—
6
—
7
—
ns
1
Access time from CLK
(CL = 1)
t AC
—
26
—
30
—
34
ns
1, 2
(CL = 2)
t AC
—
13
—
15
—
16.5
ns
(CL = 3)
t AC
—
11
—
13
—
15.5
ns
t ACK
—
26
—
30
—
34
ns
(CL = 2)
t ACK
—
28
—
30
—
34
ns
(CL = 3)
t ACK
—
36
—
43
—
50.5
ns
t OH
4
—
4
—
4
—
ns
t OH
3
—
3
—
3
—
ns
CLK to Data-out low impedance
t LZ
0
—
0
—
0
—
ns
1, 2
CLK to Data-out high impedance
(CL = 1)
t HZ
4
12
4
15
4
17
ns
1, 3
t HZ
3
9
3
10
3
12
ns
Read command to data valid time
(CL = 1)
Data-out hold time
(CL = 1)
(CL = 2, 3)
(CL = 2, 3)
1, 7
1
1, 2
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HM5241605C Series
AC Characteristics (Ta = 0 to 70°C, VCC, V CCQ = 3.3 V ± 0.3 V, VSS, V SSQ = 0 V)
(cont.)
HM5241605C
-12
-15
-17
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Unit Notes
Data-in setup time
t DS
3.5
—
4
—
4
—
ns
1
Data in hold time
t DH
1.5
—
2
—
2
—
ns
1
Address setup time
t AS
3.5
—
4
—
4
—
ns
1
Address hold time
t AH
1.5
—
2
—
2
—
ns
1
CKE setup time
t CES
3.5
—
4
—
4
—
ns
1, 4
CKE setup time for CKE function exit
t CESP
8.5
—
13
—
15
—
ns
1, 5
CKE hold time
t CEH
1.5
—
2
—
2
—
ns
1
CKE hold time for CKE function exit
t CEHP
14
—
17
—
19.5
—
ns
1, 6
Command (CS, RAS, CAS, WE, DQM)
setup time
t CS
3.5
—
4
—
4
—
ns
1
Command (CS, RAS, CAS, WE, DQM)
hold time
t CH
1.5
—
2
—
2
—
ns
1
Ref/Active to Ref/Active command
period
t RC
110
—
110
—
120
—
ns
1
Active to precharge command period
t RAS
70
10000 70
10000 75
10000 ns
1
Active to precharge on full page mode
t RASC
—
80000 —
80000 —
80000 ns
1
Active command to column command
(same bank)
t RCD
30
—
30
—
35
—
ns
1
Precharge to active command period
t RP
30
—
34
—
34
—
ns
1
The last data-in to Precharge lead time
t RWL
25
—
30
—
35
—
ns
1
Active (a) to Active (b) command period t RRD
25
—
30
—
35
—
ns
1
Register set to active command
t RSA
25
—
30
—
35
—
ns
1
Transition time (rise to fall)
tT
1
5
1
5
1
5
ns
Refresh period
t REF
—
16
—
16
—
16
ms
Notes: 1. AC measurement assumes t T = 1 ns. Reference level for timing of input signals is 1.40 V.
2. Access time is measured at 1.40 V. Load condition is C L = 50 pF with current source.
3. t HZ (max) defines the time at which the outputs achieves ± 200 mV. Load condition is CL = 5 pF
with current source.
4. t CES define CKE setup time to CLK rising edge except power down exit command and active
clock suspend exit command.
5. t CESP define CKE setup time to CLK rising edge for power down exit command and active clock
suspend exit command.
6. t CEHP define CLK rising edge to CKE hold time for self refresh exit command, power down exit
command and active clock suspend exit command.
7. t CK min = 12.0 ns (-12) is available under VCC min = 3.15 V.
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HM5241605C Series
Test Conditions
• Input and output timing reference levels: 1.4 V
• Input waveform and output load: See following figures.
2.8 V
Output
I/O
80%
Input
500 Ω
20%
V SS
+1.4 V
CL
t
T
tT
Relationship Between Frequency and Minimum Latency
HM5241605C
Parameter
-12
-15
Symbol
80
40
12.5 25
66
15
33
30
57
28.5
17.5 35
Note
Active command to column command
(same bank)
t RCD
3
2
2
1
2
1
1
Active command to active command
(same bank)
t RC
9
5
8
5
7
4
1,
= [tRAS + tRP]
Active command to precharge command
(same bank)
t RAS
6
3
5
3
5
3
1
Precharge command to active command
(same bank)
t RP
3
2
3
2
2
1
1
Last data input to precharge command
(same bank)
t RWL
2
1
2
1
2
1
1
Active command to active command
(different bank)
t RRD
2
1
2
1
2
1
1
Last data in to active command
(auto precharge, same bank)
lAPW
5
3
5
3
4
2
= [tRWL + tRP]
Self refresh exit to command input
lSEC
9
5
8
4
7
4
= [tRC]
Precharge command to high impedance
(CAS latency = 1)
lHZP
—
—
—
1
—
1
(CAS latency = 2)
lHZP
—
2
2
2
2
2
(CAS latency = 3)
lHZP
3
3
3
3
3
3
Frequency (MHz)
tCK (ns)
-17
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HM5241605C Series
HM5241605C
Parameter
-12
-15
-17
Frequency (MHz)
tCK (ns)
Symbol
80
40
12.5 25
66
15
33
30
57
28.5
17.5 35
Note
Last data out to active command
(auto precharge, same bank)
(CAS latency = 1)
lAPR
—
—
—
2
—
1
= [tRP]
(CAS latency = 2)
lAPR
2
1
2
1
—
1
= [tRP] – 1
(CAS latency = 3)
lAPR
2
1
2
1
1
0
= [tRP] – 1
—
—
—
0
—
0
Last data out to precharge (early precharge)
(CAS latency = 1)
lEP
(CAS latency = 2)
lEP
–1
–1
–1
–1
–1
–1
(CAS latency = 3)
lEP
–2
–2
–2
–2
–2
–2
Column command to column command
lCCD
1
1
1
1
1
1
Write command to data in latency
lWCD
0
0
0
0
0
0
DQM to data in
lDID
0
0
0
0
0
0
DQM to data out
lDOD
2
2
2
2
2
2
CKE to CLK disable
lCLE
1
1
1
1
1
1
Register set to active command
t RSA
2
1
2
1
2
1
CS to command disable
lCDD
0
0
0
0
0
0
Power down exit to command input
lPEC
1
1
1
1
1
1
Burst stop to output valid data hold
(CAS latency = 1)
lBSR
—
—
—
0
—
0
(CAS latency = 2)
lBSR
1
1
1
1
1
1
(CAS latency = 3)
lBSR
2
2
2
2
2
2
lBSH
—
—
—
1
—
1
(CAS latency = 2)
lBSH
2
2
2
2
2
2
(CAS latency = 3)
lBSH
3
3
3
3
3
3
lBSW
1
1
1
1
1
1
Burst stop to output high impedance
(CAS latency = 1)
Burst stop to write data ignore
Note:
1. t RCD to tRRD are recommended value.
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HM5241605C Series
Timing Waveforms
Read Cycle
t CK
t CKH t CKL
CLK
t RC
VIH
CKE
t CS t CH
t
t RAS
t RCD
t CS t CH
RP
t CS t CH
t CS t CH
t CS t CH
t CS t CH
t CS t CH
t CS t CH
CS
t CS t CH
t CS t CH
RAS
t CS t CH
t CS t CH
CAS
t CS t CH
t CS t CH
t AS t AH
t AS t AH
t AS t AH
t AS t AH
t AS t AH
t CS t CH
t CS t CH
WE
t AS t AH
A9
t AS t AH
t AS t AH
A8
t AS t AH
t AS t AH
t AS t AH
Address
t CH
t CS
DQMU/L
I/O(input)
t AC
tACK
I/O(output)
t AC
t AC
t AC
Bank 0
Active
Bank 0
Read
t LZ
t OH
t OH
t OH
Bank 0
Precharge
t HZ
Burst length = 4
Bank0 Access
= VIH or V IL
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HM5241605C Series
Write Cycle
t CK
t CKH t CKL
CLK
t RC
VIH
CKE
t RAS
t RCD
t CS t CH
t RP
t CS t CH
t CS t CH
t CS t CH
t CS t CH
t CS t CH
t CS t CH
t CS t CH
CS
t CS t CH
t CS t CH
RAS
t CS t CH
t CS t CH
CAS
t CS t CH
t CS t CH
t CS t CH
t AS t AH
t AS t AH
t AS t AH
t AS t AH
t CS t CH
WE
t AS t AH
t AS t AH
A9
t AS t AH
t AS t AH
A8
t AS t AH
t AS t AH
t AS t AH
Address
t CS
t CH
DQMU/L
t DS t DH tDS
t DH t DS t DH t DS
t DH
I/O(input)
t RWL
I/O(output)
Bank 0
Active
Bank 0
Write
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Bank 0
Precharge
Burst length = 4
Bank0 Access
= VIH or V IL
HM5241605C Series
Mode Register Set Cycle
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
CLK
CKE
VIH
CS
RAS
CAS
WE
A9(BS)
Address
code
valid
C: b’
C: b
R: b
DQMU/L
I/O(output)
b
b+3
b’
b’+1
b’+2
b’+3
High-Z
I/O(input)
t RSA
t RP
Precharge
If needed
Mode register
Set
t RCD
Bank 1
Active
Output mask
Bank 1
Read
tRCD = 3
CAS latency = 3
Burst length = 4
= VIH or VIL
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HM5241605C Series
Read Cycle/Write Cycle
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
CLK
CKE
Read cycle
RAS-CAS delay = 3
CAS latency = 3
Burst length = 4
= VIH or VIL
VIH
CS
RAS
CAS
WE
A9(BS)
Address
DQMU/L
I/O
(output)
I/O
(input)
CKE
R:a
C:a
R:b
C:b
a
C:b'
a+1 a+2 a+3
b
C:b"
b+1 b+2 b+3 b'
b'+1 b"
b"+1 b"+2 b"+3
High-Z
Bank 0
Active
Bank 0
Read
Bank 1
Active
Bank 1 Bank 0
Read
Precharge
Bank 1
Read
Bank 1
Read
Bank 1
Precharge
Write cycle
RAS-CAS delay = 3
CAS latency = 3
Burst length = 4
= VIH or VIL
VIH
CS
RAS
CAS
WE
A9(BS)
Address
DQMU/L
R:a
C:a
R:b
C:b
C:b'
C:b"
High-Z
I/O
(output)
I/O
(input)
a
Bank 0
Active
Bank 0
Write
a+1 a+2 a+3
Bank 1
Active
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b
Bank 1
Write
b+1 b+2 b+3 b'
Bank 0
Precharge
Bank 1
Write
b'+1 b"
Bank 1
Write
b"+1 b"+2 b"+3
Bank 1
Precharge
HM5241605C Series
Read/Single Write Cycle
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
CLK
CKE
VIH
CS
RAS
CAS
WE
A9(BS)
R:a
Address
C:a
R:b
DQMU/L
I/O
(input)
I/O
(output)
a
a
Bank 0
Active
CKE
C:a' C:a
Bank 0
Read
Bank 1
Active
C:a
R:b
a+1 a+2 a+3
a
Bank 0 Bank 0
Write Read
a+1 a+2 a+3
Bank 0
Precharge
Bank 1
Precharge
VIH
CS
RAS
CAS
WE
A9(BS)
Address
DQMU/L
I/O
(input)
I/O
(output)
R:a
a
Bank 0
Active
Bank 0
Read
Bank 1
Active
a+1
C:a
C:b C:c
a
b
c
a+3
Bank 0
Write
Bank 0 Bank 0
Write Write
Bank 0
Precharge
Read/Single write
RAS-CAS delay = 3
CAS latency = 3
Burst length = 4
= VIH or VIL
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HM5241605C Series
Read/Burst Write Cycle
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
CLK
CKE
CS
RAS
CAS
WE
A9(BS)
R:a
Address
DQMU/L
I/O
(input)
I/O
(output)
CKE
C:a
R:b
C:a'
a
a
Bank 0
Active
Bank 0
Read
Bank 1
Active
C:a
R:b
a+1 a+2 a+3
a+1 a+2 a+3
Clock
suspend
Bank 0
Write
Bank 0
Precharge
Bank 1
Precharge
VIH
CS
RAS
CAS
WE
A9(BS)
Address
DQMU/L
R:a
I/O
(input)
I/O
(output)
C:a
a
a
Bank 0
Active
Bank 0
Read
Bank 1
Active
a+1
a+1 a+2 a+3
a+3
Bank 0
Write
Bank 0
Precharge
Read/Burst write
RAS-CAS delay = 3
CAS latency = 3
Burst length = 4
= VIH or VIL
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HM5241605C Series
Full Page Read/Write Cycle
0
1
2
3
4
5
6
7
8
9
260 261 262 263 264 265 266 267 268 269
CLK
CKE
VIH
Read cycle
RAS-CAS delay = 3
CAS latency = 3
Burst length = full page
= VIH or VIL
CS
RAS
CAS
WE
A9(BS)
Address
DQMU/L
I/O
(output)
I/O
(input)
CKE
R:a
C:a
R:b
a
a+1
a+2
a+3
a-2
a-1
a
a+1
a+2
a+3
a+4
a+5
High-Z
Bank 0
Active
Bank 0
Read
Bank 1
Active
Burst stop
Bank 1
Precharge
VIH
Write cycle
RAS-CAS delay = 3
CAS latency = 3
Burst length = full page
= VIH or VIL
CS
RAS
CAS
WE
A9(BS)
Address
DQMU/L
R:a
C:a
R:b
High-Z
I/O
(output)
I/O
(input)
a
Bank 0
Active
Bank 0
Write
a+1
a+2
a+3
Bank 1
Active
a+4
a+5
a+6
a+1
a+2
a+3
a+4
a+5
a+6
Burst stop
Bank 1
Precharge
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HM5241605C Series
Auto Refresh Cycle
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
a
a+1
CLK
CKE
VIH
CS
RAS
CAS
WE
A9(BS)
Address
R:a
A8=1
C:a
DQMU/L
I/O(input)
High-Z
I/O(output)
t RC
t RP
Auto Refresh
Precharge
If needed
tRC
Active
Bank 0
Auto Refresh
Read
Bank 0
Refresh cycle and
Read cycle
RAS-CAS delay = 2
CAS latency = 2
Burst length = 4
= VIH or VIL
Auto refresh
Self refresh cycle
RAS-CAS delay = 3
CAS latency = 3
Burst length = 4
= VIH or VIL
Self Refresh Cycle
CLK
CKE Low
CKE
CS
RAS
CAS
WE
A9(BS)
Address
A8=1
DQMU/L
I/O(input)
High-Z
I/O(output)
tRP
Precharge command
If needed
tRC
Self refresh entry
command
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Self refresh exit
ignore command
or No operation
HM5241605C Series
Clock Suspend Mode
t CESP
0
1
2
3
4
5
t CES
t CEH
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
CLK
CKE
Read cycle
RAS-CAS delay = 2
CAS latency = 2
Burst length = 4
= VIH or VIL
CS
RAS
CAS
WE
A9(BS)
Address
R:a
C:a
R:b
DQMU/L
I/O
(output)
I/O
(input)
a
C:b
a+1 a+2
a+3
b
b+1 b+2 b+3
High-Z
Bank0 Active clock
Active suspend start
Active clock Bank0
suspend end Read
Bank1
Active
Read suspend
start
Read suspend
end
Bank1
Read
Bank0
Precharge
Earliest Bank1
Precharge
CKE
Write cycle
RAS-CAS delay = 2
CAS latency = 2
Burst length = 4
= VIH or VIL
CS
RAS
CAS
WE
A9(BS)
Address
DQMU/L
R:a
C:a R:b
C:b
High-Z
I/O
(output)
I/O
(input)
a
Bank0
Active
Active clock
suspend start
a+1 a+2
Active clock Bank0 Bank1
supend end Write Active
Write suspend
start
a+3
Write suspend
end
b
b+1 b+2 b+3
Bank1 Bank0
Write Precharge
Earliest Bank1
Precharge
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HM5241605C Series
Power Down Mode
CLK
CKE Low
CKE
CS
RAS
CAS
WE
A9(BS)
Address
R: a
A8=1
DQMU/L
I/O (input)
High-Z
I/O (output)
tRP
Precharge command
If needed
Power down entry
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Power down
mode exit
Active Bank 0
Power down cycle
RAS-CAS delay = 3
CAS latency = 3
Burst length = 4
= VIH or VIL
HM5241605C Series
Power Up Sequence (1)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
CKE
VIH
CS
RAS
CAS
WE
DQMU/L
code
valid
Address
Valid
VIH
High-Z
I/O
t RP
All banks
Precharge
t RC
t RSA
tRC
Auto Refresh *
Mode register
Set
Bank active
If needed
Auto Refresh *
Note: Set 2 or more auto refresh commands.
= VIH or VIL
Power Up Sequence (2)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
CKE
VIH
CS
RAS
CAS
WE
DQMU/L
code
valid
Address
Valid
VIH
High-Z
I/O
t RP
All banks
Precharge
t RC
Auto Refresh *
t RSA
tRC
Auto Refresh *
Mode register
Set
Bank active
If needed
Note: Set 8 or more auto refresh commands.
= VIH or VIL
53
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HM5241605C Series
Package Dimensions
HM5241605CJ Series (CP-50D)
Unit: mm
26
10.16 ± 0.13
25
3.50 ± 0.26
0.47
1.09 Max
0.32 +0.08
–0.07
0.30 +0.04
–0.05
0.80
0.10
Dimension including the plating thickness
Base material dimension
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2.55 ± 0.46
1
0.90 ± 0.26
50
11.18 ± 0.13
20.95
21.38 Max
9.40 ± 0.25
Hitachi Code
JEDEC Code
EIAJ Code
Weight (reference value)
CP-50D
MO-165-BA
—
1.2 g
HM5241605C Series
HM5241605CTT Series (TTP-50D)
Unit: mm
20.95
21.35 Max
26
10.16
50
0.80
0.27 ± 0.07
0.25 ± 0.05
25
0.80
0.13 M
11.76 ± 0.20
1.15 Max
Dimension including the plating thickness
Base material dimension
0.13 ± 0.05
0.10
0.145 ± 0.05
0.125 ± 0.04
1.20 Max
0° – 5°
0.50 ± 0.10
Hitachi Code
JEDEC
EIAJ
Weight (reference value)
0.68
1
TTP-50D
—
—
0.50 g
55
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HM5241605C Series
When using this document, keep the following in mind:
1. This document may, wholly or partially, be subject to change without notice.
2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of
this document without Hitachi’s permission.
3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any
other reasons during operation of the user’s unit according to this document.
4. Circuitry and other examples described herein are meant merely to indicate the characteristics and
performance of Hitachi’s semiconductor products. Hitachi assumes no responsibility for any intellectual
property claims or other problems that may result from applications based on the examples described
herein.
5. No license is granted by implication or otherwise under any patents or other rights of any third party or
Hitachi, Ltd.
6. MEDICAL APPLICATIONS: Hitachi’s products are not authorized for use in MEDICAL
APPLICATIONS without the written consent of the appropriate officer of Hitachi’s sales company.
Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi’s products are
requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL
APPLICATIONS.
Hitachi, Ltd.
Semiconductor & IC Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan
Tel: Tokyo (03) 3270-2111
Fax: (03) 3270-5109
For further information write to:
Hitachi America, Ltd.
Semiconductor & IC Div.
2000 Sierra Point Parkway
Brisbane, CA. 94005-1835
USA
Tel: 415-589-8300
Fax: 415-583-4207
Hitachi Europe GmbH
Continental Europe
Dornacher Straße 3
D-85622 Feldkirchen
München
Tel: 089-9 91 80-0
Fax: 089-9 29 30-00
Hitachi Europe Ltd.
Electronic Components Div.
Northern Europe Headquarters
Whitebrook Park
Lower Cookham Road
Maidenhead
Berkshire SL6 8YA
United Kingdom
Tel: 01628-585000
Fax: 01628-585160
Hitachi Asia Pte. Ltd.
16 Collyer Quay #20-00
Hitachi Tower
Singapore 049318
Tel: 535-2100
Fax: 535-1533
Hitachi Asia (Hong Kong) Ltd.
Unit 706, North Tower,
World Finance Centre,
Harbour City, Canton Road
Tsim Sha Tsui, Kowloon
Hong Kong
Tel: 27359218
Fax: 27306071
Copyright © Hitachi, Ltd., 1997. All rights reserved. Printed in Japan.
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HM5241605C Series
Revision Record
Rev. Date
Drawn by
Approved by
Apr. 17, 1995 Initial issue
S. Ishikawa
T. Kizaki
1.0
May. 22, 1996 Command Operation
Change of Command Truth Table and CKE Truth Table
Absolute Maximum Ratings
Addition of notes 2
AC Characteristic
Addition of tCEHP min: 14/17/19.5 ns
tRAS min: 70/70/80 ns to 70/70/75 ns
Addition of notes 5, 6 and 7
Relationship Between Frequency and Minimum Latency
ISEC: 9/5/8/5/7/4 to 9/5/8/4/7/4
Deletion of notes 2
Timing Waveforms
Change of Clock Suspend Mode
Addition of note for Power Up Sequence
M. Sakamoto T. Kizaki
2.0
Jan. 7, 1997
3.0
Nov. 11, 1997 Change of subtitle
Change of Command Truth Table
0.0
Contents of Modification
M. Sakamoto T. Kizaki
Features
Addition of Clock frequency: 83 MHz (VCC min = 3.15 V)
AC Characteristics
Addition of notes 7
57
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