4 GHz to 18 GHz Divide-by-4 Prescaler ADF5001 FEATURES APPLICATIONS Point-to-point radios VSAT radios Communications test equipment FUNCTIONAL BLOCK DIAGRAM CE ADF5001 BIAS VDDx 100Ω 3pF RFIN 100Ω 1pF RFOUT DIVIDE BY 4 RFOUTB 1pF 50Ω 08402-001 Divide-by-4 prescaler High frequency operation: 4 GHz to 18 GHz Integrated RF decoupling capacitors Low power consumption Active mode: 26 mA Power-down mode: 7 mA Low phase noise: −150 dBc/Hz Single dc supply: 3.3 V compatible with ADF4xxx PLLs Temperature range: −40oC to +105oC Small package: 3 mm × 3 mm LFCSP GND Figure 1. GENERAL DESCRIPTION The ADF5001 prescaler is a low noise, low power, fixed RF divider block that can be used to divide down frequencies as high as 18 GHz to a lower frequency suitable for input into a PLL IC, such as the ADF4156 or ADF4106. The ADF5001 provides a divide-by-4 function. The ADF5001 operates off a 3.3 V supply and has differential 100 Ω RF outputs to allow direct interface to the differential RF inputs of PLLs such as the ADF4156 and ADF4106. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registeredtrademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. www.analog.com Tel: 781.329.4700 Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved. ADF5001 TABLE OF CONTENTS Features .............................................................................................. 1 Pin Configuration and Function Descriptions ..............................5 Applications ....................................................................................... 1 Typical Performance Characteristics ..............................................6 General Description ......................................................................... 1 Evaluation Board PCB ......................................................................7 Functional Block Diagram .............................................................. 1 PCB Material Stack-Up.................................................................7 Revision History ............................................................................... 2 Bill of Materials ..............................................................................7 Specifications ..................................................................................... 3 Application Circuit ............................................................................8 Absolute Maximum Ratings ............................................................ 4 Outline Dimensions ..........................................................................9 ESD Caution .................................................................................. 4 Ordering Guide..............................................................................9 REVISION HISTORY 10/09—Revision 0: Initial Version Rev. 0 | Page 2 of 12 ADF5001 SPECIFICATIONS VDD1 = VDD2 = 3.3 V ± 10%, GND = 0 V; dBm referred to 50 Ω; TA = T MIN to TMAX, unless otherwise noted. Operating temperature range for the B version is −40°C to +105°C. Table 1. Parameter RF CHARACTERISTICS Maximum Input Frequency Minimum Input Frequency RF Input Sensitivity Output Power Phase Noise Reverse Leakage Second Harmonic Content Third Harmonic Content Fourth Harmonic Content Fifth Harmonic Content CE INPUT VIH, Input High Voltage VIL, Input Low Voltage POWER SUPPLIES Voltage Supply IDD (IDD1 + IDD2) Active Power-Down 1 Min B Version 1 Typ Max 18 4 −10 −15 −12 +10 −11 −8 −5 −150 −60 −38 −12 −20 −19 2.2 3.0 Unit GHz GHz dBm dBm dBm dBm dBc/Hz dBm dBc dBc dBc dBc 0.3 V V 3.3 3.6 V 26 7 42 12.5 mA mA Operating temperature range for the B version is −40°C to +105°C. Rev. 0 | Page 3 of 12 Test Conditions/Comments 4 GHz to 18 GHz. Single-ended output connected into 50 Ω load. Differential outputs connected into 50 Ω load. Differential outputs connected into 100 Ω load. Input frequency (FIN) = 12 GHz, offset = 100 kHz. RF input power (PIN) = 0 dBm, RFOUT = 4 GHz. CE is high. CE is low. ADF5001 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter VDDx to GND RFIN Operating Temperature Range Industrial (B Version) Storage Temperature Range Maximum Junction Temperature LFCSP θJA Thermal Impedance Peak Temperature Time at Peak Temperature This device is a high performance RF integrated circuit with an ESD rating of 2 kV, human body model (HBM) and is ESD sensitive. Proper precautions should be taken for handling and assembly. Rating −0.3 V to +3.9 V 10 dBm ESD CAUTION −40°C to +105°C −65°C to +150°C 150°C 27.3°C/W 260°C 40 sec Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. 0 | Page 4 of 12 ADF5001 PIN 1 INDICATOR GND 1 TOP VIEW (Not to Scale) GND 5 GND 4 CE 7 GND 3 12 GND 11 RFOUTB 10 RFOUT 9 GND GND 8 ADF5001 NC 6 RFIN 2 NOTES 1. NC = NO CONNECT. 2. THE EXPOSED PADDLE MUST BE CONNECTED TO GND. 08402-002 14 VDD2 13 GND 16 GND 15 VDD1 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 2. Pin Configuration Table 3. Pin Function Descriptions Pin No. Mnemonic Description RF Ground. All ground pins should be tied together. 1, 3, 4, 5, 8, 9, 12, GND 13, 16 2 RFIN Single-Ended 50 Ω Input to the RF Prescaler. This pin is ac-coupled internally via a 3 pF capacitor. 6 NC No Connect. This pin can be left unconnected. 7 CE Chip Enable. This pin is active high. When CE is brought low, the part enters into power-down mode. If this functionality is not required, the pin can be left unconnected because it will be pulled up internally through a weak pull-up resistor. 10 RFOUT Divided Down Output of the Prescaler. This pin has an internal 100 Ω load resistor tied to VDD2 and an ac-coupling capacitor of 1pF. 11 RFOUTB Complementary Divided Down Output of the Prescaler. This pin has an internal 100 Ω load resistor tied to VDD2 and an ac-coupling capacitor of 1 pF. 14 VDD2 Voltage Supply for the Output Stage. This pin should be decoupled to ground with a 1 nF capacitor and can be tied directly to VDD1. 15 VDD1 Voltage Supply for the Input Stage and Divider Block. This pin should be decoupled to ground with a 1 nF capacitor. EPAD The LFCSP package has an exposed paddle that must be connected to GND. Rev. 0 | Page 5 of 12 ADF5001 0 0 –10 –10 P1 –20 POWER (dBm) MINIMUM INPUT POWER (dBm) TYPICAL PERFORMANCE CHARACTERISTICS –30 –40 –20 P3 –30 P4 –40 –50 P2 –50 0 5 10 15 FREQUENCY (GHz) 20 –60 2.0 08402-003 –60 25 2.2 2.4 2.6 2.8 3.0 3.2 VDDx (V) Figure 3. RF Input Sensitivity 3.4 3.6 08402-006 ROOM TEMPERATURE VDD1 = VDD2 = 3.3V Figure 6. RF Output Harmonic Content 20 –60 IDD1 18 IDD2 16 IDDx (mA) 12 10 8 6 4 –100 –120 –140 –160 2 2.0 2.5 3.0 3.5 VDDx (V) –180 10k 08402-004 0 1.5 Figure 4. IDD1 and IDD2 vs. VDDx –5 –15 –20 –25 –30 –35 2.4 2.6 2.8 3.0 3.2 3.4 VDDx (V) 3.6 08402-005 POWER (dBm) –10 2.2 100k 1M 10M OFFSET FREQUENCY (Hz) 100M Figure 7. Phase Noise Plot of 20 GHz PLL Output Using the ADF5001 Prescaler and ADF4106 Synthesizer ICs 0 –40 2.0 REFIN = 100MHz (SMA100A) PFD = 25MHz VCO OUTPUT = 21.0GHz PRESCALAR = 16/17, A = 2, B = 13 08402-007 PHASE NOISE (dBc Hz–1) –80 14 Figure 5. RF Output Power (Single-Ended) vs. VDDx Rev. 0 | Page 6 of 12 ADF5001 EVALUATION BOARD PCB The evaluation board has four connectors as shown in Figure 8. The RF input connector (J4) is a 2.92 mm precision connector from Rosenberger. This connector is mechanically compatible with SMA/3.5 mm cables, although it is recommended to use a 2.92 mm cable when connecting the board to measurement equipment or to another RF evaluation board to avoid accidental damage to the connector. 1.5oz (53µm) FINISHED COPPER ROGERS RO4003C LAMINATE 0.008” Er = 3.38. STARTING COPPER WEIGHT 0.5oz/0.5oz 0.5oz (18µm) FINISHED COPPER 0.062” ± 0.003” COPPER TO COPPER FR4 PREPREG 0.0372” 0.5oz (18µm) FINISHED COPPER 08402-009 ROGERS RO4003C LAMINATE 0.008” Er = 3.38.STARTING COPPER WEIGHT 0.5oz/0.5oz 08402-008 1.5oz (53µm) FINISHED COPPER Figure 9. Evaluation Board PCB Layer Stack-Up Figure 8. Evaluation Board Silkscreen—Top View BILL OF MATERIALS The evaluation board is powered from a single 3.0 V to 3.6 V supply, which should be connected to the J1 SMA connector. The power supply can also be connected using the T3 (VDDx) and T2 (GND) test points. The differential RF outputs are brought out on the J2 and J3 SMA connectors. If only one of the outputs is being used, the unused output should be correctly terminated using a 50 Ω SMA termination. The chip enable (CE) pin can be controlled using the T1 test point. If this function is not required, the test point can be left unconnected. PCB MATERIAL STACK-UP Table 4. Reference Qty Designator 1 C1 1 C2 1 J1 3 J2, J3, J4 3 1 T1, T2, T3 U1 The evaluation board is built using Rogers 4003C material (0.008 in.). RF track widths are 0.015 in. to achieve a controlled 50 Ω characteristic impedance. The complete PCB stack-up is shown in Figure 9. Rev. 0 | Page 7 of 12 Description 0.1 µF, 0603 capacitor 10 pF, 0402 capacitor 2.92 mm RF connector 3.5 mm RF SMA connector Testpoints ADF5001 RF prescaler Supplier/Part Number Murata GRM188R71H104KA93D Murata GRM1555C1H100JZ01D Rosenberger 02K24340ME3 Johnson Components 142-0701-851 Vero 20-2137 Analog Devices, Inc., ADF5001BCPZ ADF5001 APPLICATION CIRCUIT The ADF5001 can be connected either single-ended or differentially to any of the Analog Devices PLL family of ICs. It is recommended to use a differential connection for best performance and to achieve maximum power transfer. The application circuit shown in Figure 10 shows the ADF5001 used as the RF prescaler in a microwave 16 GHz PLL loop. The ADF5001 divides down the 16 GHz RF signal to 4 GHz, which is input differentially into the ADF4156 PLL. An active filter topology, using the OP184 op amp, is used to provide the wide tuning ranges typically required by microwave VCOs. The positive input pin of the OP184 is biased at half the ADF4156 charge pump supply (VP). This can be easily achieved using a simple resistor divider, ensuring sufficient decoupling close to the +IN A pin of the OP184. This then allows the use of a single positive supply for the op amp. Alternatively, to optimize performance by ensuring a clean bias voltage, a low noise regulator like the ADP150 can be used to power the resistor divider network or the +IN A pin directly. 1.8nF 10pF 0.1µF 330Ω VDD2 VDD1 RFOUT ADF4156 PLL RFINA 220Ω CP PRESCALER VP/2 RFINB RFOUTB 820pF GND OP184 1µF 1.8nF MICROWAVE VCO 6dB PAD 37Ω 18Ω RFOUT 150Ω 1kΩ OP AMP 150Ω VTUNE 18Ω 08402-010 RFIN ADF5001 DECOUPLING INTEGRATED 47nF 16GHz OUT Figure 10. ADF5001 Used as the RF Prescaler in a Microwave 16 GHz PLL Loop Rev. 0 | Page 8 of 12 ADF5001 OUTLINE DIMENSIONS PIN 1 INDICATOR 0.30 0.25 0.18 0.50 BSC 13 PIN 1 INDICATOR 16 1 12 EXPOSED PAD 1.60 1.50 SQ 1.40 9 TOP VIEW 0.80 0.75 0.70 0.45 0.40 0.35 4 8 0.25 MIN BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE 5 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WEED-6. 111808-A 3.10 3.00 SQ 2.90 Figure 11. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] (CP-16-18) Dimensions shown in millimeters ORDERING GUIDE Model ADF5001BCPZ1 ADF5001BCPZ-RL71 EVAL-ADF5001EB2Z1 1 Temperature Range −40°C to +105°C −40°C to +105°C Package Description 16-Lead Lead Frame Chip Scale Package (LFCSP_WQ) 16-Lead Lead Frame Chip Scale Package (LFCSP_WQ), 7” Tape & Reel Evaluation Board Z = RoHS Compliant Part. Rev. 0 | Page 9 of 12 Package Option CP-16-18 CP-16-18 ADF5001 NOTES Rev. 0 | Page 10 of 12 ADF5001 NOTES Rev. 0 | Page 11 of 12 ADF5001 NOTES ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08402-0-10/09(0) Rev. 0 | Page 12 of 12