www.fairchildsemi.com ILC6383 1-Cell to 3-Cell Boost with True Load Disconnect, 3.3V, 5V or Adjustable Output Features Description • • • • • • • • • • • • • The ILC6383 series of step-up DC-DC converters operate from 1-cell to 3-cell input. They are direct replacement for ILC6382, in applications where SYNC pin is not used. The PFM or PWM operating mode is user selectable through SEL pin connected to ground or left open, respectively. The choice should be dependent upon the current to be delivered to the load: PFM is recommended for input voltage higher than 1.5V and loads below 100mA, while PWM is recommended for more than 50mA load current In shutdown mode, the device allows true load disconnect from battery input. Designed for wireless communications applications, the oscillator frequency is set at 300kHz with no harmonics at sub 20kHz audio band or at 455kHz IF band. 0.9V to 6V input voltage Guaranteed start up in PWM at 0.9V input Synchronous rectification requires no external diode True load disconnect from battery input in shutdown Up to 75mA at 3.3V and 40mA at 5V from 1V input Up to 375mA at 3.3V and 160mA at 5V from 3V input Peak efficiency > 90% 1µA battery input current in shutdown (with VOUT = 0V) Internal Oscillator frequency: 300kHz to ±15% ILC6383: Fixed 3.3V or 5V output ILC6383-ADJ: Adjustable output to 6V maximum Low battery detector with 100ms transient rejection delay Powergood output flag when VOUT is in regulation Internal synchronous rectification and externally selectable PFM/PWM mode of operation allows the selection of the best efficiency at light or full load. The ILC6383 is capable of delivering 75mA at 3.3V output from a single cell input. The ILC6383-XX offers 3.3V or 5V fixed output voltage while the ILC6383-ADJ allows adjustable output voltage to 6V maximum. Output voltage accuracy is ±2% over specified temperature range. Applications • Cellular Phones, Pagers • Palmtops, PDAs and portable electronics • High efficiency 1V step up converters Additional features include power good output (POK) and an internal low battery detector with 100ms transient rejection delay. The device will reject low battery input transients under 100ms in duration. The ILC6383 series is available in a space saving eight lead micro SOP (MSOP-8) package. Typical Applications C IN 47µF ILC6383-XX L C IN LX 1 VOUT 8 + 15µH VIN 1 to 3-cell ON OFF 2 VIN GND 7 3 LBI/SD LBO 6 47µF COUT + VOUT R5 R6 4 SEL POK 5 1 Figure 1: ILC6383CIR-XX 8 + OFF 2 VIN 3 LBI/SD 4 SEL GND 7 LBO 6 V FB 5 VOUT C OUT 47µF R1 ON R6 R2 MSOP-8 PWM PFM VOUT R5 MSOP-8 PWM LX 15µH VIN 1 to 3-cell Low Battery Detector Output Power Good Output ILC6383-ADJ L 47µF + PFM VOUT = 1.25 (1+R1/R2) Figure 2: ILC6383CIR-ADJ Rev. 1.2 ©2001 Fairchild Semiconductor Corporation ILC6383 Pin Assignments LX 1 8 V OUT LX 1 8 V OUT V IN 2 7 GND V IN 2 7 GND LB/SD 3 6 LBO LB/SD 3 6 LBO SEL 4 5 POK SEL 4 5 V FB MSOP MSOP (TOP VIEW) (TOP VIEW) ILC6383CIR-XX ILC6383CIR-ADJ Pin Definitions Pin Number Pin Number Pin Description 1 LX Inductor input. Inductor L connected between this pin and the battery 2 VIN Connect directly to battery 3 LBI/SD Low battery detect input and shutdown. Low battery detect threshold is set with this pin using a potential divider. If this pin is pulled to logic low then the device will shutdown. 4 SEL A low logic level signal applied to this pin selects PFM operation mode. If the pin is left open or high logic level is applied, PWM mode is selected. 5 POK (ILC6383CIR-XX) This open drain output pin will go high when output voltage is within regulation, 0.92*VOUT(NOM) < VOUT < 0.98*VOUT(NOM) VFB This pin sets the adjustable output voltage via an external resistor divider (ILC6383CIR-ADJ) network. The formula for choosing the resistors is shown in the “Applications Information” section. 6 LBO This open drain output will go low if the battery voltage is below the low battery threshold set at pin 3 7 GND Connect this pin to the battery and system ground 8 VOUT This is the regulated output voltage Absolute Maximum Ratings (Note 1) Parameter Voltage on VOUT pin Symbol Ratings Units VOUT -0.3 to 7 V - -0.3 to 7 V ILX 1 A ISINK(LBO) 5 mA Continuous total power dissipation at 85°C PD 315 mW Short circuit current ISC Internally protected (1 sec. duration) A Operating ambient temperature TA -40 to 85 °C Maximum junction temperature TJ(MAX) 150 °C Tstg -40 to 125 °C 300 °C θJA 206 °C/W Voltage on LBI, Sync, LBO, POK, VFB, LX and VIN pins Peak switch current on LX pin Current on LBO pin Storage temperature Lead temperature (soldering 10 sec.) Package thermal resistance ©2001 Fairchild Semiconductor Corporation 2 ILC6383 Electrical Characteristics ILC6383CIR-33 in PFM mode (SEL in LOW state) Unless otherwise specified all limits are at VIN = VLBI = 2.4V, IOUT = 1mA TA = 25°C. Test circuit figure 1. The • denotes specifications which apply over the specified operating temperature range. (Note 2) Parameter Symbol Output Voltage Conditions VOUT • Output Current IOUT Load Regulation ∆VOUT VOUT No Load Battery Input Current IIN(no load) η Efficiency Min. Typ. Max. Units 3.168 3.135 3.3 3.432 3.465 V VIN = 2.0V, VOUT = VOUT(NOM) ± 4% 100 mA 1 % IOUT = 0mA 250 µA IOUT = 20mA, VIN = 2.0V 88 % 1mA < IOUT < 20mA Electrical Characteristics ILC6383CIR-33 in PWM mode (SEL in open) Unless otherwise specified all limits are at VIN = VLBI = 2.4V, IOUT = 50mA TA = 25°C. Test circuit figure 1. The • denotes specifications which apply over the specified operating temperature range. (Note 2) Parameter Output Voltage Symbol Conditions VOUT(NOM) • Output Current IOUT Min. Typ. Max. Units 3.234 3.201 3.300 3.366 3.399 V VIN = 0.9V, VOUT = VOUT(NOM) ± 4% VIN = 1.2V, VOUT = VOUT(NOM) ± 4% VIN = 2.4V, VOUT = VOUT(NOM) ± 4% VIN = 3.0V, VOUT = VOUT(NOM) ± 4% 50 75 200 375 mA Load Regulation ∆VOUT VOUT VIN = 1.2V, 0mA < IOUT < 50mA 1.5 % No Load Battery Input Current I GND VIN = 1.2V, IOUT = 0mA 250 µA η IOUT = 20mA, VIN = 2.0V 90 % Efficiency General Electrical Characteristics for all voltage versions. Unless otherwise specified all limits are at VIN = VLBI = 2.4V and TA = 25°C. Test circuits figure 1 and figure 2 for ILC6383CIR-XX and ILC6383CIR-ADJ respectively. The • denotes specifications which apply over the specified operating temperature range. (Note 2) Parameter Symbol Conditions Min. LBO Output Voltage Low VLBO(low) ISINK = 2mA, open drain output, VLBI = 1V • LBO Output Leakage Current ILBO(hi) VLBO = 5V • Shutdown Input Voltage Low VSD(low) • Shutdown Input Voltage High VSD(hi) • 1 SEL Input Voltage High VSEL(hi) • 1.5 SEL Input Voltage Low VSEL(low) • Typ. 1 Max. Units 0.4 V 2 µA 0.4 V 6 V V 0.4 V ©2001 Fairchild Semiconductor Corporation 3 ILC6383 General Electrical Characteristics (continued) Parameter Symbol POK Output Voltage Low VPOK(low) POK Output Voltage High VPOK(hi) POK Output Leakage Current IL(POK) POK Threshold VTH(POK) POK Hysteresis VHYST Conditions ISINK = 2mA, open drain output Force 6V at pin 5 Min. Max. Units • 0.4 V • 6 V • 2 µA 0.98 x VOUT V 0.92 x VOUT Typ. 0.95 x VOUT 50 Feedback Voltage VFB (ILC6383CIR-ADJ only) • 1.225 1.212 VOUT(ADJ) min VIN = 0.9V, IOUT = 50mA Output Voltage Adjustment Range VOUT(ADJ) max VIN = 3V, IOUT = 50 mA (ILC6383CIR-ADJ only) 1.250 mV 1.275 1.288 2.5V 6V Minimum Startup Voltage VIN(start) IOUT = 10mA, PWM mode • Input Voltage Range VIN VOUT = VOUT(nominal) ± 4% IOUT = 10mA (Note 3) • Battery Input Current in Load Disconnect Mode IIN(SD) VLBI/SD < 0.4V, VOUT = 0V (short circuit) Switch on resistance Rds(on) N-Channel MOSFET P-Channel MOSFET Oscillator Frequency fOSC LBI Input Threshold VREF Input Leakage Current I LEAK Pins LB/SD, SEL and VFB, (Note 4) LBI Hold Time tHOLD(LBI) (Note 5) 0.9 0.9 1 • 1 V 1 V VOUT(nominal) + +0.5V V 10 µA 400 750 mΩ • 255 300 345 1.175 1.150 1.250 • 1.325 1.350 200 100 120 V kHz nA mS Notes: 1. Absolute maximum ratings indicate limits which, when exceeded, may result in damage to the component. Electrical specifications do not apply when operating the device outside its rated operating conditions. 2. Specified min/max limits are production tested or guaranteed through correlation based on statistical control methods. Measurements are taken at constant junction temperature as close to ambient as possible using low duty pulse testing. 3. VOUT(NOM) is the nominal output voltage at IOUT = 50mA in PWM mode. 4. Guaranteed by design. 5. In order to get a valid low-battery-output (LBO) signal, the input voltage must be lower than the low-battery-input (LBI) threshold for a duration greater than the low battery hold time (thold(LBI)). This feature eliminates false triggering due to voltage transients at the battery terminal. ©2001 Fairchild Semiconductor Corporation 4 ILC6383 Applications Information The ILC6383 performs boost DC-DC conversion by controlling the switch element as shown in the simplified circuit in figure 3 below. Figure 3: Basic Boost Circuit When the switch is closed, current is built up through the inductor. When the switch opens, this current has to go somewhere and is forced through the diode to the output. As this on and off switching continues, the output capacitor voltage builds up due to the charge it is storing from the inductor current. In this way, the output voltage gets boosted relative to the input. In general, the switching characteristic is determined by the output voltage desired and the current required by the load. Specifically the energy transfer is determined by the power stored in the coil during each switching cycle. PL = ƒ(tON, VIN) Synchronous Rectification The ILC6383 also uses a technique called “synchronous rectification” which removes the need for the external diode used in other circuits. The diode is replaced with a second switch or in the case of the ILC6383, an FET as shown in figure 4 below. V IN ILC6383 SW2 LX V OUT - PWM/PFM CONTROLLER SW1 GND SEL There are two key advantages of the PWM type controllers. First, because the controller automatically varies the duty cycle of the switch's on-time in response to changing load conditions, the PWM controller will always have an optimized waveform for a steady-state load. This translates to very good efficiency at high currents and minimal ripple on the output. Ripple is due to the output cap constantly accepting and storing the charge received from the inductor, and delivering charge as required by the load. The “pumping” action of the switch produces a sawtooth-shaped voltage as seen by the output. The other key advantage of the PWM type controllers is that the radiated noise due to the switching transients will always occur at the (fixed) switching frequency. Many applications do not care much about switching noise, but certain types of applications, especially communication equipment, need to minimize the high frequency interference within their system as much as possible. Using a boost converter requires a certain amount of higher frequency noise to be generated; using a PWM converter makes that noise highly predictable thus easier to filter out. PFM Mode Operation For low loads the ILC6383 can be switched to PFM, or Pulse Frequency Modulation, technique at low currents. This technique conserves power loss by only switching the output if the current drain requires it. As shown in the figure 5, the waveform actually skips pulses depending on the power needed by the output. This technique is also called “pulse skipping” because of this characteristic. + POK SHUTDOWN CONTROL 300kHz. The control circuitry varies the power being delivered to the load by varying the on-time, or duty cycle, of the switch SW1 (see fig. 5). Since more on-time translates to higher current build-up in the inductor, the maximum duty cycle of the switch determines the maximum load current that the device can support. The minimum value of the duty cycle determines the minimum load current that can maintain the output voltage within specified values. + V REF - DELAY LBO LB/SD In the ILC6383, the switchover from PWM to PFM mode is determined by the user to improve efficiency and conserve power Switch Waveform Figure 4: Simplified ILC6382 block diagram The two switches now open and close in opposition to each other, directing the flow of current to either charge the inductor or to feed the load. The ILC6383 monitors the voltage on the output capacitor to determine how much and how often to drive the switches. PWM Mode Operation The ILC6383 uses a PWM or Pulse Width Modulation technique. The switches are constantly driven at typically V SET V OUT Figure 5: PFM Waveform ©2001 Fairchild Semiconductor Corporation 5 ILC6383 The Dual PWM/PFM mode architecture was designed specifically for applications such as wireless communications, which need the spectral predictability of a PWM-type DCDC converter, yet also need the highest efficiencies possible, especially in Standby mode. 2 VIN R PU R5 6 3 + LBI/SD R6 LBO DELAY 100ms - Other Considerations The other limitation of PWM techniques is that, while the fundamental switching frequency is easier to filter out since it's constant, the higher order harmonics of PWM will be present and may have to be filtered out, as well. Any filtering requirements, though, will vary by application and by actual system design and layout, so generalizations in this area are difficult, at best. 3.3V ILC6383 Shutdown 1.25V Internal Reference 7 GND Figure 6: Low Battery Detector However, PWM control for boost DC-DC conversion is widely used, especially in audio-noise sensitive applications or applications requiring strict filtering of the high frequency components. The output of the low battery detector is an open drain capable of sinking 2mA. A 10kΩ pull-up resistor is recommended on this output. Low Battery Detector For VLBI < 1.25V The ILC6383's low battery detector is a based on a CMOS comparator. The negative input of the comparator is tied to an internal 1.25V (nominal) reference, V REF. The positive input is the LBI/SD pin. It uses a simple potential divider arrangement with two resistors to set the LBI threshold as shown in Figure 6. The input bias current of the LBI pin is only 200nA. This means that the resistor values R1 and R2 can be set quite high. The formula for setting the LBI threshold is: The low battery detector can also be configured for voltages <1.25V by bootstrapping the LBI input from VOUT. The circuitry for this is shown in figure 7. ILC6383 8 VOUT R2 VIN R1 3 LBI/SD + - VLBI = VREF x (1+R5/R6) Since the LBI input current is negligible (<200nA), this equation is derived by applying voltage divider formula across R6. A typical value for R6 is 100kΩ. R5 = 100kΩ x [(VLBI/VREF) -1], where VREF = 1.25V (nom.) The LBI detector has a built in delay of 120ms. In order to get a valid low-battery-output (LBO) signal, the input voltage must be lower than the low-battery-input (LBI) threshold for a duration greater than the low battery hold time (thold(LBI)) of 120msec. This feature eliminates false triggering due to voltage transients at the battery terminal caused by high frequency switching currents. 1.25V Internal Reference 7 GND Figure 7: VLBI < 1.25V The following equation is used when VIN is lower than 1.25V R1 = R2 x [(VREF - VIN) / (VOUT - VREF)], where VREF = 1.25V (nom.) This equation can also be derived using voltage divider formula across R2. A typical value for R2 is 100kΩ. ©2001 Fairchild Semiconductor Corporation 6 ILC6383 Shut Down Negative Voltage Output The LBI pin is shared with the shutdown pin. A low voltage (<0.4V) will put the ILC6383 into a power down state. The simplest way to implement this is with an FET across R6 as shown in figure 8. Note that when the device is not in PWM mode or is in shutdown the low battery detector does not operate. It is possible to generate a negative output voltage as a secondary supply using the ILC6383. This negative voltage may be useful in some applications where a negative bias voltage at low current is required. 1A Schottky Diodes -V 0.01µF When the ILC6383 is shut down, the synchronous rectifier disconnects the output from the input. This ensures that there is only leakage (IIN < 1µA typical) from the input to the output so that the battery is not drained when the ILC6383 is shut down. 0.01µF ILC6383 L 1 LX VIN 2 VIN Figure 10: Negative Output Voltage 2 VIN ILC6383 R5 3 LBI/SD ON/OFF R6 7 GND Figure 8: Shut Down Control Power Good Output (POK) The POK output of the ILC6383 indicates when VOUT is within the regulation tolerance of the set output voltage. POK output is an open drain device output capable of sinking 2mA. It will remain pulled low until the output voltage has risen to typically 95% of the specified VOUT. Note that a pull-up resistor must be connected from the POK output (pin 5 of ILC6383CIR-XX) to either ILC6383's output or to some other system voltage source. Adjustable Output Voltage Selection The ILC6383-ADJ allows the output voltage to be set using a potential divider. The formula for setting the adjustable output voltage is; VOUT = VFB x (1+R1/R2), where VFB is the threshold set which is 1.25V nominal. ILC6383-ADJ C IN L 47µF VOUT 1 8 + 2 VIN GND 7 3 LBI/SD LBO 6 4 SEL VFB 5 47µF COUT R5 R1 ON OFF VOUT 15µH VIN 1 to 3-cell LX R6 R2 MSOP-8 PWM PFM VOUT = 1.25 (1+R1/R2) Figure 9: Adjustable Voltage Configuration ©2001 Fairchild Semiconductor Corporation 7 ILC6383 External Component Selection Inductors The ILC6383 is designed to work with a 15µH inductor in most applications. There are several vendors who supply standard surface mount inductors to this value. Suggested suppliers are shown in table 1. Higher values of inductance will improve efficiency, but will reduce peak inductor current and consequently ripple and noise, but will also limit output current. Vendor Part No. Contact Coilcraft D03308P-153 D03316P-153 D01608C-153 (847) 639-6400 muRata LQH4N150K LQH3C150K (814) 237-1431 Sumida CDR74B-150MC CD43-150 CD54-150 (847) 956-0666 NLC453232T-150K (847) 390-4373 TDK Capacitors Layout and Grounding Considerations High frequency switching and large peak currents means PCB design for DC-DC converters requires careful consideration. A general rule is to place the DC-DC converter circuitry well away from any sensitive RF or analog components. The layout of the DC-DC converters and its external components are also based on some simple rules to minimize EMI and output voltage ripple. Layout 1. Place all power components, ILC6383, inductor, input capacitor and output capacitor as close together as possible. 2. Keep the output capacitor as close to the ILC6383 as possible with very short traces to the VOUT and GND pins. Typically it should be within 0.25 inches or 6mm. 3. Keep the traces for the power components wide, typically >50mil or 1.25mm. 4. Place the external networks for LBI and VFB close to the ILC6383, but away from the power components as far as possible. Grounding Input Capacitor The input capacitor is necessary to minimize the peak current drawn from the battery. Typically a 10µF tantalum capacitor is recommended. Low equivalent series resistance (ESR) capacitors will help to minimize battery voltage ripple. 1. Use a star grounding system with separate traces for the power ground and the low power signals such as LBI/SD and VFB. The star should radiate from where the power supply enters the PCB. 2. On multilayer boards use component side copper for grounding around the ILC6383 and connect back to a quiet ground plane using vias. Output Capacitor Description Vendor ILC6383 C IN L1 VOUT 47µF 1 LX VOUT 8 + 15µH VIN 2 VIN GND 7 3 LBI/SD LBO 6 4 SEL VFB 5 COUT 47µF R1 ON/OFF PWM PFM R3 Load Low ESR capacitors should be used at the output of the ILC6383 to minimize output ripple. The high switching speeds and fast changes in the output capacitor current, mean that the equivalent series impedance of the capacitor can contribute greatly to the output ripple. In order to minimize these effects choose an output capacitor with less than 10nH of equivalent series inductance (ESL) and less than 100mΩ of equivalent series resistance (ESR). Typically these characteristics are met with ceramic capacitors, but may also be met with certain types of tantalum capacitors. Suitable vendors are shown in table 2. R2 Local "Quiet" Ground Power Ground Recommended application circuit schematic for ILC6383CIR-ADJ Contact T495 series tantalum Kemet (864) 963-6300 595D series tantalum Sprague (603) 224-1961 TAJ, TPS series tantalum AVX (803) 946-0690 Y5V Ceramic TDK (847) 390-4373 AVX (803) 946-0690 muRata www.murata.com ©2001 Fairchild Semiconductor Corporation 8 ILC6383 U1 U1 C2 ILC6383ADJ ILC6383XX L1 L1 C2 47µF 1 VOUT LX 8 C1 15µH GND 7 2 V IN VIN ON 47µF R1 R3 VIN 10K 10K LBO 6 3 LBI 4 SEL 1 POK/VFB 5 LX VOUT 8 2 V IN GND 7 3 LBI LBO 6 ON LBO OFF POK 4 SEL SEL VOUT C1 15mH OFF SEL 47µF VOUT 47µF R1 R3 10K LBO VFB POK/VFB 5 R2 GND GND 1MW PWM PFM R4 U2 PWM PFM R4 1MW U2 NOTE: R1 and R2 are user determined values to set VOUT= VFB(1+R1/R2) Evaluation Board Parts List For Printed Circuit Board Shown Above Label Part Number Manufacturer U1 ILC6383CIR-ADJ Fairchild Semiconductor C GRM43-2X5R476K6.3 muRata 47µF, ceramic capacitor L1 LQS66C150M04 muRata 15µH, 1.3A R1 and R2 - Dale, Panasonic User Determined Values R3 - Dale, Panasonic 10kΩ, 1/10W, SMT R4 - Dale, Panasonic 1MΩ, 1/10W, SMT Part Number Manufacturer U1 ILC6383CIR-XX Fairchild Semiconductor C GRM43-2X5R476K6.3 muRata 47µF, ceremic capacitor L1 15µH, 1.3A Label Description Step-up DC-DC converter Description Step-up DC-DC converter LQS66CA50M04 muRata R1 and R3 - Dale, Panasonic 10kΩ, 1/10W, SMT R4 - Dale, Panasonic 1mΩ, 1/10W, SMT ©2001 Fairchild Semiconductor Corporation 9 ILC6383 Typical Performance Characteristics ILC6383CIR-33 ( Unless otherwise specified: TA = 25°C, CIN = 47µF, C Efficiency (PWM Mode) = 3.3 V) Efficiency (PFM Mode) 1 0.9 V IN = 2V V IN = 1.5V 0.9 V IN = 1.5V V IN = 2V 0.85 V IN = 2.5V 0.8 Efficiency Efficiency OUT OUT = 47µF, L = 15µH. 0.7 0.6 30 50 100 150 200 250 300 Load Current (mA) 350 V IN = 2.5V 0.8 0.75 400 0.7 0.65 1 5 10 15 20 Load Current (mA) 25 30 Load Regulation (PWM Mode) 3.42 Load Regulation (PFM Mode) 3.4 3.36 3.38 V IN = 3V 3.34 V IN = 2V 3.34 Output Voltage (V) Output Voltage (V) 3.36 V IN = 2.5V 3.32 3.3 3.28 3.26 3.24 V IN = 1.5V V IN = 2V 3.32 V IN = 1.5V 3.3 3.28 3.26 3.24 3.22 3.22 3.2 3.2 1 3.18 50 100 150 200 250 300 350 400 5 10 15 20 Load Current (mA) 25 Load Current (mA) Start-up Input Voltage vs Output current in PFM 1.9 Start-up Input Voltage (V) 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1 1 10 20 30 40 50 Load Current (mA) ©2001 Fairchild Semiconductor Corporation 10 ILC6383 DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com 10/5/01 0.0m 001 Stock#DSxxxxxxxx 2001 Fairchild Semiconductor Corporation