54AC646 Octal Transceiver/Register with TRI-STATE ® Outputs General Description The ’AC646 consist of registered bus transceiver circuits, with outputs, D-type flip-flops and control circuitry providing multiplexed transmission of data directly from the input bus or from the internal storage registers. Data on the A or B bus will be loaded into the respective registers on the LOW-to-HIGH transition of the appropriate clock pin (CPAB or CPBA). The four fundamental data handling functions available are illustrated in Figures 1, 2, 3, 4. n n n n n n Multiplexed real-time and stored data transfers TRI-STATE outputs 300 mil slim dual-in-line package Outputs source/sink 24 mA ’ACT646 has TTL compatible inputs Standard Microcircuit Drawing (SMD) — ’AC646: 5962-89682 Features n Independent registers for A and B buses Logic Symbols Pin Names A0–A7 Description Data Register A Inputs Data Register A Outputs B0–B7 Data Register B Inputs CPAB, CPBA Clock Pulse Inputs SAB, SBA Transmit/Receive Inputs Data Register B Outputs DS100231-1 G Output Enable Input DIR Direction Control Input IEEE/IEC DS100231-2 TRI-STATE ® is a registered trademark of National Semiconductor Corporation. FACT ® is a registered trademark of Fairchild Semiconductor Corporation. © 1998 National Semiconductor Corporation DS100231 www.national.com 54AC646 Octal Transceiver/Register with TRI-STATE Outputs August 1998 Connection Diagrams Pin Assignment for DIP and Flatpak Pin Assignment for LCC DS100231-3 DS100231-4 Storage from Bus to Register Real Time Transfer A-Bus to B-Bus DS100231-9 DS100231-7 FIGURE 3. FIGURE 1. Transfer from Register to Bus Real Time Transfer B-Bus to A-Bus DS100231-10 DS100231-8 FIGURE 4. FIGURE 2. www.national.com 2 Function Table Inputs Data I/O (Note 1) G DIR CPAB CPBA H X H or L H or L X X H X N X X X SAB SBA A0–A7 B0–B7 Input Input Function Isolation Clock An Data into A Register H X X N X X Clock Bn Data into B Register L H X X L X An to Bn — Real Time (Transparent Mode) L H N X L X L H H or L X H X L H N X H X Clock An Data into A Register and Output to Bn L L X X X L Bn to An — Real Time (Transparent Mode) Input Output Clock An Data into A Register A Register to Bn (Stored Mode) L L X N X L L L X H or L X H B Register to An (Stored Mode) L L X N X H Clock Bn Data into B Register and Output to An Output Input Clock Bn Data into B Register H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial N = LOW-to-HIGH Transition Note 1: The data output functions may be enabled or disabled by various signals at the G and DIR inputs. Data input functions are always enabled; i.e., data at the bus pins will be stored on every LOW-to-HIGH transition of the appropriate clock inputs. 3 www.national.com Logic Diagram DS100231-5 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.national.com 4 Absolute Maximum Ratings (Note 2) Junction Temperature (TJ) CDIP If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) DC Input Diode Current (IIK) VI = −0.5V VI = VCC + 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = −0.5V VO = VCC + 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) 175˚C Recommended Operating Conditions −0.5V to +7.0V Supply Voltage (VCC) ’AC Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) 54AC Minimum Input Edge Rate (∆V/∆t) ’AC Devices VIN from 30% to 70% of VCC VCC @ 3.3V, 4.5V, 5.5V −20 mA +20 mA −0.5V to VCC + 0.5V −20 mA +20 mA −0.5V to VCC + 0.5V ± 50 mA 2.0V to 6.0V 0V to VCC 0V to VCC −55˚C to +125˚C 125 mV/ns Note 2: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. National does not recommend operation of FACT ® circuits outside databook specifications. ± 50 mA −65˚C to +150˚C DC Characteristics for ’AC Family Devices Symbol Parameter 54AC TA = VCC (V) Units Conditions −55˚C to +125˚C Guaranteed Limits VIH VIL VOH Minimum High Level 3.0 2.1 Input Voltage 4.5 3.15 5.5 3.85 Maximum Low Level 3.0 0.9 Input Voltage 4.5 1.35 5.5 1.65 Minimum High Level 3.0 2.9 Output Voltage 4.5 4.4 5.5 5.4 VOUT = 0.1V V or VCC − 0.1V V or VCC − 0.1V VOUT = 0.1V IOUT = −50 µA V (Note 3) VIN = VIL or VIH VOL 3.0 2.4 4.5 3.7 5.5 4.7 Maximum Low Level 3.0 0.1 Output Voltage 4.5 0.1 5.5 0.1 IOH = −12 mA V IOH = −24 mA IOH = −24 mA IOUT = 50 µA V (Note 3) VIN = VIL or VIH IIN Maximum Input 3.0 0.50 4.5 0.50 IOH = 12 mA V IOL = 24 mA 5.5 0.50 5.5 ± 1.0 µA IOH = 24 mA VI = VCC, GND 5.5 50 mA VOLD = 1.65V Max 5.5 −50 mA VOHD = 3.85V Min Leakage Current IOLD IOHD Minimum Dynamic Output Current (Note 4) 5 www.national.com DC Characteristics for ’AC Family Devices Symbol Parameter 54AC TA = VCC (V) (Continued) Units Conditions −55˚C to +125˚C Guaranteed Limits ICC Maximum Quiescent 5.5 160.0 VIN = VCC µA Supply Current IOZT or GND VI (OE) = VIL, VIH VI = VCC, GND VO = VCC, GND Maximum I/O Leakage Current ± 10.0 5.5 µA Note 3: All outputs loaded; thresholds on input associated with output under test. Note 4: Maximum test duration 2.0 ms, one output loaded at a time. Note 5: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC. ICC for 54AC @ 25˚C is identical to 74AC @ 25˚C. AC Electrical Characteristics VCC Symbol Parameter (V) (Note 6) tPLH tPHL tPLH tPHL tPLH 54AC TA = −55˚C to +125˚C CL = 50 pF Min Max Propagation Delay 3.3 1.0 20.0 Clock to Bus 5.0 1.5 14.0 Propagation Delay 3.3 1.0 17.5 Clock to Bus 5.0 1.5 12.0 Propagation Delay 3.3 1.0 15.0 Bus to Bus 5.0 1.5 10.0 Propagation Delay 3.3 1.0 14.5 Bus to Bus 5.0 1.5 9.5 Propagation Delay 3.3 1.0 17.0 SBA or SAB to An or Bn 5.0 1.5 12.0 Fig. Units ns ns ns ns ns (w/ An or Bn HIGH or LOW) tPHL Propagation Delay 3.3 1.0 17.0 SBA or SAB to An or Bn 5.0 1.5 12.0 ns ns (w/ An or Bn HIGH or LOW) tPZH tPZL tPHZ tPLZ tPZH tPZL tPHZ www.national.com Enable Time 3.3 1.0 13.0 G to An or Bn 5.0 1.5 9.5 Enable Time 3.3 1.0 15.5 G to An or Bn 5.0 1.5 11.0 Disable Time 3.3 1.0 14.0 G to An or Bn 5.0 1.5 11.0 Disable Time 3.3 1.0 13.5 G to An or Bn 5.0 1.5 11.0 Enable Time 3.3 1.0 14.5 DIR to An or Bn 5.0 1.5 10.5 Enable Time 3.3 1.0 16.0 DIR to An or Bn 5.0 1.5 12.5 Disable Time 3.3 1.0 14.5 DIR to An or Bn 5.0 1.5 12.0 6 ns ns ns ns ns ns No. AC Electrical Characteristics (Continued) 54AC TA = −55˚C VCC Symbol Parameter (V) to +125˚C CL = 50 pF (Note 6) Min tPLZ Fig. Units No. Max Disable Time 3.3 1.0 16.5 DIR to An or Bn 5.0 1.5 12.0 ns Note 6: Voltage Range 3.3 is 3.3V ± 0.3V Voltage Range 5.0 is 5.0V ± 0.5V AC Operating Requirements 54AC TA = −55˚C VCC Symbol Parameter (V) to +125˚C CL = 50 pF (Note 7) Fig. Units No. Guaranteed Minimum ts th tw Setup Time, HIGH or LOW 3.3 6.0 Bus to Clock 5.0 4.5 Hold Time, HIGH or LOW 3.3 1.5 Bus to Clock 5.0 2.0 Clock Pulse Width 3.3 5.0 HIGH or LOW 5.0 5.0 ns ns ns Note 7: Voltage Range 3.3 is 3.3V ± 0.3V Voltage Range 5.0 is 5.0V ± 0.5V Capacitance Typ Units CIN Symbol Input Capacitance Parameter 4.5 pF CI/O Input/Output Capacitance 15.0 pF Conditions VCC = OPEN VCC = 5.0V CPD Power Dissipation 60.0 pF VCC = 5.0V Capacitance 7 www.national.com 8 Physical Dimensions inches (millimeters) unless otherwise noted 28-Terminal Ceramic Leadless Chip Carrier (L) NS Package Number E28A 24-Lead Slim (0.300" Wide) Ceramic Dual-In-Line Package (SD) NS Package Number J24F 9 www.national.com 54AC646 Octal Transceiver/Register with TRI-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 24-Lead Ceramic Flatpak (F) NS Package Number W24C LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or sysdevice or system whose failure to perform can be reatems which, (a) are intended for surgical implant into sonably expected to cause the failure of the life support the body, or (b) support or sustain life, and whose faildevice or system, or to affect its safety or effectiveness. ure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 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