ETC LM6362M

General Description
The LM6362 family of high-speed amplifiers exhibits an excellent speed-power product, delivering 300 V/µs and
100 MHz gain-bandwidth product (stable for gains as low as
+2 or −1) with only 5 mA of supply current. Further power
savings and application convenience are possible by taking
advantage of the wide dynamic range in operating supply
voltage which extends all the way down to +5V.
These amplifiers are built with National’s VIP™ (Vertically Integrated PNP) process which provides fast transistors that
are true complements to the already fast NPN devices. This
advanced junction-isolated process delivers high speed performance without the need for complex and expensive dielectric isolation.
Features
n High slew rate:
n
n
n
n
n
n
n
n
High gain-bandwidth product: 100 MHz
Low supply current: 5 mA
Fast settling time: 120 ns to 0.1%
Low differential gain: < 0.1%
Low differential phase: < 0.1˚
Wide supply range: 4.75V to 32V
Stable with unlimited capacitive load
Well behaved; easy to apply
Applications
n Video amplifier
n Wide-bandwidth signal conditioning for image
processing (FAX, scanners, laser printers)
n Hard disk drive preamplifier
n Error amplifier for high-speed switching regulator
300 V/µs
Connection Diagrams
20-Lead LCC
10-Pin Ceramic Flatpak
DS011061-15
Top View
See NS Package Number W10A
DS011061-2
See NS Package
Number N08E, M08A or
J08A
DS011061-14
Top View
See NS Package Number E20A
Temperature Range
Military
Industrial
−55˚C ≤ TA ≤ +125˚C
LM6162N
−25˚C ≤ TA ≤ +85˚C
LM6262N
LM6162/LM6262/LM6362
LM6162/LM6262/LM6362
High Speed Operational Amplifier
LM6162/LM6262/LM6362 High Speed Operational Amplifier
August 1992
Package
Commercial
NSC
Drawing
0˚C ≤ TA ≤ +70˚C
LM6362N
LM6162J/883
8-Pin Molded DIP
N08E
8-Pin Ceramic DIP
J08A
5962-9216501PA
LM6262M
LM6362M
LM6162E/883
8-Pin Molded Surface Mt.
M08A
20-Lead LCC
E20A
10-Pin Ceramic Flatpak
W10A
5962-92165012A
LM6162W/883
5962-9216501HA
VIP™ is a trademark of National Semiconductor Corporation.
© 1997 National Semiconductor Corporation
www.national.com
DS011061
PrintDate=1997/09/29 PrintTime=12:36:17 18016 ds011061 Rev. No. 1
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1
1
Absolute Maximum Ratings
(Note 1)
Infrared (15 seconds)
220˚C
See AN-450 “Surface Mounting Methods and Their Effect
on Product Reliability” for other methods of soldering
surface mount devices.
Storage Temperature Range
−65˚C ≤ TJ ≤ +150˚C
Max Junction Temperature
150˚C
± 1100V
ESD Tolerance (Note 5)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V+–V−)
Differential Input Voltage (Note 2)
Common-Mode Input Voltage
(Note 3)
Output Short Circuit to GND
(Note 4)
Soldering Information
Dual-In-Line Package (N)
Soldering (10 seconds)
Small Outline Package (M)
Vapor Phase (60 seconds)
36V
± 8V
(V+−0.7V) to
(V− + 0.7V)
Operating Ratings
Temperature Range (Note 6)
LM6162
LM6262
LM6362
Supply Voltage Range
Continuous
260˚C
−55˚C ≤ TJ ≤ +125˚C
−25˚C ≤ TJ ≤ +85˚C
0˚C ≤ TJ ≤ +70˚C
4.75V to 32V
215˚C
DC Electrical Characteristics
These limits apply for supply voltage = ± 15V, VCM = 0V, and RL ≥ 100 kΩ, unless otherwise specified. Limits in standard typeface are for TA = TJ = 25˚C; limits in boldface type apply over the Operating Temperature Range.
Symbol
VOS
Parameter
Typical
(Note 7)
Conditions
±3
Input Offset Voltage
Input Offset Voltage
LM6162
LM6262
Limit
Limit
LM6362
Limit
(Note 8)
(Note 8)
(Note 8)
±5
±8
±5
±8
± 13
± 15
7
Units
mV
max
µV/˚C
Average Drift
Ibias
IOS
Input Bias Current
2.2
± 150
Input Offset Current
Input Offset Current
3
3
4
µA
6
5
6
max
± 350
± 800
± 350
± 600
± 1500
± 1900
max
nA
0.3
nA/˚C
180
kΩ
Average Drift
RIN
Input Resistance
CIN
Input Capacitance
AVOL
Large Signal
VOUT = ± 10V, RL = 2 kΩ
1400
Voltage Gain
(Note 9)
RL = 10 kΩ
6500
Supply = ± 15V
+14.0
VCM
Input Common-Mode
Differential
2.0
Voltage Range
−13.2
Supply = +5V
4.0
(Note 9)
1.6
CMRR
Common-Mode
−10V ≤ VCM ≤ +10V
100
Rejection Ratio
PSRR
Power Supply
± 10V ≤ VS ≤ ± 16V
93
Rejection Ratio
www.national.com
pF
1000
1000
800
500
700
650
V/V
min
V/V
+13.9
+13.9
+13.8
V
+13.8
+13.8
+13.7
min
−12.9
−12.9
−12.9
V
−12.7
−12.7
−12.8
max
3.9
3.9
3.8
V
3.8
3.8
3.7
min
1.8
1.8
1.9
V
2.0
2.0
2.0
max
83
83
76
dB
79
79
74
min
83
83
76
dB
79
79
74
min
2
PrintDate=1997/09/29 PrintTime=12:36:19 18016 ds011061 Rev. No. 1
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DC Electrical Characteristics
(Continued)
These limits apply for supply voltage = ± 15V, VCM = 0V, and RL ≥ 100 kΩ, unless otherwise specified. Limits in standard typeface are for TA = TJ = 25˚C; limits in boldface type apply over the Operating Temperature Range.
Symbol
VO
Parameter
Output Voltage
Typical
(Note 7)
Conditions
Supply = ± 15V, RL = 2 kΩ
+14.2
Swing
−13.4
VO
Output Voltage Swing
Supply = +5V and
RL = 2 kΩ (Note 10)
4.2
1.3
IOSC
Output Short
Sourcing
65
Circuit Current
Sinking
IS
65
Supply Current
5.0
LM6162
LM6262
Limit
Limit
LM6362
Limit
(Note 8)
(Note 8)
(Note 8)
+13.5
+13.5
+13.4
V
+13.3
+13.3
13.3
min
Units
−13.0
−13.0
−12.9
V
−12.7
−12.8
−12.8
max
3.5
3.5
3.4
V
3.3
3.3
3.3
min
1.7
1.7
1.8
V
2.0
1.9
1.9
max
30
30
30
mA
20
25
25
min
30
30
30
mA
20
25
25
min
6.5
6.5
6.8
mA
6.8
6.7
6.9
max
AC Electrical Characteristics
These limits apply for supply voltage = ± 15V, VCM = 0V, RL ≥ 100 kΩ, and CL ≤ 5 pF, unless otherwise specified. Limits in
standard typeface are for TA = TJ = 25˚C; limits in boldface type apply over the Operating Temperature Range .
Symbol
GBW
Parameter
Gain-Bandwidth Product
Typical
(Note
7)
Conditions
f = 20 MHz
100
Supply = ± 5V
SR
Slew Rate
LM6162
LM6262
Limit
Limit
LM6362
Limit
(Note 8)
(Note 8)
(Note 8)
80
80
75
55
65
65
70
AV = +2 (Note 11)
MHz
min
MHz
300
Supply = ± 5V
Units
200
200
200
180
180
180
V/µs
min
200
V/µs
PBW
Power Bandwidth
VOUT = 20 VPP
4.5
MHz
ts
Settling Time
10V step, to 0.1%
AV = −1, RL = 2 kΩ
AV = +2
100
ns
45
deg
NTSC, AV = +2
NTSC, AV = +2
< 0.1
< 0.1
deg
10
nV/√Hz
1.2
pA/√Hz
φm
Phase Margin
Differential Gain
Differential Phase
en
Input Noise Voltage
in
Input Noise Current
f = 10 kHz
f = 10 kHz
%
Note 1: Absolute maximum ratings indicate limits beyond which damage to the component may occur. Electrical specifications do not apply when operating the device beyond its rated operating conditions.
Note 2: The ESD protection circuitry between the inputs will begin to conduct when the differential input voltage reaches 8V.
Note 3: a) In addition, the voltage between the V+ pin and either input pin must not exceed 36V.
3V below the negative supply pin voltage, a substrate diode begins to conduct. Current
through this pin must then be kept less than 20 mA to limit damage from self-heating.
Note 4: Although the output current is internally limited, continuous short-circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature of 150˚C.
Note 5: This value is the average voltage that the weakest pin combinations can withstand and still conform to the datasheet limits. The test circuit used consists
of the human body model, 100 pF in series with 1500Ω.
Note 6: The typical thermal resistance, junction-to-ambient, of the molded plastic DIP (N package) is 105˚C/W. For the molded plastic SO (M package), use 155˚C/W.
All numbers apply for packages soldered directly into a printed circuit board.
Note 7: Typical values are for TJ = 25˚C, and represent the most likely parametric norm.
Note 8: Limits are guaranteed, by testing or correlation.
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AC Electrical Characteristics
(Continued)
Note 9: Voltage Gain is the total output swing (20V) divided by the magnitude of the input signal required to produce that swing.
Note 10: For single-supply operation, the following conditions apply: V+ = 5V, V− = 0V, VCM = 2.5V, VOUT = 2.5V. Pin 1 and Pin 8 (VOS Adjust pins) are each connected to pin 4 (V−) to realize maximum output swing. This connection will increase the offset voltage.
Note 11: VIN = 10V step. For ± 5V supplies, VIN = 1V step.
Note 12: A military RETS electrical test specification is available on request.
Typical Performance Characteristics
RL = 10 kΩ, TA = 25˚C unless otherwise noted
Common-Mode
Rejection Ratio
Supply Current vs
Supply Voltage
Power Supply
Rejection Ratio
DS011061-16
Gain-Bandwidth Product
vs Supply Voltage
DS011061-17
Gain-Bandwidth Product
vs Load Capacitance
DS011061-19
Slew Rate vs
Supply Voltage
Propagation Delay,
Rise and Fall Times
DS011061-21
DS011061-20
Slew Rate vs
Load Capacitance
Overshoot vs
Load Capacitance
DS011061-22
www.national.com
DS011061-18
DS011061-23
DS011061-24
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PrintDate=1997/09/29 PrintTime=12:36:22 18016 ds011061 Rev. No. 1
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Typical Performance Characteristics
RL = 10 kΩ, TA = 25˚C unless otherwise noted (Continued)
Voltage Gain vs
Load Resistance
Output Impedance
(Open-Loop)
DS011061-25
Voltage Gain vs
Supply Voltage
DS011061-27
DS011061-26
Differential Gain (Note)
Differential Phase (Note 13)
Differential Gain (Note 13)
DS011061-5
Note 13: Differential gain and differential phase
measured for four series LM6362 op amps configured with gain of +2 each, in series with a 1:16
attenuator and an LM6321 buffer. Error added by
LM6321 is negligible. Test performed using Tektronix Type 520 NTSC test system.
DS011061-4
Step Response; Av = +2
DS011061-6
5
PrintDate=1997/09/29 PrintTime=12:36:22 18016 ds011061 Rev. No. 1
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Typical Performance Characteristics
RL = 10 kΩ, TA = 25˚C unless otherwise noted (Continued)
Input Noise Current
Input Noise Voltage
DS011061-28
Power Bandwidth
DS011061-29
Open-Loop
Frequency Response
DS011061-30
Open-Loop
High-Frequency Response
DS011061-8
Common-Mode Input
Voltage Limits
DS011061-9
Output Saturation Voltage
Bias Current vs
Common-Mode Voltage
DS011061-32
DS011061-33
DS011061-31
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PrintDate=1997/09/29 PrintTime=12:36:23 18016 ds011061 Rev. No. 1
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Simplified Schematic
DS011061-1
Application Tips
Power supply bypassing is not as critical for LM6362 as it is
for other op amps in its speed class. However, bypassing will
improve the stability and transient response of the LM6362,
and is recommended for every design. 0.01 µF to 0.1 µF ceramic capacitors should be used (from each supply “rail” to
ground); if the device is far away from its power supply
source, an additional 2.2 µF to 10 µF of tantalum may be required for extra noise reduction.
Keep all leads short to reduce stray capacitance and lead inductance, and make sure ground paths are low-impedance,
especially where heavier currents will be flowing. Stray capacitance in the circuit layout can cause signal coupling from
one pin, input or lead to another, and can cause circuit gain
to unintentionally vary with frequency.
Breadboarded circuits will work best if they are built using
generic PC boards with a good ground plane. If the op amps
are used with sockets, as opposed to being soldered into the
circuit, the additional input capacitance may degrade circuit
frequency response. At low gains (+2 or −1), a feedback capacitor Cf from output to inverting input will compensate for
the phase lag caused by capacitance at the inverting input.
Typically, values from 2 pF to 5 pF work well; however, best
results can be obtained by observing the amplifier pulse response and optimizing Cf for the particular layout.
The LM6362 has been decompensated for a wider
gain-bandwidth product than the LM6361. However, the
LM6362 still offers stability at gains of 2 (and −1) or greater
over the specified ranges of temperature, power supply voltage, and load. Since this decompensation involved reducing
the emitter-degeneration resistors in the op amp’s input
stage, the DC precision has been increased in the form of
lower offset voltage and higher open-loop gain.
Other op amps in this family include the LM6361, LM6364,
and LM6365. If unity-gain stability is required, the LM6361
should be used. The LM6364 has been decompensated for
operation at gains of 5 or more, with corresponding greater
gain-bandwidth product (125 MHz, typical) and DC precision.
The
fully-uncompensated
LM6365
offers
gain-bandwidth product of 725 MHz, typical, and is stable for
gains of 25 or more. All parts in this family, regardless of
compensation, have the same high slew rate of 300 V/µs
(typ).
The LM6362 is unusually tolerant of capacitive loads. Most
op amps tend to oscillate when their load capacitance is
greater than about 200 pF (in low-gain circuits). However,
load capacitance on the LM6362 effectively increases its
compensation capacitance, thus slowing the op amp’s response and reducing its bandwidth. The compensation is not
ideal, though, and ringing may occur in low-gain circuits with
large capacitive loads.
7
PrintDate=1997/09/29 PrintTime=12:36:23 18016 ds011061 Rev. No. 1
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Typical Applications
Offset Voltage Adjustment
Inverting Amplifier, 30 MHz Bandwidth
DS011061-11
DS011061-12
Operation on ± 15V supplies results in wider bandwidth, 50 MHz (typ).
Book
Extract
End
Video Cable Driver
DS011061-13
* Network required when operating on supply voltage over ± 5V, for overvoltage protection of LM6321. If ± 5V supplies are used, omit network and connect
output of LM6362 directly to input of LM6321.
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Physical Dimensions
inches (millimeters) unless otherwise noted
20-Lead Small Outline Package (E)
Order Number LM6162E/883
NS Package Number E20A
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Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
Ceramic Dual-In-Line Package (J)
Order Number LM6162J/883
NS Package Number J08A
Molded Package SO (M)
Order Number LM6262M or LM6362M
NS Package Number M08A
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Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
Molded Dual-In-Line Package (N)
Order Number LM6162N, LM6262N or LM6362N
NS Package Number N08E
10-Pin Ceramic Flatpak
Order Number LM6162W/883
NS Package Number W10A
11
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LM6162/LM6262/LM6362 High Speed Operational Amplifier
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
1. Life support devices or systems are devices or sysdevice or system whose failure to perform can be reatems which, (a) are intended for surgical implant into
sonably expected to cause the failure of the life support
the body, or (b) support or sustain life, and whose faildevice or system, or to affect its safety or effectiveness.
ure to perform when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
National Semiconductor
Corporation
Americas
Tel: 1-800-272-9959
Fax: 1-800-737-7018
Email: [email protected]
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Email: [email protected]
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Tel: 81-3-5620-6175
Fax: 81-3-5620-6179
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
PrintDate=1997/09/29 PrintTime=12:36:25 18016 ds011061 Rev. No. 1
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