ETC NC7SZ175P6

Revised January 2001
NC7SZ175
TinyLogic UHS D-Type Flip-Flop
with Asynchronous Clear
General Description
Features
The NC7SZ175 is a single positive edge-triggered D-type
CMOS Flip-Flop with Asynchronous Clear from Fairchild’s
Ultra High Speed Series of TinyLogic in the space saving
SC70 6-lead package. The device is fabricated with
advanced CMOS technology to achieve ultra high speed
with high output drive while maintaining low static power
dissipation over a very broad VCC operating range. The
device is specified to operate over the 1.65V to 5.5V VCC
range. The inputs and output are high impedance when
VCC is 0V. Inputs tolerate voltages up to 7V independent of
VCC operating voltage. This single flip-flop will store the
state of the D input that meets the setup and hold time
requirements on the LOW-to-HIGH Clock (CP) transition. A
LOW input to Clear sets the Q output to LOW level. The
Clear input is independent of clock.
■ Space saving SC70 6-lead package
■ Ultra High Speed; tPD 2.6 ns Typ into 50 pF at 5V VCC
■ High Output Drive; ±24 mA at 3V VCC
■ Broad VCC Operating Range; 1.65V to 5.5V
■ Matches the performance of LCX when operated at
3.3V VCC
■ Power down high impedance inputs/output
■ Overvoltage tolerant inputs facilitate 5V to 3V translation
■ Patented noise/EMI reduction circuitry implemented
Ordering Code:
Order
Package
Product Code
Number
Number
Top Mark
NC7SZ175P6
MAA06A
Z75
6-Lead SC70, EIAJ SC88, 1.25mm Wide 250 Units on Tape and Reel
NC7SZ175P6X
MAA06A
Z75
6-Lead SC70, EIAJ SC88, 1.25mm Wide 3k Units on Tape and Reel
Package Description
Function Table
Logic Symbol
Inputs
CP
D
X
H = HIGH Logic Level
L = LOW Logic Level
Supplied As
Output
C
IEEE/IEC
Q
L
H
L
H
H
H
X
H
Qn
X
L
L
Connection Diagrams
Qn = No change in data
X = Immaterial
Z = HIGH Impedance
Pin Descriptions
Pin Names
D
CP
(Top View)
Description
Data Input
Pin One Orientation Diagram
Clock Pulse Input
C
Clear Input
Q
Flip-Flop Output
AAA represents Product Code Top Mark - see ordering code
Note: Orientation of Top Mark determines Pin One location. Read the top
product code mark left to right, Pin One is the lower left pin (see diagram).
TinyLogic is a trademark of Fairchild Semiconductor Corporation.
© 2001 Fairchild Semiconductor Corporation
DS500158
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NC7SZ175 TinyLogic UHS D-Type Flip-Flop with Asynchronous Clear
May 1998
NC7SZ175
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC)
−0.5V to +7.0V
DC Input Voltage (VIN)
−0.5V to +7.0V
DC Output Voltage (VOUT)
−0.5V to +7.0V
Recommended Operating
Conditions (Note 2)
Power Supply
DC Input Diode Current (IIK)
VIN < 0V
−50 mA
DC Output Diode Current (IOK)
VOUT < 0V
−50 mA
Operating (VCC)
1.65V to 5.5V
Data Retention
1.5V to 5.5V
Input Voltage (VIN)
0V to 5.5V
Output Voltage (VOUT)
0V to VCC
Input Rise and Fall Time (tr, tf)
DC Output (IOUT) Source/Sink Current
±50 mA
VCC = 1.8V, 2.5V ± 0.2V
0 to 20 ns/V
DC VCC/GND Current (ICC/IGND)
±50 mA
VCC = 3.3V ± 0.3V
0 to 10 ns/V
−65°C to +150°C
VCC= 5.5V ± 0.5V
Storage Temperature Range (TSTG)
150°C
Junction Temperature under Bias (TJ)
0 to 5 ns/V
−40°C to +85°C
Operating Temperature (TA)
Thermal Resistance (θJA)
Junction Lead Temperature (TL)
260°C
(Soldering, 10 seconds)
Power Dissipation (PD) @+85°C
350 ° C/W
Note 1: The “Absolute Maximum Ratings”: are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
180 mW
Note 2: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Symbol
Parameter
(V)
VIH
HIGH Level Control
Input Voltage
VIL
LOW Level Control
Input Voltage
VOH
VOL
TA = +25°C
VCC
Min
Typ
TA = −40°C to +85°C
Max
1.65 to 1.95 0.75 VCC
2.3 to 5.5
Min
0.75 VCC
0.7 VCC
1.65 to 1.95
0.25 VCC
0.25 VCC
2.3 to 5.5
0.3 VCC
0.3 VCC
1.65
1.55
1.65
Output Voltage
1.8
1.7
1.8
1.7
2.3
2.2
2.3
2.2
3.0
2.9
3.0
2.9
IOH = −100 µA
4.4
4.5
4.4
1.24
1.52
1.29
2.3
1.9
2.15
1.9
IOH = −8 mA
3.0
2.4
2.8
2.4
IOH = −16 mA
3.0
2.3
2.68
2.3
IOH = −24 mA
4.5
3.8
4.2
3.8
V
0.1
Output Voltage
1.8
0.0
0.1
0.1
2.3
0.0
0.1
0.1
3.0
0.0
0.1
0.1
IOFF
Power Off Leakage Current
Quiescent Supply Current
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or VIL
IOH = −4 mA
IOH = −32 mA
0.0
ICC
VIN = VIH
4.5
1.65
1.65
Input Leakage Current
V
1.55
LOW Level Control
IIN
Conditions
V
0.7 VCC
HIGH Level Control
Unit
Max
0.1
IOL = 100 µA
VIN = VIL
4.5
0.0
0.1
0.1
1.65
0.08
0.24
0.24
2.3
0.10
0.3
0.3
IOL = 8 mA
3.0
0.15
0.4
0.4
IOL = 16 mA
3.0
0.22
0.55
0.55
IOL = 24 mA
4.5
0.22
0.55
0.55
±0.1
±1.0
µA
0 ≤ VIN ≤ 5.5V
0 to 5.5
V
or VIH
IOL = 4 mA
IOL = 32 mA
0.0
1.0
10
µA
VIN or VOUT = 5.5V
1.65 to 5.5
1.0
10.0
µA
VIN = 5.5V, GND
2
Symbol
(V)
Maximum Clock
fMAX
TA = +25°C
VCC
Parameter
Min
Typ
TA = −40°C to +85°C
Max
1.65
Frequency
Min
Max
Units
Conditions
Fig. No.
100
1.8
100
2.5 ± 0.2
125
3.3 ± 0.3
150
5.0 ± 0.5
MHz
CL = 50 pF
RL = 500 Ω
Figures
1, 4
175
tPLH
Propagation Delay
1.65
2.5
9.8
15.0
2.5
16.5
tPHL
CP to Q
1.8
2.5
6.5
10.0
2.5
11.0
2.5 ± 0.2
2.0
3.8
6.5
2.0
7.0
3.3 ± 0.3
1.5
2.8
4.5
1.4
5.0
5.0 ± 0.5
1.0
2.2
3.5
1.0
3.8
3.3 ± 0.3
2.0
3.4
5.5
1.6
6.2
CL = 50 pF
5.0 ± 0.5
1.5
2.6
4.0
1.4
4.7
RL = 500 Ω
Figures
1, 3
Propagation Delay
1.65
2.5
9.8
13.5
2.5
15.0
C to Q
1.8
2.5
6.5
9.0
2.5
10.0
2.5 ± 0.2
2.0
3.8
6.0
2.0
6.4
CL = 15 pF
3.3 ± 0.3
Figures
1, 3
1.5
2.8
4.3
1.2
4.6
5.0 ± 0.5
1.5
2.2
3.2
1.0
3.5
3.3 ± 0.3
1.5
3.4
5.3
1.5
5.8
CL = 50 pF
5.0 ± 0.5
1.0
2.7
4.0
1.2
4.5
RL = 500 Ω
tPHL
tS
tH
Setup Time
2.5 ± 0.2
2.5
CP to D
3.3 ± 0.3
2.0
5.0 ± 0.5
1.5
Hold Time,
2.5 ± 0.2
1.5
CP to D
3.3 ± 0.3
1.5
5.0 ± 0.5
1.5
2.5 ± 0.2
3.0
3.3 ± 0.3
2.8
5.0 ± 0.5
2.5
2.5 ± 0.2
3.0
3.3 ± 0.3
2.8
5.0 ± 0.5
2.5
Recovery Time,
2.5 ± 0.2
1.0
C to CP
3.3 ± 0.3
1.0
5.0 ± 0.5
1.0
Pulse Width, CP
tW
Pulse Width, C
trec
CL = 15 pF
ns
ns
RL = 1 MΩ
RL = 1 MΩ
CL = 50 pF
ns
RL = 500 Ω
ns
RL = 500 Ω
CL = 50 pF
CL = 50 pF
ns
RL = 500 Ω
Figures
1, 3
Figures
1, 3
Figures
1, 4
Figures
1, 4
Figures
1, 4
Clock HIGH or LOW
ns
CL = 50 pF
RL = 500 Ω
CL = 50 pF
ns
RL = 500 Ω
Figures
1, 4
Figures
1, 4
Capacitance (Note 3)
Symbol
Parameter
Typ
CIN
Input Capacitance
COUT
Output Capacitance
4
CPD
Power Dissipation Capacitance
10
(Note 4)
12
Max
3
Units
Conditions
pF
VCC = Open, VIN = 0V or VCC
pF
VCC = 3.3V, VIN = 0V or VCC
pF
VCC = 3.3V
VCC = 5.0V
Note 3: TA = +25C, f = 1MHz.
Note 4: CPD is defined as the value of the internal equivalent capacitance which is derived from dynamic operating current consumption (ICCD) at no output
loading and operating at 50% duty cycle. (See Figure 2)
CPD is related to ICCD dynamic operating current by the expression: ICCD = (CPD)(VCC)(fIN) + (ICCstatic).
3
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NC7SZ175
AC Electrical Characteristics
NC7SZ175
AC Loading and Waveforms
CL includes load and stray capacitance
CP Input = AC Waveform; tr = tf = 1.8 ns;
Input PRR = 1.0 MHz, tw = 500 ns
CP Input PRR = 10 MHz; Duty Cycle = 50%
D Input PRR = 5MHz; Duty Cycle = 50%
FIGURE 1. AC Test Circuit
FIGURE 2. ICCD Test Circuit
FIGURE 3. AC Waveforms
FIGURE 4. AC Waveforms
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4
TAPE FORMAT
Package
Designator
Tape
Number
Cavity
Section
Cavities
Status
Status
125 (typ)
Empty
Sealed
Leader (Start End)
P6
P6X
Carrier
Cover Tape
250
Filled
Sealed
Trailer (Hub End)
75 (typ)
Empty
Sealed
Leader (Start End)
125 (typ)
Empty
Sealed
3000
Filled
Sealed
75 (typ)
Empty
Sealed
Carrier
Trailer (Hub End)
TAPE DIMENSIONS inches (millimeters)
Package
SC70-6
Tape Size
8 mm
DIM A
DIM B
0.093
0.096
(2.35)
(2.45)
DIM F
DIM Ko
0.138 ± 0.004 0.053 ± 0.004
(3.5 ± 0.10)
5
(1.35 ± 0.10)
DIM P1
DIM W
0.157
0.315 ± 0.004
(4)
(8 ± 0.1)
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NC7SZ175
Tape and Reel Specification
NC7SZ175
Tape and Reel Specification
(Continued)
REEL DIMENSIONS inches (millimeters)
Tape
Size
8 mm
A
B
C
D
N
W1
W2
W3
7.0
0.059
0.512
0.795
2.165
0.331 + 0.059/−0.000
0.567
W1 + 0.078/−0.039
(177.8)
(1.50)
(13.00)
(20.20)
(55.00)
(8.40 + 1.50/−0.00)
(14.40)
(W1 + 2.00/−1.00)
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6
NC7SZ175 TinyLogic UHS D-Type Flip-Flop with Asynchronous Clear
Physical Dimensions inches (millimeters) unless otherwise noted
6-Lead SC70, EIAJ SC88, 1.25mm Wide
Package Number MAA06A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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7
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