DC to 2.0 GHz Multiplier ADL5391 Ultrafast symmetric multiplier Function: VW = α × (VX × VY)/1 V + VZ Unique design ensures absolute XY-symmetry Identical X and Y amplitude/timing responses Adjustable gain scaling, α DC-coupled throughout, 3 dB bandwidth of 2 GHz Fully differential inputs, may be used single ended Low noise, high linearity Accurate, temperature stable gain scaling Single-supply operation (4.5 V to 5.5 V @ 130 mA) Low current power-down mode 16-lead LFCSP FUNCTIONAL BLOCK DIAGRAM YMNS YPLS GADJ XPLS ZMNS XMNS ZPLS WPLS ENBL WMNS ADL5391 VMID W = αXY/1V+Z COMM VPOS 06059-001 FEATURES Figure 1. APPLICATIONS Wideband multiplication and summing High frequency analog modulation Adaptive antennas (diversity/phased array) Square-law detectors and true rms detectors Accurate polynomial function synthesis DC capable VGA with very fast control GENERAL DESCRIPTION The ADL5391 draws on three decades of experience in advanced analog multiplier products. It provides the same general mathematical function that has been field proven to provide an exceptional degree of versatility in function synthesis. VW = α × (VX × VY)/ 1 V + VZ The most significant advance in the ADL5391 is the use of a new multiplier core architecture, which differs markedly from the conventional form that has been in use since 1970. The conventional structure that employs a current mode, translinear core is fundamentally asymmetric with respect to the X and Y inputs, leading to relative amplitude and timing misalignments that are problematic at high frequencies. The new multiplier core eliminates these misalignments by offering symmetric signal paths for both X and Y inputs. The Z input allows a signal to be added directly to the output. This can be used to cancel a carrier or to apply a static offset voltage. The fully differential X, Y, and Z input interfaces are operational over a ±2 V range, and they can be used in single-ended fashion. The user can apply a common mode at these inputs to vary from the internally set VPOS/2 down to ground. If these inputs are ac-coupled, their nominal voltage will be VPOS/2. These input interfaces each present a differential 500 Ω input impedance up to approximately 700 MHz, decreasing to 50 Ω at 2 GHz. The gain scaling input, GADJ, can be used for fine adjustment of the gain scaling constant (α) about unity. The differential output can swing ±2 V about the VPOS/2 common-mode and can be taken in a single-ended fashion as well. The output common mode is designed to interface directly to the inputs of another ADL5391. Light dc loads can be ground referenced; however, ac-coupling of the outputs is recommended for heavy loads. The ENBL pin allows the ADL5391 to be disabled quickly to a standby mode. It operates off supply voltages from 4.5 V to 5.5 V while consuming approximately 130 mA. The ADL5391 is fabricated on Analog Devices proprietary, high performance, 65 GHz, SOI complementary, SiGe bipolar IC process. It is available in a 16-lead, Pb-free, LFCSP and operates over a −40°C to +85°C temperature range. Evaluation boards are available. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved. ADL5391 TABLE OF CONTENTS Features .............................................................................................. 1 Typical Performance Characteristics ..............................................7 Applications....................................................................................... 1 General Description....................................................................... 10 Functional Block Diagram .............................................................. 1 Basic Theory ............................................................................... 10 General Description ......................................................................... 1 Basic Connections...................................................................... 10 Revision History ............................................................................... 2 Evaluation Board ............................................................................ 13 Specifications..................................................................................... 3 Outline Dimensions ....................................................................... 15 Absolute Maximum Ratings............................................................ 5 Ordering Guide .......................................................................... 15 ESD Caution.................................................................................. 5 Pin Configuration and Function Descriptions............................. 6 REVISION HISTORY 7/06—Revision 0: Initial Version Rev. 0 | Page 2 of 16 ADL5391 SPECIFICATIONS VPOS = 5 V, TA = 25°C, ZL = 50 Ω differential, ZPLS = ZMNS = open, GADJ = open, unless otherwise noted. Transfer function: W = XY/1 V + Z, common mode internally set to 2.5 V nominal. Table 1. Parameter MULTIPLICAND INPUTS (X, Y) Differential Voltage Range Common-Mode Range Input Offset Voltage vs. Temperature Differential Input Impedance Fundamental Feedthrough, X or Y Gain DC Linearity Scale Factor CMRR SUMMING INPUT (Z) Differential Voltage Range Common-Mode Range Gain Differential Input Impedance OUTPUTS (W) Differential Voltage Range Common-Mode Output Output Noise Floor Output Noise Voltage Spectral Density Output Offset Voltage vs. Temperature Differential Output Impedance DYNAMIC CHARACTERISTICS Frequency Range Slew Rate Settling Time Second Harmonic Distortion Third Harmonic Distortion Conditions XPLS, XMNS, YPLS, YMNS Differential, common mode = 2.5 V For full differential range DC −40°C to +85°C f = dc f = 2 GHz f = 50 MHz, X (Y) = 0 V, Y (X) = 0 dBm, relative to condition where X (Y) = 1 V f = 1 GHz X = 50 MHz and 0 dBm, Y = 1 V X = 1 GHz and 0 dBm, Y = 1 V X to output, Y = 1 V X=Y=1V ±1 V p-p, Y = 1 V, f = 50 MHz ZPLS, ZMNS Common mode from 2.5 V down to COMM For full differential range From Z to W, f ≤ 10 MHz, 0 dBm, X = Y = 1 V f = dc f = 2 GHz WPLS, WMNS No external common mode Min Unit 20 ±20 500 150 −42 V p-p V mV mV Ω Ω dB −35 0.5 −1.33 1 1 42.1 dB dB dB % FS V/V dB 2.5 2 0.1 500 150 V p-p V dB Ω Ω ±2 VPOS − 2.5 V V −133 −133 dBm/Hz dBm/Hz −138 −138 26.7 19 ±19 0 75 500 dBm/Hz dBm/Hz nV/√Hz mV mV Ω Ω Ω 0 f = dc f = 200 MHz f = 2 GHz Rev. 0 | Page 3 of 16 Max 2 0 X = Y = 1 V dc f = 1 MHz f = 1 GHz X=Y=0 f = 1 MHz f = 1 GHz X = Y = 0, f = 1 MHz Z = 0 V differential X, Y, Z to W W from −2.0 V to +2.0 V, 150 Ω X stepped from −1 V to +1 V, Z = 0 V, 150 Ω X (Y) = 0 dBm, Y (X) = 1 V, fund = 10 MHz Fund = 200 MHz X (Y) = 0 dBm, Y (X) = 1 V, fund = 10 MHz Fund = 200 MHz Typ 2.5 0 2 8800 2.1 −60 −51 −61.5 −51.6 GHz V/μs ns dBc dBc dBc dBc ADL5391 Parameter OIP3 OIP2 Output 1 dB Compression Point Group Delay Differential Gain Error, X/Y Differential Phase Error, X/Y GAIN TRIMMING (α) Nominal Bias Input Range Gain Adjust Range REFERENCE VOLTAGE Source Current POWER AND ENABLE Supply Voltage Range Total Supply Current Disable Current Disable Threshold Enable Response Time Disable Response Time Conditions Two-tone IP3 test; X (Y) = 100 mV p-p/tone (−10 dBm into 50 Ω), Y (X) = 1 f1= 49 MHz, f = 50 MHz f1 = 999 MHz, f2 = 1 GHz f1 = 49 MHz, f = 50 MHz f1 = 999 MHz, f2 = 1 GHz X (Y) to W, Y (X) = 1 V, 50 MHz 1 GHz 200 MHz 1 GHz f = 3.58 MHz f = 3.58 MHz GADJ Unconnected Min Typ 26.5 14 45.5 28 15.1 13.2 0.5 0.7 2.7 0.23 Input 0 V to 2 V VMID Common-mode for X, Y, Z = 2.5 V VPOS, COMM, ENBL 2 9.5 VPOS/2 50 4.5 Rev. 0 | Page 4 of 16 Unit dBm dBm dBm dBm dBm dBm ns ns % Degrees 1.12 0 Common-mode for X, Y, Z = 2.5 V ENBL = 0 V High to Low Delay following high-to-low transition until device meets full specifications Delay following low-to-high transition until device produces full attenuation Max 5.5 V V dB V mA 135 7.5 1.5 150 V mA mA V ns 50 ns ADL5391 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Supply Voltage VPOS ENBL XPLS, XMNS, YPLS, YMNS, ZPLS, ZMNS GADJ Internal Power Dissipation θJA (With Pad Soldered to Board) Maximum Junction Temperature Operating Temperature Range Storage Temperature Range Lead Temperature (Soldering 60 sec) Rating 5.5 V 5.5 V VPOS VPOS 800 mW 73°C/W 150°C −40°C to +85°C −65°C to +150°C 300°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 0 | Page 5 of 16 ADL5391 13 XPLS ADL5391 VPOS 4 12 YMNS 11 YPLS 10 ZPLS GADJ 8 COMM 7 WPLS 5 WMNS 6 9 ZMNS 06059-002 VPOS 3 14 XMNS 16 VMID PIN 1 INDICATOR COMM 1 VPOS 2 15 ENBL PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 2. Pin Configuration Table 3. Pin Function Descriptions Pin No. 1, 7 2 to 4 5, 6 8 9, 10 11, 12 13, 14 15 16 Mnemonic COMM VPOS WPLS, WMNS GADJ ZMNS, ZPLS YPLS, YMNS XPLS, XMNS ENBL VMID Description Device Common. Connect via lowest possible impedance to external circuit common. Positive Supply Voltage. 4.5 V to 5.5 V. Differential Outputs. Denominator Scaling Input. Differential Intercept Inputs. Must be ac-coupled. Differential impedance 50 Ω nominal. Differential X-Multiplicand Inputs. Differential Y-Multiplicand Inputs. Chip Enable. High to enable. VPOS/2 Reference Output. Connect decoupling capacitor to circuit common. Rev. 0 | Page 6 of 16 ADL5391 TYPICAL PERFORMANCE CHARACTERISTICS GADJ = open. 14 Y = –2 Y = –1 Y=0 Y = +1 Y = +2 2.5 2.0 1.5 8 4 0.5 GAIN (dB) 0 –0.5 50 2 –0 0 –2 –50 –4 –6 –1.5 –100 –8 –2.0 –10 –2.5 –150 –12 0 0.5 1.0 1.5 2.0 2.5 XDIFF (VDC) –14 –200 06059-010 –0.5 FREQUENCY (MHz) Figure 3. Full Range DC Cross Plots Figure 6. Gain and Phase vs. Frequency of X Swept and Y = 1 V, Z = 0 V, PIN = 0 dBm 0 –0 –1 –50 –2 –100 –3 –150 –4 –200 –0.05 –0.20 –0.20 –0.15 –0.10 –0.05 0 0.05 0.10 0.15 0.20 XDIFF (VDC) 1 –0.15 06059-008 Y = –2 Y = –1 Y=0 Y = +1 Y = +2 –0.10 06059-011 0 1300 50 1200 1 1100 0.05 990 100 880 2 700 0.10 660 150 550 3 440 0.15 330 200 220 4 GAIN (dB) 0.20 PHASE (Degrees) –1.0 5 100 195 290 385 480 575 670 765 860 955 1050 1150 1240 1340 1430 1530 1620 1720 1810 1910 2000 –1.5 06059-007 –2.0 110 WDIFF (VDC) 100 6 –1.0 WDIFF (VDC) 150 10 1.0 –3.0 –2.5 200 12 PHASE (Degrees) 3.0 FREQUENCY (MHz) Figure 7. Gain and Phase vs. Frequency of Z Inputs, X = 0 V, Y = 0 V, PIN = 0 dBm Figure 4. Magnified DC Cross Plots 2.0 2.5 X ± INPUT = 1.0V p-p, @ 200MHz Y ± INPUT = 1.0V DC DIFFERENTIAL 1.5 2.0 WOUTPUT (V) 1.5 1.0 0.5 0 –0.5 –1.0 0.5 0 –1.0 –0.5 0 0.5 1.0 GADJ (VDC) 1.5 2.0 Figure 5. Gain vs. GADJ (X = Y = 1) –2.0 24.5 25.5 26.5 27.5 28.5 29.5 30.5 31.5 TIME (ns) Figure 8. Large Signal Pulse Response Rev. 0 | Page 7 of 16 32.5 33.5 06059-013 –1.5 06059-009 GAIN (V/V) 1.0 ADL5391 0.20 30 X ± INPUT = ±100mV p-p, @ 200MHz Y ± INPUT = 1.0V DC DIFFERENTIAL 0.15 25 20 0.05 OIP3 (dBm) WOUTPUT (V) 0.10 0 –0.05 Y=1 15 Y = 0.5 10 –0.10 25.5 26.5 27.5 28.5 29.5 30.5 31.5 0 06059-014 –0.20 24.5 32.5 TIME (ns) 0 500 1000 1500 2000 FREQUENCY (MHz) Figure 9. Small Signal Pulse Response 06059-016 5 –0.15 Figure 12. OIP3 vs. Frequency Pin 0 dBm, Y = 1 V dc, 0.5 V dc 0.05 0.04 0.03 +85°C, X = +1 +85°C, X = –1 –40°C, X = –1 –40°C, X = +1 +25°C, X = –1 +25°C, X = +1 WDIFF (VDC) 0.02 10MHz 10dBm/DIV 10dBm/DIV 200MHz 400MHz 0.01 0 –0.01 600MHz –0.02 –0.03 30MHz 06059-094 –0.05 –0.05 –0.04 –0.03 –0.02 –0.01 0 0.01 0.02 0.03 0.04 0.05 YDIFF (VDC) Figure 10. Harmonic Distortion at 10 MHz and 200 MHz; 0 dBm Input to X (Y) Channels 06059-021 –0.04 20MHz Figure 13. Z (W) Offset Over Temperature 28 45 X = 0V, Y = 1V 26 40 X = Y = 1V 22 SND (nV/ Hz) 35 20 18 16 X = Y = 0V 30 25 14 20 10 –40 –15 10 35 60 TEMPERATURE (°C) 85 15 200 400 600 800 1000 1200 1400 1600 1800 2000 FREQUENCY (MHz) Figure 11. X ( Y) Offset Drift vs. Temperature Figure 14. Noise vs. Frequency Rev. 0 | Page 8 of 16 06059-019 12 06059-015 AVERAGE VOFFSET (VDC) 24 ADL5391 S22 SE S11 SE 1.00UFS 1.00UFS S11 DIFF S22 DIFF 3001.000 0.654 U 0.594 U 0.531 U –36.340 DEG –92.533 DEG –94.448 DEG 201.000 2001.000 0.800 U 0.564 U –17.218 DEG –58.167 DEG 06059-017 201.000 1001.000 1901.000 1.000 Figure 15. Input S11 3001.000 201.000 1001.000 1901.000 0.947 U 0.569 U 0.597 U +170.736 DEG +58.257 DEG –69.673 DEG 201.000 2001.000 0.905 U 0.663 U +157.308 DEG –39.468 DEG Figure 16. Output S22 Rev. 0 | Page 9 of 16 06059-018 1.000 ADL5391 GENERAL DESCRIPTION BASIC THEORY The multiplication of two analog variables is a fundamental signal processing function that has been around for decades. By convention, the desired transfer function is given by W = αXY/U + Z (1) where: X and Y are the multiplicands. U is the multiplier scaling factor. α is the multiplier gain. W is the product output. Z is a summing input. All the variables and the scaling factor have the dimension of volts. In the past, analog multipliers, such as the AD835, were implemented almost exclusively with a Gilbert Cell topology or a close derivative. The inherently asymmetric signal paths for X and Y inevitably create amplitude and delay imbalances between X and Y. In the ADL5391, the novel multiplier core provides absolute symmetry between X and Y, minimizing scaling and phasing differences inherent in the Gilbert Cell. All input ports, X, Y, and Z, are differential and internally biased to midsupply, VPOS/2. The differential input impedance is 500 Ω up to 100 MHz, rolling off to 50 Ω at 2 GHz. All inputs can be driven in single-ended fashion and can be ac-coupled. In dc-coupled operation, the inputs can be biased to a common mode that is lower than VPOS/2. The bias current flowing out of the input pins to accommodate the lower common mode is subtracted from the 50 mA total available from the internal reference VPOS/2 at the VREF pin. Each input pin presents an equivalent 250 Ω dc resistance to VPOS/2. If all six input pins sit 1 V below VPOS/2, a total of 6 × 1 V/250 Ω = 24 mA must flow internally from VREF to the input pins. Calibration The simplified block diagram of the ADL5391 shows a main multiplier cell that receives inputs X and Y and a second multiplier cell in the feedback path around an integrating buffer. The inputs to this feedback multiplier are the difference of the output signal and the summing input, W − Z, and the internal scaling reference, U. At dc, the integrating buffer ensures that the output of both multipliers is exactly 0, therefore (W − Z)xU = XY, or W = XY/U + Z The small-signal bandwidth from the inputs X, Y, and Z to the output W is a single-pole response. The pole is inversely proportional to α. For α = 1 (GADJ floating), the bandwidth is about 2 GHz; for α > 1, the bandwidth is reduced; and for α < 1, the bandwidth is increased. (2) By using a feedback multiplier that is identical to the main multiplier, the scaling is traced back solely to U, which is an accurate reference generated on-chip. As is apparent in Equation 2, noise, drift, or distortion that is common to both multipliers is rejected to first-order because the feedback multiplier essentially compensates the impairments generated in the main multiplier. The scaling factor, U, is fixed by design to 1.12 V. However, the multiplier gain, α, can be adjusted by driving the GADJ pin with a voltage ranging from 0 V to 2 V. If left floating, then α = 1 or 0 dB, and the overall scaling is simply U = 1 V. For VGADJ = 0 V, the gain is lowered by approximately 4 dB; for VGADJ = 2 V, the gain is raised by approximately 6 dB. Figure 5 shows the relationship between α(V/V) and VGADJ. The dc offset of the ADL5391 is approximately 20 mV but changes over temperature and has variation from part to part (see Figure 4). It is generally not of concern unless the ADL5391 is operated down to dc (close to the point X = 0 V or Y = 0 V), where 0 V is expected on the output (W = 0 V). For example, when the ADL5391 is used as a VGA and a large amount of attenuation is needed, the maximum attenuation is determined by the input dc offset. Applying the proper voltage on the Z input removes the W offset. Calibration can be accomplished by making the appropriate cross plots and adjusting the Z input to remove the offset. Additionally, gain scaling can be adjusted by applying a dc voltage to the GADJ pin, as shown in Figure 5. BASIC CONNECTIONS Multiplier Connections The best ADL5391 performance is achieved when the X, Y, and Z inputs and W output are driven differentially; however, they can be driven single-ended. Single-ended-to-differential transformations (or differential-to-single-ended transformations) can be done using a balun or active components, such as the AD8313, the AD8132 (both with operation down to dc), or the AD8352 (for higher drive capability). If using the ADL5391 single-ended without ac coupling capacitors, the reference voltage of 2.5 V needs to be taken into account. Voltages above 2.5 V are positive voltages and voltages below 2.5 V are negative voltages. Care needs to be taken not to load the ADL5391 too heavily, the maximum reference current available is 50 mA. Rev. 0 | Page 10 of 16 ADL5391 The input and output impedance’s of the ADL5391 change over frequency, making it difficult to match over a broad frequency range (see Figure 15 and Figure 16). The evaluation board is matched for lower frequency operation, and the impedance change at higher frequencies causes the change in gain seen in Figure 6. If desired, the user of the ADL5391 can design a matching network to fit their application. Wideband Voltage-Controlled Amplifier/Amplitude Modulator Most of the data for the ADL5391 was collected by using it as a fast reacting analog VGA. Either X or Y inputs can be used for the RF input (and the other as the very fast analog control), because either input can be used from dc to 2 GHz. There is a linear relationship between the analog control and the output of the multiplier in the VGA mode. Figure 6 and Figure 7 show the dynamic range available in VGA mode (without optimizing the dc offsets). The speed of the ADL5391 in VGA mode allows it to be used as an amplitude modulator. Either or both inputs can have modulation or CW applied. AM modulation is achieved by feeding CW into X (or Y) and adding AM modulation to the Y (or X) input. Squaring and Frequency Doubling Amplitude domain squaring of an input signal, E, is achieved simply by connecting the X and Y inputs in parallel to produce an output of E2. The input can be single-ended, differential, or through a balun (frequency range and dynamic range can be limited if used single ended). The dc component of the output is related to the square of both the offset (OFST) and the signal input amplitude (E). The offset can be found in Figure 4 and is approximately 20 mV. The second harmonic output grows with the square of the input amplitude, and the signal bleedthrough grows proportionally with the input signal. For smaller signal amplitudes, the signal bleedthrough can be higher than the second harmonic component. As the input amplitude increases, the second harmonic component grows much faster than the signal bleedthrough and becomes the dominant signal at the output. If the X and Y inputs are driven too hard, third harmonic components will also increase. For best performance creating harmonics, the ADL5391 should be driven differentially. Figure 17 shows the performance of the ADL5391 when used as a harmonic generator (the evaluation board was used with R9 and R10 removed and R2 = 56.2 Ω). If dc operation is necessary, the ADL5391 can be driven single ended (without the dc blocks). The flatness of the response over a broad frequency range depends on the input/output match. The fundamental bleed through not only depends on the amount of power put into the device but also depends on matching the unused differential input/output to the same impedance as the used input/output. Figure 18 shows the performance of the ADL5391 when driven single ended (without ac coupling capacitors), and Figure 19 shows the schematic of the setup. A resistive input/output match were used to match the input from dc to 1 GHz and the output from dc to 2 GHz. Reactive matching can be used for more narrow frequency ranges. When matching the input/output of the ADL5391, care needs to be taken not to load the ADL5391 too heavily; the maximum reference current available is 50 mA. –15 When the input is a sine wave Esin(ωt), a signal squarer behaves as a frequency doubler, because –20 (3) –30 GAIN (dBm) Ideally, when used for squaring and frequency doubling, there is no component of the original signals on the output. Because of internal offsets, this is not the case. If Equation 3 were rewritten to include theses offsets, it could separate into three output terms (Equation 4). [Esin(ωt ) + OFST ]× [Esin(ωt ) + OFST ] = 2 E2 [cos(2ωt )] + 2Esin(ωt )OFST + ⎛⎜⎜ OFST 2 + E 2 2 ⎝ SECOND HARMONIC GAIN –25 2 [Esin(ωt )] = E (1 − cos(2ωt )) 2 2 –35 BLEEDTHRU GAIN –40 –45 –50 –55 THIRD HARMONIC GAIN –60 ⎞ ⎟⎟ ⎠ (4) –65 10 100 200 300 400 500 600 700 800 900 1000 FREQUENCY (MHz) Figure 17. ADL5391 Used as a Harmonic Generator where: The dc component is OFST2 + E2/2. The input signal bleedthrough is 2Esin(ωt)OFST. The input squared is E2/2[cos(2ωt)]. Rev. 0 | Page 11 of 16 06059-026 Matching the Input/Output ADL5391 0 be removed through calibration. Figure 20 shows the response of the ADL5391 as a square law detector, Figure 21 shows the error vs. the input power, and Figure 22 shows the configuration used. BLEEDTHRU GAIN –5 –10 SECOND HARMONIC GAIN –15 GAIN (dBm) –20 –25 0.7 –30 0.6 –35 –40 –45 0.5 THIRD HARMONIC GAIN VOUT (V) –50 –55 –65 200 300 400 500 600 700 800 900 1000 FREQUENCY (MHz) 0.2 Figure 18. Single-Ended (DC) ADL5391 Used as a Harmonic Generator 53Ω XM 74Ω 53Ω YIN 21Ω 74Ω XP WP YM WM YP 150Ω 0.1 10dB PAD 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 VIN (V rms)2 62Ω Figure 20. ADL5391 Used as Square Law Detector DC Output vs. Square of Input 200Ω 1.6 06059-028 XIN 5dB PAD 21Ω 0.3 06059-091 100 5dB PAD 1.4 Figure 19. Setup for Single-Ended Data 1.2 1.0 ERROR (dB) Use as a Detector The ADL5391 can be used as a square law detector. When amplitude squaring is performed, there are components of the multiplier output that correlate to the signal bleedthrough and second harmonic, as seen in Equation 4. However, as noted in the Squaring and Frequency Doubling section, there is also a dc component that is directly related to the offset and the squared input magnitude. If a signal is split and feed into the X and Y inputs and a low-pass filter were place on the output, the resulting dc signal would be directly related to the square of the input magnitude. The intercept of the response will shift slightly from part to part (and over temperature) with the offset, but this can 0.8 0.6 0.4 0.2 0 –0.2 –30 –25 –20 –15 –10 –5 0 PIN X (dBm) T3 TC1-1-13M R2 56.2Ω C18 0.1µF 11 XM 12 XP C4 0.1µF WM 5 T2 C20 0.1µF WP TC1-1-13M R1 56.2Ω 13 YM 14 YP R4 100Ω T1 R12 OPEN R5 24.9Ω 40µH 74µH 45nF 40µH 40nF 74µH J2 WM J1 WP 06059-093 J8 XP R6 24.9Ω 6 10 Figure 21. ADL5391Used as a Square Law Detector Error vs. Power Input C7 0.1µF J6 YP 5 06059-092 10 06059-027 –60 0.4 Figure 22. Schematic for ADL5391 Used as Square Law Detector Rev. 0 | Page 12 of 16 ADL5391 EVALUATION BOARD C16 OPEN C7 0.1µF YP J6 C6 OPEN YM J7 C19 OPEN XP_DC TP8 C4 0.1µF C1 T2 OPEN XM J9 C20 0.1µF TC1-1-13M XM_DC TP9 R8 OPEN ENBL J10 R20 0Ω R9 0Ω R16 OPEN YMNS 2 3 1 11 10 YPLS ZPLS 9 GADJ 8 R17 OPEN 14 XMNS COMM 7 WMNS 6 ADL5391 15 ENBL R13 OPEN R6 24.9Ω R4 100Ω VMID TP11 16 VMID WPLS COMM 1 VPOS VPOS VPOS 2 3 4 R18 0Ω R19 0Ω R11 OPEN ZP J5 ZM J4 C17 0.1µF ZM_DC TP4 ZMNS 13 XPLS C9 OPEN T4 TC1-1-13M R15 0Ω R1 56.2Ω C3 0.1µF ENBL_DC TP10 12 C15 OPEN C8 0.1µF ZP_DC TP5 R12 OPEN GADJ_DC TP3 GADJ J3 C14 0.1µF C5 OPEN WM_DC TP2 TC1-1-13M T1 WM J2 C2 0.1µF WP J1 5 R5 24.9Ω R7 OPEN WP_DC TP1 C13 OPEN SW1 C10 100pF C12 0.1µF TP TP COMM TP14 COMM TP12 C11 4.7µF 06059-025 XP J8 YM_DC TP7 R3 OPEN R2 OPEN T3 TC1-1-13M C18 0.1µF R14 0Ω R10 0Ω YP_DC TP6 VPOS TP13 06059-030 06059-031 Figure 23. ADL5391-EVALZ Evaluation Board Schematic Figure 25. Component Side Silkscreen of Evaluation Board Figure 24. Component Side Metal of Evaluation Board Rev. 0 | Page 13 of 16 ADL5391 Table 4. Evaluation Board Configuration Options Component J1, J5, J6, J8 J2, J4, J7, J9 J3 T1, T2, T3, T4 C2, C4, C7, C8, C14, C17, C18, C20 C1, C5, C6, C9, C13, C15, C16, C19 R9, R10, R14, R15, R18 R19, R20 R7, R13, R16, R17 C10 C12 C3 C11 R1 R2, R3, R12 R5, R6 R4 R8, R11 SW1 TP1, TP2, TP4, TP5, TP6, TP7, TP8, TP9 TP13 TP12, TP14 TP3, TP10, TP11 DUT Function SMA connectors for single-ended, high frequency operation. If J5 and J6 are used, R9, R10, R14, and R15 should be removed. R2 and R3 should also be populated to match the inputs. If used in broadband operation, C4, C7, C8, and C2 need to be replaced with 0 Ω resistors. SMA connectors for broadband differential operation. If these are used, baluns should be removed and jumped over using 0 Ω resistors, and C14, C15, C18, and C20 should be removed. SMA connector for connection to GADJ. Single-ended-to-differential transformation for high frequency ac operation. If dc operation is necessary, the baluns can be removed and jumped over using 0 Ω resistors. DC block capacitors. Part Number Default Value WP, ZP, YP, XP WM, ZM, YM, XM TC1-1-13M+ Mini-Circuits GADJ T3 and T4 are populated, but the Y and Z inputs are set up for dc operation. 0.1 μF, 0402 capacitors Not installed, dc block capacitors. Open, 0402 capacitors Snubbing resistors. Snubbing resistors. Snubbing resistors. Filter capacitor. Filter capacitor. Filter capacitor. Filter capacitor. Matching resistor. Matching resistors. Input impedance to X, Y, and Z inputs are the same. For the same frequency, R1, R2, and R3 should be the same. Matching resistor.s Matching resistor. Can be used for voltage divider or filtering. Enable switch: enable = 5 V, disable = 0 V. Green test loop. 0 Ω, 0402 resistors 0 Ω, 0603 resistors Open, 0402 resistors 100 pF, 0402 capacitor 0.1 μF, 0402 capacitor 0.1 μF, 0603 capacitor 4.7 μF, 3216 capacitor 56.2 Ω, 0603 resistor Open, 0603 resistors Red test loop. Black test loops. Yellow test loops. ADL5391. 24.9 Ω, 0402 resistors 100 Ω, 0603 resistor Open, 0603 resistors SW1 installed WP_DC, WM_DC, ZM_DC, ZP_DC, YP_DC, YM_DC, XP_DC, XM_DC VPOS COMM GADJ_DC, ENBL_DC, VMID ADL5391ACPZ Rev. 0 | Page 14 of 16 ADL5391 OUTLINE DIMENSIONS 3.00 BSC SQ 0.60 MAX 0.45 PIN 1 INDICATOR TOP VIEW 13 12 2.75 BSC SQ 0.80 MAX 0.65 TYP 12° MAX SEATING PLANE 16 PIN 1 INDICATOR *1.65 1.50 SQ 1.35 1 EXPOSED PAD 0.50 BSC 0.90 0.85 0.80 0.50 0.40 0.30 9 (BOTTOM VIEW) 4 8 5 0.25 MIN 1.50 REF 0.05 MAX 0.02 NOM 0.30 0.23 0.18 0.20 REF *COMPLIANT TO JEDEC STANDARDS MO-220-VEED-2 EXCEPT FOR EXPOSED PAD DIMENSION. Figure 26. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 3 mm × 3 mm Body, Very Thin Quad (CP-16-3) Dimensions shown in millimeters ORDERING GUIDE Model ADL5391ACPZ-R2 1 ADL5391ACPZ-R71 ADL5391ACPZ-WP1 ADL5391-EVALZ1 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 16-Lead LFCSP_VQ 16-Lead LFCSP_VQ 16-Lead LFCSP_VQ Evaluation Board Z = Pb-free part. Rev. 0 | Page 15 of 16 Package Option CP-16-3 CP-16-3 CP-16-3 Ordering Quantity 250 1,500 50 1 ADL5391 NOTES ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06059-0-7/06(0) T T Rev. 0 | Page 16 of 16

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