Ultralow Distortion Current Feedback Differential ADC Driver ADA4927-1/ADA4927-2 –FB 1 Differential gain configurations are easily realized using an external feedback network comprising four resistors. The current feedback architecture provides loop gain that is nearly independent of closed-loop gain, achieving wide bandwidth, low distortion, and low noise at higher gains and lower power consumption than comparable voltage feedback amplifiers. The ADA4927 is fabricated using the Analog Devices, Inc., silicongermanium complementary bipolar process, enabling very low levels of distortion with an input voltage noise of only 1.3 nV/√Hz. 07574-001 +IN1 –FB1 –VS1 –VS1 PD1 –OUT1 24 23 22 21 20 19 1 2 3 4 5 6 ADA4927-2 18 17 16 15 14 13 +OUT1 VOCM1 –VS2 –VS2 PD2 –OUT2 07574-002 –IN2 +FB2 +VS2 +VS2 VOCM2 +OUT2 7 8 9 10 11 12 –IN1 +FB1 +VS1 +VS1 –FB2 +IN2 Figure 2. –40 VOUT, dm = 2V p-p –50 –60 –70 –80 –90 –100 G=1 G = 10 G = 20 –110 –120 –130 1 10 100 FREQUENCY (MHz) 1k 07574-026 The ADA4927 is a low noise, ultralow distortion, high speed, current feedback differential amplifier that is an ideal choice for driving high performance ADCs with resolutions up to 16 bits from dc to 100 MHz. The output common-mode level can easily be matched to the required ADC input common-mode levels. The internal common-mode feedback loop provides exceptional output balance and suppression of even-order distortion products. +VS 8 9 VOCM +VS 7 10 +OUT +FB 4 +VS 5 11 –OUT –IN 3 Figure 1. SPURIOUS-FREE DYNAMIC RANGE (dBc) GENERAL DESCRIPTION 12 PD +IN 2 APPLICATIONS ADC drivers Single-ended-to-differential converters IF and baseband gain blocks Differential buffers Differential line drivers 13 –VS ADA4927-1 +VS 6 Extremely low harmonic distortion −105 dBc HD2 @ 10 MHz −91 dBc HD2 @ 70 MHz −87 dBc HD2 @ 100 MHz −103 dBc HD3 @ 10 MHz −98 dBc HD3 @ 70 MHz −89 dBc HD3 @ 100 MHz Better distortion at higher gains than VF amplifiers Low input voltage noise: 1.4 nV/√Hz High speed −3 dB bandwidth of 2.3 GHz 0.1 dB gain flatness: 150 MHz Slew rate: 5000 V/μs, 25% to 75% Fast 0.1% settling time: 10 ns Low input offset voltage: 0.3 mV typical Externally adjustable gain Stability and bandwidth controlled by feedback resistor Differential-to-differential or single-ended-to-differential operation Adjustable output common-mode voltage Wide supply operation: +5 V to ±5 V 14 –VS FUNCTIONAL BLOCK DIAGRAMS 16 –VS 15 –VS FEATURES Figure 3. Spurious-Free Dynamic Range vs. Frequency at Various Gains The low dc offset and excellent dynamic performance of the ADA4927 make it well suited for a wide variety of data acquisition and signal processing applications. The ADA4927-1 is available in a Pb-free, 3 mm × 3 mm 16-lead LFCSP, and the ADA4927-2 is available in a Pb-free, 4 mm × 4 mm 24-lead LFCSP. The pinouts are optimized to facilitate printed circuit board (PCB) layout and to minimize distortion. They are specified to operate over the −40°C to +105°C temperature range. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2008 Analog Devices, Inc. All rights reserved. ADA4927-1/ADA4927-2 TABLE OF CONTENTS Features .............................................................................................. 1 Definition of Terms .................................................................... 16 Applications ....................................................................................... 1 Applications Information .............................................................. 17 General Description ......................................................................... 1 Analyzing an Application Circuit ............................................ 17 Functional Block Diagrams ............................................................. 1 Setting the Closed-Loop Gain .................................................. 17 Revision History ............................................................................... 2 Estimating the Output Noise Voltage ...................................... 17 Specifications..................................................................................... 3 Impact of Mismatches in the Feedback Networks ................. 18 ±5 V Operation ............................................................................. 3 +5 V Operation ............................................................................. 5 Calculating the Input Impedance for an Application Circuit ............................................................... 18 Absolute Maximum Ratings............................................................ 7 Input Common-Mode Voltage Range ..................................... 20 Thermal Resistance ...................................................................... 7 Input and Output Capacitive AC Coupling ............................ 20 Maximum Power Dissipation ..................................................... 7 Setting the Output Common-Mode Voltage .......................... 20 ESD Caution .................................................................................. 7 Power Down ................................................................................ 21 Pin Configurations and Function Descriptions ........................... 8 Layout, Grounding, and Bypassing .............................................. 22 Typical Performance Characteristics ............................................. 9 High Performance ADC Driving ................................................. 23 Test Circuits ..................................................................................... 15 Outline Dimensions ....................................................................... 24 Theory of Operation ...................................................................... 16 Ordering Guide .......................................................................... 24 REVISION HISTORY 10/08—Revision 0: Initial Version Rev. 0 | Page 2 of 24 ADA4927-1/ADA4927-2 SPECIFICATIONS ±5 V OPERATION TA = 25°C, +VS = 5 V, −VS = − 5 V, VOCM = 0 V, RF = 301 Ω, RG = 301 Ω, RT = 56.2 Ω (when used), RL, dm = 1 kΩ, unless otherwise noted. All specifications refer to single-ended input and differential outputs, unless otherwise noted. Refer to Figure 46 for signal definitions. ±DIN to VOUT, dm Performance Table 1. Parameter DYNAMIC PERFORMANCE −3 dB Small Signal Bandwidth −3 dB Large Signal Bandwidth Bandwidth for 0.1 dB Flatness Slew Rate Settling Time to 0.1% Overdrive Recovery Time NOISE/HARMONIC PERFORMANCE Second Harmonic Third Harmonic IMD Voltage Noise (RTI) Input Current Noise Crosstalk INPUT CHARACTERISTICS Offset Voltage Conditions Min VOUT, dm = 0.1 V p-p VOUT, dm = 2.0 V p-p VOUT, dm = 0.1 V p-p, ADA4927-1 VOUT, dm = 0.1 V p-p, ADA4927-2 VOUT, dm = 2 V step, 25% to 75% VOUT, dm = 2 V step VIN = 0 V to 0.9 V step, G = 10 See Figure 45 for distortion test circuit VOUT, dm = 2 V p-p, 10 MHz VOUT, dm = 2 V p-p, 70 MHz VOUT, dm = 2 V p-p, 100 MHz VOUT, dm = 2 V p-p, 10 MHz VOUT, dm = 2 V p-p, 70 MHz VOUT, dm = 2 V p-p, 100 MHz f1 = 70 MHz, f2 = 70.1 MHz, VOUT, dm = 2 V p-p f1 = 140 MHz, f2 = 140.1 MHz, VOUT, dm = 2 V p-p f = 100 kHz, G = 28 f = 100 kHz, G = 28 f = 100 MHz, ADA4927-2 VIP = VIN = VOCM = 0 V tMIN to tMAX variation Input Bias Current −1.3 −15 tMIN to tMAX variation Input Offset Current Input Resistance Input Capacitance Input Common-Mode Voltage Range CMRR Open-Loop Transresistance OUTPUT CHARACTERISTICS Output Voltage Swing Linear Output Current Output Balance Error −10.5 Differential Common mode Differential ∆VOUT, dm/∆VIN, cm, ∆VIN, cm = ±1 V DC −3.5 −70 120 Each single-ended output, RF = RG = 10 kΩ −3.8 ∆VOUT, cm/∆VOUT, dm, ∆VOUT, dm = 1 V, 10 MHz, see Figure 44 for test circuit Rev. 0 | Page 3 of 24 Typ Max Unit 2300 1500 150 120 5000 10 10 MHz MHz MHz MHz V/μs ns ns −105 −91 −87 −103 −98 −89 −94 −85 1.4 14 −75 dBc dBc dBc dBc dBc dBc dBc dBc nV/√Hz pA/√Hz dB +0.3 ±1.5 +0.5 ±0.1 −0.6 14 120 0.5 +1.3 +15 +10.5 +3.5 −93 185 +3.8 65 −65 mV μV/°C μA μA/°C μA Ω kΩ pF V dB kΩ V mA p-p dB ADA4927-1/ADA4927-2 VOCM to VOUT, cm Performance Table 2. Parameter VOCM DYNAMIC PERFORMANCE Small Signal −3 dB Bandwidth Slew Rate Input Voltage Noise (RTI) VOCM INPUT CHARACTERISTICS Input Voltage Range Input Resistance Input Offset Voltage VOCM CMRR Gain Conditions Min VOUT, cm = 100 mV p-p VIN = −1.0 V to +1.0 V, 25% to 75% f = 100 kHz Typ Max 1300 1000 15 3.8 −10 −70 0.90 VOS, cm = VOUT, cm, VDIN+ = VDIN− = +VS/2 ΔVOUT, dm/ΔVOCM, ΔVOCM = ±1 V ΔVOUT, cm/ΔVOCM, ΔVOCM = ±1 V ±3.5 5.0 −2 −97 0.97 Unit MHz V/μs nV/√Hz 7.5 +5.2 1.00 V kΩ mV dB V/V General Performance Table 3. Parameter POWER SUPPLY Operating Range Quiescent Current per Amplifier Power Supply Rejection Ratio POWER-DOWN (PD) PD Input Voltage Turn-Off Time Turn-On Time PD Pin Bias Current per Amplifier Enabled Disabled Conditions Min Typ Max Unit 11.0 22.1 −89 V mA μA/°C mA dB <1.8 >3.2 15 400 V V μs ns 4.5 tMIN to tMAX variation Powered down ΔVOUT, dm/ΔVS, ΔVS = 1 V 20.0 ±9.0 2.4 −70 Powered down Enabled To 0.1% To 0.1% PD = 5 V PD = 0 V OPERATING TEMPERATURE RANGE Rev. 0 | Page 4 of 24 −2 −110 +2 −90 μA μA −40 +105 °C ADA4927-1/ADA4927-2 +5 V OPERATION TA = 25°C, +VS = 5 V, −VS = 0 V, VOCM = 2.5 V, RF = 301 Ω, RG = 301 Ω, RT = 56.2 Ω (when used), RL, dm = 1 kΩ, unless otherwise noted. All specifications refer to single-ended input and differential outputs, unless otherwise noted. Refer to Figure 46 for signal definitions. ±DIN to VOUT, dm Performance Table 4. Parameter DYNAMIC PERFORMANCE −3 dB Small Signal Bandwidth −3 dB Large Signal Bandwidth Bandwidth for 0.1 dB Flatness Slew Rate Settling Time to 0.1% Overdrive Recovery Time NOISE/HARMONIC PERFORMANCE Second Harmonic Third Harmonic IMD Voltage Noise (RTI) Input Current Noise Crosstalk INPUT CHARACTERISTICS Offset Voltage Conditions Min VOUT, dm = 0.1 V p-p VOUT, dm = 2.0 V p-p VOUT, dm = 0.1 V p-p, ADA4927-1 VOUT, dm = 0.1 V p-p, ADA4927-2 VOUT, dm = 2 V step, 25% to 75% VOUT, dm = 2 V step VIN = 0 V to 0.15 V step, G = 10 See Figure 45 for distortion test circuit VOUT, dm = 2 V p-p, 10 MHz VOUT, dm = 2 V p-p, 70 MHz VOUT, dm = 2 V p-p, 100 MHz VOUT, dm = 2 V p-p, 10 MHz VOUT, dm = 2 V p-p, 70 MHz VOUT, dm = 2 V p-p, 100 MHz f1 = 70 MHz, f2 = 70.1 MHz, VOUT, dm = 2 V p-p f1 = 140 MHz, f2 = 140.1 MHz, VOUT, dm = 2 V p-p f = 100 kHz, G = 28 f = 100 kHz, G = 28 f = 100 MHz, ADA4927-2 VIP = VIN = VOCM = 0 V tMIN to tMAX variation Input Bias Current −1.3 −30 tMIN to tMAX variation Input Offset Current Input Resistance Input Capacitance Input Common-Mode Voltage Range CMRR Open-Loop Transresistance OUTPUT CHARACTERISTICS Output Voltage Swing Linear Output Current Output Balance Error −10.5 Differential Common mode Differential ∆VOUT, dm/∆VIN, cm, ∆VIN, cm = ±1 V DC 1.3 −70 120 Each single-ended output +1.0 ∆VOUT, cm/∆VOUT, dm, ∆VOUT, dm = 1 V, 10 MHz, see Figure 44 for test circuit Rev. 0 | Page 5 of 24 Typ Max Unit 2000 1300 150 110 4200 10 10 MHz MHz MHz MHz V/μs ns ns −104 −91 −86 −95 −80 −76 −93 −84 1.4 19 −75 dBc dBc dBc dBc dBc dBc dBc dBc nV/√Hz pA/√Hz dB +0.3 ±1.5 −12 ±0.12 −0.8 14 120 0.5 +1.3 +4.0 +10.5 3.7 −96 185 +4.0 50 −65 mV μV/°C μA μA/°C μA Ω kΩ pF V dB kΩ V mA p-p dB ADA4927-1/ADA4927-2 VOCM to VOUT, cm Performance Table 5. Parameter VOCM DYNAMIC PERFORMANCE Small signal −3 dB Bandwidth Slew Rate Input Voltage Noise (RTI) VOCM INPUT CHARACTERISTICS Input Voltage Range Input Resistance Input Offset Voltage VOCM CMRR Gain Conditions Min VOUT, cm = 100 mV p-p VIN = 1.5 V to 3.5 V, 25% to 75% f = 100 kHz Typ Max 1300 1000 15 VOS, cm = VOUT, cm, VDIN+ = VDIN− = +VS/2 ΔVOUT, dm/ΔVOCM, ΔVOCM = ±1 V ΔVOUT, cm/ΔVOCM, ΔVOCM = ±1 V 3.8 −5.0 −70 0.90 1.5 to 3.5 5.0 +2.0 −100 0.97 Conditions Min Typ Unit MHz V/μs nV/√Hz 7.5 +10 1.00 V kΩ mV dB V/V General Performance Table 6. Parameter POWER SUPPLY Operating Range Quiescent Current per Amplifier Power Supply Rejection Ratio POWER-DOWN (PD) PD Input Voltage Turn-Off Time Turn-On Time PD Pin Bias Current per Amplifier Enabled Disabled Max Unit 11.0 21.6 −89 V mA μA/°C mA dB <1.7 >3.0 20 500 V V μs ns 4.5 tMIN to tMAX variation Powered down ΔVOUT, dm/ΔVS, ΔVS = 1 V 20 ±7.0 0.6 −70 Powered down Enabled PD = 5 V PD = 0 V OPERATING TEMPERATURE RANGE Rev. 0 | Page 6 of 24 −2 −105 +2 −95 μA μA −40 +105 °C ADA4927-1/ADA4927-2 ABSOLUTE MAXIMUM RATINGS Parameter Supply Voltage Power Dissipation Input Currents +IN, −IN, PD Storage Temperature Range Operating Temperature Range Lead Temperature (Soldering, 10 sec) Junction Temperature Rating 11 V See Figure 4 ±5 mA −65°C to +125°C −40°C to +105°C 300°C 150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE The power dissipated in the package (PD) is the sum of the quiescent power dissipation and the power dissipated in the package due to the load drive. The quiescent power is the voltage between the supply pins (VS) times the quiescent current (IS). The power dissipated due to the load drive depends upon the particular application. The power due to load drive is calculated by multiplying the load current by the associated voltage drop across the device. RMS voltages and currents must be used in these calculations. Airflow increases heat dissipation, effectively reducing θJA. In addition, more metal directly in contact with the package leads/ exposed pad from metal traces, throughholes, ground, and power planes reduces θJA. Figure 4 shows the maximum safe power dissipation in the package vs. the ambient temperature for the single 16-lead LFCSP (87°C/W) and the dual 24-lead LFCSP (47°C/W) on a JEDEC standard 4-layer board with the exposed pad soldered to a PCB pad that is connected to a solid plane. θJA is specified for the device (including exposed pad) soldered to a high thermal conductivity 2s2p circuit board, as described in EIA/JESD 51-7. 4.5 MAXIMUM POWER DISSIPATION (W) 4.0 Table 8. Package Type 16-Lead LFCSP (Exposed Pad) 24-Lead LFCSP (Exposed Pad) θJA 87 47 Unit °C/W °C/W MAXIMUM POWER DISSIPATION The maximum safe power dissipation in the ADA4927 package is limited by the associated rise in junction temperature (TJ) on the die. At approximately 150°C, which is the glass transition temperature, the plastic changes its properties. Even temporarily exceeding this temperature limit can change the stresses that the package exerts on the die, permanently shifting the parametric performance of the ADA4927. Exceeding a junction temperature of 150°C for an extended period can result in changes in the silicon devices, potentially causing failure. 3.5 3.0 ADA4927-2 2.5 2.0 ADA4927-1 1.5 1.0 0.5 0 –40 –20 0 20 40 60 80 AMBIENT TEMPERATURE (°C) Figure 4. Maximum Power Dissipation vs. Ambient Temperature for a 4-Layer Board ESD CAUTION Rev. 0 | Page 7 of 24 100 07574-003 Table 7. ADA4927-1/ADA4927-2 +IN1 –FB1 –VS1 –VS1 PD1 –OUT1 24 23 22 21 20 19 14 –VS 13 –VS 15 –VS 16 –VS PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 12 PD 11 –OUT –IN 3 TOP VIEW (Not to Scale) 10 +OUT 9 VOCM PIN 1 INDICATOR ADA4927-2 TOP VIEW (Not to Scale) 18 17 16 15 14 13 +OUT1 VOCM1 –VS2 –VS2 PD2 –OUT2 –IN2 +FB2 +VS2 +VS2 VOCM2 +OUT2 07574-005 NOTES 1. CONNECT THE EXPOSED PADDLE TO ANY PLANE BETWEEN AND INCLUDING +VS AND –VS. 1 2 3 4 5 6 7 8 9 10 11 12 +VS 8 +VS 5 +FB 4 +VS 7 ADA4927-1 +VS 6 +IN 2 –IN1 +FB1 +VS1 +VS1 –FB2 +IN2 NOTES 1. CONNECT THE EXPOSED PADDLE TO ANY PLANE BETWEEN AND INCLUDING +VS AND –V S. Figure 5. ADA4927-1 Pin Configuration 07574-006 PIN 1 INDICATOR –FB 1 Figure 6. ADA4927-2 Pin Configuration Table 9. ADA4927-1 Pin Function Descriptions Table 10. ADA4927-2 Pin Function Descriptions Pin No. 1 Mnemonic −FB 2 3 4 +IN −IN +FB 5 to 8 9 10 11 12 13 to 16 17 (EPAD) +VS VOCM +OUT −OUT PD −VS Exposed Pad (EPAD) Pin No. 1 2 3, 4 5 6 7 8 9, 10 11 12 13 14 15, 16 17 18 19 20 21, 22 23 24 25 (EPAD) Description Negative Output for Feedback Component Connection Positive Input Summing Node Negative Input Summing Node Positive Output for Feedback Component Connection Positive Supply Voltage Output Common-Mode Voltage Positive Output for Load Connection Negative Output for Load Connection Power-Down Pin Negative Supply Voltage Connect the exposed pad to any plane between and including +VS and −VS. Rev. 0 | Page 8 of 24 Mnemonic −IN1 +FB1 +VS1 −FB2 +IN2 −IN2 +FB2 +VS2 VOCM2 +OUT2 −OUT2 PD2 −VS2 VOCM1 +OUT1 −OUT1 PD1 −VS1 −FB1 +IN1 Exposed Pad (EPAD) Description Negative Input Summing Node 1 Positive Output Feedback 1 Positive Supply Voltage 1 Negative Output Feedback 2 Positive Input Summing Node 2 Negative Input Summing Node 2 Positive Output Feedback 2 Positive Supply Voltage 2 Output Common-Mode Voltage 2 Positive Output 2 Negative Output 2 Power-Down Pin 2 Negative Supply Voltage 2 Output Common-Mode Voltage 1 Positive Output 1 Negative Output 1 Power-Down Pin 1 Negative Supply Voltage 1 Negative Output Feedback 1 Positive Input Summing Node 1 Connect the exposed pad to any plane between and including +VS and −VS. ADA4927-1/ADA4927-2 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, +VS = 5 V, −VS = −5 V, VOCM = 0 V, RG = 301 Ω, RF = 301 Ω, RT = 56.2 Ω (when used), RL, dm = 1 kΩ, unless otherwise noted. Refer to Figure 43 for basic test setup. Refer to Figure 46 for signal definitions. 3 3 0 –3 –6 1 10 100 FREQUENCY (MHz) 1k 10k G = 1, RF = 301Ω G = 10, RF = 442Ω G = 20, RF = 604Ω –9 –12 Figure 7. Small Signal Frequency Response for Various Gains 1 CLOSED-LOOP GAIN (dB) –3 –6 –3 –6 VS = ±5V VS = ±2.5V 1k 10k –9 10 07574-008 100 FREQUENCY (MHz) 3 0 CLOSED-LOOP GAIN (dB) –3 –6 TA +25°C TA +105°C TA –40°C –9 1 10 –3 –6 TA +25°C TA +105°C TA –40°C –9 100 FREQUENCY (MHz) 1k 10k –12 07574-009 CLOSED-LOOP GAIN (dB) 10k VOUT, dm = 2V p-p VOUT, dm = 100mV p-p 0 –12 100 1k FREQUENCY (MHz) Figure 11. Large Signal Frequency Response for Various Supplies Figure 8. Small Signal Frequency Response for Various Supplies 3 10k 0 VS = ±5V VS = ±2.5V 10 1k VOUT, dm = 2V p-p 0 1 100 FREQUENCY (MHz) 3 VOUT, dm = 100mV p-p –9 10 Figure 10. Large Signal Frequency Response for Various Gains 3 CLOSED-LOOP GAIN (dB) –6 Figure 9. Small Signal Frequency Response for Various Temperatures 1 10 100 FREQUENCY (MHz) 1k 10k 07574-012 –12 G = 1, RF = 301Ω G = 10, RF = 442Ω G = 20, RF = 604Ω –3 07574-011 –9 0 07574-010 NORMALIZED CLOSED-LOOP GAIN (dB) VOUT, dm = 2V p-p 07574-007 NORMALIZED CLOSED-LOOP GAIN (dB) VOUT, dm = 100mV p-p Figure 12. Large Signal Frequency Response for Various Temperatures Rev. 0 | Page 9 of 24 ADA4927-1/ADA4927-2 3 3 VOUT, dm = 100mV p-p VOUT, dm = 2V p-p –3 –6 RL = 200Ω RL = 1kΩ –9 1 10 100 FREQUENCY (MHz) 1k 10k –12 3 VOUT, dm = 100mV p-p 100 FREQUENCY (MHz) 1k 10k VOUT, dm = 2V p-p –6 VOCM = –4V VOCM = –3.5V VOCM = 0V VOCM = +3.5V VOCM = +4V 1 10 100 FREQUENCY (MHz) –6 VOCM = –3.5V VOCM = 0V VOCM = +3.5V –9 1k 10k –12 1 10 100 FREQUENCY (MHz) 1k 10k Figure 17. Large Signal Frequency Response at Various VOCM Levels Figure 14. Small Signal Frequency Response at Various VOCM Levels 3 0.5 VOUT, dm = 100mV p-p VOUT, cm = 100mV p-p NORMALIZED CLOSED-LOOP GAIN (dB) 0.4 0.3 0.2 0.1 0 –0.1 –0.2 VS = ±5V, RL = 1kΩ VS = ±2.5V, RL = 1kΩ VS = ±5V, RL = 200Ω VS = ±2.5V, RL = 200Ω –0.4 1 10 100 FREQUENCY (MHz) 1k 0 –3 –6 Figure 15. 0.1 dB Flatness Small Signal Frequency Response for Various Loads and Supplies VOCM = 0V dc VOCM = +2.5V dc VOCM = +4.1V dc VOCM = –2.5V dc VOCM = –4.1V dc –9 –12 07574-015 –0.3 –0.5 –3 07574-017 CLOSED-LOOP GAIN (dB) –3 07574-014 CLOSED-LOOP GAIN (dB) 10 0 –9 NORMALIZED CLOSED-LOOP GAIN (dB) 1 Figure 16. Large Signal Frequency Response for Various Loads 0 –12 RL = 1kΩ RL = 200Ω –9 Figure 13. Small Signal Frequency Response for Various Loads 3 –6 1 10 100 FREQUENCY (MHz) 1k 5k 07574-018 –12 –3 07574-016 CLOSED-LOOP GAIN (dB) 0 07574-013 CLOSED-LOOP GAIN (dB) 0 Figure 18. VOCM Small Signal Frequency Response at Various DC Levels Rev. 0 | Page 10 of 24 ADA4927-1/ADA4927-2 –40 –40 VOUT, dm = 2V p-p VOUT, dm = 2V p-p HARMONIC DISTORTION (dBc) –50 –70 –80 –90 –100 HD2, HD3, HD2, HD3, –110 –120 1 10 100 FREQUENCY (MHz) –70 –80 –90 –100 –120 1k –130 Figure 19. Harmonic Distortion vs. Frequency at Various Loads 1k –70 –80 –90 –100 –120 VS = ±5V VS = ±5V VS = ±2.5V VS = ±2.5V 10 100 FREQUENCY (MHz) 1k Figure 20. Harmonic Distortion vs. Frequency at Various Supplies –70 –80 –90 –100 HD2, HD3, HD2, HD3, –110 –130 0 1 2 3 4 5 6 VOUT, dm (V p-p) 7 VS = ±5V VS = ±5V VS = ±2.5V VS = ±2.5V 8 9 Figure 23. Harmonic Distortion vs. VOUT, dm and Supply Voltage, f = 10 MHz –20 –40 VOUT, dm = 2V p-p VOUT, dm = 2V p-p –30 –50 HARMONIC DISTORTION (dBc) –40 –50 –60 –70 –80 –90 –100 0.6 0.8 1.0 1.2 07574-021 0.4 –60 HD2, 10MHz HD3, 10MHz –70 –80 –90 –100 –110 HD2, 10MHz HD3, 10MHz –110 –120 –1.2 –1.0 –0.8 –0.6 –0.4 –0.2 0 0.2 VOCM (V) –60 –120 07574-020 HD2, HD3, HD2, HD3, –110 –50 07574-023 HARMONIC DISTORTION (dBc) –60 1 VOUT, dm = 2V p-p –40 –50 HARMONIC DISTORTION (dBc) 10 100 FREQUENCY (MHz) –30 VOUT, dm = 2V p-p HARMONIC DISTORTION (dBc) 1 =1 =1 = 10 = 10 = 20 = 20 Figure 22. Harmonic Distortion vs. Frequency at Various Gains –40 –130 HD2, G HD3, G HD2, G HD3, G HD2, G HD3, G –110 –120 –4 –3 –2 –1 0 VOCM (V) 1 2 3 4 Figure 24. Harmonic Distortion vs. VOCM at 10 MHz, ±5 V Supplies Figure 21. Harmonic Distortion vs. VOCM at 10 MHz, ±2.5 V Supplies Rev. 0 | Page 11 of 24 07574-024 –130 RL = 1kΩ RL = 1kΩ RL = 200Ω RL = 200Ω –60 07574-022 –60 07574-019 HARMONIC DISTORTION (dBc) –50 ADA4927-1/ADA4927-2 20 –40 VS = ±2.5V VOUT, dm = 2V p-p NORMALIZED SPECTRUM (dBc) 0 –60 –70 –80 –90 –100 –120 –130 1 VOUT, dm = 2V p-p VOUT, dm = 2V p-p VOUT, dm = 1V p-p VOUT, dm = 1V p-p 10 100 FREQUENCY (MHz) –40 –60 –80 –100 1k –120 69.6 Figure 25. Harmonic Distortion vs. Frequency at Various VOUT, dm –50 –50 –60 –60 CROSSTALK (dB) –70 –80 –90 –100 G=1 G = 10 G = 20 –110 –120 70.3 70.4 70.5 10 100 FREQUENCY (MHz) INPUT AMP2 TO OUTPUT AMP1 INPUT AMP1 TO OUTPUT AMP2 –70 –80 –90 –100 –110 –120 –130 1k –140 0.1 07574-026 SPURIOUS-FREE DYNAMIC RANGE (dBc) 69.9 70.0 70.1 70.2 FREQUENCY (MHz) –40 VOUT, dm = 2V p-p 1 69.8 Figure 28. 70 MHz Intermodulation Distortion –40 –130 69.7 07574-028 HD2, HD3, HD2, HD3, –20 Figure 26. Spurious-Free Dynamic Range vs. Frequency at Various Gains 1 10 FREQUENCY (MHz) 100 1k 07574-029 –110 07574-025 HARMONIC DISTORTION (dBc) –50 Figure 29. Crosstalk vs. Frequency for ADA4927-2 –20 –40 RL, dm = 200Ω RL, dm = 200Ω –45 –30 –50 –40 PSRR (dB) –60 –65 –70 –75 –50 –60 –70 –80 1 10 100 FREQUENCY (MHz) 1k –90 1 10 100 FREQUENCY (MHz) Figure 30. PSRR vs. Frequency Figure 27. CMRR vs. Frequency Rev. 0 | Page 12 of 24 1k 07574-030 –90 VS = ±5V, –PSRR VS = ±5V, +PSRR –80 –85 07574-027 CMRR (dB) –55 ADA4927-1/ADA4927-2 1k –30 50 –50 –60 1 10 100 FREQUENCY (MHz) 1k Figure 31. Output Balance vs. Frequency –50 10 1 –150 0.1 10 CLOSED-LOOP OUTPUT IMPEDANCE (Ω) RETURN LOSS (dB) –30 –40 S11 S22 –60 10 100 FREQUENCY (MHz) 1k 30 10k 100k 1M 10M FREQUENCY (Hz) 100M –200 10G 1G 25 VOP, VS = ±5V VON, VS = ±5V VOP, VS = ±2.5V VON, VS = ±2.5V 20 15 10 5 0 –5 –10 0.1 07574-032 1 1k 35 RL, dm = 200Ω INPUT SINGLE-ENDED, 50Ω LOAD TERMINATION –10 OUTPUT DIFFERENTIAL, 100Ω SOURCE TERMINATION S11: COMMON-MODE-TO-COMMON-MODE S22: DIFFERENTIAL-TO-DIFFERENTIAL –20 –70 100 Figure 34. Open-Loop Transimpedance Magnitude and Phase vs. Frequency 0 –50 –100 PHASE 1 10 FREQUENCY (MHz) 100 1k 07574-035 –80 07574-031 –70 0 MAGNITUDE 100 Figure 35. Closed-Loop Output Impedance Magnitude vs. Frequency at Various Supplies, G = 1 Figure 32. Return Loss (S11, S12) vs. Frequency 10 100 VOLTAGE (V) 5 10 VOUT, dm 0 100 1k 10k 100k FREQUENCY (Hz) 1M 10M 100M –10 Figure 33. Voltage Noise Spectral Density, Referred to Input 0 10 20 30 40 50 60 TIME (ns) 70 80 Figure 36. Overdrive Recovery, G = 10 Rev. 0 | Page 13 of 24 90 100 07574-036 –5 07574-033 INPUT VOLTAGE NOISE (nV/ Hz) VIN × 10 1 10 07574-034 IMPEDANCE MAGNITUDE (kΩ) OUTPUT BALANCE (dB) –40 IMPEDANCE PHASE (Degrees) RL, dm = 200Ω ADA4927-1/ADA4927-2 1.0 40 30 20 10 0 –10 –20 –30 –40 –50 0 1 2 3 4 5 6 7 8 9 10 TIME (ns) 0 –0.5 –1.0 0 1 6 7 8 9 10 30 20 10 0 –10 –20 –30 –40 –50 1 2 3 4 5 6 7 8 9 10 9 10 0.5 0 –0.5 –1.0 –1.5 0.6 7 1.0 0.5 6 0.8 0.4 0.6 0.3 –0.1 –0.4 –0.2 –0.6 –0.3 INPUT 0 10 20 30 40 50 60 TIME (ns) 70 80 7 8 2.00 1.75 1.50 1.25 2 1 1.00 0 0.75 –1 –2 –4 –0.4 –1.0 6 0.50 –3 –5 –0.5 –6 –0.6 90 –7 07574-039 –0.8 5 3 PD VOLTAGE (V) 0 –0.2 4 4 ERROR (%) 0.1 0 3 5 0.2 ERROR 2 Figure 41. VOCM Large Signal Pulse Response 1.2 0.2 1 TIME (ns) Figure 38. VOCM Small Signal Pulse Response 0.4 0 0.25 PD VOUT, dm 0 –0.25 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 TIME (µs) Figure 42. PD Response Time Figure 39. Settling Time Rev. 0 | Page 14 of 24 OUTPUT VOLTAGE (V) 0 1.0 07574-041 COMMON-MODE OUTPUT VOLTAGE (mV) 40 07574-038 DIFFERENTIAL OUTPUT VOLTAGE (mV) 5 1.5 50 TIME (ns) INPUT SIGNAL (mV) 4 Figure 40. Large Signal Pulse Response 60 –1.2 –10 3 TIME (ns) Figure 37. Small Signal Pulse Response –60 2 07574-042 –60 0.5 07574-040 DIFFERENTIAL OUTPUT VOLTAGE (mV) 50 07574-037 DIFFERENTIAL OUTPUT VOLTAGE (mV) 60 ADA4927-1/ADA4927-2 TEST CIRCUITS 301Ω DC-COUPLED GENERATOR +5V 50Ω VIN 301Ω ADA4927 56.2Ω 1kΩ 301Ω 07574-043 0.1µF –5V 301Ω Figure 43. Equivalent Basic Test Circuit, G = 1 DIFFERENTIAL NETWORK ANALYZER INPUT NETWORK ANALYZER OUTPUT AC-COUPLED 301Ω 49.9Ω 50Ω +5V 50Ω 301Ω 56.2Ω VIN VOCM ADA4927 301Ω –5V 301Ω DIFFERENTIAL NETWORK ANALYZER INPUT 49.9Ω 50Ω 07574-044 0.1µF Figure 44. Test Circuit for Output Balance, CMRR 301Ω DC-COUPLED GENERATOR VIN +5V 0.1µF 301Ω LOW-PASS FILTER 56.2Ω VOCM ADA4927 25.5Ω 261Ω 0.1µF 301Ω 442Ω 200Ω 2:1 50Ω DUAL FILTER HP LP CT 442Ω 0.1µF –5V 301Ω Figure 45. Test Circuit for Distortion Measurements Rev. 0 | Page 15 of 24 07574-045 50Ω ADA4927-1/ADA4927-2 THEORY OF OPERATION Two feedback loops are employed to control the differential and common-mode output voltages. The differential feedback loops use a current feedback architecture with external resistors and control only the differential output voltage. The common-mode feedback loop is internal, uses voltage feedback, and controls only the common-mode output voltage. This architecture makes it easy to set the output common-mode level to any arbitrary value within the specified limits. The output common-mode voltage is forced, by the internal common-mode loop, to be equal to the voltage applied to the VOCM input. DEFINITION OF TERMS –FB +DIN RG RF +IN VOCM –DIN –OUT ADA4927 RG R F RL, dm VOUT, dm +OUT –IN +FB 07574-046 The ADA4927 differs from conventional operational amplifiers in that it has two outputs whose voltages move in opposite directions and an additional input, VOCM. Moreover, the ADA4927 uses a current feedback architecture. Like a traditional current feedback op amp, the ADA4927 relies on high open-loop transimpedance, T(s), and negative current feedback to force the outputs to the desired voltages. The ADA4927 behaves much like a standard current feedback op amp and facilitates singleended-to-differential conversions, common-mode level shifting, and amplifications of differential signals. Also, like a current feedback op amp, the ADA4927 has low input impedance summing nodes, which are actually emitter-follower outputs. The ADA4927 outputs are low impedance, and the closed-loop output impedances are equal to the open-loop output impedances divided by a factor of 1 + loop gain. Because it uses current feedback, the ADA4927 manifests a nominally constant feedback resistance, bandwidth product. In other words, the closedloop bandwidth and stability of the ADA4927 depend primarily on the feedback resistor value. The closed-loop gain equations for typical configurations are the same as those of comparable voltage feedback differential amplifiers. The chief difference is that the ADA4927 dynamic performance depends on the feedback resistor value rather than on the noise gain. Because of this, the elements used in the feedback loops must be resistive with values that ensure stability and sufficient bandwidth. Figure 46. Circuit Definitions Differential Voltage Differential voltage refers to the difference between two node voltages. For example, the output differential voltage (or equivalently, output differential-mode voltage) is defined as VOUT, dm = (V+OUT − V−OUT) where V+OUT and V−OUT refer to the voltages at the +OUT and −OUT terminals with respect to a common ground reference. Similarly, the differential input voltage is defined as VIN, dm = (+DIN − (−DIN)) Common-Mode Voltage Common-mode voltage refers to the average of two node voltages with respect to the local ground reference. The output common-mode voltage is defined as VOUT, cm = (V+OUT + V−OUT)/2 Balance Output balance is a measure of how close the differential signals are to being equal in amplitude and opposite in phase. Output balance is most easily determined by placing a well-matched resistor divider between the differential voltage nodes and comparing the magnitude of the signal at the divider midpoint with the magnitude of the differential signal (see Figure 44). By this definition, output balance is the magnitude of the output common-mode voltage divided by the magnitude of the output differential mode voltage. The internal common-mode feedback loop produces outputs that are highly balanced over a wide frequency range without requiring tightly matched external components. This results in differential outputs that are very close to the ideal of being identical in amplitude and are exactly 180° apart in phase. Rev. 0 | Page 16 of 24 Output Balance Error = ΔVOUT , cm ΔVOUT , dm ADA4927-1/ADA4927-2 APPLICATIONS INFORMATION ANALYZING AN APPLICATION CIRCUIT ESTIMATING THE OUTPUT NOISE VOLTAGE The ADA4927 uses high open-loop transimpedance and negative current feedback to control its differential output voltage in such a way as to minimize the differential error currents. The differential error currents are defined as the currents that flow in and out of the differential inputs labeled +IN and −IN (see Figure 46). For most purposes, these currents can be assumed to be zero. The voltage between the +IN and −IN inputs is internally bootstrapped to 0 V; therefore, the voltages at the amplifier inputs are equal, and external analysis can be carried out in a similar fashion to that of voltage feedback amplifiers. Similarly, the difference between the actual output commonmode voltage and the voltage applied to VOCM can also be assumed to be zero. Starting from these principles, any application circuit can be analyzed. The differential output noise of the ADA4927 can be estimated using the noise model in Figure 47. The input-referred noise voltage density, vnIN, is modeled as a differential input, and the noise currents, inIN− and inIN+, appear between each input and ground. The output voltage due to vnIN is obtained by multiplying vnIN by the noise gain, GN (defined in the GN equation). The noise currents are uncorrelated with the same mean-square value, and each produces an output voltage that is equal to the noise current multiplied by the associated feedback resistance. The noise voltage density at the VOCM pin is vnCM. When the feedback networks have the same feedback factor, as in most cases, the output noise due to vnCM is common mode. Each of the four resistors contributes (4kTRxx)1/2. The noise from the feedback resistors appears directly at the output, and the noise from each gain resistor appears at the output multiplied by RF/RG. Table 11 summarizes the input noise sources, the multiplication factors, and the output-referred noise density terms. SETTING THE CLOSED-LOOP GAIN Using the approach previously described, the differential gain of the circuit in Figure 46 can be determined by VIN , dm = RF RG RG1 VnRF1 RF1 inIN+ + inIN– This presumes that the input resistors (RG) and feedback resistors (RF) on each side are of equal value. VnIN ADA4927 VnOD VOCM VnRG2 RG2 RF2 VnCM VnRF2 07574-047 VOUT , dm VnRG1 Figure 47. Noise Model Table 11. Output Noise Voltage Density Calculations for Matched Feedback Networks Input Noise Contribution Differential Input Inverting Input Noninverting Input VOCM Input Gain Resistor, RG1 Gain Resistor, RG2 Feedback Resistor, RF1 Feedback Resistor, RF2 Input Noise Term vnIN inIN inIN vnCM vnRG1 vnRG2 vnRF1 vnRF2 Input Noise Voltage Density vnIN inIN × (RF2) inIN × (RF1) vnCM (4kTRG1)1/2 (4kTRG2)1/2 (4kTRF1)1/2 (4kTRF2)1/2 Rev. 0 | Page 17 of 24 Output Multiplication Factor GN 1 1 0 RF1/RG1 RF2/RG2 1 1 Differential Output Noise Voltage Density Term vnO1 = GN(vnIN) vnO2 = (inIN)(RF2) vnO3 = (inIN)(RF1) vnO4 = 0 vnO5 = (RF1/RG1)(4kTRG1)1/2 vnO6 = (RF2/RG2)(4kTRG2)1/2 vnO7 = (4kTRF1)1/2 vnO8 = (4kTRF2)1/2 ADA4927-1/ADA4927-2 Table 12. Differential Input, DC-Coupled Nominal Gain (dB) 0 20 26 RF (Ω) 301 442 604 RG (Ω) 301 44.2 30.1 RIN, dm (Ω) 602 88.4 60.2 Differential Output Noise Density (nV/√Hz) 8.0 21.8 37.9 Table 13. Single-Ended Ground-Referenced Input, DC-Coupled, RS = 50 Ω Nominal Gain (dB) 0 20 26 RG1 (Ω) 301 39.2 28 RT (Ω) 56.2 158 649 RIN, cm (Ω) 401 73.2 54.2 RG2 (Ω)1 328 77.2 74.4 Differential Output Noise Density (nV/√Hz) 8.1 18.6 29.1 RG2 = RG1 + (RS||RT). Similar to the case of a conventional op amp, the output noise voltage densities can be estimated by multiplying the inputreferred terms at +IN and −IN by the appropriate output factor, where: GN = β1 = 2 (β1 + β2 ) is the circuit noise gain. RG1 RG2 and β2 = are the feedback factors. RF1 + RG1 RF2 + RG2 When the feedback factors are matched, RF1/RG1 = RF2/RG2, β1 = β2 = β, and the noise gain becomes GN = 1 R =1+ F β RG Note that the output noise from VOCM goes to zero in this case. The total differential output noise density, vnOD, is the root-sumsquare of the individual output noise terms. v nOD = 8 2 ∑ vnOi i =1 Table 12 and Table 13 list several common gain settings, associated resistor values, input impedance, and output noise density for both balanced and unbalanced input configurations. IMPACT OF MISMATCHES IN THE FEEDBACK NETWORKS As previously mentioned, even if the external feedback networks (RF/RG) are mismatched, the internal common-mode feedback loop still forces the outputs to remain balanced. The amplitudes of the signals at each output remain equal and 180° out of phase. The input-to-output differential mode gain varies proportionately to the feedback mismatch, but the output balance is unaffected. The feedback loops are nominally matched to within 1% in most applications, and the output noise and offsets due to the VOCM input are negligible. If the loops are intentionally mismatched by a large amount, it is necessary to include the gain term from VOCM to VO, dm and account for the extra noise. For example, if β1 = 0.5 and β2 = 0.25, the gain from VOCM to VO, dm is 0.67. If the VOCM pin is set to 2.5 V, a differential offset voltage is present at the output of (2.5 V)(0.67) = 1.67 V. The differential output noise contribution is (15 nV/√Hz)(0.67) = 10 nV/√Hz. Both of these results are undesirable in most applications; therefore, it is best to use nominally matched feedback factors. Mismatched feedback networks also result in a degradation of the ability of the circuit to reject input common-mode signals, much the same as for a four-resistor difference amplifier made from a conventional op amp. As a practical summarization of the previous issues, resistors of 1% tolerance produce a worst-case input CMRR of approximately 40 dB, a worst-case differential-mode output offset of 25 mV due to a 2.5 V VOCM input, negligible VOCM noise contribution, and no significant degradation in output balance error. CALCULATING THE INPUT IMPEDANCE FOR AN APPLICATION CIRCUIT The effective input impedance of a circuit depends on whether the amplifier is being driven by a single-ended or differential signal source. For balanced differential input signals, as shown in Figure 48, the input impedance (RIN, dm) between the inputs (+DIN and −DIN) is simply RIN, dm = RG + RG = 2 × RG. RF +VS +DIN RG The gain from the VOCM pin to VO, dm is equal to –DIN 2(β1 − β2)/(β1 + β2) When β1 = β2, this term goes to zero and there is no differential output voltage due to the voltage on the VOCM input (including noise). The extreme case occurs when one loop is open and the other has 100% feedback; in this case, the gain from VOCM input to VO, dm is either +2 or −2, depending on which loop is closed. +IN VOCM RG ADA4927 VOUT, dm –IN –VS RF 07574-048 1 RF (Ω) 309 511 806 Figure 48. The ADA4927 Configured for Balanced (Differential) Inputs Rev. 0 | Page 18 of 24 ADA4927-1/ADA4927-2 RF For an unbalanced, single-ended input signal (see Figure 49), the input impedance is ⎛ ⎞ ⎜ ⎟ R G ⎟ =⎜ RF ⎜1− ⎟ ⎜ ⎟ ( ) 2 R R × + F ⎠ G ⎝ VS 2V p-p +VS RS RG 50Ω 348Ω VOCM RL VOUT, dm 348Ω RF –VS +VS RIN, SE ADA4927 RG RF RG 07574-050 RIN , SE 348Ω RIN 464Ω 348Ω Figure 50. Calculating Single-Ended Input Impedance RIN RL VOUT, dm 2. 07574-049 –VS RF To match the 50 Ω source resistance, the termination resistor, RT, is calculated using RT||464 Ω = 50 Ω. The closest standard 1% value for RT is 56.2 Ω. RF 348Ω +VS RIN 50Ω Figure 49. The ADA4927 with Unbalanced (Single-Ended) Input The input impedance of the circuit is effectively higher than it would be for a conventional op amp connected as an inverter because a fraction of the differential output voltage appears at the inputs as a common-mode signal, partially bootstrapping the voltage across the input resistor RG. The common-mode voltage at the amplifier input terminals can be easily determined by noting that the voltage at the inverting input is equal to the noninverting output voltage divided down by the voltage divider formed by RF and RG in the lower loop. This voltage is present at both input terminals due to negative voltage feedback and is in phase with the input signal, thus reducing the effective voltage across RG in the upper loop and partially bootstrapping RG. RS VS 2V p-p RG 50Ω RT 56.2Ω 348Ω VOCM ADA4927 RL VOUT, dm RG 348Ω –VS RF 07574-051 ADA4927 RG 348Ω Figure 51. Adding Termination Resistor RT 3. Terminating a Single-Ended Input This section deals with how to properly terminate a singleended input to the ADA4927 with a gain of 1, RF = 348 Ω, and RG = 348 Ω. An example using an input source with a terminated output voltage of 1 V p-p and a source resistance of 50 Ω illustrates the four simple steps that must be followed. Note that, because the terminated output voltage of the source is 1 V p-p, the open circuit output voltage of the source is 2 V p-p. The source shown in Figure 50 indicates this open-circuit voltage. 1. The input impedance must be calculated using the following formula: ⎛ ⎞ ⎛ ⎞ ⎜ ⎟ ⎜ ⎟ RG 348 ⎟=⎜ ⎟ = 464 Ω RIN = ⎜ ⎜ ⎟ ⎜ 348 ⎟ RF ⎜ 1 − 2 × ( R + R ) ⎟ ⎜ 1 − 2 × ( 348 + 348) ⎟ ⎝ ⎠ ⎝ G F ⎠ Rev. 0 | Page 19 of 24 It can be seen from Figure 51 that the effective RG in the upper feedback loop is now greater than the RG in the lower loop due to the addition of the termination resistors. To compensate for the imbalance of the gain resistors, a correction resistor (RTS) is added in series with RG in the lower loop. RTS is equal to the Thevenin equivalent of the source resistance RS and the termination resistance RT and is equal to RS||RT. RS VS 2V p-p 50Ω RTH RT 56.2Ω VTH 1.06V p-p 26.5Ω Figure 52. Calculating the Thevenin Equivalent 07574-052 VOCM ADA4927-1/ADA4927-2 RTS = RTH = RS||RT = 26.5 Ω. Note that VTH is greater than 1 V p-p, which was obtained with RT = 50 Ω. The modified circuit with the Thevenin equivalent (closest 1% value used for RTH) of the terminated source and RTS in the lower feedback loop is shown in Figure 53. RF RF 1V p-p RS VS 2V p-p RG 348Ω RTS 26.7Ω ADA4927 07574-053 348Ω Figure 53. Thevenin Equivalent and Matched Gain Resistors Figure 53 presents a tractable circuit with matched feedback loops that can be easily evaluated. It is useful to point out two effects that occur with a terminated input. The first is that the value of RG is increased in both loops, lowering the overall closed-loop gain. The second is that VTH is a little larger than 1 V p-p, as it is when RT = 50 Ω. These two effects have opposite impacts on the output voltage, and for large resistor values in the feedback loops (~1 kΩ), the effects essentially cancel each other out. For small RF and RG, or high gains, however, the diminished closed-loop gain is not canceled completely by the increased VTH. This can be seen by evaluating Figure 53. The desired differential output in this example is 1 V p-p because the terminated input signal is 1 V p-p and the closed-loop gain = 1. The actual differential output voltage, however, is equal to (1.06 V p-p)(348/374.7) = 0.984 V p-p. To obtain the desired output voltage of 1 V p-p, a final gain adjustment can be made by increasing RF without modifying any of the input circuitry. This is discussed in Step 4. The feedback resistor value is modified as a final gain adjustment to obtain the desired output voltage. To make the output voltage VOUT = 1 V p-p, RF must be calculated using the following formula: VTH VOUT, dm 1.01V p-p 348Ω INPUT COMMON-MODE VOLTAGE RANGE RF OUT , dm RL Figure 54. Terminated Single-Ended-to-Differential System with G = 1 –VS (Desired V ADA4927 357Ω RL VOUT, dm 348Ω RF = VOCM –VS RG 4. 348Ω RF VOCM RTS 26.7Ω RG RT 56.2Ω 07574-054 VTH 1.06V p-p RTH 50Ω RG 348Ω +VS 26.7Ω 357Ω +VS )(R G + RTS ) = (1V p − p)(374.7 Ω) = 35 1.06 V p − p The closest standard 1% values to 353 Ω are 348 Ω and 357 Ω. Choosing 357 Ω for RF gives a differential output voltage of 1.01 V p-p. The closed-loop bandwidth is diminished by a factor of approximately 348/357 from what it would be with RF = 348 Ω due to the inversely proportional relationship between RF and closed-loop gain that is characteristic of current feedback amplifiers. The final circuit is shown in Figure 54. The ADA4927 input common-mode range is centered between the two supply rails, in contrast to other ADC drivers with level-shifted input ranges, such as the ADA4937. The centered input commonmode range is best suited to ac-coupled, differential-to-differential, and dual supply applications. For operation with ±5 V supplies, the input common-mode range at the summing nodes of the amplifier is specified as −3.5 V to +3.5 V and is specified as +1.3 V to +3.7 V with a single +5 V supply. To avoid nonlinearities, the voltage swing at the +IN and −IN terminals must be confined to these ranges. INPUT AND OUTPUT CAPACITIVE AC COUPLING Input ac coupling capacitors can be inserted between the source and RG. This ac coupling blocks the flow of the dc commonmode feedback current and causes the ADA4927 dc input common-mode voltage to equal the dc output common-mode voltage. These ac coupling capacitors must be placed in both loops to keep the feedback factors matched. Output ac coupling capacitors can be placed in series between each output and its respective load. See Figure 58 for an example that uses input and output capacitive ac coupling. SETTING THE OUTPUT COMMON-MODE VOLTAGE The VOCM pin of the ADA4927 is internally biased with a voltage divider comprising two 10 kΩ resistors at a voltage approximately equal to the midsupply point, [(+VS) + (−VS)]/2. Because of this internal divider, the VOCM pin sources and sinks current, depending on the externally applied voltage and its associated source resistance. Relying on the internal bias results in an output common-mode voltage that is within about 100 mV of the expected value. In cases where accurate control of the output common-mode level is required, it is recommended that an external source or resistor divider be used with source resistance less than 100 Ω. The output common-mode offset listed in the Specifications section presumes that the VOCM input is driven by a low impedance voltage source. It is also possible to connect the VOCM input to a common-mode level (CML) output of an ADC; however, care must be taken to ensure that the output has sufficient drive capability. The input impedance of the VOCM pin is approximately 10 kΩ. If multiple ADA4927 devices share one ADC reference output, a buffer may be necessary to drive the parallel inputs. Rev. 0 | Page 20 of 24 ADA4927-1/ADA4927-2 POWER-DOWN Power-Down in Cold Applications The power-down feature can be used to reduce power consumption when a particular device is not in use and does not place the output in a high-Z state when asserted. The ADA4927 is generally enabled by pulling the power-down pin to the positive supply. See the Specifications tables for the specific voltages required to assert and deassert the powerdown feature. The power-down feature should not be used in applications in which the ambient temperature falls below 0°C. Contact sales for information regarding applications that require the powerdown feature to be used at ambient temperatures below 0°C. Rev. 0 | Page 21 of 24 ADA4927-1/ADA4927-2 LAYOUT, GROUNDING, AND BYPASSING As a high speed device, the ADA4927 is sensitive to the PCB environment in which it operates. Realizing its superior performance requires attention to the details of high speed PCB design. This section shows a detailed example of how the ADA4927-1 was addressed. Bypassed the power supply pins as close to the device as possible and directly to a nearby ground plane. Use high frequency ceramic chip capacitors. It is recommended that two parallel bypass capacitors (1000 pF and 0.1 μF) be used for each supply. The 1000 pF capacitor should be placed closer to the device. Further away, provide low frequency bulk bypassing, using 10 μF tantalum capacitors from each supply to ground. The first requirement is a solid ground plane that covers as much of the board area around the ADA4927-1 as possible. However, clear the area near the feedback resistors (RF), gain resistors (RG), and the input summing nodes (Pin 2 and Pin 3) of all ground and power planes (see Figure 55). Clearing the ground and power planes minimizes any stray capacitance at these nodes and prevents peaking of the response of the amplifier at high frequencies. Whereas ideal current feedback amplifiers are insensitive to summing node capacitance, real-world amplifiers can exhibit peaking due to excessive summing node capacitance. Make signal routing short and direct to avoid parasitic effects. Wherever complementary signals exist, provide a symmetrical layout to maximize balanced performance. When routing differential signals over a long distance, place PCB traces close together, and twist any differential wiring such that the loop area is minimized. Doing this reduces radiated energy and makes the circuit less susceptible to interference. 1.30 The thermal resistance, θJA, is specified for the device, including the exposed pad, soldered to a high thermal conductivity 4-layer circuit board, as described in EIA/JESD 51-7. 0.80 07574-056 1.30 0.80 07574-055 Figure 56. Recommended PCB Thermal Attach Pad Dimensions (Millimeters) Figure 55. Ground and Power Plane Voiding in Vicinity of RF AND RG 1.30 TOP METAL GROUND PLANE 0.30 PLATED VIA HOLE 07574-057 POWER PLANE BOTTOM METAL Figure 57. Cross-Section of 4-Layer PCB Showing Thermal Via Connection to Buried Ground Plane (Dimensions in Millimeters) Rev. 0 | Page 22 of 24 ADA4927-1/ADA4927-2 HIGH PERFORMANCE ADC DRIVING In this example, the signal generator has a 1 V p-p symmetric, ground-referenced bipolar output when terminated in 50 Ω. The ADA4927 is ideally suited for high gain, broadband accoupled and differential-to-differential applications on a single supply, though other applications are possible. Compared with voltage feedback amplifiers, the current feedback architecture provides superior distortion and bandwidth performance at high gains. This is because the ideal current feedback amplifier loop gain depends only on the feedback value and open-loop transimpedance, T(s). The VOCM pin of the ADA4927 is bypassed for noise reduction and left floating such that the internal divider sets the output common-mode voltage nominally at midsupply. Because the inputs are ac-coupled, no dc common-mode current flows in the feedback loops, and a nominal dc level of midsupply is present at the amplifier input terminals. Besides placing the amplifier inputs at their optimum levels, the ac coupling technique lightens the load on the amplifier and dissipates less power than applications with dc-coupled inputs. The circuit in Figure 58 shows a front-end connection for an ADA4927 driving an AD9445, 14-bit, 105 MSPS ADC, with ac coupling on the ADA4927 input and output. (The AD9445 achieves its optimum performance when driven differentially.) The ADA4927 eliminates the need for a transformer to drive the ADC and performs a single-ended-to-differential conversion and buffering of the driving signal. The output of the amplifier is ac-coupled to the ADC through a second-order, low-pass filter with a cutoff frequency of 100 MHz. This reduces the noise bandwidth of the amplifier and isolates the driver outputs from the ADC inputs. The ADA4927 is configured with a single 5 V supply and gain of 10 for a single-ended input to differential output. The 158 Ω termination resistor, in parallel with the single-ended input impedance of approximately 73.2 Ω, provides a 50 Ω termination for the source. The additional 38.3 Ω at the inverting input closely matches the parallel impedance of the 50 Ω source and the termination resistor driving the noninverting input. Because of the high gain, a few iterations of the termination technique described in the Terminating a Single-Ended Input section are required. Two objectives of the design are to make RF close to 500 Ω and obtain resistor values that are close to standard 1% values. The AD9445 is configured for a 2 V p-p full-scale input by connecting the SENSE pin to AGND, as shown in Figure 58. 5V (A) 3.3V (A) 3.3V (D) 511Ω 5V 50Ω 0.1µF 158Ω VOCM 0.1µF + ADA4927 0.1µF AVDD2 AVDD1 DRVDD AD9445 VIN– BUFFER T/H 24.3Ω 47pF ADC 24.3Ω 39.2Ω 0.1µF 30nH 0.1µF 30nH 38.3Ω 511Ω 14 VIN+ CLOCK/ TIMING REF AGND SENSE 07574-058 SIGNAL GENERATOR 39.2Ω Figure 58. ADA4927 Driving an AD9445 ADC with AC-Coupled Input and Output Rev. 0 | Page 23 of 24 ADA4927-1/ADA4927-2 OUTLINE DIMENSIONS 3.00 BSC SQ 0.60 MAX 0.45 13 16 12 (BOTTOM VIEW) 1 2.75 BSC SQ TOP VIEW EXPOSED PAD 9 0.50 BSC 0.30 0.23 0.18 4 5 0.25 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.05 MAX 0.02 NOM SEATING PLANE *1.45 1.30 SQ 1.15 1.50 REF 0.80 MAX 0.65 TYP 12° MAX 1.00 0.85 0.80 8 PIN 1 INDICATOR 0.20 REF 072208-A PIN 1 INDICATOR 0.50 0.40 0.30 *COMPLIANT TO JEDEC STANDARDS MO-220-VEED-2 EXCEPT FOR EXPOSED PAD DIMENSION. Figure 59. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 3 mm × 3 mm Body, Very Thin Quad (CP-16-2) Dimensions shown in millimeters 0.60 MAX 4.00 BSC SQ TOP VIEW 3.75 BSC SQ 0.50 BSC 0.50 0.40 0.30 1.00 0.85 0.80 12° MAX 0.80 MAX 0.65 TYP 0.30 0.23 0.18 SEATING PLANE PIN 1 INDICATOR 24 1 19 18 2.25 2.10 SQ 1.95 EXPOSED PAD (BOTTOM VIEW) 13 12 7 6 0.25 MIN 2.50 REF 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-2 072208-A PIN 1 INDICATOR 0.60 MAX Figure 60. 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 4 mm × 4 mm Body, Very Thin Quad (CP-24-1) Dimensions shown in millimeters ORDERING GUIDE Model ADA4927-1YCPZ-R2 1 ADA4927-1YCPZ-RL1 ADA4927-1YCPZ-R71 ADA4927-2YCPZ-R21 ADA4927-2YCPZ-RL1 ADA4927-2YCPZ-R71 1 Temperature Range −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C Package Description 16-Lead LFCSP_VQ 16-Lead LFCSP_VQ 16-Lead LFCSP_VQ 24-Lead LFCSP_VQ 24-Lead LFCSP_VQ 24-Lead LFCSP_VQ Z = RoHS Compliant Part. ©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07574-0-10/08(0) Rev. 0 | Page 24 of 24 Package Option CP-16-2 CP-16-2 CP-16-2 CP-24-1 CP-24-1 CP-24-1 Ordering Quantity 250 5,000 1,500 250 5,000 1,500 Branding H1M H1M H1M