ETC NTD6N40/D

NTD6N40
Preferred Device
Advance Information
Power MOSFET
6 Amps, 400 Volts
N–Channel DPAK
Designed for high voltage, high speed switching applications in
power supplies, converters, power motor controls and bridge circuits.
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6 AMPERES
400 VOLTS
RDS(on) = 1100 mΩ
Features
•
•
•
•
•
•
•
Higher Current Rating
Lower RDS(on)
Lower Capacitances
Lower Total Gate Charge
Tighter VSD Specifications
Avalanche Energy Specified
Industry Standard DPAK Surface Mount Package
N–Channel
D
Typical Applications
•
•
•
•
Switch Mode Power Supplies
PWM Motor Controls
Converters
Bridge Circuits
G
S
MARKING
DIAGRAMS
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Drain–Source Voltage
Drain–Gate Voltage (RGS = 1.0 MΩ)
Gate–Source Voltage
– Continuous
– Non–Repetitive (tp10 ms)
Drain – Continuous
– Continuous @ 100°C
– Single Pulse (tp10 µs)
Total Power Dissipation
Derate above 25°C
Total Power Dissipation @ TC = 25°C
when mounted with the minimum
recommended pad size
Operating and Storage Temperature
Range
Single Drain–to–Source Avalanche
Energy – Starting TJ = 25°C
(VDD = 100 Vdc, VGS = 10 Vdc,
IL = 6 A, L = 10 mH, RG = 25 Ω)
Thermal Resistance
– Junction–to–Case
– Junction–to–Ambient
– Junction–to–Ambient (Note 1.)
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from case for 10 seconds
Symbol
Value
Unit
VDSS
VDGR
400
Vdc
400
Vdc
Vdc
VGS
VGSM
ID
ID
IDM
PD
20
40
6.0
4.2
21
Adc
96
0.77
1.75
Watts
W/°C
W/°C
TJ, Tstg
–55 to
150
°C
EAS
180
mJ
RθJC
RθJA
RθJA
TL
1.30
100
71.4
°C/W
°C
260
This document contains information on a new product. Specifications and information
herein are subject to change without notice.
November, 2000 – Rev. 1
1 2
3
Y
WW
T
1
YWW
T
6N40
CASE 369A
DPAK
STYLE 2
= Year
= Work Week
= MOSFET
PIN ASSIGNMENT
Drain
Gate
Drain
Source
ORDERING INFORMATION
Device
1. When surface mounted to an FR4 board using the minimum recommended
pad size.
 Semiconductor Components Industries, LLC, 2000
4
Package
Shipping
NTD6N40
DPAK
75 Units/Rail
NTD6N40–1
DPAK
75 Units/Rail
NTD6N40T4
DPAK
2500 Tape & Reel
Preferred devices are recommended choices for future use
and best overall value.
Publication Order Number:
NTD6N40/D
NTD6N40
ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
Unit
400
–
–
500
–
–
–
–
–
–
10
100
–
–
–
–
100
100
2.0
–
2.7
6.0
4.0
–
mV/°C
–
900
1100
mOhm
–
–
–
–
7.9
6.9
gFS
2.0
4.4
–
mhos
Ciss
–
515
720
pF
Coss
–
185
260
Crss
–
15
30
td(on)
–
7.0
10
tr
–
11
20
td(off)
–
19
40
OFF CHARACTERISTICS
Drain–to–Source Breakdown Voltage
(VGS = 0 Vdc, ID = 0.25 mAdc)
Temperature Coefficient (Positive)
V(BR)DSS
Zero Gate Voltage Collector Current
(VDS = 400 Vdc, VGS = 0 Vdc)
(VDS = 400 Vdc, VGS = 0 Vdc, TJ = 125°C)
Vdc
µAdc
IDSS
Gate–Body Leakage Current (VGS = ±20 Vdc, VDS = 0)
IGSS(f)
IGSS(r)
mV/°C
nAdc
ON CHARACTERISTICS (Note 2.)
Gate Threshold Voltage
ID = 0.25 mA, VDS = VGS
Temperature Coefficient (Negative)
VGS(th)
Static Drain–to–Source On–Resistance (VGS = 10 Vdc, ID = 3 Adc)
RDS(on)
Drain–to–Source On–Voltage
(VGS = 10 Vdc, ID = 6 Adc)
(VGS = 10 Vdc, ID = 3 Adc, TJ = 125°C)
VDS(on)
Forward Transconductance (VDS = 15 Vdc, ID = 3 Adc)
Vdc
Vdc
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
(VDS = 25 Vd
Vdc, VGS = 0 Vdc,
Vd
f = 1.0 MHz)
Transfer Capacitance
SWITCHING CHARACTERISTICS (Note 3.)
Turn–On Delay Time
Rise Time
Turn–Off Delay Time
(VDD = 200 Vdc, ID = 6 Adc,
VGS = 10 Vdc,
Vdc
RG = 9.1 Ω)
Fall Time
Gate Charge
(VDS = 320 Vdc, ID = 6 Adc,
VGS = 10 Vdc)
tf
–
10
20
QT
–
9.5
19
Q1
–
2.0
–
Q2
–
3.0
–
Q3
–
6.0
–
–
–
0.9
0.8
1.0
–
trr
–
270
–
ta
–
110
–
tb
–
160
–
QRR
–
1.6
–
ns
nC
SOURCE–DRAIN DIODE CHARACTERISTICS
Forward On–Voltage (Note 2.)
VSD
(IS = 6 Adc, VGS = 0 Vdc)
(IS = 6 Adc, VGS = 0 Vdc, TJ = 125°C)
Reverse Recovery Time
(IS = 6 Adc
Adc, VGS = 0 Vdc,
Vdc
diS/dt = 100 A/µs)
Reverse Recovery Stored
Charge
2. Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.
3. Switching characteristics are independent of operating junction temperature.
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2
Vdc
ns
µC
NTD6N40
PACKAGE DIMENSIONS
DPAK
CASE 369A–13
ISSUE AA
C
B
V
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
SEATING
PLANE
–T–
E
R
4
Z
A
S
1
2
3
U
K
F
J
L
H
D
G
2 PL
0.13 (0.005)
M
T
DIM
A
B
C
D
E
F
G
H
J
K
L
R
S
U
V
Z
INCHES
MIN
MAX
0.235
0.250
0.250
0.265
0.086
0.094
0.027
0.035
0.033
0.040
0.037
0.047
0.180 BSC
0.034
0.040
0.018
0.023
0.102
0.114
0.090 BSC
0.175
0.215
0.020
0.050
0.020
--0.030
0.050
0.138
---
STYLE 2:
PIN 1.
2.
3.
4.
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3
GATE
DRAIN
SOURCE
DRAIN
MILLIMETERS
MIN
MAX
5.97
6.35
6.35
6.73
2.19
2.38
0.69
0.88
0.84
1.01
0.94
1.19
4.58 BSC
0.87
1.01
0.46
0.58
2.60
2.89
2.29 BSC
4.45
5.46
0.51
1.27
0.51
--0.77
1.27
3.51
---
NTD6N40
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
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4
NTD6N40/D