AD ADP3307

a
High Accuracy anyCAP™
100 mA Low Dropout Linear Regulator
ADP3307
FEATURES
0.8% Accuracy Over Line and Load Regulations @ +258C
Ultralow Dropout Voltage: 120 mV Typical @ 100 mA
Requires only CO = 0.47 mF for Stability
anyCAP = Stable with All Types of Output Capacitors
(Including MLCC)
Current and Thermal Limiting
Low Noise
Dropout Detector
Low Shutdown Current: 1 mA
3.0 V to 12 V Supply Range
–208C to +858C Ambient Temperature Range
Several Fixed Voltage Options
Ultrasmall SOT-23-6 (RT-6) Package
Excellent Line and Load Regulations
APPLICATIONS
Cellular Telephones
Notebook, Palmtop Computers
Battery Powered Systems
PCMCIA Regulator
Bar Code Scanners
Camcorders, Cameras
FUNCTIONAL BLOCK DIAGRAM
ADP3307
Q1
IN
R1
THERMAL
PROTECTION
ERR
OUT
CC
NR
Q2
DRIVER
GM
R2
SD
BANDGAP
REF
GND
NR
ADP3307-3.3
VIN
IN
OUT
C1 +
0.47mF –
ERR
R1
330kV
EOUT
VOUT = +3.3V
C2
0.47mF
ON
OFF
SD
GND
Figure 1. Typical Application Circuit
GENERAL DESCRIPTION
The ADP3307 is a member of the ADP330x family of precision
low dropout anyCAP voltage regulators. The ADP3307 stands
out from the conventional LDOs with a novel architecture and
an enhanced process. Its patented design requires only a 0.47 µF
output capacitor for stability. This device is stable with any type
of capacitor regardless of its ESR (Equivalent Series Resistance)
value, including ceramic types (MLCC) for space restricted
applications. The ADP3307 achieves exceptional accuracy of
± 0.8% at room temperature and ± 1.4% overall accuracy over
temperature, line and load regulations. The dropout voltage of
the ADP3307 is only 120 mV (typical) at 100 mA.
lose regulation or when the short circuit or thermal overload
protection is activated. Other features include shutdown and
optional noise reduction capabilities. The ADP330x anyCAP
LDO family offers a wide range of output voltages and output
current levels from 50 mA to 300 mA:
ADP3300 (50 mA, SOT-6)
ADP3307 (100 mA, SOT)
ADP3301 (100 mA, SO-8)
ADP3302 (100 mA, Dual Output)
ADP3303 (200 mA)
ADP3306 (300 mA)
The ADP3307 operates with a wide input voltage range from
3.0 V to 12 V and delivers a load current in excess of 100 mA.
It features an error flag that signals when the device is about to
anyCAP is a trademark of Analog Devices, Inc.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1997
(@ T = –208C to +858C, V
ADP3307–SPECIFICATIONS
otherwise noted) The following specifications apply to all voltage options.
A
IN
1
= 7 V, CIN = 0.47 mF, COUT = 0.47 mF, unless
Parameter
Symbol
Conditions
Min
OUTPUT VOLTAGE ACCURACY
VOUT
VIN = VOUTNOM + 0.3 V to 12 V
IL = 0.1 mA to 100 mA
TA = +25°C
VIN = VOUTNOM + 0.3 V to 12 V
IL = 0.1 mA to 100 mA
Typ
Max
Units
–0.8
+0.8
%
–1.4
+1.4
%
∆V O
∆V IN
VIN = VOUTNOM + 0.3 V to 12 V
TA = +25°C
0.02
mV/V
∆V O
∆I L
IL = 0.1 mA to 100 mA
TA = +25°C
0.06
mV/mA
GROUND CURRENT
IGND
IL = 100 mA
IL = 0.1 mA
0.76
0.19
2.0
0.3
mA
mA
GROUND CURRENT IN DROPOUT
IGND
VIN = 2.5 V
IL = 0.1 mA
0.6
1.2
mA
VOUT = 98% of VOUTNOM
IL = 100 mA
IL = 10 mA
IL = 1 mA
0.126
0.025
0.004
0.22
0.07
0.015
V
V
V
0.75
0.75
0.3
V
V
1
22
µA
µA
0.005
1
µA
0.01
3
µA
LINE REGULATION
LOAD REGULATION
DROPOUT VOLTAGE
SHUTDOWN THRESHOLD
SHUTDOWN PIN INPUT CURRENT
VDROP
VTHSD
ISDIN
GROUND CURRENT IN SHUTDOWN IQ
MODE
ON
OFF
2.0
0 < VSD, < 5 V
5 < VSD ≤ 12 V @ VIN = 12 V
VSD = 0 V, VIN = 12 V
TA = +25°C
VSD = 0 V, VIN = 12 V
TA = +85°C
OUTPUT CURRENT IN SHUTDOWN
MODE
IOSD
TA = +25°C @ VIN = 12 V
TA = +85°C @ VIN = 12 V
2
4
µA
µA
ERROR PIN OUTPUT LEAKAGE
IEL
VEO = 5 V
13
µA
ERROR PIN OUTPUT
“LOW” VOLTAGE
VEOL
ISINK = 400 µA
0.12
0.3
V
PEAK LOAD CURRENT
ILDPK
VIN = VOUTNOM + 1 V
170
mA
OUTPUT NOISE @ 3.3 V OUTPUT
VNOISE
f = 10 Hz–100 kHz
CNR = 0
CNR = 10 nF, CL = 10 µF
100
30
µV rms
µV rms
NOTES
Ambient temperature of +85°C corresponds to a junction temperature of 125°C under typical full load test conditions.
1
Specifications subject to change without notice.
–2–
REV. 0
ADP3307
ABSOLUTE MAXIMUM RATINGS*
PIN FUNCTION DESCRIPTIONS
Input Supply Voltage . . . . . . . . . . . . . . . . . . . –0.3 V to +16 V
Shutdown Input Voltage . . . . . . . . . . . . . . . . –0.3 V to +16 V
Error Flag Output Voltage . . . . . . . . . . . . . . . –0.3 V to +16 V
Noise Bypass Pin Voltage . . . . . . . . . . . . . . . . –0.3 V to +5 V
Power Dissipation . . . . . . . . . . . . . . . . . . . . Internally Limited
Operating Ambient Temperature Range . . . –55°C to +125°C
Operating Junction Temperature Range . . . –55°C to +125°C
θJA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230°C/W
θJC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92°C/W
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature Range (Soldering 10 s) . . . . . . . . . +300°C
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
*This is a stress rating only; operation beyond these limits can cause the device to
be permanently damaged.
ORDERING GUIDE
Model
Output
Voltage
Package
Option
Marking
Code
ADP3307ART-2.7
ADP3307ART-3
ADP3307ART-3.2
ADP3307ART-3.3
2.7 V
3.0 V
3.2 V
3.3 V
RT-6
RT-6
RT-6
RT-6
LTC
LUC
LVC
LWC
Pin
Name
Function
1
2
GND
NR
3
SD
4
OUT
5
6
IN
ERR
Ground Pin.
Noise Reduction Pin. Used for further reduction of the output noise. (See text for details.)
No connection if not used.
Active Low Shutdown Pin. Connect to ground
to disable the regulator output. When shutdown is not used, this pin should be connected to the input pin.
Output of the Regulator, fixed 2.7 V, 3.0 V,
3.2 V or 3.3 V output voltage. Bypass to
ground with a 0.47 µF or larger capacitor.
Regulator Input.
Open Collector Output that goes low to indicate that the output is about to go out of
regulation.
PIN CONFIGURATION
GND 1
ADP3307
6 ERR
NR 2
5 IN
TOP VIEW
SD 3 (Not to Scale) 4 OUT
Contact the factory for the availability of other output voltage options.
Other Members of anyCAP Family 1
Model
Output
Current
Package
Options2
ADP3300
ADP3301
ADP3302
ADP3303
ADP3306
50 mA
100 mA
100 mA
200 mA
300 mA
SOT-23-6
SO-8
SO-8
SO-8
SO-8, TSSOP-14
Comments
High Accuracy
High Accuracy
Dual Output
High Accuracy
High Accuracy,
High Current
NOTES
1
See individual data sheets for detailed ordering information.
2
SO = Small Outline, SOT-23 = Surface Mount, TSSOP = Thin Shrink Small
Outline.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADP3307 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
REV. 0
–3–
WARNING!
ESD SENSITIVE DEVICE
ADP3307–Typical Performance Characteristics
3.202
3.202
IL = 0mA
3.199
IL = 50mA
3.198
3.197
GROUND CURRENT – mA
OUTPUT VOLTAGE – Volts
IL = 10mA
3.200
VOUT = 3.2V
IL = 0
VOUT = 3.2V
VIN = 7V
3.201
3.201
OUTPUT VOLTAGE – Volts
800
VOUT = 3.2V
3.200
3.199
3.198
3.197
640
480
320
160
3.196
3.196
IL = 100mA
3.195
3.3
3.195
4
5
6 7 8 9 10 11 12 13 14
INPUT VOLTAGE – Volts
Figure 2. Line Regulation Output
Voltage vs. Supply Voltage
0
600
450
IL = 0 TO 100mA
300
1000
IL = 0
0.0
–0.1
IL = 50mA
–0.2
IL = 100mA
–0.3
0
25
50
75
OUTPUT LOAD – mA
100
–0.4
–45 –25
–5
48
24
25
50
75
OUTPUT LOAD – mA
Figure 8. Dropout Voltage vs.
Output Current
100
200
–5
15
35
55 75
95
TEMPERATURE – 8C
115 135
VIN
4
3
2
1
0
0
400
8.0
VOUT = 3.2V
RL = 32V
INPUT/OUTPUT VOLTAGE – Volts
INPUT/OUTPUT VOLTAGE – Volts
72
600
Figure 7. Quiescent Current vs.
Temperature
5
96
800
0
–25
15 35 55 75 95 115 135
TEMPERATURE – 8C
Figure 6. Output Voltage Variation %
vs. Temperature
120
1.2 2.4 3.6 4.8 6.0 7.2 8.4 9.6 10.8 12.0
INPUT VOLTAGE – Volts
Figure 4. Quiescent Current vs. Supply Voltage—3.2 V (Both Outputs)
GROUND CURRENT – mA
OUTPUT VOLTAGE – %
GROUND CURRENT – mA
90 100
0.1
Figure 5. Ground Current vs. Load
Current
INPUT/OUTPUT VOLTAGE – mV
30 40 50 60 70 80
OUTPUT LOAD – mA
0.2
750
0
10 20
Figure 3. Output Voltage vs. Load
Current Up to 100 mA
900
150
0
0
0
1
2
3
4
3
2
INPUT VOLTAGE – Volts
1
0
Figure 9. Power-Up/Power-Down
–4–
7.0
6.0
5.0
4.0
VOUT
3.0
VSD = VIN
CL = 0.47mF
RL = 32V
VOUT = 3.2V
2.0
1.0
0
0
20 40 60
80 100 120 140 160 180 200
TIME – ms
Figure 10. Power-Up Overshoot
REV. 0
ADP3307
3.220
3.220
3.220
VOUT = 3.2V
3.210
3.200
3.200
3.190
3.190
RL = 32V
CL = 0.47mF
3.180
VIN
3.180
VIN
7.0
7.0
40 80 120 160 200 240 280 320 360 400
TIME – ms
Figure 11. Line Transient Response
100
mA
7.5
0
3.200
3.190
RL = 3.2kV
CL = 0.47mF
3.180
7.5
10
20 40 60
0
0
80 100 120 140 160 180 200
TIME – ms
Figure 12. Line Transient Response
200
300
TIME – ms
500
400
4
VOUT = 3.2V
CL = 4.7mF
CL = 0.47mF
300
mA
3.210
VOLTS
100
Figure 13. Load Transient
3.220
3.200
200
IOUT
3.2V
2
VOLTS
3.190
0
3.180
VOLTS
4
mA
100
10
VOUT = 3.2V
VOUT
200
300
TIME – ms
400
0 0.5
500
Figure 14. Load Transient
1 1.5
2 2.5 3 3.5
TIME – sec
0
VOUT = 3.2V
RL = 32V
CL = 0.47mF
2
1
0
3
5
–20
–30
b
–40
–50
d
a
–60
c
–70 b d
–80
VSD
0
4 4.5
VOUT = 3.3V
a. 0.47mF, RL = 33kV
b. 0.47mF, RL = 33V
c. 10mF, RL = 33kV
d. 10mF, RL = 33V
–10
RIPPLE REJECTION – dB
3
–90
0
10
20
30
TIME – ms
40
Figure 17. Turn Off
REV. 0
VSD
3V
0
20
50
–100
a c
10
100
100k
1k
10k
FREQUENCY – Hz
1M
10M
Figure 18. Power Supply Ripple
Rejection
–5–
40
60
TIME – ms
80
100
Figure 16. Turn On
Figure 15. Short Circuit Current
4
3.2V
VOUT = 3.2V
RL = 32V
0
VOLTAGE NOISE SPECTRAL DENSITY – mV Hz
100
CL = 4.7mF
1
0
3
2
0
0
VOUT
3
100
VOLTS
VOUT = 3.2V
CL = 0.47mF
3.210
VOLTS
3.210
VOLTS
VOLTS
VOUT = 3.2V
10
0.47mF BYPASS
PIN 5 TO PIN 1
VOUT = 5V, CL = 0.47mF
IL = 1mA, CNR = 0
1
VOUT = 3.3V, CL = 0.47mF
IL = 1mA, CNR = 0
0.1 VOUT = 2.7– 5.0V, CL = 0.47mF
IL = 1mA, CNR = 10nF
0.01
100
VOUT = 2.7– 5.0V, CL = 4.7mF
IL = 1mA, CNR = 10nF
1k
10k
FREQUENCY – Hz
100k
Figure 19. Output Noise Density
ADP3307
This is no longer true with the ADP3307 anyCAP LDO. It can
be used with virtually any good quality capacitor, with no constraint on the minimum ESR. The innovative design allows the
circuit to be stable with just a small 0.47 µF capacitor on the
output. Additional advantages of the design scheme include
superior line noise rejection and very high regulator gain that
lead to excellent line and load regulation. An impressive ± 1.4%
accuracy is guaranteed over line, load and temperature.
THEORY OF OPERATION
The ADP3307 anyCAP LDO uses a single control loop for
regulation and reference functions. The output voltage is sensed
by a resistive voltage divider consisting of R1 and R2 which is
varied to provide the available output voltage option. Feedback
is taken from this network by way of a series diode (D1) and a
second resistor divider (R3 and R4) to the input of an amplifier.
INPUT
OUTPUT
Additional features of the circuit include current limit, thermal
shutdown and noise reduction. Compared to the standard solutions that give warning after the output has lost regulation, the
ADP3307 provides improved system performance by enabling
the ERR pin to give warning before the device loses regulation.
COMPENSATION ATTENUATION R1
CAPACITOR
(VBANDGAP/VOUT)
Q1
NONINVERTING
WIDEBAND
DRIVER
GM
R3
PTAT
VOS
D1
(a)
R4
ADP3307
PTAT
CURRENT
RLOAD
As the chip’s temperature rises above 165°C, the circuit activates a soft thermal shutdown, indicated by a signal low on the
ERR pin, to reduce the current to a safe level.
R2
CLOAD
To reduce the noise gain of the loop, the node of the main divider network (a) is made available at the noise reduction (NR)
pin which can be bypassed with a small capacitor (10 nF–100 nF).
GND
Figure 20. Functional Block Diagram
A very high gain error amplifier is used to control this loop. The
amplifier is constructed in such a way that at equilibrium it
produces a large, temperature proportional input “offset voltage” that is repeatable and very well controlled. The gained up
temperature proportional offset voltage is combined with the
diode voltage to form a “virtual bandgap” voltage, implicit in
the network, although it never appears explicitly in the circuit.
Ultimately, this patented design makes it possible to control the
loop with only one amplifier. This technique also improves the
noise characteristics of the amplifier by providing more flexibility on the trade-off of noise sources that leads to a low noise
design.
APPLICATION INFORMATION
Capacitor Selection: anyCAP
Output Capacitors: as with any micropower device, output
transient response is a function of the output capacitance. The
ADP3307 is stable with a wide range of capacitor values, types
and ESR (anyCAP). A capacitor as low as 0.47 µF is all that is
needed for stability. However, larger capacitors can be used if
high output current surges are anticipated. There is an upper
limit on the size of the output capacitor. The ADP3307 is stable
with extremely low ESR capacitors (ESR ≈ 0), such as multilayer ceramic capacitors (MLCC) or OSCON.
Input Bypass Capacitor: an input bypass capacitor is not required; however, for applications where the input source is high
impedance or far from the input pins, a bypass capacitor is
recommended. Connecting a 0.47 µF capacitor from the input
to ground reduces the circuit’s sensitivity to PC board layout. If
a bigger output capacitor is used, the input capacitor should be
1 µF minimum.
The R1, R2 divider is chosen in the same ratio as the bandgap
voltage to the output voltage. Although the R1, R2 resistor
divider is loaded by the diode D1, and a second divider consisting of R3 and R4, the values are chosen to produce a temperature stable output.
The patented amplifier controls a new and unique noninverting
driver that drives the pass transistor, Q1. The use of this special
noninverting driver enables the frequency compensation to
include the load capacitor in a pole splitting arrangement to
achieve reduced sensitivity to the value, type and ESR of the
load capacitance.
Noise Reduction
A noise reduction capacitor (CNR) can be used to further reduce
the noise by 6 dB–10 dB (Figure 21). Low leakage capacitors in
10 nF–100 nF range provide the best performance. As the noise
reduction capacitor increases the high frequency loop-gain of
the regulator, the circuit requires a larger output capacitor if it is
used. The recommended value is 4.7 µF, as shown in Figure 21.
Since the noise reduction pin (NR) is internally connected to a
high impedance node, any connection to this node should be
carefully done to avoid noise pick up from external sources. The
pad connected to this pin should be as small as possible. Long
PC board traces are not recommended.
Most LDOs place strict requirements on the range of ESR values for the output capacitor because they are difficult to stabilize
due to the uncertainty of load capacitance and resistance.
Moreover, the ESR value, required to keep conventional LDOs
stable, changes depending on load and temperature. These
ESR limitations make designing with conventional LDOs more
difficult because of their unclear specifications and the dependence of ESR over temperature.
–6–
REV. 0
ADP3307
Shutdown Mode
NR
ADP3307-3.3
VIN
OUT
IN
C1+
1mF
Applying a TTL high signal to the shutdown pin or tying it to
the input pin will turn the output ON. Pulling the shutdown pin
down to a TTL low level or tying it to ground will turn the
output OFF. In shutdown mode, quiescent current is reduced
to less than 1 µA.
CNR
10nF
R1
330k
ERR
EOUT
+
VOUT = 3.3V
C2
4.7mF
Error Flag Dropout Detector
ON
The ADP3307 will maintain its output voltage over a wide
range of load, input voltage and temperature conditions. If the
output is about to lose regulation, for example, by reducing the
supply voltage below the combined regulated output and dropout voltages, the ERR pin will be activated. The ERR output is
an open collector that will be driven low.
OFF
SD
GND
Figure 21. Noise Reduction Circuit
Thermal Overload Protection
The ADP3307 is protected against damage due to excessive
power dissipation by its thermal overload protection circuit,
which limits the die temperature to a maximum of 165°C. Under extreme conditions (i.e., high ambient temperature and
power dissipation), where die temperature starts to rise above
165°C, the output current is reduced until the die temperature
has dropped to a safe level. Output current is restored when the
die temperature is reduced.
Once set, the ERRor flag’s hysteresis will keep the output low
until a small margin of operating range is restored either by
raising the supply voltage or reducing the load.
APPLICATIONS CIRCUITS
Crossover Switch
The circuit in Figure 22 shows that two ADP3307s can be used
to form a mixed supply voltage system. The output switches
between two different levels selected by an external digital input.
Output voltages can be any combination of voltages from the
Ordering Guide of the data sheet.
Current and thermal limit protections are intended to protect
the device against accidental overload conditions. For normal
operation, device power dissipation should be externally limited
so that junction temperatures will not exceed 125°C.
Calculating Junction Temperature
VIN = 4V TO 12V
Device power dissipation is calculated as follows:
IN
OUTPUT SELECT
4V
0V
PD = (VIN – VOUT) ILOAD + (VIN) IGND
Where ILOAD and IGND are load current and ground current, VIN
and VOUT are input and output voltages respectively.
VOUT = 2.7V/3.3V
OUT
ADP3307-2.7
SD
GND
Assuming ILOAD= 100 mA, IGND= 2 mA, VIN = 5.5 V and
VOUT = 3.3 V, device power dissipation is:
PD = (5.5 – 3.3) 0.1 + 5.5 × 2 mA = 0.231 W
C1
1.0mF
∆T = TJ – TA = PD × θJA = 0.231 × 165 = 38°C
+
OUT
IN
+
ADP3307-3.3
C2
0.47mF
SD
With a maximum junction temperature of 125°C, this yields a
maximum ambient temperature of ~72°C.
GND
Printed Circuit Board Layout Consideration
Figure 22. Crossover Switch
Surface mount components rely on the conductive traces or
pads to transfer heat away from the device. Appropriate PC
board layout techniques should be used to remove heat from the
immediate vicinity of the package.
Higher Output Current
The ADP3307 can source up to 100 mA without any heatsink
or pass transistor. If higher current is needed, an appropriate
pass transistor can be used, as in Figure 23, to increase the
output current to 1 A.
The following general guidelines will be helpful when designing
a board layout:
1. PC board traces with larger cross section areas will remove
more heat. For optimum results, use PC boards with thicker
copper and wider traces.
VIN = 4V TO 8V
MJE253*
C1
47mF
VOUT = [email protected]
R1
50V
2. Increase the surface area exposed to open air so heat can be
removed by convection or forced air flow.
IN
OUT
+
3. Do not use solder mask or silkscreen on the heat dissipating
traces because it will increase the junction-to-ambient thermal resistance of the package.
ADP3307-3.3
SD
C2
10mF
ERR
GND
*AAVID531002 HEAT SINK IS USED
Figure 23. High Output Current Linear Regulator
REV. 0
–7–
ADP3307
The circuit in Figure 24 provides high precision with low dropout for any regulated output voltage. It significantly reduces the
ripple from a switching regulator while providing a constant
L1
6.8mH
D1
1N5817
ADP3307-3.3
VIN = 2.5V TO 3.5V
IN
R1
120V
ILIM
C2
100mF
10V
R2
30.1kV
1%
VIN
SW1
SD
GND
Q1
2N3906
ADP3000-ADJ
[email protected]
OUT
+
C3
2.2mF
Q2
2N3906
FB
GND
R3
124kV
1%
SW2
R4
274kV
Figure 24. Constant Dropout Post Regulator
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
6-Lead Plastic Surface Mount
(RT-6)
0.122 (3.10)
0.106 (2.70)
0.071 (1.80)
0.059 (1.50)
6
5
4
1
2
3
0.118 (3.00)
0.098 (2.50)
PIN 1
0.037 (0.95) BSC
0.075 (1.90)
BSC
0.051 (1.30)
0.035 (0.90)
0.059 (0.15)
0.000 (0.00)
0.057 (1.45)
0.035 (0.90)
0.020 (0.50) SEATING
0.010 (0.25) PLANE
10°
0.009 (0.23) 0°
0.003 (0.08)
0.022 (0.55)
0.014 (0.35)
PRINTED IN U.S.A.
C1
100mF
10V
C3234–8–12/97
dropout voltage, which limits the power dissipation of the LDO
to 30 mW. The ADP3000 used in this circuit is a switching
regulator in the step-up configuration.
Constant Dropout Post Regulator
–8–
REV. 0