ETC OM6208

INTEGRATED CIRCUITS
DATA SHEET
OM6208
65 x 96 pixels matrix grey-scale
LCD driver
Product specification
Supersedes data of 2003 Jan 30
2003 feb 10
Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
CONTENTS
OM6208
11.4
11.5
11.6
11.6.1
11.6.2
11.7
11.8
11.9
11.10
11.10.1
11.10.2
11.10.3
11.11
11.12
Reset function
Power-down mode
Display Control
Horizontal mirroring
Vertical mirroring
Set Y address of RAM
Set X address of RAM
Bias levels
LCD drive voltage
LCD drive voltage generation
Temperature measurement
Temperature compensation
Grey-scale mode and black-and-white mode
N-line inversion and frame inversion
12
LIMITING VALUES
13
HANDLING
14
DC CHARACTERISTICS
15
AC CHARACTERISTICS
16
APPLICATION INFORMATION
16.1
16.2
16.3
Protection from light
Chip-on-glass displays
Application examples
1
FEATURES
2
APPLICATIONS
3
GENERAL DESCRIPTION
4
ORDERING INFORMATION
5
BLOCK DIAGRAM
6
PINNING
7
FUNCTIONAL DESCRIPTION
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
7.12
7.13
I/O buffers and interfaces
Oscillator
Address counter
Display data RAM
Display address counter
Timing generator
Data processing
High voltage generator
Bias voltage generator
Command decoder
Orthogonal function generator
Reset
Row drivers and column drivers
8
RAM ADDRESSING
17
MODULE MAKER PROGRAMMING
8.1
8.1.1
8.1.2
8.1.3
Display data RAM structure
Horizontal/vertical addressing
Mirror Y
Mirror X
9
SERIAL INTERFACING
9.1
9.1.1
9.1.2
9.2
9.2.1
9.2.2
9.2.3
Serial peripheral interface
Write mode
Read mode
Serial interface (3-line)
Write mode
Read mode
Read data format
17.1
17.2
17.2.1
17.2.2
17.3
17.4
17.4.1
17.5
17.5.1
17.5.2
17.6
17.7
17.8
VLCD calibration
Factory defaults
Configuration derived from OTP cells
Defaults from interface registers
Seal bit
OTP architecture
OTP operational effects
Interface commands
CALMM instruction
Refresh instruction
Example of filling the shift register
Programming flow
Programming specification
10
I2C-BUS INTERFACE
18
DEVICE PROTECTION DIAGRAM
10.1
10.1.1
10.1.2
10.1.3
10.1.4
10.2
10.3
10.4
Characteristics of the I2C-bus (Hs-mode)
System configuration
Bit transfer
Start and stop conditions
Acknowledge
I2C-bus Hs-mode protocol
Command decoder
Read mode
19
BONDING PAD INFORMATION
20
TRAY INFORMATION
21
DATA SHEET STATUS
22
DEFINITIONS
23
DISCLAIMERS
24
PURCHASE OF PHILIPS I2C COMPONENTS
11
INSTRUCTIONS
11.1
11.2
11.3
Description of command bits
Frame frequency setting and oscillator tuning
Initialization
2003 feb 10
2
Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
1
OM6208
FEATURES
• Single chip LCD Multiple Row Addressing (MRA)
grey-scale/colour controller/driver
• Four grey levels/colours
• 65 row outputs and 96 column outputs
• Programmable row pad mirroring for compatibility with
Tape Carrier Packages (TCP) and with Chip-On
Glass (COG) applications
• Display Data RAM (DDRAM) 65 × 96 × 2 bits
• Selectable interface:
– 6.5 MHz 3-line or 4-line Serial Peripheral
Interface (SPI)
• Status read which allows chip recognition
• Start address line; for example, for scrolling the
displayed image
– 6.5 MHz 3-line serial interface
– High speed I2C-bus interface.
• Slim chip layout; suitable for COG, COF and TCP
applications
• On-chip:
• Operating temperature range −40 to +85 °C.
– Configurable voltage multiplier generating VLCD;
external VLCD also possible
– Four-segment VLCD temperature compensation
2
– Generation of intermediate LCD bias voltage
APPLICATIONS
• Telecom equipment
– Oscillator requires no external components; external
clock input also possible
• Portable instruments
• Point of sale terminals.
– Integrated charge pump capacitors (reducing total
system cost).
• External reset input
3
• Temperature read-back
The OM6208 is a low power CMOS LCD controller driver,
designed to drive a graphic display of 65 rows and
96 columns. All necessary functions for the display are
provided in a single chip, including on-chip generation of
LCD supply and bias voltages, resulting in a minimum of
external components and low power consumption. The
OM6208 can be interfaced to microcontrollers via a serial
bus and I2C-bus.
• Selectable N-line inversion and frame inversion
• CMOS compatible inputs
• Logic supply voltage range 1.7 to 3.3 V
• High-voltage generator supply voltage range
2.4 to 4.5 V
• Display supply voltage range 5 to 9 V
The OM6208 is manufactured in n-well CMOS technology.
• Low power consumption; suitable for battery operated
systems
4
GENERAL DESCRIPTION
Operation is with the substrate at VSS potential.
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME
OM6208MU/2DA/1
2003 feb 10
−
DESCRIPTION
chip with bumps in tray
3
VERSION
−
Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
5
OM6208
BLOCK DIAGRAM
C0 to C95
R0 to R64
COLUMN DRIVERS
ROW DRIVERS
DATA PROCESSING
ORTHOGONAL
FUNCTION
GENERATOR
handbook, full pagewidth
VDD1
VDD2
VDD3
VLCDIN
BIAS
VOLTAGE
GENERATOR
VSS1
VSS2
RESET
RES
OSCILLATOR
OSC
VOTPPROG
VLCDSENSE
VLCDOUT
DISPLAY DATA RAM
(DDRAM)
HIGH
VOLTAGE
GENERATOR
[65 × 96] × 2
TIMING
GENERATOR
T1
T2
DISPLAY
ADDRESS
COUNTER
ADDRESS COUNTER
T3
T4
T5
COMMAND
DECODER
T6
V2H
OM6208
V1H
T7
VC
T8
V1L
I/O BUFFERS and INTERFACES
V2L
Fig.1 Block diagram.
2003 feb 10
4
SDAHOUT
SDAH
SDO
SDATA
SCLK
SCLH/SCE
D/C
PS [1:0]
ID3/SA0; ID4/SA1
MX
MGW821
Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
6
OM6208
PINNING
SYMBOL
PAD(1)
DESCRIPTION
VLCDIN
5 to 8
LCD supply voltage input; note 2
VLCDOUT
9 to 15
LCD supply voltage output from high voltage generator; note 2
VLCDSENSE
16
regulation input to high voltage generator; note 2
VDD2
17 to 26
supply voltage 2; note 3
VDD3
27 to 29
supply voltage 3; note 3
OSC
30
oscillator input; note 4
31
data/command input/output; note 5
D/C
PS[1:0]
VDD1
32 and 33
interface selection inputs
34 to 39
supply voltage 1; note 3
SDAHOUT
44
I2C-bus data output; note 6
SCLK
46
serial data clock input; used in 3-line or 4-line SPI or 3-line serial interface
mode
SDAH
52
I2C-bus data input; note 7
SDO
53
serial data output; note 8
SDATA
54
serial data input; note 9
VSS2
55 to 61
ground 2 (analog ground); note 10
VSS1
62 to 67
ground 1 (digital ground); note 10
MX
68
horizontal mirroring input
T3
69
test outputs; note 11
T4
70
T1
71
T2
72
T5
73
T6
ID3/SA0; ID4/SA1
74
75 and 76
manufacturer device identification/I2C-bus slave address input pads; note 12
VDD1
77
supply voltage 1 (tie-off pad)
SCLH/SCE
83
I2C-bus clock input/serial chip enable input in 3-line or 4-line SPI mode; note 5
VOTPPROG
RES
R32 to R64
84 to 86
88
105 to 137
supply voltage input for OTP programming; note 13
external reset input; active low; must be applied to initialize the chip properly
LCD row driver outputs
VC
138
bias buffer output; note 14
T8
141
test outputs; note 11
T7
142
V1L
143
bias buffer output; note 14
C95 to C48
144 to 191
LCD column driver outputs
C47 to C0
194 to 241
R31 to R0
247 to 278
V1H
244
V2L
245
V2H
246
2003 feb 10
LCD row driver outputs
bias buffer outputs; note 14
5
Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
OM6208
Notes
1. Dummy pads are located at positions 1, 2, 4, 40 to 43, 45, 47 to 51, 78 to 82, 87, 89 to 92, 95 to 104, 139, 140, 192,
193, 242, 243, 279 and 280; alignment marks are located at positions 3 and 93; an alignment bump is located at
position 94.
2. Positive power supply for the liquid crystal display (see also Figs 38, 39 and 40):
a) If the internal voltage generator is used, pads VLCDIN, VLCDSENSE and VLCDOUT must be connected together.
b) An external LCD supply voltage can be incorporated using the VLCDIN pad; the internal voltage generator must
then switched off, pad VLCDOUT must be open-circuit (not connected to pad VLCDIN) and pad VLCDSENSE
connected to the VLCDIN input; VDD2,3 should be applied according to the specified voltage range. In Power-down
mode, the external LCD supply voltage must be switched off.
3. VDD2 and VDD3 supply the internal voltage generator, both have the same voltage and may be connected together
outside of the chip; VDD1 supplies the remainder of the chip. VDD1, VDD2 and VDD3 can be connected together but
then care must be taken with respect to the supply voltage range.
4. When the on-chip oscillator is used, the OSC input must be connected to VDD1. If an external clock signal is used,
then this is connected to the OSC input. If both the oscillator and external clock are inhibited by connecting pad OSC
to VSS1, the display is not clocked and may be in a DC state. To avoid this, the chip should always be put into
Power-down mode before stopping the clock.
5. This input is not used with the 3-line serial interface and must be connected to VDD1 or VSS1 when this interface is in
use.
6. SDAHOUT is the serial data acknowledge output from the I2C-bus interface. By connecting SDAHOUT to SDAH
externally, the SDAH line becomes fully I2C-bus compatible. Having the acknowledge output separated from the
serial data line is advantageous in COG applications because here the track resistance from the SDAHOUT pad to
the system SDAH line can be significant and a potential divider can be generated by the bus pull-up resistor and the
ITO track resistance. It is possible that during the acknowledge cycle the OM6208 will not be able to create a valid
logic 0. By splitting the SDAH input from the SDAHOUT output the device could be used in a mode that ignores the
acknowledge bit. Therefore in COG applications where the acknowledge cycle is required, it is necessary to minimize
the track resistance from the SDAHOUT pad to the system SDAH line to guarantee a valid logic 0. When SDAHOUT
is not used, it must be connected to VDD1 or VSS1.
7. When I2C-bus is not used, this pad must be connected to VDD1 or VSS1.
8. SDO is a push-pull output; when it is intended to use the readback function of the OM6208, this pad must be
connected to the SDATA pad, or used separately; when I2C-bus interface is selected, this pad should be connected
to VDD1 or VSS1.
9. When I2C-bus interface is selected this pin should be connected to VDD1 or VSS1.
10. Supply rails VSS1 and VSS2 must be connected together.
11. Test pads T1 to T8 are not accessible to users: T1, T2, T5 and T6 must be connected to VSS; T3, T4, T7 and T8 must
be open-circuit.
12. Module identification bits: these bits may be read back via the ‘read back’ instruction; when the I2C-bus interface is
being used, these bits are the two LSBs of the slave address.
13. VOTPROG can be connected to SCLH/SCE pad to reduce the external connections. If not connected in this
configuration, then VOTPROG should be open-circuit during normal operation.
14. These pads are not accessible to users and must be left open-circuit; an explanation of the bias buffer function is
given in Section 11.9.
2003 feb 10
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Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
7
7.6
FUNCTIONAL DESCRIPTION
7.1
One of four industrial standard interfaces can be selected
using the interface configuration inputs PS1 and PS0.
7.2
7.7
Serial/I2C-bus interface selection
PS1
PS0
0
0
3-line SPI
0
1
4-line SPI
1
0
I2C-bus interface
1
1
3-line serial interface
7.8
Oscillator
7.9
Bias voltage generator
The bias voltage generator generates all the voltage levels
required for the MRA driving system.
7.10
Address counter
Command decoder
The command decoder identifies command words arriving
at the interface and routes the data bytes that follow to
their destination.
7.11
Display data RAM
Orthogonal function generator
The orthogonal function generator generates a set of
orthogonal functions suitable for the selected value of p
(number of active rows).
The OM6208 contains a 65 × 96 × 2 bit static RAM which
stores the display data. The display data RAM is divided
into 17 banks of 96 bytes, although only two bits of the
17th bank are used. During RAM access, data is
transferred to the RAM via the serial interface. There is a
direct correspondence between X address and column
output number.
7.5
High voltage generator
The high voltage generator provides the programmed
VLCD to the bias voltage generator block.
The Address Counter (AC) assigns addresses to the
display data RAM for writing. The X address X[6:0] and the
Y address Y[4:0] are set separately.
7.4
Data processing
The data processing block receives data from the RAM
and the orthogonal function from the logic circuits, then
selects the correct voltage level to be provided to the
columns.
SELECTED INTERFACE
The on-chip oscillator provides the clock signal for the
display system. No external components are required
when the internal oscillator is used. An external clock
signal, if used, is connected to this input.
7.3
Timing generator
The timing generator produces the various signals
required to drive the internal circuitry. Internal chip
operation is not affected by operations on the data bus.
I/O buffers and interfaces
Table 1
OM6208
7.12
Reset
The reset block handles the hardware reset input (RES)
and software reset and provides all internal blocks with the
required reset signal.
Display address counter
7.13
The display is generated by simultaneously reading out
the RAM content for two or four rows, depending on the
current display size that is selected. This content will be
processed with the corresponding set of two or four
orthogonal functions and so generate the signals for
switching the pixels of the display on or off according to the
RAM content.
The OM6208 contains 65 row and 96 column drivers
which connect the appropriate LCD bias voltages in
sequence to the display in accordance with the data to be
displayed. A typical MRA driving scheme with waveforms
for p = 4 is shown in Fig.2. The value of p represents the
number of simultaneously selected rows.
The display status (all dots on/all dots off and
normal/inverse video) is set by the bits DON, DAL and E
in the command Display control (see Table 8).
2003 feb 10
Row drivers and column drivers
7
Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
OM6208
G1(t)
handbook, full pagewidth
G2(t)
G3(t)
F1(t)
F2(t)
F3(t)
F4(t)
Vcol(max)
G1(t)
G1(t) = C [+ F1(t) − F2(t) − F3(t) + F4(t) ]
VC
Vcol(min)
G1(t)
G2(t)
G3(t)
F1(t)
F2(t)
F3(t)
F4(t)
Vcol(max)
G1(t)
G1(t) = C [− F1(t) − F2(t) − F3(t) + F4(t) ]
VC
MGW822
Vcol(min)
Fig.2 Typical MRA LCD driver waveforms for p = 4.
2003 feb 10
8
Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
8
RAM ADDRESSING
are X = 0 to 95 and Y = 0 to 16. The Y address represents
the bank number. Addresses outside these ranges are not
allowed.
Data is downloaded in bytes into the RAM matrix of the
OM6208 as indicated in Fig.3. The display RAM has a
matrix of 65 × 96 × 2 bits. The columns are addressed by
the address pointer. The address ranges (decimal values)
handbook, full pagewidth
DOR
LSB
OM6208
The Data Order Bit (DOR) defines the bit order (LSB on
top or MSB on top) for writing into the RAM.
=1
LSB
P0
DB0
MSB
DB1
P0
LSB
DB2
P1
MSB
MSB
P0
P0
P1
P2
bank 0
P1
P2
P3
top of LCD
R0
P3
bank 1
DB3 P1
LSB
R4
DB4 P2
MSB
bank 2
DB5 P2
LSB
R8
DB6 P3
MSB
bank 3
MSB DB7 P3
LSB
R12
.
.
.
DOR = 0
.
.
.
P3
LSB DB0 LSB
DB1
P3
MSB
DB2
P2
LSB
bank 13
.
.
R16
LCD
R52
bank 14
DB3 P2
MSB
DB4 P1
LSB
R56
bank 15
DB5 P1
MSB
DB6 P0
LSB
MSB DB7 P0
MSB
R60
X
bank 16
X
X
X
X
R64
X
MGW823
Fig.3 DDRAM-to-display mapping.
2003 feb 10
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Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
8.1
In the horizontal addressing mode (V = 0) the X address
increments after each byte. After the last X address
(X = 95), X wraps around to 0 and Y increments to
address the next row (see Fig.4).
Display data RAM structure
The mode for storing data in the display data RAM is
dependent on:
• Horizontal/vertical addressing mode set by bit V in the
‘RAM addressing mode’ instruction
In the vertical addressing mode (V = 1), the Y address
increments after each byte. After the last Y address
(Y = 16), Y wraps around to 0 and X increments to
address the next column (see Fig.5).
• Data order set by bit DOR in the ‘data order’ instruction
• Mirror the X-axis set by input MX.
8.1.1
OM6208
After the very last address, the address pointers wrap
around to address X = 0 and Y = 0 in both horizontal and
vertical addressing modes.
HORIZONTAL/VERTICAL ADDRESSING
Two different addressing modes are possible; horizontal
addressing mode and vertical addressing mode.
handbook, full pagewidth
0
1
2
95
96
97
98
191
192
193
194
288
289
290
384
385
386
1440
1441
1442
1536
1537
0
0
Y address
1535
1631
X address
95
16
MGW824
Fig.4 Sequence of writing data bytes into RAM with horizontal addressing (V = 0).
handbook, full pagewidth
0
17
1
18
2
19
3
20
4
21
5
22
16
33
0
0
Y address
1631
X address
95
16
MGW825
Fig.5 Sequence of writing data bytes into the RAM with vertical addressing (V = 1).
2003 feb 10
10
Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
8.1.2
OM6208
• When MY = 0, the mirroring is disabled and the address
Y = 0 is located at top of the display (see Fig.7).
MIRROR Y
The Mirror Y (MY) bit allows vertical mirroring:
Refer also to Section 11.6.
• When MY = 1, the Y address space is mirrored; the
address Y = 0 is then located at the bottom of the
display (see Fig.6)
handbook, full pagewidth
16
0
0
X address
95
Y address
MGW826
Fig.6 RAM format addressing (MY = 1).
handbook, full pagewidth
0
16
0
X address
95
Y address
MGW827
Fig.7 RAM format addressing (MY = 0).
2003 feb 10
11
Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
8.1.3
OM6208
• When MX = 0, the mirroring is disabled and the address
X = 0 is located at the left side (column 0) of the display
(see Fig.9).
MIRROR X
The Mirror X (MX) input allows a horizontal mirroring:
• When MX = 1, the X address space is mirrored; the
address X = 0 is then located at the right side (Xmax) of
the display (see Fig.8)
Refer also to Section 11.6.
handbook, full pagewidth
0
16
95
X address
0
Y address
MGW828
Fig.8 RAM format addressing (MX = 1).
handbook, full pagewidth
0
16
0
X address
95
Y address
MGW829
Fig.9 RAM format addressing (MX = 0).
2003 feb 10
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Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
9
SERIAL INTERFACING
9.1.1
WRITE MODE
The display data/command indication may be controlled
by software or by the D/C select pin. When the D/C pad is
used, display data is transmitted when D/C is HIGH, and
command data is transmitted when D/C is LOW (see
Figs 10 and 11). When D/C is not used, the ‘display data
length’ instruction is used to indicate that a specific number
of display data bytes (1 to 255) are to be transmitted (see
Fig.11). The next byte after the display data string is
handled as an instruction command.
Communication with the microcontroller can occur via a
clock-synchronized serial peripheral interface. It is
possible to select two different 3-line (SPI and serial
interface) or a 4-line SPI interface. Selection is done via
the PS[1:0] inputs.
9.1
OM6208
Serial peripheral interface
The Serial Peripheral Interface (SPI) is a 3-line or 4-line
interface for communication between the microcontroller
and the LCD driver chip. Three lines are common to both
3-line and 4-line SPI, these are SCE (chip enable), SCLK
(serial clock) and SDATA (serial data). For the 4-line SPI a
separate D/C line is added. The OM6208 is connected to
the serial data I/O of the microcontroller by pads SDATA
(data input) and SDO (data output) connected together.
When the 3-line SPI interface is used the display
data/command is controlled by software (see Fig.12).
If SCE is pulled high during a serial display data stream,
the interrupted byte is invalid data but all previously
transmitted data is valid. The next byte received will be
handled as an instruction command (see Fig.13).
handbook, full pagewidth
SCE
D/C
SCLK
SDATA
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
MGW744
Fig.10 4-line SPI bus protocol; transmission of one byte.
handbook, full pagewidth
SCE
D/C
SCLK
SDATA
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5
MGW745
Fig.11 4-line SPI bus protocol; transmission of several bytes.
2003 feb 10
13
Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
OM6208
handbook, full pagewidth
SCE
SCLK
SDATA
DB7 DB6 DB5 DB4
DB2 DB1 DB0 data
display length instruction
and length data (two bytes)
data
last
data
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
display data string
instruction
MGW746
Fig.12 3-line SPI bus protocol; transmission of several bytes.
handbook, full pagewidth
SCE
SCLK
SDATA
data
data
data
data
data
data
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4
MGW747
instruction
display data string
Fig.13 3-line SPI bus protocol: transmission interrupted by SCE.
2003 feb 10
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Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
9.1.2
READ MODE
OM6208
the SDO data is available to be read by the microcontroller
at rising SCLK edges.
The read mode of the interface means that the
microcontroller reads data from the OM6208. To do so the
microcontroller first has to send a command, the read
status command, and then OM6208 will respond by
transmitting data on the SDO line. After that, SCE is
required to go HIGH (see Fig.14).
After the read status command has been sent, the SDATA
line must be set to 3-state (high-impedance) not later than
at the falling SCLK edge of the last bit (see Fig.14).
For the read data format, see Section 9.2.3; the serial
interface timing diagram is given in Chapter 15.
The OM6208 samples the SDATA data at rising SCLK
edges, but shifts SDO data at falling SCLK edges. Thus
handbook, full pagewidth
SCE
RES
SCLK
SDATA
DB7 DB6 DB5 DB4 DB3 DB2
SDO
DB1 DB0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
read out data
instruction
Fig.14 Read mode SPI 3- and 4-line interfaces.
2003 feb 10
15
MGU629
Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
9.2
pulses have no effect and no power is consumed by the
serial interface. A falling edge on SCE enables the serial
interface and indicates the start of data transmission.
Serial interface (3-line)
The serial interface is also a 3-line bidirectional interface
for communication between the microcontroller and the
LCD driver chip. The three lines are SCE (chip enable),
SCLK (serial clock) and SDATA (serial data). The OM6208
is connected to the SDA of the microcontroller by the
SDATA (data input) and SDO (data output) pads which are
connected together.
9.2.1
OM6208
Figures 16, 17 and 18 show the protocol of the write
mode:
• When SCE is HIGH, SCLK clocks are ignored. During
the HIGH time of SCE the serial interface is initialized
(see Fig.16)
• At the falling SCE edge, SCLK must be LOW
(see Fig.32)
WRITE MODE
The write mode of the interface means that the
microcontroller writes instructions and data to the
OM6208. Each data packet contains a control bit D/C and
a transmission byte. If D/C is LOW, the following byte is
interpreted as command byte. The instruction set is given
in Table 7. If D/C is HIGH, the following byte is stored in
the display data RAM. After every data byte the address
counter is incremented automatically. The general format
of the write mode and the definition of the transmission
byte is shown in Fig.15.
• SDATA is sampled at the rising edge of SCLK
• D/C indicates whether the byte is a command (D/C = 0)
or RAM data (D/C = 1) byte; it is sampled with the first
rising SCLK edge
• If SCE stays LOW after the last bit of a command/data
byte, the serial interface is ready for the D/C bit of the
next byte at the next rising edge of SCLK (see Fig.17)
• A reset pulse with RES interrupts the transmission. The
data being written into the RAM may be corrupted. The
registers are cleared. If SCE is LOW after the rising
edge of RES, the serial interface is ready to receive the
D/C bit of a command/data byte (see Fig.18).
Any instruction can be sent in any order to the OM6208.
The MSB is transmitted first. The serial interface is
initialized when SCE is HIGH. In this state, SCLK clock
transmission byte (1)
handbook, full pagewidth
D/C
D7
D6
D5
D4
D3
D2
D1
MSB
D/C
D0
LSB
transmission byte
D/C
transmission byte
D/C
transmission byte
MGW713
(1) A transmission byte may be a command byte or a data byte.
Fig.15 Serial data stream, write mode.
2003 feb 10
16
Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
OM6208
handbook, full pagewidth
SCE
SCLK
SDATA
D/C
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
MGU630
Fig.16 Write mode: a control bit followed by a transmission byte.
handbook, full pagewidth
SCE
SCLK
SDATA
D/C
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 D/C
transmission byte
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 D/C
transmission byte
MGU631
Fig.17 Write mode: transmission of several bytes.
handbook, full pagewidth
SCE
RES
SCLK
SDATA
D/C DB7 DB6 DB5 DB4
D/C
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
D/C
DB7 DB6
MGU632
Fig.18 Write mode: interrupted by reset (RES).
2003 feb 10
17
Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
9.2.2
OM6208
READ MODE
handbook, full pagewidth
SCE
SCLK
SDATA
D/C
DB7 DB6 DB5 DB4
DB3 DB2 DB1 DB0
SDO
D/C
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
MCE176
Fig.19 Read mode serial interface 3-line.
The read mode of the interface means that the
microcontroller reads data from the OM6208. To do so the
microcontroller first has to send a command, the read
status command, and then the following byte is transmitted
in the opposite direction using SDO (see Fig.19). After
that, SCE is required to go HIGH before a new command
is sent.
The 8th read bit is shorter than the others because it is
terminated by the rising SCLK edge (see Fig.35). The last
rising SCLK edge sets SDO to 3-state after the delay
time t4.
9.2.3
Regardless of which serial interface is used there are five
bits that can be read (ID1 to ID4 and VM) and one
temperature register. For the bits, one bit is transmitted per
byte read and is selected by issuing the appropriate read
instruction from the instruction set. Bits ID1 and ID2 are
hard-wired so that ID1 always returns a logic 0 and ID2
always returns a logic 1. Bits ID3 and ID4 are the
identification bits and are set via ID3/SA0 and ID4/SA1
pads. The format for the read bit, B, is shown in Table 2.
The OM6208 samples the SDATA data at rising SCLK
edges and shifts SDO data at falling SCLK edges. Thus
the SDO data is available for the microcontroller to read at
rising SCLK edges.
After the read status command has been sent, the SDATA
line must be set to 3-state not later then at the falling SCLK
edge of the last bit (see Fig.19).
Table 2
READ DATA FORMAT
Read data format
D7 (MSB)
D6
D5
D4
D3
D2
D1
D0 (LSB)
x(1)
B
B
B
B
B
B
B
Note
1. x = undefined.
Table 3 Read temperature sensor
Sending the instruction to read back the temperature sensor data will select the following status byte.
D7 (MSB)
D6
D5
D4
D3
D2
D1
D0 (LSB)
x(1)
TD[6]
TD[5]
TD[4]
TD[3]
TD[2]
TD[1]
TD[0]
Note
1. x = undefined.
2003 feb 10
18
Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
10.1.1
10 I2C-BUS INTERFACE
10.1
• Transmitter: the device that sends the data to the bus
The I2C-bus Hs-mode is for bidirectional, two-line
communication between different ICs or modules with
speeds up to 3.4 MHz. The only difference between
Hs-mode slave devices and F/S-mode slave devices is the
speed at which they operate, therefore the buffers on the
SDAH output have an open drain. This is the same for
I2C-bus master devices which have an open-drain SDAH
output and a combination of an open-drain pull-down and
current source pull-up circuits on the SCLH output. Only
the current source of one master is enabled at any one
time and only during Hs-mode. Both lines must be
connected to a positive supply via a pull-up resistor.
• Receiver: the device that receives the data from the bus
• Master: the device that initiates a transfer, generates
clock signals and terminates a transfer
• Slave: the device addressed by a master
• Multi-master: more than one master can attempt to
control the bus at the same time without corrupting the
message
• Arbitration: procedure to ensure that, if more than one
master simultaneously tries to control the bus, only one
is allowed to do so and the message is not corrupted
• Synchronisation: procedure to synchronize the clock
signals of two or more devices.
Data transfer may be initiated only when the bus is not
busy.
SLAVE
RECEIVER
SYSTEM CONFIGURATION
Definition (see Fig.20):
Characteristics of the I2C-bus (Hs-mode)
MASTER
TRANSMITTER/
RECEIVER
OM6208
SLAVE
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER
MASTER
TRANSMITTER/
RECEIVER
SDA
SCL
MGA807
Fig.20 System configuration.
10.1.2
BIT TRANSFER
during the HIGH period of the clock pulse as changes in
the data line at this time will be interpreted as a control
signal.
One data bit is transferred during each clock pulse (see
Fig.21). The data on the SDAH line must remain stable
handbook, full pagewidth
SDA
SCL
data line
stable;
data valid
change
of data
allowed
Fig.21 Bit transfer.
2003 feb 10
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MBC621
Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
10.1.3
OM6208
line, while the clock is HIGH is defined as the START
condition (S). A LOW-to-HIGH transition of the data line
while the clock is HIGH is defined as the STOP
condition (P).
START AND STOP CONDITIONS
Both data and clock lines remain HIGH when the bus is not
busy (see Fig.22). A HIGH-to-LOW transition of the data
handbook, full pagewidth
SDA
SDA
SCL
SCL
S
P
START condition
STOP condition
MBC622
Fig.22 Definition of START and STOP conditions.
10.1.4
ACKNOWLEDGE
slave transmitter. The device that acknowledges must
pull-down the SDA line during the acknowledge clock
pulse, so that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse (set-up and
hold times must be taken into consideration). A master
receiver must signal an end of data to the transmitter by
not generating an acknowledge on the last byte that has
been clocked out of the slave. In this event the transmitter
must leave the data line HIGH to enable the master to
generate a stop condition.
Each byte of 8 bits is followed by an acknowledge bit (see
Fig.23). The acknowledge bit is a HIGH signal put on the
bus by the transmitter during which time the master
generates an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an
acknowledge after the reception of each byte. Also a
master receiver must generate an acknowledge after the
reception of each byte that has been clocked out of the
handbook, full pagewidth
DATA OUTPUT
BY TRANSMITTER
not acknowledge
DATA OUTPUT
BY RECEIVER
acknowledge
SCL FROM
MASTER
1
2
8
9
S
clock pulse for
acknowledgement
START
condition
MBC602
Fig.23 Acknowledge on the I2C-bus.
2003 feb 10
20
Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
10.2
R/W bit, and receives an acknowledge bit (A) from the
selected slave. After each acknowledge bit (A) or
not-acknowledge bit (A) the active master disables its
current-source pull-up circuit. The active master
re-enables its current source again when all devices have
released and the SCLH signal reaches a HIGH level. The
rising of the SCLH is done by a resistor pull-up and so is
slower, the last part of the SCLH rise time is speeded up
because the current source is enabled. Data transfer only
switches back to F/S-mode after a STOP (P) condition.
I2C-bus Hs-mode protocol
The OM6208 is a slave receiver/transmitter. If data is to be
read from the device the SDAHOUT and SDAH pads must
be connected for acknowledge to be used (see Table 1,
note 6).
Hs-mode can only commence after the following
conditions.
• START condition (S)
• 8-bit master code (00001XXX)
The write sequence that occurs after the Hs-mode is
selected is shown in Fig.26. The sequence is initiated with
a START (S) condition from the I2C-bus master which is
followed by the slave address. All slaves with the
corresponding address acknowledge in parallel, all the
others will ignore the I2C-bus transfer.
• not-acknowledge bit (A).
The master code has two functions as shown in Figs 24
and 25, it allows arbitration and synchronization between
competing masters at F/S-mode speeds, resulting in one
winner. Also the master code indicates the beginning of an
Hs-mode transfer.
After an acknowledgement cycle of a write (W), one or
more command words follow which define the status of the
addressed slaves. A command word consists of a control
byte, which defines Co and D/C, plus a data byte (see
Fig.26 and Table 4).
As no device is allowed to acknowledge the master code,
then a master code transmission must be followed by a
not-acknowledge (A). After this A bit, and the SCLH line
has been pulled up to a HIGH level, the active master
switches to Hs-mode and enables at tH the current-source
pull-up circuit for the SCLH signal (see Fig.25).
The last control byte is tagged with a cleared most
significant bit, the continuation bit Co. The control and data
bytes are also acknowledged by all addressed slaves on
the bus.
The active master will then send a repeated START
condition (Sr) followed by a 7-bit slave address with a
Table 4
OM6208
Co and Sr definition
Co
D/C
R/W
0
−
−
last control byte to be sent; only a stream of data bytes are allowed to follow; this stream
may only be terminated by a STOP or repeated START condition
1
−
−
another control byte will follow the data byte unless a STOP or repeated START condition
is received
−
0
0
data byte will be decoded and used to set up the device
1
data byte will return the status byte
0
data byte will be stored in the display RAM
1
RAM read back is not supported
−
1
ACTION
transmission the I2C-bus master issues a STOP
condition (P) and switches back to F/S-mode, however, to
reduce the overhead of the master code, it i s possible that
a master links a number of Hs-mode transfers, separated
by repeated START conditions (Sr).
After the last control byte, depending on the D/C bit setting,
a series of display data bytes or command data bytes may
follow. If the Sr bit was set to logic 1, these display bytes
are stored in the display RAM at the address specified by
the data pointer. The data pointer is automatically updated
and the data is directed to the intended OM6208 device.
If the Sr bit of the last control byte was set to logic 0, these
command bytes will be decoded and the setting of the
device will be changed according to the received
commands. The acknowledgement after each byte is
made only by the addressed OM6208. At the end of the
2003 feb 10
A read sequence (see Fig.27) follows after the Hs-mode is
selected. The OM6208 will immediately start to output the
requested data until a not acknowledge is transmitted by
the master. The write access should be terminated by a
repeated START condition so that the Hs-mode is not
disabled.
21
Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
OM6208
,,,,,
,,,,,
,,,,,,,,,,
handbook, full pagewidth
Hs-mode (current-source for SCLH enabled)
F/S-mode
S
MASTER CODE
A
Sr
SLAVE ADD. R/W
A
DATA
,,
,,
,,,,
,,,,
F/S-mode
A/A P
(n bytes + ack.)
Hs-mode continues
Sr SLAVE ADD.
MSC616
Fig.24 Data transfer format in Hs-mode.
handbook, full pagewidth
8-bit Master code 00001xxx
S
A
t1
tH
SDAH
SCLH
1
6
2 to 5
7
8
9
F/S mode
R/W
7-bit SLA
Sr
n × (8-bit DATA
A
+
A/A)
Sr P
SDAH
SCLH
1
2 to 5
6
7
8
9
1
2 to 5
6
7
8
9
If P then
F/S mode
Hs-mode
If Sr (dotted lines)
then Hs-mode
tH
tFS
= MCS current source pull-up
= Rp resistor pull-up
Fig.25 Complete data transfer in Hs-mode.
2003 feb 10
22
MSC618
Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
acknowledge
from OM6208
handbook, full pagewidth
S S
Sr 0 1 1 1 1 A A 0 A 1 D/C
1 0
slave address
acknowledge
from OM6208
control byte
A
acknowledge
from OM6208
data byte
2n ≥ 0 bytes
R/W Co
OM6208
A 0 D/C
acknowledge
from OM6208
control byte
1 byte
Co
acknowledge
from OM6208
data byte
A
A P
n ≥ 0 bytes
MSB . . . . . . . . . . . LSB
MGW830
Fig.26 Master transmits in Hs-mode to slave receiver; write mode.
acknowledgement
from OM6208
handbook, full pagewidth
S S
Sr 0 1 1 1 1 A A 1 A
1 0
NOT acknowledgement
from Master
status information
A P
slave address
R/W
STOP condition
(1)
MGW831
(1) These bits are set by inputs ID3/SA0 and ID4/SA1.
Fig.27 Master receives from slave transmitter (status register is read); read mode.
10.3
Command decoder
The most-significant bit of a control byte is the continuation
bit Co. If this bit is logic 1, it indicates that only one byte,
either command or RAM-data, will follow. If this bit is
logic 0, it indicates that a series of bytes, either command
or RAM-data, may follow. The DB6 bit of a control byte is
the RAM-data/command bit D/C. When this bit is logic 1, it
indicates that a RAM-data byte will be transferred next.
If the bit is logic 0, it indicates that a command byte will be
transferred next.
The command decoder identifies command words that
arrive on the I2C-bus:
• Pairs of bytes
– first byte determines whether information is display or
instruction data
– 2nd byte contains information.
• Stream of information bytes after Co = 0; display or
instruction data depending on last D/C.
2003 feb 10
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Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
10.4
Sending the instruction to read ID1, ID2 and VM will select
the status byte shown in Table 5.
Read mode
I2C-bus
read mode operates differently from the other
interfaces. Two different status bytes can be read back
and are selected by first sending a ‘read’ instruction.
A repeated START or STOP and START must then be
generated followed by the slave address with the R/W bit
set to read in order to read the status register.
Table 5
OM6208
Sending the instruction to read back the temperature
sensor will select the status byte shown in Table 6.
Read status byte ID1, ID2 and VM
D7 (MSB)
D6
D5
D4
D3
x(1)
x(1)
x(1)
x(1)
x(1)
D2
D1
D0 (LSB)
VM
ID2(2)
ID1(2)
Notes
1. x = undefined.
2. Bits ID3 and ID4 are not available for I2C-bus because they are used to make up the two LSBs of the slave address.
Table 6
Read temperature sensor
D7 (MSB)
D6
D5
D4
D3
D2
D1
D0 (LSB)
x(1)
TD[6]
TD[5]
TD[4]
TD[3]
TD[2]
TD[1]
TD[0]
Note
1. x = undefined.
2003 feb 10
24
Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
11 INSTRUCTIONS
D/C bit definitions:
• With 4-line SPI interface selected, the D/C bit is
implemented as hard-wired input at pad D/C
The OM6208 may be interfaced via 3-line or 4-line Serial
Peripheral Interface (SPI), 3-line serial interface or I2C-bus
interface. In all cases, processing of instructions is
asynchronous and does not require the internal/external
oscillator to be running.
• With 3-line SPI interface selected, the D/C bit is not
implemented and all transmission are commands by
default unless preceded by the Display data length
command
Data transmission to OM6208 may be of two types, those
that define the operating mode of the device (commands)
and those that fill display RAM (data). Table 7 lists all
commands that are recognised by OM6208.
• With 3-line serial and I2C-bus interface selected, the D/C
bit is implemented through the interface protocol.
Commands can consist of one byte (single-byte) and two
bytes (double-byte). Unless otherwise specified,
commands may be executed in any order.
The Most Significant Bit (MSB) is sent first. The mode in
which the D/C bit is defined varies with the type of serial
interface that is used.
Table 7
OM6208
Instruction set
Instructions not expressly defined in this table and reserved instructions must not be used.
COMMAND BYTE
COMMAND NAME
D/C
(MSB)
D6
D5
D4
D3
D2
D1
D0
(LSB)
FUNCTION DESCRIPTION
Write data
1
D7
D6
D5
D4
D3
D2
D1
D0
RAM data
Horizontal addressing
0
0
0
0
0
X3
X2
X1
X0
set X address; lower 4 bits
1
δ(1)
X6
X5
X4
set X address; upper 3 bits
δ(1)
charge pump on/off
Horizontal addressing
0
0
0
0
Power control
0
0
0
1
0
1
PC
δ(1)
Charge pump control
0
0
0
1
1
1
1
0
1
0
δ(1)
δ(1)
δ(1)
δ(1)
δ(1)
δ(1)
S1
S0
set multiplication factor
Set VPR
0
0
0
1
0
0
Vpr7
Vpr6
Vpr5
write Vpr register
Set VPR
0
1
0
0
Vpr4
Vpr3
Vpr2
Vpr1
Vpr0
write Vpr register
Set bias
0
0
0
1
1
0
BS2
BS1
BS0
set bias
Display mode
0
1
0
1
0
0
1
0
DAL
all on/normal display
Display mode
0
1
0
1
0
0
1
1
E
Display mode
0
1
0
1
0
1
1
1
DON
display ON/OFF
Data order
0
1
0
1
0
1
0
0
DOR
swap RAM MSB/LSB order
RAM addressing
0
1
0
1
0
1
0
1
V
vertical or horizontal mode
Vertical addressing
0
1
0
1
1
Y3
Y2
Y1
Y0
set Y address
normal/inverse display
Vertical addressing
0
0
0
1
1
1
1
1
Y4
set Y address
Vertical mirroring
0
1
1
0
0
MY
δ(1)
δ(1)
δ(1)
mirror Y
ID read
0
1
1
0
1
1
0
1
0
identification: ID1(2)(3)
ID read
0
1
1
0
1
1
0
1
1
identification: ID2(2)(3)
ID read
0
1
1
0
1
1
1
0
0
identification: ID3(2)
ID read
0
1
1
0
1
1
1
0
1
identification: ID4(2)
Temperature sense
0
1
1
0
1
1
1
1
0
temperature read back
VM read
0
1
1
0
1
1
1
1
1
voltage monitor(3)(4)
Row control
0
1
1
1
0
0
0
0
BRS
2003 feb 10
25
swap the bottom rows
Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
OM6208
COMMAND BYTE
COMMAND NAME
D/C
(MSB)
D6
D5
D4
D3
D2
D1
D0
(LSB)
FUNCTION DESCRIPTION
Software reset
0
1
1
1
0
0
0
1
0
internal reset
NOP
0
1
1
1
0
0
0
1
1
no operation
Display data length
0
1
1
1
0
1
0
0
0
0
display data length for 3-line
SPI
D7
D6
D5
D4
D3
D2
D1
D0
Temperature
compensation
0
0
0
1
1
1
0
0
0
0
δ(1)
Temperature
compensation
0
0
0
δ(1)
0
0
Frame frequency
range, oscillator tune
and mode
SLB2 SLB1 SLB0
0
1
1
1
SLD2 SLD1 SLD0
0
1
δ(1)
δ(1)
SLA2 SLA1
0
0
SLC2 SLC1
SLA0
1
SLC0
1
1
1
0
0
FR2
FR1
FR0
set TC slopes A and B (SLA
and SLB)
set TC slopes C and D
(SLC and SLD)
frame frequency range and
oscillator tune and working
mode
0
MOD
T2
T1
T0
δ(1)
Temperature
compensation enable
0
1
1
1
0
1
0
1
TCE
Oscillator selection
0
0
0
1
1
1
0
1
EC
external oscillator
OTP programming
0
1
1
1
1
0
0
OSE
CAL
MM
enter calibration mode and
control programming
LOAD 0
0
1
1
0
1
1
0
0
0
write 0 to shift register
LOAD 1
0
1
1
0
1
1
0
0
1
write 1 to shift register
Select factory
defaults
0
1
1
1
0
1
1
0
SFD
enable/disable defaults
N-line inversion and
super-frame inversion
0
1
0
1
0
1
1
0
1
0
FI
NL6
NL5
NL4
NL3
NL2
NL1
NL0
N-line inversion and
super-frame Inversion
0
0
1
δ(1)
δ(1)
δ(1)
δ(1)
δ(1)
δ(1)
reserved
δ(1)
reserved
enable/disable temperature
compensation
0
1
0
1
0
0
0
δ(1)
0
1
0
1
0
1
1
0
0
reserved
δ(1)
δ(1)
reserved
0
1
1
0
1
0
δ(1)
0
1
1
1
0
1
0
0
1
reserved
0
1
1
1
0
0
1
δ(1)
δ(1)
reserved
1
1
δ(1)
reserved
δ(1)
reserved for testing
δ(1)
reserved for testing
0
1
1
1
0
1
0
1
1
1
1
0
1
δ(1)
0
1
1
1
1
1
δ(1)
δ(1)
Notes
1. δ = don’t care.
2. ID1, ID2, ID3, ID4 and VM are read back via interface as described in Section 9.2.3. Reading back with I2C-bus
interface is possible for temperature, ID1, ID2 and VM, as described in Section 10.4.
3. ID1 will always return to logic 0; ID2 will always return to logic 1. The VM bit is set to logic 1 when the charge pump
is running and logic 0 when the charge pump is not running.
4. If the Factory Defaults bit (MMFD) has been programmed to 1, then the SFD instruction is ignored and the device
will always use the OTP default data.
2003 feb 10
26
Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
11.1
OM6208
Description of command bits
Table 8
Bit descriptions
BIT
0
1
RESET STATE
DON
display off
display on
0
E
normal display
inverse video mode
0
DAL
normal display
all pixel on
1
MY
no Y mirroring
Y mirroring
0
PC
charge pump off
charge pump on
0
DOR
normal data order
MSB/LSB transposed for RAM data
0
V
horizontal addressing
vertical addressing
0
BRS
bottom rows are not mirrored
bottom rows are mirrored
0
EC
internal oscillator is selected
external clock to be used
0
CALMM
exit OTP calibration mode
enter OTP calibration mode(1)
0
TCE
disable temperature compensation
enable temperature compensation
1
OSE
disable OTP programmed voltage
enable OTP programmed voltage(1)
0
SFD
use interface programmed data
use OTP programmed data(2)
0
MOD
grey-scale mode is selected
black-and-white mode is selected
0
SLA[2:0]
select slope for segment A
000(2)
SLB[2:0]
select slope for segment B
000(2)
SLC[2:0]
select slope for segment C
000(2)
SLD[2:0]
select slope for segment D
000(2)
sets X address (column) for writing in the RAM
0000000
X[6:0]
Y[4:0]
sets Y address (bank) for writing in the RAM
00000
S[1:0]
charge pump multiplication factor (see Table 10)
0000(2)
NL[6:0]
sets N-line inversion (see Table 18)
0001101(2)
FR[2:0]
sets frame frequency range (see Table 11)
001(2)(3)
T[2:0]
oscillator tune; sets frame frequency within a range (see Table 11)
110(2)(3)
D[7:0]
display data length for 3-line SPI interface
00000000
VPR register
00000000(2)
bias setting level (see Table 13)
000(2)
super-frame inversion
0(2)
VPR[7:0]
BS[2:0]
FI
Notes
1. Calibration mode may not be entered if the SEAL bit has been set. Programming is only possible when in calibration
mode.
2. These values can be set by the module maker. If the factory defaults OTP bit (MMFD) has been set then these values
cannot be changed via the interface. Otherwise, the OTP data will only be used if bit SFD is set to 1.
3. FR[2:0] = 001 and T[2:0] = 110 gives 150 Hz as default frame frequency.
2003 feb 10
27
Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
Table 9
Table 11 Frame frequencies for fosc = 400 kHz
Display and power mode bits DON, DAL and E
DON
DAL(1)
E(2)
DESCRIPTION
0
0
X(3)
display off; all row and column
outputs at VSS; oscillator on;
HV generator enabled
0
X(3)
1
OM6208
FR2
FR1
FR0
DIVISION
RATIO
fframe (Hz)
0
0
0
2448
163.4
0
0
1
3265
122.5
Power-down mode; display off;
all row and column outputs at
VSS; oscillator off;
HV generator disabled
0
1
0
4082
98.0
0
1
1
4896
81.7
1
0
0
5714
70.0
7340
54.5
1
0
0
normal display mode
1
0
1
1
0
1
inverse display mode
1
1
0
8968
44.6
1
X(3)
all pixels on
1
1
1
11428
35.0
1
Notes
Oscillator tuning is controlled by the parameter T[2:0]. As
a result of oscillator tuning, fOSC is increased by
approximately 4% per step according to the equation
1. The DAL bit has priority over the E bit.
2. Refer also to Table 17.
3. X = don’t care.
f OSC = 400 kHz × ( 1 + 0.04 × T )
Table 10 Multiplication settings for charge pump
11.2
S1
S0
VOLTAGE
MULTIPLIER
0
0
4×
0
1
5×
1
0
6×
1
1
7×
where T is the decimal value of T[2:0].
Example. For the default values given in Table 8
(i.e. FR[2:0] = 001 and T[2:0] = 110) the selected frame
frequency is 122.5 Hz × (1 + 6 × 0.04) = 151.9 Hz.
Equation (1) shows the typical value of the oscillator
frequency. The accuracy of this parameter is defined in
Chapter 15. The frame frequency accuracy results directly
from the oscillator accuracy.
Frame frequency setting and oscillator tuning
11.3
Grey-scale mode and black-and-white mode require
different frame frequencies. The appropriate frame
frequency (fframe) is derived from the oscillator frequency
(fosc) using a presettable divider as shown in the equation
f frame
(1)
Initialization
Immediately following power-on, all internal registers and
the RAM content are undefined. A reset pulse must be
applied to the RES pad.
Reset is accomplished by applying an external reset pulse
(active LOW) to the RES input. When reset occurs within
the specified time, all internal registers are reset, however
the RAM remains undefined. The state after reset is
described in Section 11.4.
f OSC
= -------------------------------division ratio
There are eight possible divider settings and these are
selected by the parameter FR[2:0], see Table 11.
At power-on, the RES input must be ≤0.3VDD1 when VDD1
reaches VDD(min) (or higher) within the maximum time tVHRL
after VDD1 going HIGH (see Fig.37). Alternatively a reset
pulse can be applied when VDD1 is stable.
A reset can also be made by sending a reset command.
This command can be used during normal operation but
not to initialize the chip after power-on.
After power-off, the RES input must not be HIGH when
VDD1 is not HIGH.
2003 feb 10
28
Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
11.4
11.7
Reset function
OM6208
Set Y address of RAM
Y[4:0] defines the Y address of the display RAM.
After reset, the LCD driver is in Power-down mode, the
RAM is undefined and the internal registers have the
status shown in Table 8.
Table 12 Y address range
Y4
Y3
Y2
Y1
Y0
DISPLAY RAM
0
0
0
0
0
bank 0
• All LCD outputs (row and column outputs) are at VSS
(display off)
0
0
0
0
1
bank 1
0
0
0
1
0
bank 2
• Bias generator and VLCD generator are switched off;
external VLCD supply can be applied or disconnected
0
0
0
1
1
bank 3
0
0
1
0
0
bank 4
• Oscillator is off (an external clock is possible)
0
0
1
0
1
bank 5
• RAM contents are unchanged; RAM data can be written
0
0
1
1
0
bank 6
• VLCD is discharged to VSS.
0
0
1
1
1
bank 7
0
1
0
0
0
bank 8
0
1
0
0
1
bank 9
0
1
0
1
0
bank 10
0
1
0
1
1
bank 11
0
1
1
0
0
bank 12
0
1
1
0
1
bank 13
0
1
1
1
0
bank 14
0
1
1
1
1
bank 15
1
0
0
0
1
bank 16
11.5
Power-down mode
In the Power-down mode:
Power-down mode is active when the display is off
(DON = 0) and all the pixels are on (DAL = 1).
11.6
Display Control
The bits DON, E and DAL select the display mode (see
Table 9).
11.6.1
HORIZONTAL MIRRORING
When the MX input is at logic 0, the display RAM is written
from left to right (X = 0 is on the left side).
When the MX input is set to 1, the display RAM is written
from right to left (X = 0 is on the right side).
11.8
The X address points to the columns. The range of X is
0 to 95.
The MX input value has an impact on the way the RAM is
written: if a horizontal mirroring of the display is desired,
the RAM must be rewritten after changing the MX pad
value.
11.6.2
11.9
Bias levels
The OM6208 is a grey-scale driver able to provide different
bias voltage levels for rows and columns. The row voltage
values are VLCD, VSS and VC, generated using the resistor
chain shown in Fig.28.
VERTICAL MIRRORING
When the MY bit is set to logic 1, the display is mirrored
vertically.
The five levels used to drive the columns are shown in
Fig.28. These are V2L, V1L, VC, V1H and V2H, all of which
depend on the value of alpha. Table 13 shows all possible
combinations of alpha settable by programming the
BS[2:0] bits.
A change of this bit has an immediate effect on the display,
it is not necessary to rewrite RAM for the effect to take
place.
2003 feb 10
Set X address of RAM
29
Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
handbook, halfpage
OM6208
VLCD = Vrow(max)
αR
V2H
R
F
G
V1H
R
VC
R
V1L
R
V2L
αR
VSS = Vrow(min)
MGW832
α is in the range 0.0 to 1.05.
Fig.28 Bias system.
Because the voltage level of the row depends on the
programmed bias level, it can be seen that F ≥ G
Table 13 Bias setting levels for p = 4
BS2
BS1
BS0
F/G
α
a
0
0
0
1.000
0.00
4.00
0
0
1
1.075
0.15
4.30
0
1
0
1.150
0.30
4.60
0
1
1
1.225
0.45
4.90
1
0
0
1.300
0.60
5.20
1
0
1
1.375
0.75
5.50
1
1
0
1.450
0.90
5.80
1
1
1
1.525
1.05
6.10
The situation where F = G occurs only when BS[2:0] is
zero and alpha is zero. In this case αR = 0 and G = F;
therefore V2H = VLCD and V2L = VSS, also two of the
internal buffers are no longer needed and therefore are
switched off to reduce power consumption.
The relationship between F and G is defined by the
parameter a (indicated in Table 13) and p as follows
F
a
---- = --G
p
It can be seen from Fig.28 that
Each of the eight possible values of alpha results in a
different set of five values for the column voltages.
F
a
(α + 2)
α
---- = --- = ------------------ = 1 + --G
p
2
2
Bias level F (see Fig.28) is half of the maximum row
voltage level as shown by the equation
or
V LCD
F = -----------2
α
a =  --- + 1 ⋅ p
2

Figure 28 also shows that G is used to define the
maximum column voltage level related to the VC level.
2003 feb 10
a
α =  --- – 1 ⋅ 2
p

The BS[2:0] bias bits can be selected by a command and
also can be programmed by OTP.
30
Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
The relationship between the parameters F, p, a and N
(number of rows of the display) and the Von(rms) and
Voff(rms) voltage values according to the typical LCD
properties of the pixel are shown in equations (2) and (3).
Table 14 Parameters of VLCD
2
F p ⋅ ( a + N + 2a )
V on(rms) = --- ⋅ ------------------------------------------N
a
V off(rms)
UNIT
b
0.03
V
a
3
V
As the programming range for the internally generated
VLCD allows values above the maximum allowed VLCD
(9 V), the user has to ensure, while setting the VPR
register and selecting the temperature compensation,
that under all conditions and including all tolerances
VLCD remains below 9.0 V.
(3)
11.10.1 LCD DRIVE VOLTAGE GENERATION
VLCD may be supplied externally or generated internally by
the on-chip capacitive charge pump. OM6208 features
on-chip capacitors resulting in a minimum of external
components required for operation (see Chapter 16).
Also, because the programming range for the internally
generated VLCD allows values below the minimum
allowed VLCD (5 V), the user has to ensure, while setting
the VPR register and selecting the temperature
compensation, that under all conditions and including all
tolerances VLCD remains above 5.0 V.
The ‘power control’ instruction may be used to switch VLCD
generation on or off. The charge pump control instruction
may be used to select the required voltage multiplication
factor. The ‘set VPR’ instruction is used for programming
the LCD drive voltage VLCD.
The generation of VLCD in OM6208 is illustrated in Fig.29.
This shows all factors that effect VLCD generation,
including the 6 bits of MMVOPCAL (from OTP) and the
7 bits resulting from the temperature compensation
mechanism. Equations summarizing all factors are
V OP = V PR + MMVOPCAL + V T
(4)
and
(5)
Where:
VPR[7:0] is set in the instruction decoder and is the
programmed VPR register value as an unsigned number
MMVOPCAL[5:0] is the value of the offset stored in the
OTP cells in twos complement format
VT[7:0] in twos complement format comes from the
temperature compensation block (see Table 16)
a and b are fixed constant values (see Table 14).
2003 feb 10
VALUE
CAUTION
11.10 LCD drive voltage
V LCD = V OP ⋅ b + a
SYMBOL
(2)
2
F p ⋅ ( a + N – 2a )
= --- ⋅ -----------------------------------------N
a
OM6208
31
Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
OM6208
measured temperature slopes
handbook, full pagewidth
B
A
C
D
VT
TEMPERATURE TD
MEASUREMENT
VT
7
−40
0
+85
8
T (°C)
TEMPERATURE COMPENSATION
MMVOPCAL [5:0]
b
a
VPR [7:0]
8
8
VLCD
VOP
MGW833
Fig.29 VLCD generation including the temperature compensation and OTP calibration.
handbook, full pagewidth
MGT847
V LCD
b
a
00
01
02
03
04
05
06
...
...
FD
FE
VPR[7:0] programming: 00 to FF (HEX).
Assuming MMVOPCAL = 0 and VT = 0 V.
Fig.30 VLCD programming of OM6208 shown as plots of equations (4) and (5).
2003 feb 10
32
FF
V OP
Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
OM6208
Table 15 Temperature coefficients
Slopes of VLCD are calculated from equations (4), (5), (6)
and Table 16.
11.10.2 TEMPERATURE MEASUREMENT
The temperature measurement is repeated every
10 seconds. The measured value is provided as a 7-bit
digital value TD[6:0] which can be read back via the
interface. The temperature can be determined from
TD[6:0] using the equation
T = ( 1.875 × TD – 40 )°C
(6)
SLA, SLB, SLC
and SLD
MA, MB, MC
and MD
SLOPE
(mV/K)
111
3.00
−48
110
2.00
−32
101
1.25
−20
100
1.00
−16
011
0.75
−12
010
0.50
−8
001
0.25
−4
000
0.00
0
11.10.3 TEMPERATURE COMPENSATION
Due to the temperature dependency of the liquid crystal’s
viscosity, the LCD controlling voltage VLCD may have to be
adjusted at different temperatures to maintain optimal
contrast.
Internal temperature compensation may be enabled via
the ‘temperature compensation enable’ instruction. When
the internal temperature compensation is applied (TCE bit
is set to 1) then according to Equation (4) the VLCD
depends also on VT (the temperature compensation
component defined in Table 16), otherwise VT is
considered to be 0 V.
Temperature compensation is implemented by adding an
offset VT to the VPR value (additionally to the OTP
calibration offset MMVOPCAL).
The final result for VLCD calculation is an 8-bit positive
number as shown in equations (4) and (5). Care must be
taken by the user to ensure that the ranges of VPR,
MMVOPCAL and VT do not cause clipping and hence
undesired results. The adder stages will not permit
overflow or underflow and will clamp results to either end
of the range.
After the reset, the VLCD is fixed because the VPR is a
register that is reset to zero. The MMVOPCAL is also set
to zero because this comes from the registers of OTP that
are not refreshed yet, also VT is evaluated after the reset
because the temperature measurement block supplies a
TD value that is the default value stored in the register
after the reset.
The temperature read-out generates a 7-bit result,
TD[6:0]. For temperatures below −40 °C, the value of TD
is zero. For temperatures above 79 °C, the value of TD is
higher than 63, but for VT calibration the value TD = 63 is
used.
The four temperature coefficients MA, MB, MC and MD
correspond to four equally spaced temperature regions.
Each coefficient can be selected from a choice of eight
different slopes, or multiplication factors. Each one of
these coefficients may be independently selected by the
user via the ‘temperature compensation enable’
instruction. The default for each slope register can be
stored in OTP.
The offset value VT may be calculated from Table 16. The
effect on VLCD can be calculated by multiplying the offset
value with the value of b (from Table 14).
For example, if T = −10 °C, TD = 16 and MB = 1.25 then
VLCDoffset = 30 mV × (32 − 16) × 1.25 = 600 mV.
Table 16 Temperature compensation equations
TEMPERATURE RANGE (°C)
2003 feb 10
TD RANGE
EQUATION
−40 to −11
0 to 15
VT = (16 × MB) + MA × (16 − TD)
−10 to +19
16 to 31
VT = (32 − TD) × MB
+20 to +49
32 to 47
VT = −(TD − 32) × MC
+50 to +79
48 to 63
VT = −(16 × MC) + MD × (TD − 48)
33
Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
handbook, full pagewidth
A
B
OM6208
C
D
MGW834
VLCD
−40
−10
20
50
80
T (°C)
Fig.31 Example of segmented temperature coefficients.
11.11 Grey-scale mode and black-and-white mode
Table 17 Grey-scale levels with FRC
It is possible to set via command the working mode of the
OM6208. This is by setting the MOD bit of the ‘frame
frequency’ instruction, oscillator tune and mode.
By default, the MOD bit is set to logic 0 and grey-scale
mode is selected. In that mode, grey-scales are generated
using Frame Rate Control (FRC). Three frames together
form a super-frame. The frame frequency is adjustable but
all three frames have the same duration. A grey-scale is
generated by selecting either 0, 1, 2 or all 3 frames (see
Table 17).
GS[1:0]
SUPER-FRAME(1)
GREY-SCALE
LEVELS
Normal mode (E = 0)
0
0
000
white
0
1
001
light grey
1
0
110
dark grey
1
1
111
black
Inverse mode (E = 1)
If the MOD bit is set to logic 1 black-and-white mode is
selected, meaning that only black-and-white levels are
generated and only one frame type is sent to the display.
Thus only the MSBs stored in the RAM are used for all
three frames. The LSBs are ignored. Thus the way the
data is stored in the RAM is the same as for grey-scale.
As all frames are identical the frame frequency may be
reduced (see Table 11).
0
0
111
black
0
1
110
dark grey
1
0
001
light grey
1
1
000
white
Note
1. The first and second frames in each super-frame are
related to the MSB of GS[1:0] (GS = 11); the third
frame is related to the LSB (GS = 00).
11.12 N-line inversion and frame inversion
N-line inversion can be set from 0 to 127 as shown in
Table 18.
2003 feb 10
34
Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
OM6208
Table 18 N-line inversion
NL6
NL5
NL4
NL3
NL2
NL1
NL0
FI
0-line inversion
0
0
0
0
0
0
0
0
1-line inversion
0
0
0
0
0
0
1
0
2-line inversion
0
0
0
0
0
1
0
0
3-line inversion
0
0
0
0
0
1
1
0
4-line inversion
0
0
0
0
1
0
0
0
5-line inversion
0
0
0
0
1
0
1
0
6-line inversion
0
0
0
0
1
1
0
0
7-line inversion
0
0
0
0
1
1
1
0
8-line inversion
0
0
0
1
0
0
0
0
:
:
:
:
:
:
:
:
:
66-line inversion
1
0
0
0
0
1
0
0
67-line inversion
1
0
0
0
0
1
1
0
68-line inversion
1
0
0
0
1
0
0
0
:
:
:
:
:
:
:
:
:
127-line inversion
0
1
0
0
0
0
0
0
0 only super-frame inversion
0
0
0
0
0
0
0
1
1-line inversion and super-frame inversion
0
0
0
0
0
0
1
1
2-line inversion and super-frame inversion
0
0
0
0
0
1
0
1
3-line inversion and super-frame inversion
0
0
0
0
0
1
1
1
4-line inversion and super-frame inversion
0
0
0
0
1
0
0
1
5-line inversion and super-frame inversion
0
0
0
0
1
0
1
1
6-line inversion and super-frame inversion
0
0
0
0
1
1
0
1
7-line inversion and super-frame inversion
0
0
0
0
1
1
1
1
8-line inversion and super-frame inversion
0
0
0
1
0
0
0
1
INVERSION AFTER
:
:
:
:
:
:
:
:
:
66-line inversion and super-frame inversion
1
0
0
0
0
1
0
1
67-line inversion and super-frame inversion
1
0
0
0
0
1
1
1
68-line inversion and super-frame inversion
1
0
0
0
1
0
0
1
:
:
:
:
:
:
:
:
:
127-line inversion and super-frame inversion
1
1
1
1
1
1
1
1
Notes
1. In grey-scale mode the super-frame inversion is performed if bit FI in the ‘N-line inversion and super-frame inversion’
instruction is set to logic 1. In black-and-white mode, the super-frame inversion continues in groups of three frames.
2. NL[6:0] may be set in the range 0 to 127. If NL = 0, then no line inversion is performed; if NL = MUX rate = 68 then
N-line inversion is equal to frame inversion.
3. With N-line inversion the output signal polarity changes every N row pulse periods (with p = 4 this means inversion
occurs after every 4 × NL rows of the display).
4. If after a super-frame FI = 1 and there is an inversion due to an N-line inversion, this inversion occurs only once.
2003 feb 10
35
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Table 19 Example showing line inversions in one super-frame: NL = 3, MUX = 20 and p = 4
SUPER-FRAME 1
FRAME 1
FRAME 2
FRAME 3
SUB
FRAME 0
SUB
FRAME 1
SUB
FRAME 2
SUB
FRAME 3
SUB
FRAME 0
SUB
FRAME 1
SUB
FRAME 2
SUB
FRAME 3
SUB
FRAME 0
SUB
FRAME 1
SUB
FRAME 2
SUB
FRAME 3
+
−
−
−
+
+
+
−
−
−
+
+
+
−
−
−
+
+
+
−
−
−
+
+
+
−
−
−
+
+
+
−
−
−
+
+
+
−
−
−
+
+
+
−
−
−
+
+
+
−
+
−
−
+
+
−
+
−
−
+
36
+
+
−
−
−
+
+
+
−
−
−
+
+
+
−
−
−
+
+
+
−
−
−
+
+
+
−
−
−
+
+
+
−
−
−
+
+
+
+
−
−
−
+
+
+
−
−
−
+
+
+
−
−
−
+
+
+
−
−
−
+
+
+
−
−
−
+
+
+
−
−
−
+
+
+
−
−
−
+
+
+
−
−
−
−
+
+
+
−
−
−
+
+
+
−
−
−
+
+
+
−
−
−
+
+
+
−
−
−
+
+
+
−
−
−
+
+
+
−
−
−
+
+
−
+
−
−
+
+
−
+
Philips Semiconductors
Super-frame inversion requires that the state of the previous super-frame is remembered, i.e., if the previous super-frame started ‘+’, then the next
super-frame must start ‘−’. This has priority over inversions triggered by the counter, so that if the counter triggers an inversion at a super-frame
boundary and super-frame inversion is active, then the two do not cancel each other out but the super-frame inversion has priority.
65 x 96 pixels matrix grey-scale LCD driver
2003 feb 10
The example in Table 19 shows the first super-frame with the settings NL = 3, MUX = 20 and p = 4 applied; the super-frame contains three frames. The
next super-frame will be a repeat of the first super-frame if bit FI is set to logic 0 (no super-frame inversion), or will start with the first frame having the
opposite sign if bit FI is at logic 1 (super-frame inversion) and the N-line inversion counter will also restart.
−
+
+
+
−
−
−
+
+
+
−
−
−
+
+
+
−
−
−
+
+
+
−
−
−
+
+
+
−
−
−
+
+
+
−
−
−
+
+
+
−
−
−
+
+
+
−
Product specification
−
OM6208
−
Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
OM6208
12 LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); notes 1 and 2.
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
VDD1
supply voltage (logic circuits)
−0.5
+6.5
V
VDD2,
VDD3
supply voltage (analog circuits)
−0.5
+5.0
V
VLCD
LCD supply voltage
−0.5
+10.0
V
VI
input voltage (any pad)
−0.5
VDD1 + 0.5
V
ISS
ground supply current
−50
+50
mA
II, IO
DC input or output current
−10
+10
mA
Ptot
total power dissipation
−
300
mW
P/out
power dissipation per output
−
30
mW
Tstg
storage temperature
−65
+150
°C
Notes
1. Stresses above those listed under limiting values may cause permanent damage to the device.
2. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to
VSS unless otherwise noted.
13 HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling MOS devices (see “Handling MOS devices”).
14 DC CHARACTERISTICS
VDD1 = 1.7 to 3.3 V; VSS = 0 V; VLCD = 5 to 9.0 V; Tamb = −40 to +85 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VDD1
supply voltage (logic circuits)
1.7
−
3.3
V
VDD2,
VDD3
supply voltage (analog circuits)
2.4
−
4.5
V
VLCDIN
LCD supply voltage input
LCD voltage supplied
externally; high voltage
generator disabled
−
−
9.0
V
VLCDOUT
LCD supply voltage output
LCD voltage generated
internally; high voltage
generator enabled; note 1
−
−
9.0
V
VLCD(tol)
tolerance of generated VLCD
with calibration; note 2
−70
−
+70
mV
IDD
supply current; pins VDD1,
VDD2 and VDD3
Power-down mode (all static
currents switched off); note 3
−
3
−
µA
IDD1
supply current; pin VDD1
notes 3 and 4
−
20
40
µA
IDD2, IDD3
supply current; pins VDD2
and VDD3
notes 3 and 4
DC load on VLCD = 300 µA
−
2400
−
µA
DC load on VLCD = 170 µA
−
1200
2000
µA
supply current; pin VDD2
notes 4 and 5
−
360
−
µA
IDD2
DC load on VLCD = 32 µA
2003 feb 10
37
Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
SYMBOL
PARAMETER
OM6208
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Logic circuits
VOL
LOW-level output voltage
IOL = 0.5 mA
VSS
−
0.2VDD1
V
VOH
HIGH-level output voltage
IOH = −0.5 mA
0.8VDD1
−
VDD1
V
VIL
LOW-level input voltage
VSS
−
0.3VDD1
V
VIH
HIGH-level input voltage
IL
leakage current
0.7VDD1
−
VDD1
V
VI = VDD1 or VSS
−1
−
+1
µA
Column and row outputs
Rcol
column output resistance
C0 to C95
VLCD = 7 V
−
3
7
kΩ
Rrow
row output resistance
R0 to R64
VLCD = 7 V; load 10 µA;
outputs tested one at a time
−
2
5
kΩ
Vcol
bias tolerance C0 to C95
−70
0
+70
mV
Vrow
bias tolerance R0 to R64
−70
0
+70
mV
−8
−
+8
°C
Temperature read-back
∆TRB
temperature read-back
tolerance
Notes
1. The maximum possible VLCD voltage that may be generated is dependent on voltage, temperature and (display) load.
2. Valid for the values of temperature, VPR and temperature compensation used at calibration.
3. VDD1 = 1.8 V; VDD2 = 2.7 V; inputs at VDD1 or VSS; interface inactive; internal VLCD generation.
4. Grey-scale or black-and-white mode; display mode ON; all outputs open-circuit; BS[2:0] = 000.
5. VLCD = 6.84 V; default frequency; data pattern in RAM is with all bytes = AA(HEX); multiplication factor = 5.
2003 feb 10
38
Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
OM6208
15 AC CHARACTERISTICS
VDD1 = 1.7 to 3.3 V; VSS = 0 V; VLCD = max. 9.0 V; Tamb = −40 to +85 °C; all timings are between 20% and 80% of VDD1;
unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
see Section 11.2, equation (1)
MIN.
TYP.
MAX.
400(1)
496(2)
512(3)
UNIT
kHz
400
496
512
kHz
fOSC
oscillator frequency selection
fEXT
external clock frequency
fframe
frame frequency selection
default frequency: FR[2:0] = 001;
T[2:0] = 110
35
151.9
210
Hz
∆fOSC,
∆fframe
accuracy of oscillator frequency
and frame frequency
VDD1 = 2.8 V;
Tamb = −20 to +70 °C
−15
−
+15
%
Serial timing characteristics: 3-line and 4-line SPI and serial interface; VDD1 = 1.8 to 3.3 V; see Figs 32 to 35
−
−
6.5
MHz
SCLK clock cycle time
153
−
−
ns
SCLK pulse width high
70
−
−
ns
tPWL1
SCLK pulse width low
60
−
−
ns
tS2
SCE set-up time
60
−
−
ns
tH2
SCE hold time
60
−
−
ns
tPWH2
SCE minimum HIGH time
50
−
−
ns
tS4
SDATA set-up time
60
−
−
ns
tH4
SDATA hold time
60
−
−
ns
tS3
data/command set-up time
60
−
−
ns
tH3
data/command hold time
60
−
−
ns
tS1
SDATA set-up time
50
−
−
ns
tH1
SDATA hold time
70
−
−
ns
t1
SDO access time
−
−
50
ns
t2
SDO disable time
−
−
50
ns
t3
SCE hold time
50
−
−
ns
t4
SDO disable time
3-line serial interface
25
−
110
ns
Cb
capacitive load for SDO
note 4
−
−
50
pF
Rb
series resistance for SDO
note 4
−
−
500
Ω
fSCLK
clock frequency
TCYC
tPWH1
3-line SPI or 4-line SPI interface
I2C-bus interface timing characteristics; VDD1 = 1.8 to 3.3 V; see Fig.36
fSCLH
SCLH clock frequency
0
−
3.4
MHz
tSU;STA
set-up time (repeated) START
condition
160
−
−
ns
tHD;STA
hold time (repeated) START
condition
160
−
−
ns
tLOW
LOW period of the SCLH clock
160
−
−
ns
tHIGH
HIGH period of the SCLH clock
60
−
−
ns
tSU;DAT
data set-up time
10
−
−
ns
tHD;DAT
data hold time
15
−
70
ns
trDA
rise time of SDAH signal
20
−
80
ns
tfDA
fall time of SDAH signal
20
−
80
ns
2003 feb 10
39
Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
SYMBOL
PARAMETER
OM6208
CONDITIONS
MIN.
TYP.
MAX.
UNIT
160
−
−
ns
−
−
100
pF
capacitive load for SDAH + SDA
line and SCLH + SCL line
−
−
400
pF
tSW
tolerable spike width on bus
−
−
5
ns
VnL
noise margin at the LOW level for
each connected device (including
hysteresis)
0.1VDD −
−
V
VnH
noise margin at the HIGH level for
each connected device (including
hysteresis)
0.2VDD −
−
V
tSU;STO
set-up time for STOP condition
Cb
capacitive load for SDAH and
SCLH lines
note 5
RESET timing characteristics; see Fig.37
tVHRL
VDD to RES LOW
0(6)
−
1
µs
tRW
reset low pulse width
1000
−
−
ns
tRWS
reset pulse width spike
suppression
−
−
100
ns
Notes
1. fOSC defined for T[2:0] = 000.
2. fOSC defined for T[2:0] = 110 (default value).
3. fOSC defined for T[2:0] = 111.
4. Maximum value is for fSCLK = 6.5 MHz; series resistance includes ITO track + connector resistance + PCB.
5. Cb = 100 pF total capacitance of one bus line.
6. RES may be LOW before VDD1 goes HIGH.
2003 feb 10
40
Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
handbook, full pagewidth
t S2
OM6208
t H2
t PWH2
SCE
t S2
t PWL1
T cyc
t PWH1
SCLK
t H1
t S1
SDATA
MGU642
Fig.32 3-line serial interface timing.
t S2
handbook, full pagewidth
t H2
t PWH2
SCE
t S3
t H3
D/C
t S2
t PWL1
t PWH1
T cyc
SCLK
t S4
t H4
SDATA
MGU643
Fig.33 4-line SPI interface timing.
2003 feb 10
41
Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
OM6208
handbook, full pagewidth
SCE
t3
SCLK
t H1
t S1
SDATA
t1
t2
SDO
MCE174
Fig.34 3-line and 4-line SPI timing (read mode).
handbook, full pagewidth
SCE
t3
SCLK
t H1
t S1
SDATA
t1
t4
SDO
MCE175
Fig.35 3-line serial interface timing (read mode).
2003 feb 10
42
Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
handbook, full pagewidth
Sr
OM6208
Sr
trDA
tfDA
P
SDAH
tSU;STA
tHD;DAT
tSU;STO
tHD;STA
tSU;DAT
SCLH
tfCL
trCL1
(1)
trCL1
trCL
tHIGH
tLOW
tLOW
(1)
tHIGH
MGK871
= MCS current source pull-up
= Rp resistor pull-up
Fig.36 I2C-bus timing diagram (Hs-mode).
handbook, full pagewidth
VDD1
t RW
t RW
t RWS
RES
VDD1
t VHRL
t RW
t RW
RES
MGW835
Fig.37 Reset timing.
2003 feb 10
43
Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
OM6208
16 APPLICATION INFORMATION
16.3
16.1
In the following application examples, the required values
of the external capacitors are:
Protection from light
Application examples
Semiconductors are light sensitive. Exposure to light
sources can cause malfunction of the IC. In the application
it is therefore required to protect the IC from light. The
protection has to be done on all sides of the IC, i.e. front,
rear and all edges.
• CVDD, CVDD1 and CVDD2 = 1 µF minimum
16.2
When the internal charge pump is used, the VLCD lines
must be short-circuited externally to ensure that the
resistance between pads is zero. This is to allow the bias
system to work correctly when BS[2:0] is not 000.
• CVLCD = 1 µF minimum
• Higher capacitor values can be used for the supply.
Chip-on-glass displays
The pinning of the OM6208 has an optimal design for
single plane wiring, e.g. for chip-on-glass display modules.
handbook, full pagewidth
DISPLAY 65 × 96 pixels
96
33
VSS1
VSS2
VDD2,3
VDD1
OM6208
VLCDSENSE
VLCDOUT
VLCDIN
32
CVLCD
I/O
CVDD
VDD
VSS
MGW836
Fig.38 Application example using the internal charge pump and a single VDD source.
2003 feb 10
44
Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
OM6208
handbook, full pagewidth
DISPLAY 65 × 96 pixels
96
33
VSS1
VSS2
VDD1
VDD2,3
OM6208
C
VDD1 VDD1
I/O
VLCDSENSE
VLCDOUT
VLCDIN
32
CVLCD
CVDD2
VDD2
MGW837
VSS
Fig.39 Application example using the internal charge pump and two separate VDD sources (VDD1 and VDD2).
handbook, full pagewidth
DISPLAY 65 × 96 pixels
96
I/O
VSS1
VSS2
VDD2
VDD1
OM6208
33
VLCDSENSE
VLCDOUT
VLCDIN
32
CVDD
VDD
VSS
VLCDIN
MGW838
Fig.40 Application example using external high voltage generation.
2003 feb 10
45
Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
OM6208
17 MODULE MAKER PROGRAMMING
17.1
VLCD calibration
One Time Programmable (OTP) technology has been
implemented in the OM6208. This enables the module
maker to program some extended features of the OM6208
after it has been assembled on an LCD module.
Programming is made under the control of the interfaces
and the use of one special pin. This pin must be made
available on the module glass but does not need to be
accessed by the set maker.
The first OTP feature included is the ability to tune the
VLCD voltage with a 6-bit code (MMVOPCAL). This code is
implemented in twos complement notation giving rise to a
positive or negative offset to the VPR register. The adder in
the circuit has underflow and overflow protection. In the
event of an overflow, the output will be clamped to 255;
with an underflow, the output will be clamped to logic 0.
The final control to the high voltage generator, VOP, will be
the sum of all the calibration registers according to
Section 11.10, equation (4).
The OM6208 features the following module maker
programmable parameters:
• VLCD calibration
Table 20 VLCD calibration
• Default temperature compensation slopes
• Default charge pump multiplication factor
MMVOPCAL
• Default VPR value
5
4
3
2
1
DECIMAL
EQUIVALENT
0
• Default bias levels BS[2:0]
0
1
1
1
1
1
31
930
• Default frame frequency range in grey-scale mode
GFR[2:0]
0
1
1
1
1
0
30
900
0
1
1
1
0
1
29
870
• Default oscillator tuning in grey-scale mode GT[2:0]
• Default frame frequency in black-and-white mode
SFR[2:0]
• Default oscillator tune in black-and-white mode ST[2:0]
• Default N-line inversion NL[6:0]
• Default frame inversion FI
• Enable factory default FD
• Seal bit.
handbook, full pagewidth
Temperature compensation VT, 7 bit value
VLCD OFFSET
(mV)
:
:
:
:
:
:
:
:
0
0
0
0
1
0
2
60
0
0
0
0
0
1
1
30
0
0
0
0
0
0
0
0
1
1
1
1
1
1
−1
−30
1
1
1
1
1
0
−2
−60
:
:
:
:
:
:
:
:
1
0
0
0
1
0
−30
−900
1
0
0
0
0
1
−31
−930
1
0
0
0
0
0
−32
−960
range: − 64 to + 63
VT [6:0]
OTP VLCD calibration, 6 bit offset
range: −32 to + 31
+
MMVOPCAL [5:0]
VPR register, 8 bit value
VPR [7:0]
range: 0 to + 255
(usable range + 32 to + 224)
Fig.41 VLCD calibration.
2003 feb 10
46
VOP
range: 0 to + 255
MGW839
to high voltage
generator
Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
17.2
17.2.1
OM6208
• Default N-line inversion NL[6:0]
Factory defaults
• Default frame inversion FI
CONFIGURATION DERIVED FROM OTP CELLS
• Enable factory default FD
In some instances it is desirable that the configuration is
derived from OTP cells and not from user-configurable
registers. It is therefore possible to pre-define the following
features using the OTP facility:
• Seal bit.
The selection of the mode for factory defaults is made by
setting the factory default OTP cell bit MMFD.
• Default temperature compensation slopes
• Default charge pump multiplication factor
Table 21 Factory default bit MMFD
• Default VPR value
MMFD
ACTION
• Default bias levels BS[2:0]
0
configuration data is taken from the interface
• Default frame frequency range in grey-scale mode
GFR[2:0]
1
OTP values are used for configuration data
• Default oscillator tune in grey-scale mode GT[2:0]
The operation can be shown as a switch that selects
between two sources of data (see Fig.42). When the OTP
defaults are selected, changing the default values via the
interface is not possible.
• Default frame frequency in black-and-white mode
SFR[2:0]
• Default oscillator tune in black-and-white mode ST[2:0]
handbook, full pagewidth
FACTORY
DEFAULT
INTERFACE
INTERFACE
REGISTERS
e.g. SLA [2:0]
OTP DEFAULTS
e.g. SLA [2:0]
MMFD
=0
MMFD
=1
to temperature
compensation circuit
MGW840
Fig.42 Factory defaults.
2003 feb 10
47
Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
17.2.2
calibration mode. This seal bit, once programmed, cannot
be reversed, thus further changes in programmed values
are not possible. Applying the programming voltages when
not in CALMM mode has no effect on the programmed
values.
DEFAULTS FROM INTERFACE REGISTERS
Factory defaults available from user-configurable registers
are as follows:
• Temperature slope selection values are set by SLA[2:0],
SLB[2:0], SLC[2:0] and SLD[2:0]
• Default charge pump multiplication factor value is set by
S[1:0]
Table 22 Seal bit definition
SEAL BIT
• Default VPR value is set by VPR[7:0]
• Default bias level values are set by BS[2:0]
• Grey-scale mode default frame frequency and tuning
values are set by GFR[2:0] and GT[2:0]
17.4
• Black-and-white mode default frame frequency and
tuning values are set by SFR[2:0] and ST[2:0].
17.3
OM6208
ACTION
0
possible to enter calibration mode
1
calibration mode disabled
OTP architecture
The OTP circuitry in the OM6208 contains many bits of
data. The circuitry for one bit is called an OTP slice. Each
OTP slice consists of two main parts: the OTP cell (a
non-volatile memory cell) and the shift register cell (a
flip-flop). The OTP cells are accessible only through their
shift register cells: both reading from and writing to the
OTP cells are performed with the shift register cells, but
only the shift register cells are visible to the rest of the
circuit. The basic OTP architecture is shown in Fig.43.
Seal bit
The module maker programming is performed in a special
mode: the calibration mode (CALMM). This mode is
entered via a special interface command, CALMM. To
prevent wrongful programming, a seal bit has been
implemented which prevents the device from entering the
DATA TO THE CIRCUIT FOR
CONFIGURATION AND CALIBRATION
handbook, full pagewidth
OTP slice
SHIFT
REGISTER
FLIP-FLOP
read data
from the
OTP cell
SHIFT
REGISTER
DATA
INPUT
SHIFT
REGISTER
write data
to the
OTP cell
OTP CELLS
MGW841
OTP CELL
Fig.43 Basic OTP architecture.
2003 feb 10
48
Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
17.4.1
OM6208
The shifting of the data into the shift register is performed
in the special mode CALMM. In the OM6208, the CALMM
mode is entered through the CALMM command. Once in
the CALMM mode the data is shifted into the shift register
via the interface at the rate of 1-bit per command. After
transmitting the last bit and exiting the CALMM mode the
serial interface is again in the normal mode and all other
commands can be sent. Care should be taken that always
all bits of data (or a multiple of all bits) are transferred
before exiting the CALMM mode, otherwise the bits will be
in the wrong positions.
OTP OPERATIONAL EFFECTS
The OTP architecture allows the following operations:
• Reading data from the OTP cells. The content of the
non-volatile OTP cells is transferred to the shift register
where upon it may affect the OM6208 operation.
• Writing data to the OTP cells. First, all 9 bits of data are
shifted into the shift register via the interface. Then the
content of the shift register is transferred to the OTP
cells (there are some limitations related to storing data
in these cells, see Section 17.7).
• Checking calibration without writing to the OTP cells.
Shifting data into the shift register allows the effects on
the VLCD voltage to be observed.
In the shift register the value of the seal bit is, like the other
bits, always zero at reset. To make sure the security
feature works correctly, the CALMM command is disabled
until a Power-down mode has been left. Once a refresh is
completed, the seal bit value in the shift register is valid
and permission to enter CALMM mode can thus be
determined.
The reading of data from the OTP cells is initiated by
writing to the DON register. The OTP cells will not be
updated until the device leaves power down and the
oscillator starts. The reading operation needs up to 5 ms
to complete.
The bits are shifted into the shift register in a predefined
order as shown in Table 23.
Table 23 OTP bit order (See Fig.44 for a graphical representation)
POSITION
OTP CELL
POSITION
OTP CELL
POSITION
OTP CELL
1
MMVPR[7]
19
MMSLA[1]
37
MMGT[1]
2
MMVPR[6]
20
MMSLA[0]
38
MMGT[0]
3
MMVPR[5]
21
MMS[1]
39
MMSFR[2]
4
MMVPR[4]
22
MMS[0]
40
MMSFR[1]
5
MMVPR[3]
23
MMBS[2]
41
MMSFR[0]
6
MMVPR[2]
24
MMBS[1]
42
MMST[2]
7
MMVPR[1]
25
MMBS[0]
43
MMST[1]
8
MMVPR[0]
26
MMFD
44
MMST[0]
9
MMSLD[2]
27
MMVOPCAL[5]
45
MMNL[6]
10
MMSLD[1]
28
MMVOPCAL[4]
46
MMNL[5]
11
MMSLD[0]
29
MMVOPCAL[3]
47
MMNL[4]
12
MMSLC[2]
30
MMVOPCAL[2]
48
MMNL[3]
13
MMSLC[1]
31
MMVOPCAL[1]
49
MMNL[2]
14
MMSLC[0]
32
MMVOPCAL[0]
50
MMNL[1]
15
MMSLB[2]
33
MMGFR[2]
51
MMNL[0]
16
MMSLB[1]
34
MMGFR[1]
52
MMFI
17
MMSLB[0]
35
MMGFR[0]
53
SEAL
18
MMSLA[2]
36
MMGT[2]
−
−
2003 feb 10
49
Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
17.5
OM6208
Interface commands
Table 24 OTP instructions
These instructions are in addition to those in the Instruction set, Table 7.
COMMAND BYTE
NAME
ACTION
D/C
D7
D6
D5
D4
D3
D2
D1
D0
OTP
programming
0
1
1
1
1
0
0
OSE
DON
(refresh)
0
1
0
1
0
1
1
1
DON
Load 0
0
1
1
0
1
1
0
0
0
write 0 to shift
register
Load 1
0
1
1
0
1
1
0
0
1
write 1 to shift
register
17.5.1
CALMM INSTRUCTION
17.5.2
This instruction enters the device into the calibration
mode. This mode enables the shift register for loading and
allows programming of the non-volatile OTP cells to take
place. If the seal bit is set, then this mode cannot be
accessed and the instruction will be ignored. Once in
calibration mode, data may be loaded into the shift register
via the ‘LOAD0’ and ‘LOAD1’ instructions (on the falling
edge of SCLK).
display ON/OFF
REFRESH INSTRUCTION
The action of the ‘refresh’ instruction is to force the OTP
shift register to reload from the non-volatile OTP cells. This
instruction takes up to 5 ms to complete. During this time
all other instructions may be sent.
In the OM6208 the ‘refresh’ instruction is associated with
the ‘DON’ instruction so that the shift register is
automatically refreshed every time DON is enabled or
disabled.
The CALMM mode may be left by setting the CALMM bit
to logic 0. Reset will also clear this mode.
Note: If this instruction is sent while in power save mode,
the DON bit will be updated but the refreshing is delayed
until the device leaves power-down.
The programming can only take place when OTP Switch
Enable (OSE) has been set to logic 1. This bit enables the
VOTPPROG input to be passed to the OTP cells. This allows
VOTPGATE to be tied to SCLH/SCE on the module for
normal operation. Reset will also clear this mode.
2003 feb 10
CALMM enter calibration
mode and control
programming
50
Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
17.6
Example of filling the shift register
OM6208
mode the interface does not recognize commands in the
normal sense.
An example sequence of commands and data is shown in
Table 25. In this example the shift register is filled with the
following data: MMVPR = 11010000, and the seal bit
is logic 0.
After this sequence has been applied it is possible to
observe the impact of the data shifted in. The sequence
described is not useful for OTP programming because the
number of bits with the value logic 1’ is greater than that
allowed for programming (see Section 17.7). The shift
register contents after this action are shown in Fig.44.
It is assumed that the OM6208 has just been reset. After
transmitting the last bit, the OM6208 can exit or remain in
CALMM mode (see step 1). Note that while in CALMM
Table 25 Example sequence for filling the shift register
STEP
D/C
D7
D6
D5
D4
D3
D2
D1
D0
1
0
1
0
1
0
1
1
1
1
ACTION
exit power-down
2
wait 5 ms for refresh to take effect
3
0
1
1
1
1
0
0
0
1
enter CALMM mode
4
0
1
1
0
1
1
0
0
1
shift in data, first bit is MMVPR[7]; note 1
5
0
1
1
0
1
1
0
0
1
MMVPR[6]
6
0
1
1
0
1
1
0
0
0
MMVPR[5]
7
0
1
1
0
1
1
0
0
1
MMVPR[4]
8
0
1
1
0
1
1
0
0
0
MMVPR[3]
9
0
1
1
0
1
1
0
0
0
MMVPR[2]
:
:
:
:
:
:
:
:
:
:
57
0
1
1
0
1
1
0
0
1
MMFI
58
0
1
1
0
1
1
0
0
0
seal bit
59
0
1
1
1
1
0
0
0
0
exit CALMM mode
10
Note
1. The data for the bits is not in the correct shift register position until all bits have been sent.
OTP SHIFT REGISTER
handbook, full pagewidth
shifting
direction
MMNL [6:0]
SEAL BIT MMFI LSB
0
1
0
0
0
1
1
MSB
1
0
MMST MMSLD [2:0]
1
1
0
MMVPR [7:0]
LSB
1
0
0
0
0
1
0
MSB
1
1
MGW842
Fig.44 Shift register contents after example sequence of Table 25.
2003 feb 10
51
Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
17.7
Programming flow
OM6208
Although the order for programming cells is not significant,
it is recommended that the seal bit is programmed last.
Once this bit has been programmed it will not be possible
to re-enter the CALMM mode.
Programming is achieved whilst in CALMM mode and with
the application of the programming voltages. As the data
for programming the OTP cell is contained in the
corresponding shift register cell, the shift register cell must
be loaded with a logic 1 in order to program the
corresponding OTP cell. If the shift register cell contains
a logic 0, then no action will take place when the
programming voltages are applied.
During programming, a substantial current flows in the
VLCDIN pin. For this reason it is recommended
programming only one OTP cell at a time. This is achieved
by filling all but one shift register cells with logic 0.
The programming specification refers to the voltages at
the chip pads, therefore the contact resistance is
significant and must be considered by the user.
Once an OTP cell is programmed it cannot be
de-programmed. An already programmed cell (an OTP
cell containing a logic 1) must not be reprogrammed.
A sequence of commands and data for OTP programming
is shown as an example in Table 26.
Table 26 Sequence for OTP programming
This sequence assumes the OM6208 has just been reset.
STEP
D/C
D7
D6
D5
D4
D3
D2
D1
D0
1
0
1
0
1
0
1
1
1
1
2
ACTION
exit power-down (DON = 1)
wait 5 ms for refresh to take effect
3
0
1
1
1
1
0
0
1
1
enter CALMM mode and OSE
4
0
1
1
0
1
1
0
0
1
shift-in data, MMVPR[7] is first bit; note 1
5
0
1
1
0
1
1
0
0
0
MMVPR[6]
6
0
1
1
0
1
1
0
0
0
MMVPR[5]
7
0
1
1
0
1
1
0
0
0
MMVPR[4]
7
0
1
1
0
1
1
0
0
0
MMVPR[3]
9
0
1
1
0
1
1
0
0
0
MMVPR[2]
:
:
:
:
:
:
:
:
:
:
58
0
1
1
0
1
1
0
0
0
MMFI
59
0
1
1
0
1
1
0
1
0
seal bit
10
60
apply programming voltage at
pins VOTPPROG and VLCDIN according to
Section 17.8
Repeat steps 5 to 60 for each bit that should be programmed to 1
61
apply external reset
Note
1. The data for the bits is not in the correct shift register position until all the bits have been sent.
2003 feb 10
52
Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
17.8
OM6208
Programming specification
Table 27 Programming specification (refer to Fig.45)
SYMBOL
VOTPPROG
VLCDIN
PARAMETER
voltage applied to
pad VOTPPROG
voltage applied to
pad VLCDIN
CONDITION
MIN.
TYP.
MAX.
UNIT
VOTPPROG relative to VSS1;
note 1
programming active
11.0
programming inactive
11.5
12.0
V
VSS − 0.2 0
VDD1
V
programming active
9.0
9.5
10.0
V
programming inactive
VSS2
VDD2
4.5
V
−
850
1000
µA
VLCDIN relative to VSS1;
notes 1 and 2
ILCDIN
current drawn by pad VLCDIN
during programming
IOTPPROG
current drawn by
pad VOTPPROG during
programming
−
100
200
µA
TPROG
ambient temperature during
programming
0
25
40
°C
tsu(SCLK)
internal data set-up time
after last clock
1
−
−
µs
thd(SCLK)
internal data hold time
before next clock
1
−
−
µs
tsu(gate)
VOTPPROG gate set-up time
prior to programming
1
−
10
µs
thd(gate)
VOTPPROG gate hold time
after programming
1
−
10
µs
tPW
pulse width of programming
voltage
100
120
200
ms
when programming a single
bit to logic 1
Notes
1. The voltage drop across the ITO track and zebra connector must be taken into account to guarantee sufficient
voltage at the chip pads.
2. The Power-down mode (DON = 0 and DAL = 1) and CALMM mode must be active while the VLCDIN input is being
driven.
2003 feb 10
53
Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
t hd(SCLK)
t su(SCLK)
handbook, full pagewidth
OM6208
SCLK
VVOTPPROG
VLCDIN
t su(gate)
t hd(gate)
t PW
Fig.45 Programming waveforms.
2003 feb 10
54
MGW843
Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
OM6208
18 DEVICE PROTECTION DIAGRAM
handbook, full pagewidth
VDD1
VDD2
VDD3
VSS1
VSS1
VSS1
VSS2
VSS2
VLCDIN ,
VLCDSENSE
VLCDOUT
VSS1
VSS1
VLCDIN
VDD1
VSS1
VOTPPROG
VSS1
SCLK,
SDATA,
SDO
LCD
outputs
VDD1
OSC, RES,
D/C, PS [2:0],
T1, T2, T5
VSS1
VSS1
VDD1
VDD1
I2C-bus
pads
T3, T4,
VSS1, VDD
VSS1
VSS1
VSS1
MGW850
Protection diode maximum forward current = 5 mA.
Fig.46 Protection circuit diagrams.
2003 feb 10
55
Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
OM6208
19 BONDING PAD INFORMATION
R32
handbook, full pagewidth
RES
33 row
driver
outputs
VOTPPROG
SCLH/SCE
R64
ID3/SA0, ID4/SA1
C95
MX
VSS1, VSS2
SDATA
x
SDO
y
SDAH
96 column
driver
outputs
SCLK
SDAHOUT
VDD1
C0
PS [1:0]
R31
D/C
OSC
32 row
driver
outputs
VDD2, VDD3
VLCDIN, VLCDOUT, VLCDSENSE
R0
MGW844
Fig.47 Bonding pad locations (viewed from bump side).
2003 feb 10
56
Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
Table 28 Bonding pad locations
All x and y coordinates indicate pad centres and are
referenced to the centre of the chip; dimensions in µm
(see Fig.47).
VDD1
COORDINATES
VDD1
SYMBOL
dummy
COORDINATES
SYMBOL
PAD
1
x
y
−4919
+1279
dummy
2
−4856
+1279
alignment mark
3
−4762
+1220
dummy
4
−4649
+1279
VLCDIN
5
−4586
+1279
VLCDIN
6
−4523
+1279
VLCDIN
7
−4460
+1279
VLCDIN
8
−4397
+1279
VLCDOUT
9
−4323
+1279
VLCDOUT
10
−4260
+1279
VLCDOUT
11
−4197
+1279
VLCDOUT
12
−4134
+1279
VLCDOUT
13
−4071
+1279
VLCDOUT
14
−4008
+1279
OM6208
PAD
x
y
37
−1913
+1279
38
−1850
+1279
VDD1
39
−1787
+1279
dummy
40
−1669
+1279
dummy
41
−1503
+1279
dummy
42
−1337
+1279
dummy
43
−1172
+1279
SDAHOUT
44
−1006
+1279
dummy
45
−829
+1279
SCLK
46
−657
+1279
dummy
47
−468
+1279
dummy
48
−303
+1279
dummy
49
−137
+1279
dummy
50
29
1 279
dummy
51
194
1 279
SDAH
52
360
1 279
SDO
53
605
1 279
SDATA
54
696
1 279
VLCDOUT
15
−3945
+1279
VLCDSEN
16
−3882
+1279
VSS2
55
795
1 279
VDD2
17
−3566
+1279
VSS2
56
858
1 279
57
921
1 279
VDD2
18
−3503
+1279
VSS2
VDD2
19
−3440
+1279
VSS2
58
984
1 279
VDD2
20
−3377
+1279
VSS2
59
1047
1 279
60
1110
1 279
VDD2
21
−3314
+1279
VSS2
VDD2
22
−3251
+1279
VSS2
61
1173
1 279
VDD2
23
−3188
+1279
VSS1
62
1246
1 279
63
1309
1 279
VDD2
24
−3125
+1279
VSS1
VDD2
25
−3062
+1279
VSS1
64
1372
1 279
VDD2
26
−2999
+1279
VSS1
65
1435
1 279
66
1498
1 279
VDD3
27
−2928
+1279
VSS1
VDD3
28
−2865
+1279
VSS1
67
1561
1 279
VDD3
29
−2802
+1279
MX
68
1693
1 279
OSC
30
−2639
+1279
T3
69
1865
1 279
T4
70
2028
1 279
T1
71
2114
1 279
T2
72
2232
1 279
T5
73
2350
1 279
T6
74
2468
1 279
ID3_SA0
75
2586
1 279
DC
31
−2475
+1279
PS1
32
−2345
+1279
PS0
33
−2217
+1279
VDD1
34
−2102
+1279
VDD1
35
−2039
+1279
VDD1
36
−1976
+1279
2003 feb 10
57
Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
OM6208
COORDINATES
COORDINATES
SYMBOL
SYMBOL
PAD
x
y
PAD
x
y
ID4_SA1
76
2704
1 279
R42
115
+3812
−1275
VDD1
77
2849
1 279
R43
116
+3760
−1275
dummy
78
3005
1 279
R44
117
+3708
−1275
dummy
79
3171
1 279
R45
118
+3656
−1275
dummy
80
3336
1 279
R46
119
+3604
−1275
dummy
81
3502
1 279
R47
120
+3553
−1275
dummy
82
3667
1 279
R48
121
+3501
−1275
SCLH
83
3833
1 279
R49
122
+3449
−1275
VOTPPROG
84
3958
1 279
R50
123
+3397
−1275
VOTPPROG
85
4021
1 279
R51
124
+3345
−1275
VOTPPROG
86
4084
1 279
R52
125
+3293
−1275
dummy
87
4243
1 279
R53
126
+3242
−1275
RES
88
4387
1 279
R54
127
+3190
−1275
dummy
89
4489
1 279
R55
128
+3138
−1275
dummy
90
4552
1 279
R56
129
+3086
−1275
dummy
91
4615
1 279
R57
130
+3034.
−1275
dummy
92
4678
1 279
R58
131
+2982
−1275
alignment mark
93
4799
1220
R59
132
+2931
−1275
bumps alignment
mark
94
4902
1258
R60
133
+2879
−1275
R61
134
+2829
95
+4900
−1275
−1275
dummy
R62
135
+2775
dummy
96
+4849
−1275
−1275
R63
136
+2723
97
+4797
−1275
−1275
dummy
R64
137
+2671
98
+4745
−1275
−1275
dummy
VC
138
+2620
dummy
99
+4693
−1275
−1275
dummy
139
+2568
100
+4641
−1275
−1275
dummy
dummy
140
+2516
101
+4589
−1275
−1275
dummy
T8
141
+2413
dummy
102
+4538
−1275
−1275
T7
142
+2360
103
+4486
−1275
−1275
dummy
V1_L
143
+2308
104
+4434
−1275
−1275
dummy
C95
144
+2257
105
+4330
−1275
−1275
R32
C94
145
+2205
106
+4278
−1275
−1275
R33
C93
146
+2153
107
+4227
−1275
−1275
R34
C92
147
+2101
108
+4175
−1275
−1275
R35
C91
148
+2049
R36
109
+4123
−1275
−1275
C90
149
+1997
110
+4071
−1275
−1275
R37
C89
150
+1946
111
+4019
−1275
−1275
R38
C88
151
+1894
R39
112
+3967
−1275
−1275
C87
152
+1842
113
+3916
−1275
−1275
R40
C86
153
+1790
114
+3864
−1275
−1275
R41
2003 feb 10
58
Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
OM6208
COORDINATES
SYMBOL
COORDINATES
PAD
SYMBOL
x
PAD
y
x
y
C85
154
+1738
−1275
dummy
193
−335
−1275
C84
155
+1686
−1275
C47
194
−387
−1275
C83
156
+1635
−1275
C46
195
−439
−1275
C82
157
+1583
−1275
C45
196
−491
−1275
C81
158
+1531
−1275
C44
197
−543
−1275
C80
159
+1479
−1275
C43
198
−595
−1275
C79
160
+1427
−1275
C42
199
−646
−1275
C78
161
+1375
−1275
C41
200
−698
−1275
C77
162
+1324
−1275
C40
201
−750
−1275
C76
163
+1272
−1275
C39
202
−802
−1275
C75
164
+1219.86
−1275
C38
203
−854
−1275
C74
165
+1168
−1275
C37
204
−906
−1275
C73
166
+1116
−1275
C36
205
−957
−1275
C72
167
+1064
−1275
C35
206
−1 009
−1275
C71
168
+961
−1275
C34
207
−1061
−1275
C70
169
+909
−1275
C33
208
−1113
−1275
C69
170
+857
−1275
C32
209
−1165
−1275
C68
171
+805
−1275
C31
210
−1217
−1275
C67
172
+753
−1275
C30
211
−1268
−1275
C66
173
+701
−1275
C29
212
−1320
−1275
C65
174
+650
−1275
C28
213
−1372
−1275
C64
175
+598
−1275
C27
214
−1424
−1275
C63
176
+546
−1275
C26
215
−1476
−1275
C62
177
+494
−1275
C25
216
−1528
−1275
C61
178
+442
−1275
C24
217
−1579
−1275
C60
179
+390
−1275
C23
218
−1683
−1275
C59
180
+339
−1275
C22
219
−1735
−1275
C58
181
+287
−1275
C21
220
−1787
−1275
C57
182
+235
−1275
C20
221
−1839
−1275
C56
183
+183
−1275
C19
222
−1891
−1275
C55
184
+131
−1275
C18
223
−1942
−1275
C54
185
+79
−1275
C17
224
−1994
−1275
C53
186
+28
−1275
C16
225
−2046
−1275
C52
187
−24
−1275
C15
226
−2098
−1275
C51
188
−76
−1275
C14
227
−2150
−1275
C50
189
−128
−1275
C13
228
−2202
−1275
C49
190
−180
−1275
C12
229
−2253
−1275
C48
191
−232
−1275
C11
230
−2305
−1275
dummy
192
−283
−1275
C10
231
−2357
−1275
2003 feb 10
59
Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
OM6208
COORDINATES
SYMBOL
COORDINATES
PAD
SYMBOL
x
y
PAD
x
y
C9
232
−2409
−1275
R21
257
−3705
−1275
C8
233
−2461
−1275
R20
258
−3757
−1275
C7
234
−2513
−1275
R19
259
−3809
−1275
C6
235
−2564
−1275
R18
260
−3860
−1275
C5
236
−2616
−1275
R17
261
−3912
−1275
C4
237
−2668
−1275
R16
262
−3964
−1275
C3
238
−2720
−1275
R15
263
−4016
−1275
C2
239
−2772
−1275
R14
264
−4068
−1275
C1
240
−2824
−1275
R13
265
−4120
−1275
C0
241
−2875
−1275
R12
266
−4171
−1275
dummy
242
−2927
−1275
R11
267
−4223
−1275
dummy
243
−2979
−1275
R10
268
−4275
−1275
V1_H
244
−3031
−1275
R9
269
−4327
−1275
V2_L
245
−3083
−1275
R8
270
−4379
−1275
V2_H
246
−3135
−1275
R7
271
−4431
−1275
R31
247
−3187
−1275
R6
272
−4483
−1275
R30
248
−3238
−1275
R5
273
−4534
−1275
R29
249
−3290
−1275
R4
274
−4586
−1275
R28
250
−3342
−1275
R3
275
−4638
−1275
R27
251
−3394
−1275
R2
276
−4690
−1275
R26
252
−3446
−1275
R1
277
−4742
−1275
R25
253
−3498
−1275
R0
278
−4794
−1275
R24
254
−3549
−1275
dummy
279
−4845
−1275
R23
255
−3601
−1275
dummy
280
−4897
−1275
R22
256
−3653
−1275
2003 feb 10
60
Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
OM6208
Table 29 Chip information
ITEM
ROW/COL SIDE
UNIT
Row/column side
Pad pitch
51.84 (minimum)
µm
CBB opening
15.3 × 5.4
µm
Bump dimensions
30.0 × 99 (±3)
µm
Bump height
15.0
µm
Minimum bump
distance
21.8
µm
Wafer thickness
(excl. bumps)
381 (±25)
µm
10.140 mm
handbook, halfpage
2.840
mm
OM6208
pitch
y
Interface side
Pad pitch
63 (minimum)
µm
CBB opening
25.7 × 5.4
µm
Bump dimensions
42 × 90 (±3)
µm
Bump height
15.0
µm
Minimum bump
distance
shortened bumps: 21
normal bumps: 22
µm
Wafer thickness
(excl. bumps)
381 (±25)
µm
bump distance
x
MGW845
Fig.48 Chip size and pad pitch.
handbook, halfpage
handbook, halfpage
60 µm
90
µm
y centre
x centre
x centre
MGW846
MGW847
Fig.49 Shape of alignment mark.
2003 feb 10
60 µm
y centre
Fig.50 Shape of bump alignment mark.
61
Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
OM6208
20 TRAY INFORMATION
x
handbook, full pagewidth
A
C
y
D
B
F
E
MGW848
Fig.51 Tray details.
Table 30 Tray dimensions
DIM.
handbook, halfpage
OM6208-1
A
pocket pitch, x direction
Fig.52 Tray alignment.
2003 feb 10
62
VALUE
14.25 mm
B
pocket pitch, y direction
4.87 mm
C
pocket width, x direction
10.24 mm
D
pocket width, y direction
2.94mm
E
tray width, x direction
50.80 mm
F
tray width, y direction
50.80 mm
x
number of pockets in
X direction
3
y
number of pockets in
Y direction
9
MGW849
The orientation of the IC in a pocket is indicated by the position of
the IC type name on the die surface with respect to the chamfer on
the upper left corner of the tray. Refer to the bonding pad location
diagram (Fig.47) for the orientation and position of the type name on
the die surface.
DESCRIPTION
Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
OM6208
21 DATA SHEET STATUS
LEVEL
DATA SHEET
STATUS(1)
PRODUCT
STATUS(2)(3)
Development
DEFINITION
I
Objective data
II
Preliminary data Qualification
This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
III
Product data
This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Relevant changes will
be communicated via a Customer Product/Process Change Notification
(CPCN).
Production
This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
22 DEFINITIONS
23 DISCLAIMERS
Short-form specification  The data in a short-form
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
Life support applications  These products are not
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition  Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Right to make changes  Philips Semiconductors
reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design
and/or performance. When the product is in full production
(status ‘Production’), relevant changes will be
communicated via a Customer Product/Process Change
Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these
products, conveys no licence or title under any patent,
copyright, or mask work right to these products, and
makes no representations or warranties that these
products are free from patent, copyright, or mask work
right infringement, unless otherwise specified.
Application information  Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.
2003 feb 10
63
Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
Bare die  All die are tested and are guaranteed to
comply with all data sheet limits up to the point of wafer
sawing for a period of ninety (90) days from the date of
Philips' delivery. If there are data sheet limits not
guaranteed, these will be separately indicated in the data
sheet. There are no post packing tests performed on
individual die or wafer. Philips Semiconductors has no
control of third party procedures in the sawing, handling,
OM6208
packing or assembly of the die. Accordingly, Philips
Semiconductors assumes no liability for device
functionality or performance of the die or systems after
third party sawing, handling, packing or assembly of the
die. It is the responsibility of the customer to test and
qualify their application in which the die is used.
24 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
2003 feb 10
64
Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
NOTES
2003 feb 10
65
OM6208
Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
NOTES
2003 feb 10
66
OM6208
Philips Semiconductors
Product specification
65 x 96 pixels matrix grey-scale LCD driver
NOTES
2003 feb 10
67
OM6208
Philips Semiconductors – a worldwide company
Contact information
For additional information please visit http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
For sales offices addresses send e-mail to: [email protected].
SCA75
© Koninklijke Philips Electronics N.V. 2003
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
403512/02/pp68
Date of release: 2003
feb 10
Document order number:
9397 750 11077