PI6C39911/PI6C39912 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 3.3V High Speed LVTTL or Balanced Output Programmable Skew Clock Buffer-SuperClock® Features Description All output pair skew <100ps typical (250 Max.) 12.5 MHz to 135 MHz output operation 3.125 MHz to 135 MHz input operation (input as low as 3.125 MHz for 4x operation, or 6.25 MHz for 2x operation) User-selectable output functions Selectable skew to 18ns Inverted and non-inverted Operation at ½ and ¼ input frequency Operation at 2X and 4X input frequency Zero input-to-output delay 50% duty-cycle outputs LVTTL outputs drive 50-ohm terminated lines Operates from a single 3.3V supply Low operating current 32-pin PLCC package Jitter < 200ps peak-to-peak (< 25ps RMS) Available in LVTTL (PI6C39911) or Balanced (PI6C39912) PI6C39911 is a pin-to-pin compatible with CY7B9911V The PI6C39911 and PI6C39912 offer selectable control over system clock functions. These multiple-output clock drivers provide the system integrator with functions necessary to optimize the timing of high-performance computer systems. Eight individual drivers, arranged as four pairs of user-controllable outputs, can each drive terminated transmission lines with impedances as low as 50 ohms while delivering minimal and specified output skews and full-swing logic levels. Logic Block Diagram Pin Configuration Each output can be hardwired to one of nine skews or function configurations. Delay increments of 0.7ns to 1.5ns are determined by the operating frequency with outputs able to skew up to ±6 time units from their nominal zero skew position. The completely integrated PLL allows external load and transmission line delay effects to be canceled. The user can create output-to-output skew of up to ±12 time units. Divide-by-two and divide-by-four output functions are provided for additional flexibility in designing complex clock systems. When combined with the internal PLL, these divide functions allow distribution of a low-frequency clock that can be multiplied by two or four at the clock destination. This feature allows flexibility and simplifies system timing distribution design for complex high-speed systems. Filter VCO and Time Unit Generator 4F0 4F1 Select Inputs (three level) 3F0 3F1 2F0 2F1 1F0 1F1 Skew Select 1Q0 1Q1 4 2 1 32 31 30 5 29 6 28 4Q0 7 27 4Q1 VCCQ 8 VCCN 9 4Q1 4Q0 GND GND 10 24 11 23 12 22 3Q0 3Q1 2Q0 Matrix 3 3F1 4F0 4F1 32 Pin J 26 25 13 21 14 15 16 17 18 19 2F0 GND 1F1 1F0 VCCN 1Q0 1Q1 GND GND 20 2Q1 1Q0 VCCN FB VCCN 2Q1 2Q0 REF Phase Freq. DET 3Q1 3Q0 FB 3F0 FS VCCQ REF GND TEST 2F1 Test 1Q1 1 PS8497C 04/10/01 PI6C39911/PI6C39912 3.3V High Speed LVTTL or Balanced Output Programmable Skew Clock Buffer - SuperClock 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Pin Descriptions Signal Name I/O REF I Reference frequency input supplies the frequency and timing against which all functional variation is measured. FB I PLL feedback input (typically connected to one of the eight outputs) FS I Three- level frequency range select. see Table 1. 1F0, 1F1 I Three- level function select inputs for output pair 1 (1Q0, 1Q1). see Table 2. 2F0, 2F1 I Three- level function select inputs for output pair 2 (2Q0, 2Q1). see Table 2. 3F0, 3F1 I Three- level function select inputs for output pair 3 (3Q0, 3Q1). see Table 2. 4F0, 4F1 I Three- level function select inputs for output pair 4 (4Q0, 4Q1). see Table 2. TEST I Three- level select. See test mode section under the block diagram descriptions 1Q0, 1Q1 O Output pair 1. see Table 2 2Q0, 2Q1 O Output pair 2. see Table 2 3Q0, 3Q1 O Output pair 3. see Table 2 4Q0, 4Q1 O Output pair 4. see Table 2 De s cription VCCN PWR Power supply for output drivers VCCQ PWR Power supply for internal circuitry GND PWR Ground Table 1. Frequency Range Select and tU Calculation(1) FS(1,2) FNOM (M Hz) tU = 1 fNOM × N Approximate Fre q. (M Hz) at which tU= 1.0ns M in. M ax. whe re N= LO W 12.5 30 44 22.7 MID 25 50 26 38.5 HIGH 40 133 16 62.5 Table 2. Programmable Skew Configurations(1) Function Se le cts Output Functions 1F1, 2F1, 3F1, 4F1 1F0, 2F0, 3F0, 4F0 1Q0, 1Q1, 2Q0, 2Q1 LOW LO W 4tU LOW MID 3tU 6tU 6tU LOW HIGH 2tU 4tU 4tU MID LO W 1tU 2tU 2tU MID MID 0tU 0tU 0tU 3Q0, 3Q1 4Q0, 4Q1 Divide by 2 Divide by 2 MID HIGH +1tU +2tU +2tU HIGH LO W +2tU +4tU +4tU HIGH MID +3tU +6tU +6tU HIGH HIGH +4tU Divide by 4 Inverted Notes: 1. For all three-state inputs, HIGH indicates a connection to VCC, LOW indicates a connection to GND, and MID indicates an open connection. Internal termination circuitry holds an unconnected input to VCC/2. 2. The level to be set on FS is determined by the normal operating frequency (fNOM) and Time Unit Generator (see Logic Block Diagram). Nominal frequency (fNOM) always appears at 1Q0 and the other outputs when they are operated in their undivided modes (see Table 2). The frequency appearing at the REF and FB inputs will be f NOM when the output connected to FB is undivided. The frequency of the REF and FB inputs will be fNOM/2 or fNOM/4 when the part is configured for a frequency multiplication by using a divided output as the FB input. 2 PS8497C 04/10/01 PI6C39911/PI6C39912 3.3V High Speed LVTTL or Balanced Output Programmable Skew Clock Buffer - SuperClock 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Test Mode Maximum Ratings The TEST input is a three-level input. In normal system operation, this pin is connected to ground, allowing the PI6C39911 to operate as explained briefly above (for testing purposes, any of the three level inputs can have a removable jumper to ground, or be tied LOW through a 100 Ohm resistor. This will allow an external tester to change the state of these pins.) If the TEST input is forced to its MID or HIGH state, the device will operate with its internal phase locked loop disconnected, and input levels supplied to REF will directly control all outputs. Relative output to output functions are the same as in normal mode. In contrast with normal operation (TEST tied LOW). All outputs will function based only on the connection of their own function select inputs (xF0 and xF1) and the waveform characteristics of the REF input. Storage Temperature ..................................... 65°C to +150°C Ambient Temperature with Power Applied ............................................... 55°C to +125°C Supply Voltage to Ground Potential ................ 0.5V to +5.0V DC Input Voltage .............................................. 0.5V to +5.0V Output Current into Outputs (LOW) .............................. 64mA Static Discharge Voltage ............................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current .........................................................>200mA Maximum Power Dissipation at TA=85°C(23) ............... 0.80watts 1Fx 2Fx (N/A) t0 +6tU t0 +5tU t0 +4tU t0 +3tU 3.3V ±10% t0 +2tU 40°C to +85°C t0 +1tU Industrial t0 3.3V ±10% t0 –1tU 0°C to +70°C t0 –3tU Commercial t0 –4tU VCC t0 –5tU Ambie nt Te mpe rature t0 –6tU Range t0 –2tU Operating Range FB Input REF Input 3Fx 4Fx LM –6tU LL LH –4tU LM (N/A) –3tU LH ML –2tU ML (N/A) –1tU MM MH MM (N/A) 0tU +1tU HL MH +2tU HM (N/A) +3tU HH HL +4tU (N/A) HM +6tU (N/A) LL/HH Divided (N/A) HH Invert Figure 1. Typical Outputs with FB Connected to a Zero-Skew Output(3) Note: 3. FB connected to an output selected for zero skew (i.e., xF1 = xF0 = MID) 3 PS8497C 04/10/01 PI6C39911/PI6C39912 3.3V High Speed LVTTL or Balanced Output Programmable Skew Clock Buffer - SuperClock 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Capacitance(6) Parame te r D e s cription Te s t Conditions M ax. Units CIN Input Capacitance TA = 25°C, f = 1MHz, VCC = 3.3V 10 pF Electrical Characteristics (Over the Operating Range) Parame te r De s cription Te s t Conditions M in. M ax. VOH Output HIGH Voltage VCC = Min., IOH = 18mA VOL Output LOW Voltage VCC = Min., IOL = 35mA VIH Input HIGH Voltage (REF and FB inputs only) 2.0 VCC VIL Input LOW Voltage (REF and FB inputs only) 0.5 0.8 2.4 0.45 VIHH Three- Level Input HIGH Voltage (Test, FS, xFn)(4) Min. ≤ VCC ≤ Max. 0.87 VCC VCC VIMM Three- Level Input MID Voltage (Test, FS, xFn)(4) Min. ≤ VCC ≤ Max. 0.47 VCC 0.53 VCC VILL Three- Level Input LOW Voltage (Test, FS, xFn)(4) Min. ≤ VCC ≤ Max. 0.0 0.13 VCC IIH Input HIGH Leakage Current (REF and FB inputs only) VCC = Max., VIN = Max. IIL Input LOW Leakage Current (REF and FB inputs only) VCC = Max., VIN = 0.4V IIHH Input HIGH Current (Test, FS, xFn) VIN = VCC IIMM Input MID Current (Test, FS, xFn) VIN = VCC/2 50 IILL Input LOW Current (Test, FS, xFn) VIN = GND 200 IOS ICCQ ICCN PD (5) Units V 20 20 200 Short Circuit Current VCC = Max., VOUT = GND (25°C only) Operating Current Used by Internal Circuitry VCCN = VCCQ = Max., All Input Selects Open Output Buffer Current per Output Pair Power Dissipation per Output Pair µA 50 200 mA Com'l 95 Mil/Ind 100 mA VCCN = VCCQ = Max., IOUT = 0mA All Input Selects Open, fMAX 25 mA VCCN = VCCQ = Max., IOUT = 0mA All Input Selects Open, fMAX 130 mW Notes: 4. These inputs are normally wired to VCC, GND, or left unconnected (actual threshold voltages vary as a percentage of VCC). Internal termination resistors hold unconnected inputs at VCC/2. If these inputs are switched, the function and timing of the outputs may glitch and the PLL may require an additional tLOCK time before all data sheet limits are achieved. 5. PI6C39911 should be tested one output at a time, output shorted for less than one second, less than 10% duty cycle. Room temperature only. 6. Applies to REF and FB inputs only. Tested initially and after any design or process changes that may affect these parameters. 7. Test measurement levels for the PI6C39911 are TTL levels (1.5V to 1.5V). Test conditions assume signal transition times of 2ns or less and output loading as shown in the AC Test Loads and Waveforms unless otherwise specified. 8. Guaranteed by statistical correlation. 4 PS8497C 04/10/01 PI6C39911/PI6C39912 3.3V High Speed LVTTL or Balanced Output Programmable Skew Clock Buffer - SuperClock 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Switching Characteristics (Over the Operating Range)(2,7) Parame te r PI6C39911-2 PI6C39912-2 De s cription M in. Typ. M ax. PI6C39911-5 PI6C39912-5 M in. Typ. PI6C39911 PI6C39912 FS = LOW(1,2) Operating Clock Frequency FS = MID(1,2) in MHz FS = HIGH(1,2,19) 12.5 30 12.5 30 12.5 30 25 50 25 50 25 50 40 135 40 135 40 135 tRPWH REF Pulse Width HIGH 3.0 3.0 3.0 tRPWL REF Pulse Width LOW 3.0 3.0 3.0 fNOM(1,2) tU Programmable Skew Unit See Table 1 See Table 1 See Table 1 Zero Output Matched - Pair Skew (XQ0, XQ1)(9,10) 0.1 0.25 0.1 0.25 0.1 0.25 tSKEW0 Zero Output Skew (All Outputs)(9,11) 0.20 0.25 0.25 0.5 0.3 0.75 tSKEW1 Output Skew (Rise- Rise, Fall- Fall, Same Class Outputs)(9,13) 0.4 0.5 0.6 0.7 0.6 1.0 tSKEW2 Output Skew (Rise- Fall, Nominal- Inverted, Divided- Divided)(9,13) 0.6 0.8 0.5 1.0 1.0 1.5 tSKEW3 Output Skew (Rise- Rise, Fall- Fall, Different Class Outputs)(9,13) 0.4 0.5 0.5 0.7 0.7 1.2 tSKEW4 Output Skew (Rise- Fall, Nominal- Divided, Divided- Inverted)(9,13) 0.5 0.8 0.5 1.0 1.2 1.7 Device- to- Device Skew (8,14) tPD Propagation Delay, REF Rise to FB Rise tODCV tPWH Output Duty Cycle Variation 1.0 (15) 1.25 0.0 +0.3 0.5 0.0 +0.5 0.7 0.0 +0.7 0.7 0.0 +0.7 1.0 0.0 +1.0 1.2 0.0 +1.2 (16) 2.5 2.5 3.0 (16) 3.0 3.0 3.5 tPWL Output LOW Time Deviation from 50% tORISE (16,17) Output Rise Time 0.15 1.0 1.5 0.15 1.0 1.5 0.15 1.0 1.5 tOFALL Output Fall Time(16,17) 0.15 1.0 1.5 0.15 1.0 1.5 0.15 1.0 1.5 tLOCK tJR (18) PLL Lock Time Cycle- to- cycle Output Jitter RMS (8) Peak- to- peak (8) ns 1.65 0.3 Output HIGH Time Deviation from 50% MHz ns tSKEWPR tDEV Units M ax. M in. Typ. M ax. 0.5 0.5 0.5 25 25 25 200 200 200 ms ps Notes: 9. SKEW is defined as the time between the earliest and the latest output transition among all outputs for which the same tU delay has been selected when all are loaded with 30pF and terminated with 50 ohms to VCC/2. 10. tSKEWPR is defined as the skew between a pair of outputs (XQ0 and XQ1) when all eight outputs are selected for 0tU. 11. tSKEW0 is defined as the skew between outputs when they are selected for 0tU. Other outputs are divided or inverted but not shifted. 12. CL = 0pF. For CL = 30pF, tSKEW0 = 0.35ns. 13. There are three classes of outputs: Nominal (multiple of tU delay), Inverted (4Q0 and 4Q1 only with 4F0 = 4F1 = HIGH), and Divided (3Qx and 4Qx only in Divide-by-2 or Divide-by-4 mode). 14. tDEV is the output-to-output skew between any two devices operating under the same conditions (VCC ambient temperature, air flow, etc.) 15. tODCV is the deviation of the output from a 50% duty cycle. Output pulse width variations are included in tSKEW2 and tSKEW4 specifications. 16. Specified with outputs loaded with 30pF for the PI6C39911 and PI6C39912 devices. Devices are terminated through 50 Ohm to VCC/2. tPWH is measured at 2.0V. tPWL is measured at 0.8V. 17. tORISE and tOFALL measured between 0.8V and 2.0V. 18. tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VCC is stable and within normal operating limits. This parameter is measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits. 19. For frequencies higher than 110MHz output load should be less than 15pF to meet package thermal requirement. 5 PS8497C 04/10/01 PI6C39911/PI6C39912 3.3V High Speed LVTTL or Balanced Output Programmable Skew Clock Buffer - SuperClock 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 AC Test Loads and Waveforms TTL AC Test Load TTL Input Test Waveform VCC ≤1ns R1 CL ≤1ns 3.0V 2.0V Vth =1.5V 0.8V 0V R2 R1=100 R2=100 CL=30pF (Includes fixture and probe capacitance) AC Timing Diagrams tREF tRPWH tRPWL REF tPD tODCV tODCV FB tJR Q tSKEWPR tSKEW0, 1 tSKEWPR tSKEW0, 1 Other Q tSKEW2 tSKEW2 Inverted Q tSKEW3,4 tSKEW3,4 tSKEW3,4 REF Divided by 2 tSKEW1,3,4 tSKEW2,4 REF Divided by 4 6 PS8497C 04/10/01 PI6C39911/PI6C39912 3.3V High Speed LVTTL or Balanced Output Programmable Skew Clock Buffer - SuperClock 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Operational Mode Descriptions REF FB System Clock LOAD REF L1 FS 4F0 4Q0 4F1 4Q1 3F0 3Q0 3F1 3Q1 2F0 2Q0 2F1 2Q1 1F0 1Q0 1F1 1Q1 Z0 LOAD L2 Z0 L3 LOAD Z0 L4 Z0 TEST LOAD LENGTH: L1 = L2 = L3 = L4 Figure 2. Zero-Skew and/or Zero-Delay Clock Driver Figure 2 shows the SUPERCLOCK configured as a zero-skew clock buffer. In this mode the PI6C39911 can be used as the basis for a lowskew clock distribution tree. When all of the function select inputs (xF0, xF1) are left open, the outputs are aligned and may each drive a terminated transmission line to an independent load. The FB input can be tied to any output in this configuration and the operating frequency range is selected with the FS pin. The low-skew specification, coupled with the ability to drive terminated transmission lines (with impedances as low as 50 Ohm), allows efficient printed circuit board design. REF FB System Clock LOAD REF L1 FS 4F0 4Q0 4F1 4Q1 3F0 3Q0 3F1 3Q1 2F0 2Q0 2F1 2Q1 1F0 1Q0 1F1 1Q1 Z0 LOAD L2 Z0 L3 LOAD Z0 L4 Z0 TEST LOAD LENGTH: L1 = L2, L3 < L2 by 6", L4 > L2 by 6" Figure 3. Programmable Skew Clock Driver 7 PS8497C 04/10/01 PI6C39911/PI6C39912 3.3V High Speed LVTTL or Balanced Output Programmable Skew Clock Buffer - SuperClock 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Figure 3 shows a configuration to equalize skew between metal traces of different lengths. In addition to low skew between outputs, the SuperClock can be programmed to stagger the timing of its outputs. The four groups of output pairs can each be programmed to different output timing. Skew timing can be adjusted over a wide range in small increments with the appropriate strapping of the function select pins. In this configuration the 4Q0 output is fed back to FB and configured for zero skew. The other three pairs of outputs are programmed to yield different skews relative to the feedback. By advancing the clock signal on the longer traces or retarding the clock signal on shorter traces, all loads can receive the clock pulse at the same time. In this illustration the FB input is connected to an output with 0ns skew (xF1, xF0 = MID) selected. The internal PLL synchronizes the FB and REF inputs and aligns their rising edges to insure that all outputs have precise phase alignment. Clock skews can be advanced by ±6 time units (tU) when using an output selected for zero skew as the feedback. A wider range of delays is possible if the output connected to FB is also skewed. Since Zero Skew, +tU, and tU are defined relative to output groups, and since the PLL aligns the rising edges of REF and FB, it is possible to create wider output skews by proper selection of the xFn inputs. For example a +10 tU between REF and 3Qx can be achieved by connecting 1Q0 to FB and setting 1F0 = 1F1 = GND, 3F0 = MID, and 3F1 = High. (Since FB aligns at 4 tU and 3Qx skews to +6 tU , a total of +10 tU skew is realized). Many other configurations can be realized by skewing both the output used as the FB input and skewing the other outputs. Figure 4 shows an example of the invert function of the SuperClock. In this example the 4Q0 output used as the FB input is programmed for invert (4F0 = 4F1 = HIGH) while the other three pairs of outputs are programmed for zero skew. When 4F0 and 4F1 are tied HIGH, 4Q0 and 4Q1 become inverted zero phase outputs. The PLL aligns the rising edge of the FB input with the rising edge of the REF. This causes the 1Q, 2Q, and 3Q outputs to become the inverted outputs with respect to the REF input. By selecting which output is connect to FB, it is possible to have 2 inverted and 6 non-inverted outputs or 6 inverted and 2 non-inverted outputs. The correct configuration would be determined by the need for more (or fewer) inverted outputs. 1Q, 2Q, and 3Q outputs can also be skewed to compensate for varying trace delays independent of inver-sion on 4Q. REF FB 20 MHz REF FS 4F0 4Q0 4F1 4Q1 3F0 3Q0 3F1 3Q1 2F0 2Q0 2F1 2Q1 1F0 1Q0 1F1 1Q1 40 MHz 20 MHz 80 MHz TEST REF Figure 5. Frequency Multiplier with Skew Connections FB REF Figure 5 illustrates the SuperClock configured as a clock multiplier. The 3Q0 output is programmed to divide by four and is fed back to FB. This causes the PLL to increase its frequency until the 3Q0 and 3Q1 outputs are locked at 20 MHz while the 1Qx and 2Qx outputs run at 80 MHz. The 4Q0 and 4Q1 outputs are programmed to divide by two, which results in a 40 MHz waveform at these outputs. Note that the 20 and 40 MHz clocks fall simultaneously and are out of phase on their rising edge. This will allow the designer to use the rising edges of the ½ frequency and ¼ frequency outputs without concern for rising-edge skew. The 2Q0, 2Q1, 1Q0, and 1Q1 outputs run at 80 MHz and are skewed by programming their select inputs accordingly. Note that the FS pin is wired for 80 MHz operation because that is the frequency of the fastest output. FS 4F0 4Q0 4F1 4Q1 3F0 3Q0 3F1 3Q1 2F0 2Q0 2F1 2Q1 1F0 1Q0 1F1 1Q1 TEST Figure 4. Inverted Output Connections 8 PS8497C 04/10/01 PI6C39911/PI6C39912 3.3V High Speed LVTTL or Balanced Output Programmable Skew Clock Buffer - SuperClock 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Figure 7 shows some of the functions that are selectable on the 3Qx and 4Qx outputs. These include inverted outputs and outputs that offer divide-by-2 and divide-by-4 timing. An inverted output allows the system designer to clock different sub-systems on opposite edges, without suffering from the pulse asymmetry typical of nonideal loading. This function allows the two subsystems to each be clocked 180 degrees out of phase, but still to be aligned within the skew spec. The divided outputs offer a zero-delay divider for portions of the system that need the clock to be divided by either two or four, and still remain within a narrow skew of the 1X clock. Without this feature, an external divider would need to be add-ed, and the propagation delay of the divider would add to the skew between the different clock signals. These divided outputs, coupled with the Phase Locked Loop, allow the SuperClock to multiply the clock rate at the REF input by either two or four. This mode will enable the designer to distribute a lowfrequency clock between various portions of the system, and then locally multiply the clock rate to a more suitable frequency, while still maintaining the low-skew characteristics of the clock driver. The SuperClock can perform all of the functions described above at the same time. It can multiply by two and four or divide by two (and four) at the same time that it is shifting its outputs over a wide range or maintaining zero skew between selected outputs. REF FB 20 MHz REF FS 4F0 4Q0 4F1 4Q1 3F0 3Q0 3F1 3Q1 2F0 2Q0 2F1 2Q1 1F0 1Q0 1F1 1Q1 10 MHz 5 MHz 20 MHz TEST Figure 6. Frequency Divider Connections Figure 6 demonstrates the SuperClock in a clock divider application. 2Q0 is fed back to the FB input and programmed for zero skew. 3Qx is programmed to divide by four. 4Qx is programmed to divide by two. Note that the falling edges of the 4Qx and 3Qx outputs are aligned. This allows use of the rising edges of the ½ frequency and ¼ frequency without concern for skew mismatch. The 1Qx outputs are programmed to zero skew and are aligned with the 2Qx outputs. In this example, the FS input is grounded to configure the device in the 15 to 30 MHz range since the highest frequency output is running at 20 MHz. REF LOAD FB 27.5 MHz Distribution Clock REF Z0 FS 4F0 4Q0 4F1 4Q1 3F0 3Q0 3F1 3Q1 2F0 2Q0 2F1 2Q1 1F0 1Q0 1F1 1Q1 110 MHz Inverted LOAD 27.5 MHz 110 MHz Zero Skew 110 MHz Skewed –2.273ns (–4tU) TEST Z0 LOAD Z0 Z0 LOAD Figure 7. Multi-Function Clock Driver 9 PS8497C 04/10/01 PI6C39911/PI6C39912 3.3V High Speed LVTTL or Balanced Output Programmable Skew Clock Buffer - SuperClock 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 REF LOAD System Clock FB Z0 L1 REF FS 4F0 4Q0 4F1 4Q1 3F0 3Q0 3F1 3Q1 2F0 2Q0 2F1 2Q1 1F0 1Q0 1F1 1Q1 LOAD L2 Z0 L3 LOAD Z0 L4 TEST FB Z0 REF FS 4F0 4Q0 4F1 4Q1 3F0 3Q0 3F1 3Q1 2F0 2Q0 2F1 2Q1 1F0 1Q0 1F1 1Q1 LOAD LOAD TEST Figure 8. Board-to-Board Clock Distribution Figure 8 shows the PI6C39911 connected in series to construct a zero skew clock distribution tree between boards. Delays of the down stream clock buffers can be programmed to compensate for the wire length (i.e., select negative skew equal to the wire delay) necessary to connect them to the master clock source, approximating a zero- delay clock tree. Cascaded clock buffers will accumulate low-frequency jitter because of the non-ideal filtering characteristics of the PLL filter. It is recommended that not more than two clock buffers be connected in series. 10 PS8497C 04/10/01 PI6C39911/PI6C39912 3.3V High Speed LVTTL or Balanced Output Programmable Skew Clock Buffer - SuperClock 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Package Diagram - 32-Pin PLCC (J) Ordering Information Accuracy (ps ) Orde ring Code 250 PI6C39911- 2J 500 PI6C39911- 5J 700 PI6C39911J 250 PI6C39912- 2J 500 PI6C39912- 5J 700 PI6C39912J Package Name Package Type Ope rating Range J32 32- Pin Plastic Leaded Chip Carrier Commercial Pericom Semiconductor Corporation 2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com 11 PS8497C 04/10/01