ETC 5962R9858001V9A

REVISIONS
LTR
DESCRIPTION
DATE (YR-MO-DA)
APPROVED
A
Change package designation and add case outline figure. - jak
00-04-11
Monica L. Poelking
B
Add device type 02. - jak
00-05-30
Monica L. Poelking
C
Correct supply voltage nomenclature to comply with device characterization.
Correct dimension A minimum values for Case Outline X in table of Figure 1.
Update boilerplate to latest MIL-PRF-38535 requirements. - CFS
01-03-06
Thomas M. Hess
D
Add device type 03. - CFS
02-05-10
Thomas M. Hess
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PMIC N/A
PREPARED BY
Charles F. Saffle, Jr.
STANDARD
MICROCIRCUIT
DRAWING
THIS DRAWING IS AVAILABLE
FOR USE BY ALL
DEPARTMENTS
AND AGENCIES OF THE
DEPARTMENT OF DEFENSE
AMSC N/A
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216
http://www.dscc.dla.mil
CHECKED BY
Charles F. Saffle, Jr.
APPROVED BY
Monica L. Poelking
DRAWING APPROVAL DATE
99-05-10
REVISION LEVEL
D
MICROCIRCUIT, DIGITAL, RADIATION HARDENED,
ADVANCED CMOS, SCHMITT 16-BIT BIDIRECTIONAL
MULTI-PURPOSE TRANSCEIVER WITH THREE-STATE
OUTPUTS, MONOLITHIC SILICON
SIZE
CAGE CODE
A
67268
5962-98580
SHEET
1
DSCC FORM 2233
APR 97
DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited.
OF
43
5962-E407-02
1. SCOPE
1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and
M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part
or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN.
1.2 PIN. The PIN is as shown in the following example:
5962
R
98580
Federal
stock class
designator
\
RHA
designator
(see 1.2.1)
01
V
X
X
Device
type
(see 1.2.2)
Device
class
designator
(see 1.2.3)
Case
outline
(see 1.2.4)
Lead
finish
(see 1.2.5)
/
\/
Drawing number
1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are
marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A
specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device.
1.2.2 Device type(s). The device type(s) identify the circuit function as follows:
Device type
Generic number
Circuit function
01
54ACS164245S
Radiation hardened, Schmitt 16-bit bidirectional
multi-purpose transceiver with three-state outputs
and cold sparing
02
54ACS164245S 1/
Radiation hardened, Schmitt 16-bit bidirectional
multi-purpose transceiver with three-state outputs,
cold sparing, and extended voltage range
03
54ACS164245S 1/ 2/
Radiation hardened, Schmitt 16-bit bidirectional
multi-purpose transceiver with three-state outputs,
cold sparing, extended voltage range, and extended
industrial temperature range of -40°C to +125°C
1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as
follows:
Device class
Device requirements documentation
M
Vendor self-certification to the requirements for MIL-STD-883 compliant,
non-JAN class level B microcircuits in accordance with MIL-PRF-38535,
appendix A
Q or V
Certification and qualification to MIL-PRF-38535
1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows:
Outline letter
X
Descriptive designator
See figure 1
Terminals
Package style
48
Flat pack
_______
1/ Device types 02 and 03 have an extended voltage range.
2/ Device type 03 has an extended industrial temperature range of -40°C to +125°C.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
DSCC FORM 2234
APR 97
SIZE
5962-98580
A
REVISION LEVEL
D
SHEET
2
1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535,
appendix A for device class M.
1.3 Absolute maximum ratings. 1/ 2/ 3/
Supply voltage ranges (VDD):
5.0 V supply (VDD1) ........................................................................................... -0.3 V dc to +6.0 V dc
3.3 V supply (VDD2) ........................................................................................... -0.3 V dc to +6.0 V dc
DC input voltage range (VIN): 4/
A port ................................................................................................................. -0.3 V dc to VDD1 + 0.3 V dc
B port ................................................................................................................. -0.3 V dc to VDD1 + 0.3 V dc
DC output voltage range (VOUT):
A port ................................................................................................................. -0.3 V dc to VDD1 + 0.3 V dc
B port ................................................................................................................. -0.3 V dc to VDD1 + 0.3 V dc
DC input current, any one input (IIN):
A port ................................................................................................................. ±10 mA
B port ................................................................................................................. ±10 mA
Storage temperature range (TSTG) ....................................................................... -65°C to +150°C
Lead temperature (soldering, 10 seconds).......................................................... +300°C
Thermal resistance, junction-to-case (θJC) .......................................................... See MIL-STD-1835
Junction temperature (TJ) .................................................................................... +175°C
Maximum power dissipation at TA = +55°C (in still air) (PD)................................. 1.0 W 5/
1.4 Recommended operating conditions. 2/ 3/ 6/
Supply voltage range (VDD):
(VDD1) Device type 01 ........................................................................................ +4.5 V dc to +5.5 V dc
or 3.13 V dc to 3.6 V dc
(VDD1) Device types 02 and 03...........................................................................+4.5 V dc to +5.5 V dc
or 3.0 V dc to 3.6 V dc
(VDD2) Device type 01 ........................................................................................ +3.13 V dc to +3.6 V dc
or +4.5 V dc to +5.5 V dc
(VDD2) Device types 02 and 03........................................................................... +3.00 V dc to +3.6 V dc
or +4.5 V dc to +5.5 V dc
Input voltage range (VIN)...................................................................................... +0.0 V dc to VDD1
Output voltage range (VOUT) ................................................................................ +0.0 V dc to VDD1
Case operating temperature range (TC): (Device types 01 and 02).................... -55°C to +125°C
(Device type 03).................................. -40°C to +125°C
Maximum input rise and fall time at VDD1 = 4.5 V (tr, tf) ....................................... 1 ns/V 7/
1.5 Radiation features. 8/
Maximum total dose available (dose rate = 50 - 300 rads (Si)/s) ........................ 1 x 105 Rads (Si)
Single event phenomenon (SEP) effective linear energy
threshold (LET). No upsets (see 4.4.4.4).......................................................... > 80 MeV/(mg/cm2)
Single event latch-up ........................................................................................... > 120 MeV/(mg/cm2)
_______
1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the
maximum levels may degrade performance and affect reliability.
2/ Unless otherwise noted, all voltages are referenced to VSS.
3/ The limits for the parameters specified herein shall apply over the full specified VDD range and case temperature range of
-55°C to +125°C for device types 01 and 02, -40°C to +125°C for device type 03.
4/ For cold spare mode (VDD = VSS), VIN may be –0.3V to the maximum recommended operating VDD + 0.3V.
5/ The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of
750 mils
6/ Unused inputs must be held high or low to prevent them from floating.
7/ Derate system propagation delays by difference in rise time to switch point for tr or tf > 1 ns/V.
8/ Radiation testing is performed on the standard evaluation circuit.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
DSCC FORM 2234
APR 97
SIZE
5962-98580
A
REVISION LEVEL
D
SHEET
3
2. APPLICABLE DOCUMENTS
2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part
of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those listed in the
issue of the Department of Defense Index of Specifications and Standards (DoDISS) and supplement thereto, cited in the
solicitation.
SPECIFICATIONS
DEPARTMENT OF DEFENSE
MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for.
STANDARDS
DEPARTMENT OF DEFENSE
MIL-STD-883 MIL-STD-1835 -
Test Method Standard Microcircuits.
Interface Standard Electronic Component Case Outlines.
HANDBOOKS
DEPARTMENT OF DEFENSE
MIL-HDBK-103 MIL-HDBK-780 -
List of Standard Microcircuit Drawings.
Standard Microcircuit Drawings.
(Unless otherwise indicated, copies of the specification, standards, and handbooks are available from the Standardization
Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.)
2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text
of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a
specific exemption has been obtained.
3. REQUIREMENTS
3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with
MIL-PRF-38535 and as specified herein or as modified in the device manufacturer's Quality Management (QM) plan. The
modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for
device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified
herein.
3.1.1 Microcircuit die. For the requirements for microcircuit die, see appendix A to this document.
3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified
in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M.
3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.4 herein and figure 1.
3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2.
3.2.3 Truth table. The truth table shall be as specified on figure 3.
3.2.4 Logic diagram. The logic diagram shall be as specified on figure 4.
3.2.5 Switching waveforms and test circuit. The switching waveforms and test circuit shall be as specified on figure 5.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
DSCC FORM 2234
APR 97
SIZE
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A
REVISION LEVEL
D
SHEET
4
3.2.6 Irradiation test connections. The irradiation test connections shall be as specified in table III.
3.2.7 Radiation exposure circuit. The radiation exposure circuit shall be maintained by the manufacturer under document
revision level control and shall be made available to the preparing and acquiring activity upon request.
3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the
electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full
case operating temperature range.
3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical
tests for each subgroup are defined in table IA.
3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be
marked as listed in MIL-HDBK-103. For packages where marking of the entire SMD PIN number is not feasible due to space
limitations, the manufacturer has the option of not marking the "5962-" on the device. For RHA product using this option, the
RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535.
Marking for device class M shall be in accordance with MIL-PRF-38535, appendix A.
3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a "QML" or "Q" as required in
MIL-PRF-38535. The compliance mark for device class M shall be a "C" as required in MIL-PRF-38535, appendix A.
3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535
listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of
compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see
6.6.2 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this
drawing shall affirm that the manufacturer's product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and
herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein.
3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or
for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing.
3.8 Notification of change for device class M. For device class M, notification to DSCC-VA of change of product (see 6.2
herein) involving devices acquired to this drawing is required for any change as defined in MIL-PRF-38535, appendix A.
3.9 Verification and review for device class M. For device class M, DSCC, DSCC's agent, and the acquiring activity retain the
option to review the manufacturer's facility and applicable required documentation. Offshore documentation shall be made
available onshore at the option of the reviewer.
3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in
microcircuit group number 37 (see MIL-PRF-38535, appendix A).
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
DSCC FORM 2234
APR 97
SIZE
5962-98580
A
REVISION LEVEL
D
SHEET
5
TABLE IA. Electrical performance characteristics.
Test
Schmitt trigger
positive going
threshold
Symbol
VT+
Test conditions 1/ 2/
-55°C ≤ TC ≤ +125°C
For 5.0 V supply:
+4.5 V ≤ VDD1 ≤ +5.5 V
For 3.3 V supply:
+3.0 V ≤ VDD2 ≤ +3.6 V
unless otherwise specified
A Port = 3.3V
A Port = 3.3V
01
A Port = 5.0V
B Port = 3.3V
0.7VDD2
1
0.7VDD2
VDD1 =4.5 V
and 5.5 V,
VDD2 = 3.0 V
and 3.6 V
1, 2, 3
0.7VDD2
1
0.7VDD2
VDD1 =4.5 V
and 5.5 V,
VDD2 = 4.5 V
and 5.5 V
1, 2, 3
0.7VDD2
1
0.7VDD2
VDD1 =3.13 V
and 3.6 V,
VDD2 = 3.13 V
and 3.6 V
1, 2, 3
0.7VDD1
1
0.7VDD1
VDD1 =3.0 V
and 3.6 V,
VDD2 = 3.0 V
and 3.6 V
1, 2, 3
0.7VDD1
1
0.7VDD1
VDD1 =4.5 V
and 5.5 V,
VDD2 = 3.13 V
and 3.6 V
1, 2, 3
0.7VDD1
1
0.7VDD1
VDD1 =4.5 V
and 5.5 V,
VDD2 = 3.0 V
and 3.6 V
1, 2, 3
0.7VDD1
1
0.7VDD1
02, 03
All
01
M, D, P, L, R 5/
B Port = 3.3V
01
02, 03
M, D, P, L, R 5/
B Port = 5.0V
02, 03
01
M, D, P, L, R 5/
B Port = 5.0V
01
02, 03
M, D, P, L, R 5/
Max
1, 2, 3
All
M, D, P, L, R 5/
Unit
Limits 4/
VDD1 =4.5 V
and 5.5 V,
VDD2 = 3.13 V
and 3.6 V
02, 03
M, D, P, L, R 5/
Group A
subgroups
Min
01
M, D, P, L, R 5/
VDD
3/
Device
type
02, 03
V
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
DSCC FORM 2234
APR 97
SIZE
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A
REVISION LEVEL
D
SHEET
6
TABLE IA. Electrical performance characteristics – Continued.
Test
Schmitt trigger
negative going
threshold
Symbol
VT-
Test conditions 1/ 2/
-55°C ≤ TC ≤ +125°C
For 5.0 V supply:
+4.5 V ≤ VDD1 ≤ +5.5 V
For 3.3 V supply:
+3.0 V ≤ VDD2 ≤ +3.6 V
unless otherwise specified
A Port = 3.3V
A Port = 3.3V
01
A Port = 5.0V
0.3VDD2
1
0.3VDD2
VDD1 =4.5 V
and 5.5 V,
VDD2 = 3.0 V
and 3.6 V
1, 2, 3
0.3VDD2
1
0.3VDD2
VDD1 =4.5 V
and 5.5 V,
VDD2 = 4.5 V
and 5.5 V
1, 2, 3
0.3VDD2
1
0.3VDD2
VDD1 =3.13 V
and 3.6 V,
VDD2 = 3.13 V
and 3.6 V
1, 2, 3
0.3VDD1
1
0.3VDD1
VDD1 =3.0 V
and 3.6 V,
VDD2 = 3.0 V
and 3.6 V
1, 2, 3
0.3VDD1
1
0.3VDD1
VDD1 =4.5 V
and 5.5 V,
VDD2 = 3.13 V
and 3.6 V
1, 2, 3
0.3VDD1
1
0.3VDD1
VDD1 =4.5 V
and 5.5 V,
VDD2 = 3.0 V
and 3.6 V
1, 2, 3
0.3VDD1
1
0.3VDD1
All
M, D, P, L, R 5/
B Port = 3.3V
All
01
M, D, P, L, R 5/
B Port = 3.3V
01
02, 03
M, D, P, L, R 5/
B Port = 5.0V
02, 03
01
M, D, P, L, R 5/
B Port = 5.0V
01
02, 03
M, D, P, L, R 5/
Max
1, 2, 3
02, 03
02, 03
Unit
Limits 4/
VDD1 =4.5 V
and 5.5 V,
VDD2 = 3.13 V
and 3.6 V
02, 03
M, D, P, L, R 5/
Group A
subgroups
Min
01
M, D, P, L, R 5/
VDD
3/
Device
type
V
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
DSCC FORM 2234
APR 97
SIZE
5962-98580
A
REVISION LEVEL
D
SHEET
7
TABLE IA. Electrical performance characteristics - Continued.
Test
Schmitt trigger
range of
hysteresis
Symbol
VH
6/
Test conditions 1/ 2/
-55°C ≤ TC ≤ +125°C
For 5.0 V supply:
+4.5 V ≤ VDD1 ≤ +5.5 V
For 3.3 V supply:
+3.0 V ≤ VDD2 ≤ +3.6 V
unless otherwise specified
A Port = 3.3V
A Port = 3.3V
A Port = 5.0V
B Port = 3.3V
M, D, P, L, R 5/
B Port = 3.3V
1
0.4
VDD1 =4.5 V
and 5.5 V,
VDD2 = 3.0 V
and 3.6 V
1, 2, 3
0.4
1
0.4
VDD1 =4.5 V
and 5.5 V,
VDD2 = 4.5 V
and 5.5 V
1, 2, 3
0.6
1
0.6
VDD1 =3.13 V
and 3.6 V,
VDD2 = 3.13 V
and 3.6 V
1, 2, 3
0.4
1
0.4
VDD1 =3.0 V
and 3.6 V,
VDD2 = 3.0 V
and 3.6 V
1, 2, 3
0.4
1
0.4
VDD1 =4.5 V
and 5.5 V,
VDD2 = 3.13 V
and 3.6 V
1, 2, 3
0.6
1
0.6
VDD1 =4.5 V
and 5.5 V,
VDD2 = 3.0 V
and 3.6 V
1, 2, 3
0.6
1
0.6
VDD1 = 5.5 V,
VDD2 = 3.6 V
1, 2, 3
3.0
1
3.0
1, 2, 3
3.0
1
3.0
All
01
02, 03
M, D, P, L, R 5/
B Port = 5.0V
02, 03
01
M, D, P, L, R 5/
B Port = 5.0V
01
02, 03
M, D, P, L, R 5/
IIH
7/
0.4
02, 03
01
A Port = 3.3V
For input under test, VIN = VDD2
Other inputs, VIN = VDD2 or VSS
M, D, P, L, R 5/
A Port = 5.0V
For input under test, VIN = VDD2
Other inputs, VIN = VDD2 or VSS
M, D, P, L, R 5/
Max
1, 2, 3
All
M, D, P, L, R 5/
Input current
high
01
Unit
Limits 4/
VDD1 =4.5 V
and 5.5 V,
VDD2 = 3.13 V
and 3.6 V
02, 03
M, D, P, L, R 5/
Group A
subgroups
Min
01
M, D, P, L, R 5/
VDD
3/
Device
type
02, 03
All
All
VDD1 = 5.5 V,
VDD2 = 5.5 V
All
All
V
µA
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
DSCC FORM 2234
APR 97
SIZE
5962-98580
A
REVISION LEVEL
D
SHEET
8
TABLE IA. Electrical performance characteristics - Continued.
Test
Input current
high
Symbol
IIH
7/
Test conditions 1/ 2/
-55°C ≤ TC ≤ +125°C
For 5.0 V supply:
+4.5 V ≤ VDD1 ≤ +5.5 V
For 3.3 V supply:
+3.0 V ≤ VDD2 ≤ +3.6 V
unless otherwise specified
B Port = 3.3V
For input under test, VIN = VDD1
Other inputs, VIN = VDD1 or VSS
M, D, P, L, R 5/
B Port = 5.0V
For input under test, VIN = VDD1
Other inputs, VIN = VDD1 or VSS
M, D, P, L, R 5/
Input current
low
IIL
7/
A Port = 3.3V
For input under test, VIN = VSS
Other inputs, VIN = VDD2 or VSS
M, D, P, L, R 5/
A Port = 5.0V
For input under test, VIN = VSS
Other inputs, VIN = VDD2 or VSS
M, D, P, L, R 5/
B Port = 3.3V
For input under test, VIN = VSS
Other inputs, VIN = VDD1 or VSS
M, D, P, L, R 5/
B Port = 5.0V
For input under test, VIN = VSS
Other inputs, VIN = VDD1 or VSS
M, D, P, L, R 5/
Input current
cold spare
mode
ICS
A Port = B Port = 5.5 V = VIN
DIRn = 5.5V, OEn = 5.5V
M, D, P, L, R 5/
A Port = B Port = 5.5 V = VIN
DIRn = 0.0V, OEn = 5.5V
M, D, P, L, R 5/
A Port = B Port = 5.5 V = VIN
DIRn = 5.5V, OEn = 0.0V
M, D, P, L, R 5/
A Port = B Port = 5.5 V = VIN
DIRn = 0.0V, OEn = 0.0V
M, D, P, L, R 5/
Device
type
VDD
3/
Group A
subgroups
Min
All
VDD1 =3.6 V,
VDD2 = 3.6 V
All
All
VDD1 =5.5 V,
VDD2 = 3.6 V
All
VDD1 =5.5 V,
VDD2 = 3.6 V
All
All
VDD1 = 5.5 V,
VDD2 = 5.5 V
All
All
VDD1 = 3.6 V,
VDD2 = 3.6 V
All
All
VDD1 = 5.5 V,
VDD2 = 3.6 V
All
All
All
VDD1 = 0.0 V,
VDD2 = 0.0 V
All
All
VDD1 = 0.0 V,
VDD2 = 0.0 V
All
All
VDD1 = 0.0 V,
VDD2 = 0.0 V
All
All
VDD1 = 0.0 V,
VDD2 = 0.0 V
All
Unit
Limits 4/
Max
1, 2, 3
3.0
1
3.0
1, 2, 3
3.0
1
3.0
µA
µA
1, 2, 3
-1.0
1
-1.0
1, 2, 3
-1.0
1
-1.0
1, 2, 3
-1.0
1
-1.0
1, 2, 3
-1.0
1
-1.0
1, 2, 3
-1.0
5.0
1
-1.0
5.0
1, 2, 3
-1.0
5.0
1
-1.0
5.0
1, 2, 3
-1.0
5.0
1
-1.0
5.0
1, 2, 3
-1.0
5.0
1
-1.0
5.0
µA
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
DSCC FORM 2234
APR 97
SIZE
5962-98580
A
REVISION LEVEL
D
SHEET
9
TABLE IA. Electrical performance characteristics - Continued.
Test
Low level output
voltage
Symbol
VOL1
8/
Test conditions 1/ 2/
-55°C ≤ TC ≤ +125°C
For 5.0 V supply:
+4.5 V ≤ VDD1 ≤ +5.5 V
For 3.3 V supply:
+3.0 V ≤ VDD2 ≤ +3.6 V
unless otherwise specified
A Port = 3.3V, IOL = 8 mA
For all inputs affecting output
under test, VIN = VDD2 or VSS
M, D, P, L, R 5/
A Port = 3.3V, IOL = 8 mA
For all inputs affecting output
under test, VIN = VDD2 or VSS
M, D, P, L, R 5/
A Port = 5.0V, IOL = 8 mA
For all inputs affecting output
under test, VIN = VDD2 or VSS
M, D, P, L, R 5/
B Port = 3.3V, IOL = 8 mA
For all inputs affecting output
under test, VIN = VDD1 or VSS
M, D, P, L, R 5/
B Port = 3.3V, IOL = 8 mA
For all inputs affecting output
under test, VIN = VDD1 or VSS
M, D, P, L, R 5/
B Port = 5.0V, IOL = 8 mA
For all inputs affecting output
under test, VIN = VDD1 or VSS
M, D, P, L, R 5/
B Port = 5.0V, IOL = 8 mA
For all inputs affecting output
under test, VIN = VDD1 or VSS
M, D, P, L, R 5/
Device
type
VDD
3/
Group A
subgroups
Limits 4/
Min
VDD1 =4.5 V,
VDD2 = 3.13 V
01
01
02, 03
VDD1 =4.5 V,
VDD2 = 3.0 V
02, 03
VDD1 =4.5 V,
VDD2 = 4.5 V
All
All
VDD1 =3.13 V,
VDD2 = 3.13 V
01
01
02, 03
VDD1 =3.0 V,
VDD2 = 3.0 V
02, 03
VDD1 = 4.5 V,
VDD2 = 3.13 V
01
01
02, 03
02, 03
VDD1 = 4.5 V,
VDD2 = 3.0 V
Unit
Max
1, 2, 3
0.5
1
0.5
1, 2, 3
0.5
1
0.5
1, 2, 3
0.4
1
0.4
1, 2, 3
0.5
1
0.5
1, 2, 3
0.5
1
0.5
1, 2, 3
0.4
1
0.4
1, 2, 3
0.4
1
0.4
V
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
DSCC FORM 2234
APR 97
SIZE
5962-98580
A
REVISION LEVEL
D
SHEET
10
TABLE IA. Electrical performance characteristics - Continued.
Test
Low level output
voltage
Symbol
VOL2
9/
Test conditions 1/ 2/
-55°C ≤ TC ≤ +125°C
For 5.0 V supply:
+4.5 V ≤ VDD1 ≤ +5.5 V
For 3.3 V supply:
+3.0 V ≤ VDD2 ≤ +3.6 V
unless otherwise specified
A Port = 3.3V, IOL = 100 µA
For all inputs affecting output
under test, VIN = VDD2 or VSS
M, D, P, L, R 5/
A Port = 3.3V, IOL = 100 µA
For all inputs affecting output
under test, VIN = VDD2 or VSS
M, D, P, L, R 5/
A Port = 5.0V, IOL = 100 µA
For all inputs affecting output
under test, VIN = VDD2 or VSS
M, D, P, L, R 5/
B Port = 3.3V, IOL = 100 µA
For all inputs affecting output
under test, VIN = VDD1 or VSS
M, D, P, L, R 5/
B Port = 3.3V, IOL = 100 µA
For all inputs affecting output
under test, VIN = VDD1 or VSS
M, D, P, L, R 5/
B Port = 5.0V, IOL = 100 µA
For all inputs affecting output
under test, VIN = VDD1 or VSS
M, D, P, L, R 5/
B Port = 5.0V, IOL = 100 µA
For all inputs affecting output
under test, VIN = VDD1 or VSS
M, D, P, L, R 5/
Device
type
VDD
3/
Group A
subgroups
Limits 4/
Min
VDD1 = 4.5 V,
VDD2 = 3.13 V
01
01
1, 2, 3
1
02, 03
VDD1 = 4.5 V,
VDD2 = 3.0 V
02, 03
1
VDD1 = 4.5 V,
VDD2 = 4.5 V
All
All
VDD1= 3.13 V,
VDD2 = 3.13 V
01
01
02, 03
VDD1= 3.0 V,
VDD2 = 3.0 V
02, 03
VDD1 = 4.5 V,
VDD2 = 3.13 V
01
01
02, 03
02, 03
1, 2, 3
VDD1 = 4.5 V,
VDD2 = 3.0 V
Unit
Max
0.2
V
0.2
0.2
0.2
1, 2, 3
0.2
1
0.2
1, 2, 3
0.2
1
0.2
1, 2, 3
0.2
1
0.2
1, 2, 3
0.2
1
0.2
1, 2, 3
0.2
1
0.2
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
DSCC FORM 2234
APR 97
SIZE
5962-98580
A
REVISION LEVEL
D
SHEET
11
TABLE IA. Electrical performance characteristics - Continued.
Test
High level
output
voltage
Test conditions 1/ 2/
-55°C ≤ TC ≤ +125°C
For 5.0 V supply:
+4.5 V ≤ VDD1 ≤ +5.5 V
For 3.3 V supply:
+3.0 V ≤ VDD2 ≤ +3.6 V
unless otherwise specified
Symbol
VOH1
8/
A Port = 3.3V, IOH = -8 mA
For all inputs affecting output
under test, VIN = VDD2 or VSS
M, D, P, L, R 5/
A Port = 3.3V, IOH = -8 mA
For all inputs affecting output
under test, VIN = VDD2 or VSS
M, D, P, L, R 5/
A Port = 5.0V, IOH = -8 mA
For all inputs affecting output
under test, VIN = VDD2 or VSS
M, D, P, L, R 5/
B Port = 3.3V, IOH = -8 mA
For all inputs affecting output
under test, VIN = VDD1 or VSS
M, D, P, L, R 5/
B Port = 3.3V, IOH = -8 mA
For all inputs affecting output
under test, VIN = VDD1 or VSS
M, D, P, L, R 5/
B Port = 5.0V, IOH = -8 mA
For all inputs affecting output
under test, VIN = VDD1 or VSS
M, D, P, L, R 5/
B Port = 5.0V, IOH = -8 mA
For all inputs affecting output
under test, VIN = VDD1 or VSS
M, D, P, L, R 5/
VDD
3/
Device
type
Group A
subgroups
Min
VDD1 = 4.5 V,
VDD2 = 3.13 V
01
01
02, 03
VDD1 = 4.5 V,
VDD2 = 3.0 V
02, 03
VDD1 = 4.5 V,
VDD2 = 4.5 V
All
All
VDD1 =3.13 V,
VDD2 = 3.13 V
01
01
02, 03
VDD1 =3.0 V,
VDD2 = 3.0 V
02, 03
VDD1 = 4.5 V,
VDD2 = 3.13 V
01
01
02, 03
VDD1 = 4.5 V,
VDD2 = 3.0 V
02, 03
Unit
Limits 4/
Max
1, 2, 3
VDD2 –
0.9V
1
VDD2 –
0.9V
1, 2, 3
VDD2 –
0.9V
1
VDD2 –
0.9V
1, 2, 3
VDD2 –
0.7V
1
VDD2 –
0.7V
1, 2, 3
VDD1 –
0.9V
1
VDD1 –
0.9V
1, 2, 3
VDD1 –
0.9V
1
VDD1 –
0.9V
1, 2, 3
VDD1 –
0.7V
1
VDD1 –
0.7V
1, 2, 3
VDD1 –
0.7V
1
VDD1 –
0.7V
V
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
DSCC FORM 2234
APR 97
SIZE
5962-98580
A
REVISION LEVEL
D
SHEET
12
TABLE IA. Electrical performance characteristics - Continued.
Test
High level
output
voltage
Symbol
VOH2
9/
Test conditions 1/ 2/
-55°C ≤ TC ≤ +125°C
For 5.0 V supply:
+4.5 V ≤ VDD1 ≤ +5.5 V
For 3.3 V supply:
+3.0 V ≤ VDD2 ≤ +3.6 V
unless otherwise specified
A Port = 3.3V, IOH = -100 µA
For all inputs affecting output
under test, VIN = VDD2 or VSS
M, D, P, L, R 5/
A Port = 3.3V, IOH = -100 µA
For all inputs affecting output
under test, VIN = VDD2 or VSS
M, D, P, L, R 5/
A Port = 5.0V, IOH = -100 µA
For all inputs affecting output
under test, VIN = VDD2 or VSS
M, D, P, L, R 5/
B Port = 3.3V, IOH = -100 µA
For all inputs affecting output
under test, VIN = VDD1 or VSS
M, D, P, L, R 5/
B Port = 3.3V, IOH = -100 µA
For all inputs affecting output
under test, VIN = VDD1 or VSS
M, D, P, L, R 5/
B Port = 5.0V, IOH = -100 µA
For all inputs affecting output
under test, VIN = VDD1 or VSS
M, D, P, L, R 5/
B Port = 5.0V, IOH = -100 µA
For all inputs affecting output
under test, VIN = VDD1 or VSS
M, D, P, L, R 5/
VDD
3/
Device
type
Group A
subgroups
Min
VDD1 = 4.5 V,
VDD2 = 3.13 V
01
01
VDD1 = 4.5 V,
VDD2 = 3.0 V
02, 03
02, 03
VDD1 = 4.5 V,
VDD2 = 4.5 V
All
All
VDD1 =3.13 V,
VDD2 = 3.13 V
01
01
VDD1 =3.0 V,
VDD2 = 3.0 V
02, 03
02, 03
VDD1 = 4.5 V,
VDD2 = 3.13 V
01
01
02, 03
02, 03
VDD1 = 4.5 V,
VDD2 = 3.0 V
Unit
Limits 4/
1, 2, 3
VDD2 0.2V
1
VDD2 0.2V
1, 2, 3
VDD2 0.2V
1
VDD2 0.2V
1, 2, 3
VDD2 0.2V
1
VDD2 0.2V
1, 2, 3
VDD1 0.2V
1
VDD1 0.2V
1, 2, 3
VDD1 0.2V
1
VDD1 0.2V
1, 2, 3
VDD1 0.2V
1
VDD1 0.2V
1, 2, 3
VDD1 0.2V
1
VDD1 0.2V
Max
V
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
DSCC FORM 2234
APR 97
SIZE
5962-98580
A
REVISION LEVEL
D
SHEET
13
TABLE IA. Electrical performance characteristics - Continued.
Test
Output current
(Sink)
Symbol
IOL
10/
Test conditions 1/ 2/
-55°C ≤ TC ≤ +125°C
For 5.0 V supply:
+4.5 V ≤ VDD1 ≤ +5.5 V
For 3.3 V supply:
+3.0 V ≤ VDD2 ≤ +3.6 V
unless otherwise specified
IOH
10/
Group A
subgroups
Min
Max
VDD1 = 4.5 V,
VDD2 =3.13 V
1, 2, 3
8.0
02, 03
VDD1 = 4.5 V,
VDD2 =3.0 V
1, 2, 3
8.0
A Port = 5.0V
VIN = VSS
VOL = 0.4 V
All
VDD1 = 4.5 V,
VDD2 = 4.5 V
1, 2, 3
8.0
B Port = 3.3V
VIN = VSS
VOL = 0.5 V
01
VDD1 =3.13V,
VDD2 = 3.13V
1, 2, 3
8.0
02, 03
VDD1 =3.0V,
VDD2 = 3.0V
1, 2, 3
8.0
01
VDD1 = 4.5 V,
VDD2 =3.13 V
1, 2, 3
8.0
02, 03
VDD1 = 4.5 V,
VDD2 =3.0 V
1, 2, 3
8.0
01
VDD1 = 4.5 V,
VDD2 =3.13 V
1, 2, 3
-8.0
02, 03
VDD1 = 4.5 V,
VDD2 =3.0 V
1, 2, 3
-8.0
A Port = 5.0V
VIN = VDD2 or VSS
VOH = VDD2 - 0.7 V
All
VDD1 = 4.5 V,
VDD2 = 4.5 V
1, 2, 3
-8.0
B Port = 3.3V
VIN = VDD1 or VSS
VOH = VDD1 - 0.9 V
01
VDD1 =3.13V,
VDD2 = 3.13V
1, 2, 3
-8.0
02, 03
VDD1 =3.0V,
VDD2 = 3.0V
1, 2, 3
-8.0
01
VDD1 = 4.5 V,
VDD2 = 3.13V
1, 2, 3
-8.0
02, 03
VDD1 = 4.5 V,
VDD2 = 3.0V
1, 2, 3
-8.0
A Port = 3.3V
VIN = VDD2 or VSS
VOH = VDD2 - 0.9 V
B Port = 5.0V
VIN = VDD1 or VSS
VOH = VDD1 - 0.7 V
Unit
Limits 4/
01
A Port = 3.3V
VIN = VSS
VOL = 0.5 V
B Port = 5.0V
VIN = VSS
VOL = 0.4 V
Output current
(Source)
VDD
3/
Device
type
mA
mA
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
DSCC FORM 2234
APR 97
SIZE
5962-98580
A
REVISION LEVEL
D
SHEET
14
TABLE IA. Electrical performance characteristics - Continued.
Test
Three-state
output
leakage
current high
Test conditions 1/ 2/
-55°C ≤ TC ≤ +125°C
For 5.0 V supply:
+4.5 V ≤ VDD1 ≤ +5.5 V
For 3.3 V supply:
+3.0 V ≤ VDD2 ≤ +3.6 V
unless otherwise specified
Device
type
A Port = 3.3V
For input under test, VIN = VDD2
Other inputs, VIN = VDD2 or VSS
VOUT = VDD2
M, D, P, L, R 5/
All
Symbol
IOZH
7/
A Port = 5.0V
For input under test, VIN = VDD2
Other inputs, VIN = VDD2 or VSS
VOUT = VDD2
M, D, P, L, R 5/
B Port = 3.3V
For input under test, VIN = VDD1
Other inputs, VIN = VDD1 or VSS
VOUT = VDD1
M, D, P, L, R 5/
B Port = 5.0V
For input under test, VIN = VDD1
Other inputs, VIN = VDD1 or VSS
VOUT = VDD1
Three-state
output
leakage
current low
IOZL
7/
All
B Port = 5.0V
For input under test, VIN = VSS
Other inputs, VIN = VDD1 or VSS
VOUT = VSS
M, D, P, L, R 5/
VDD1 = 3.6 V,
VDD2 = 3.6 V
All
All
VDD1 = 5.5 V,
VDD2 = 3.6 V
All
All
B Port = 3.3V
For input under test, VIN = VSS
Other inputs, VIN = VDD1 or VSS
VOUT = VSS
M, D, P, L, R 5/
VDD1 = 5.5 V,
VDD2 = 5.5 V
All
A Port = 3.3V
For input under test, VIN = VSS
Other inputs, VIN = VDD2 or VSS
VOUT = VSS
M, D, P, L, R 5/
M, D, P, L, R 5/
VDD1 = 5.5 V,
VDD2 = 3.6 V
All
All
VOUT = VSS
Group A
subgroups
VDD1 = 5.5 V,
VDD2 = 3.6 V
All
VDD1 = 5.5 V,
VDD2 = 5.5 V
All
All
VDD1 = 3.6 V,
VDD2 = 3.6 V
All
All
VDD1 = 5.5 V,
VDD2 = 3.6 V
All
All
Unit
Limits 4/
Min
M, D, P, L, R 5/
A Port = 5.0V
For input under test, VIN = VSS
Other inputs, VIN = VDD2 or VSS
VDD
3/
Max
1, 2, 3
3.0
1
3.0
1, 2, 3
3.0
1
3.0
1, 2, 3
3.0
1
3.0
1, 2, 3
3.0
1
3.0
1, 2, 3
-1.0
1
-1.0
1, 2, 3
-1.0
1
-1.0
1, 2, 3
-1.0
1
-1.0
1, 2, 3
-1.0
1
-1.0
A
A
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
DSCC FORM 2234
APR 97
SIZE
5962-98580
A
REVISION LEVEL
D
SHEET
15
TABLE IA. Electrical performance characteristics - Continued.
Test
Short circuit
output current
Symbol
IOS
11/
12/
Test conditions 1/ 2/
-55°C ≤ TC ≤ +125°C
For 5.0 V supply:
+4.5 V ≤ VDD1 ≤ +5.5 V
For 3.3 V supply:
+3.0 V ≤ VDD2 ≤ +3.6 V
unless otherwise specified
VDD
3/
Device
type
Group A
subgroups
Unit
Limits 4/
Min
Max
A Port = 3.3V
VOUT = VDD2 or VSS
01
VDD1 = 4.5 V
and 5.5 V,
VDD2 =3.13 V
and 3.6 V
1, 2, 3
-100.0
100.0
A Port = 3.3V
VOUT = VDD2 or VSS
02, 03
VDD1 = 4.5 V
and 5.5 V,
VDD2 =3.0 V
and 3.6 V
1, 2, 3
-100.0
100.0
A Port = 5.0V
VOUT = VDD2 or VSS
All
VDD1 = 4.5 V
and 5.5 V,
VDD2 = 4.5 V
and 5.5 V
1, 2, 3
-200.0
200.0
B Port = 3.3V
VOUT = VDD1 or VSS
01
VDD1 =3.13 V
and 3.6 V,
VDD2 =3.13 V
and 3.6 V
1, 2, 3
-100.0
100.0
B Port = 3.3V
VOUT = VDD1 or VSS
02, 03
VDD1 =3.0 V
and 3.6 V,
VDD2 =3.0V
and 3.6 V
1, 2, 3
-100.0
100.0
B Port = 5.0V
VOUT = VDD1 or VSS
01
VDD1 = 4.5 V
and 5.5 V,
VDD2 =3.13 V
and 3.6 V
1, 2, 3
-200.0
200.0
B Port = 5.0V
VOUT = VDD1 or VSS
02, 03
VDD1 = 4.5 V
and 5.5 V,
VDD2 =3.0 V
and 3.6 V
1, 2, 3
-200.0
200.0
mA
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
DSCC FORM 2234
APR 97
SIZE
5962-98580
A
REVISION LEVEL
D
SHEET
16
TABLE IA. Electrical performance characteristics - Continued.
Test
Power
dissipation
Symbol
PD
11/ 13/
14/
Test conditions 1/ 2/
-55°C ≤ TC ≤ +125°C
For 5.0 V supply:
+4.5 V ≤ VDD1 ≤ +5.5 V
For 3.3 V supply:
+3.0 V ≤ VDD2 ≤ +3.6 V
unless otherwise specified
VDD
3/
Device
type
Group A
subgroups
Min
Max
A Port = 3.3V
CL = 50 pF,
per switching output
01
VDD1 = 4.5 V
and 5.5 V,
VDD2 =3.13 V
and 3.6 V
4, 5, 6
1.5
A Port = 3.3V
CL = 50 pF,
per switching output
02, 03
VDD1 = 4.5 V
and 5.5 V,
VDD2 =3.0 V
and 3.6 V
4, 5, 6
1.5
All
VDD1 = 4.5 V
and 5.5 V,
VDD2 = 4.5 V
and 5.5 V
4, 5, 6
2.0
01
VDD1 =3.13 V
and 3.6 V,
VDD2 =3.13 V
and 3.6 V
4, 5, 6
1.5
02, 03
VDD1 =3.0 V
and 3.6 V,
VDD2 =3.0 V
and 3.6 V
4, 5, 6
1.5
01
VDD1 = 4.5 V
and 5.5 V,
VDD2 =3.13 V
and 3.6 V
4, 5, 6
2.0
02, 03
VDD1 = 4.5 V
and 5.5 V,
VDD2 =3.0 V
and 3.6 V
4, 5, 6
2.0
A Port = 5.0V
CL = 50 pF,
per switching output
B Port = 3.3V
CL = 50 pF,
per switching output
B Port = 3.3V
CL = 50 pF,
per switching output
B Port = 5.0V
CL = 50 pF,
per switching output
B Port = 5.0V
CL = 50 pF,
per switching output
Unit
Limits 4/
mW/
MHz
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
DSCC FORM 2234
APR 97
SIZE
5962-98580
A
REVISION LEVEL
D
SHEET
17
TABLE IA. Electrical performance characteristics - Continued.
Test
Quiescent
supply
current
Test conditions 1/ 2/
-55°C ≤ TC ≤ +125°C
For 5.0 V supply:
+4.5 V ≤ VDD1 ≤ +5.5 V
For 3.3 V supply:
+3.0 V ≤ VDD2 ≤ +3.6 V
unless otherwise specified
Symbol
IDDQ
A Port = 5.0V
VIN = VDD2 or VSS
M, D, P, L, R 5/
B Port = 5.0V
VIN = VDD1 or VSS
M, D, P, L, R 5/
VDD
3/
Device
type
Group A
subgroups
Min
All
VDD1 = 5.5 V,
VDD2 = 5.5 V
All
All
VDD1 = 5.5 V,
VDD2 = 5.5 V
All
Unit
Limits 4/
Max
1
10.0
2, 3
100.0
1
500.0
1
10.0
2, 3
100.0
1
500.0
µA
Input
capacitance
CIN
f = 1 MHz,
See 4.4.1c
All
VDD1, VDD2 =
0.0 V
4
15
pF
Output
capacitance
COUT
f = 1 MHz,
See 4.4.1c
All
VDD1, VDD2 =
0.0 V
4
15
pF
Functional test
15/
VIH = 0.7VDD, VIL = 0.3VDD
See 4.4.1b
01
VDD1 = 4.5 V
and 5.5 V,
7, 8
L
H
7
L
H
7, 8
L
H
7
L
H
M, D, P, L, R 5/
VIH = 0.7VDD, VIL = 0.3VDD
See 4.4.1b
M, D, P, L, R 5/
01
02, 03
02, 03
VDD2 =3.13 V
and 3.6 V
VDD1 = 4.5 V
and 5.5 V,
VDD2 =3.0 V
and 3.6 V
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
DSCC FORM 2234
APR 97
SIZE
5962-98580
A
REVISION LEVEL
D
SHEET
18
TABLE IA. Electrical performance characteristics - Continued.
Test
Propagation
delay time,
data to bus
(active low)
Test conditions 1/ 2/
-55°C ≤ TC ≤ +125°C
For 5.0 V supply:
+4.5 V ≤ VDD1 ≤ +5.5 V
For 3.3 V supply:
+3.0 V ≤ VDD2 ≤ +3.6 V
unless otherwise specified
Symbol
tPLH
16/
B Port = 5V, A Port = 3.3V
CL = 50 pF, see figure 4
M, D, P, L, R 5/
B Port = 5V, A Port = 3.3V
CL = 50 pF, see figure 4
M, D, P, L, R 5/
A Port = B Port, 5V operation
CL = 50 pF, see figure 4
Propagation
delay time,
data to bus
(active high)
tPHL
16/
01
01
01
B Port = 5V, A Port = 3.3V
CL = 50 pF
see figure 4
M, D, P, L, R 5/
B Port = 5V, A Port = 3.3V
CL = 50 pF
see figure 4
M, D, P, L, R 5/
A Port = B Port, 5V operation
CL = 50 pF
see figure 4
M, D, P, L, R 5/
A Port = B Port
3.3 V operation
CL = 50 pF,
M, D, P, L, R 5/
see figure 4
A Port = B Port
3.3 V operation
CL = 50 pF,
M, D, P, L, R 5/
see figure 4
01
9
1.0
20.0
VDD1 = 4.5 V
and 5.5 V,
VDD2 =3.0 V
and 3.6 V
9, 10, 11
1.0
20.0
9
1.0
20.0
VDD1 = 4.5 V
and 5.5 V,
VDD2 = 4.5 V
and 5.5 V
9, 10, 11
1.0
15.0
9
1.0
15.0
VDD1 =3.13 V
and 3.6 V,
VDD2 =3.13 V
and 3.6 V
9, 10, 11
1.0
20.0
9
1.0
20.0
VDD1 =3.0 V
and 3.6 V,
VDD2 =3.0 V
and 3.6 V
9, 10, 11
1.0
20.0
9
1.0
20.0
VDD1 = 4.5 V
and 5.5 V,
VDD2 =3.13 V
and 3.6 V
9, 10, 11
1.0
20.0
9
1.0
20.0
VDD1 = 4.5 V
and 5.5 V,
VDD2 =3.0 V
and 3.6 V
9, 10, 11
1.0
20.0
9
1.0
20.0
VDD1 = 4.5 V
and 5.5 V,
VDD2 = 4.5 V
and 5.5 V
9, 10, 11
1.0
15.0
9
1.0
15.0
VDD1 =3.13 V
and 3.6 V,
VDD2 =3.13 V
and 3.6 V
9, 10, 11
1.0
20.0
9
1.0
20.0
VDD1 =3.0 V
and 3.6 V,
VDD2 =3.0 V
and 3.6 V
9, 10, 11
1.0
20.0
9
1.0
20.0
02, 03
01
02, 03
02, 03
All
All
01
01
Max
20.0
02, 03
01
Min
1.0
All
A Port = B Port
3.3 V operation
CL = 50 pF,
M, D, P, L, R 5/
see figure 4
Unit
Limits 4/
9, 10, 11
02, 03
All
Group A
subgroups
VDD1 = 4.5 V
and 5.5 V,
VDD2 =3.13 V
and 3.6 V
02, 03
M, D, P, L, R 5/
A Port = B Port
3.3V operation
CL = 50 pF,
M, D, P, L, R 5/
see figure 4
VDD
3/
Device
type
02, 03
02, 03
ns
ns
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
DSCC FORM 2234
APR 97
SIZE
5962-98580
A
REVISION LEVEL
D
SHEET
19
TABLE IA. Electrical performance characteristics - Continued.
Test
Propagation
delay time,
output enable,
OEn to bus
(active low)
Symbol
tPZL
16/
Test conditions 1/ 2/
-55°C ≤ TC ≤ +125°C
For 5.0 V supply:
+4.5 V ≤ VDD1 ≤ +5.5 V
For 3.3 V supply:
+3.0 V ≤ VDD2 ≤ +3.6 V
unless otherwise specified
Device
type
B Port = 5V, A Port = 3.3V
CL = 50 pF
see figure 4
M, D, P, L, R 5/
01
B Port = 5V, A Port = 3.3V
CL = 50 pF
see figure 4
M, D, P, L, R 5/
02, 03
A Port = B Port, 5V operation
CL = 50 pF, see figure 4
Propagation
delay time,
output enable,
OEn to bus
(active high)
tPZH
16/
01
VDD
3/
A Port = B Port
3.3 V operation
CL = 50 pF
M, D, P, L, R 5/
see figure 4
01
A Port = B Port
3.3V operation
CL = 50 pF
M, D, P, L, R 5/
see figure 4
02, 03
B Port = 5V, A Port = 3.3V
CL = 50 pF
see figure 4
M, D, P, L, R 5/
01
B Port = 5V, A Port = 3.3V
CL = 50 pF
see figure 4
M, D, P, L, R 5/
02, 03
A Port = B Port, 5V operation
CL = 50 pF
see figure 4
M, D, P, L, R 5/
All
A Port = B Port
3.3 V operation
CL = 50 pF
M, D, P, L, R 5/
see figure 4
01
A Port = B Port
3.3 V operation
CL = 50 pF
M, D, P, L, R 5/
see figure 4
02, 03
01
18.0
9
1.0
18.0
VDD1 = 4.5 V
and 5.5 V,
VDD2 =3.0 V
and 3.6 V
9, 10, 11
1.0
18.0
9
1.0
18.0
VDD1 = 4.5 V
and 5.5 V,
VDD2 = 4.5 V
and 5.5 V
9, 10, 11
1.0
12.0
9
1.0
12.0
VDD1 =3.13 V
and 3.6 V,
VDD2 =3.13 V
and 3.6 V
9, 10, 11
1.0
18.0
9
1.0
18.0
VDD1 =3.0 V
and 3.6 V,
VDD2 =3.0 V
and 3.6 V
9, 10, 11
1.0
18.0
9
1.0
18.0
VDD1 = 4.5 V
and 5.5 V,
VDD2 =3.13 V
and 3.6 V
9, 10, 11
1.0
18.0
9
1.0
18.0
VDD1 = 4.5 V
and 5.5 V,
VDD2 =3.0 V
and 3.6 V
9, 10, 11
1.0
18.0
9
1.0
18.0
VDD1 = 4.5 V
and 5.5 V,
VDD2 = 4.5 V
and 5.5 V
9, 10, 11
1.0
12.0
9
1.0
12.0
VDD1 =3.13 V
and 3.6 V,
VDD2 =3.13 V
and 3.6 V
9, 10, 11
1.0
18.0
9
1.0
18.0
VDD1 =3.0 V
and 3.6 V,
VDD2 =3.0 V
and 3.6 V
9, 10, 11
1.0
18.0
9
1.0
18.0
02, 03
All
01
Max
1.0
02, 03
01
Min
9, 10, 11
All
All
Unit
Limits 4/
VDD1 = 4.5 V
and 5.5 V,
VDD2 =3.13 V
and 3.6 V
02, 03
M, D, P, L, R 5/
Group A
subgroups
02, 03
ns
ns
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
DSCC FORM 2234
APR 97
SIZE
5962-98580
A
REVISION LEVEL
D
SHEET
20
TABLE IA. Electrical performance characteristics - Continued.
Test
Propagation
delay time,
output disable,
OEn to bus
(high
impedance)
Propagation
delay time,
output disable,
OEn to bus
(high
impedance)
Symbol
tPLZ
16/
tPHZ
16/
Test conditions 1/ 2/
-55°C ≤ TC ≤ +125°C
For 5.0 V supply:
+4.5 V ≤ VDD1 ≤ +5.5 V
For 3.3 V supply:
+3.0 V ≤ VDD2 ≤ +3.6 V
unless otherwise specified
Device
type
B Port = 5V
A Port = 3.3V
CL = 50 pF
M, D, P, L, R 5/
see figure 4
01
B Port = 5V
A Port = 3.3V
CL = 50 pF
M, D, P, L, R 5/
see figure 4
02, 03
A Port = B Port
5V operation
CL = 50 pF
M, D, P, L, R 5/
see figure 4
All
A Port = B Port
3.3 V operation
CL = 50 pF
M, D, P, L, R 5/
see figure 4
01
A Port = B Port
3.3 V operation
CL = 50 pF
M, D, P, L, R 5/
see figure 4
02, 03
B Port = 5V
A Port = 3.3V
CL = 50 pF
M, D, P, L, R 5/
see figure 4
01
B Port = 5V
A Port = 3.3V
CL = 50 pF
M, D, P, L, R 5/
see figure 4
02, 03
A Port = B Port
5V operation
CL = 50 pF
M, D, P, L, R 5/
see figure 4
All
A Port = B Port
3.3 V operation
CL = 50 pF
M, D, P, L, R 5/
see figure 4
01
A Port = B Port
3.3 V operation
CL = 50 pF
M, D, P, L, R 5/
see figure 4
02, 03
01
VDD
3/
Max
1.0
20.0
9
1.0
20.0
VDD1 = 4.5 V
and 5.5 V,
VDD2 =3.0 V
and 3.6 V
9, 10, 11
1.0
20.0
9
1.0
20.0
VDD1 = 4.5 V
and 5.5 V,
VDD2 = 4.5 V
and 5.5 V
9, 10, 11
1.0
15.0
9
1.0
15.0
VDD1 =3.13 V
and 3.6 V,
VDD2 =3.13 V
and 3.6 V
9, 10, 11
1.0
20.0
9
1.0
20.0
VDD1 =3.0 V
and 3.6 V,
VDD2 =3.0 V
and 3.6 V
9, 10, 11
1.0
20.0
9
1.0
20.0
VDD1 = 4.5 V
and 5.5 V,
VDD2 =3.13 V
and 3.6 V
9, 10, 11
1.0
20.0
9
1.0
20.0
VDD1 = 4.5 V
and 5.5 V,
VDD2 =3.0 V
and 3.6 V
9, 10, 11
1.0
20.0
9
1.0
20.0
VDD1 = 4.5 V
and 5.5 V,
VDD2 = 4.5 V
and 5.5 V
9, 10, 11
1.0
15.0
9
1.0
15.0
VDD1 =3.13 V
and 3.6 V,
VDD2 =3.13 V
and 3.6 V
9, 10, 11
1.0
20.0
9
1.0
20.0
VDD1 =3.0 V
and 3.6 V,
VDD2 =3.0 V
and 3.6 V
9, 10, 11
1.0
20.0
9
1.0
20.0
02, 03
02, 03
All
01
Min
9, 10, 11
All
01
Unit
Limits 4/
VDD1 = 4.5 V
and 5.5 V,
VDD2 =3.13 V
and 3.6 V
02, 03
01
Group A
subgroups
02, 03
ns
ns
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
DSCC FORM 2234
APR 97
SIZE
5962-98580
A
REVISION LEVEL
D
SHEET
21
TABLE IA. Electrical performance characteristics - Continued.
Test
Propagation
delay time,
output enable,
DIRn to bus
(active low)
Symbol
tPZL
17/
Test conditions 1/ 2/
-55°C ≤ TC ≤ +125°C
For 5.0 V supply:
+4.5 V ≤ VDD1 ≤ +5.5 V
For 3.3 V supply:
+3.0 V ≤ VDD2 ≤ +3.6 V
unless otherwise specified
Device
type
B Port = 5V
A Port = 3.3V
CL = 50 pF
M, D, P, L, R 5/
see figure 4
01
B Port = 5V
A Port = 3.3V
CL = 50 pF
M, D, P, L, R 5/
see figure 4
A Port = B Port
5V operation
CL = 50 pF
M, D, P, L, R 5/
see figure 4
A Port = B Port
3.3 V operation
CL = 50 pF
M, D, P, L, R 5/
see figure 4
A Port = B Port
3.3 V operation
CL = 50 pF
M, D, P, L, R 5/
see figure 4
Propagation
delay time,
output enable,
DIRn to bus
(active high)
tPZH
17/
B Port = 5V
A Port = 3.3V
CL = 50 pF
M, D, P, L, R 5/
see figure 4
B Port = 5V
A Port = 3.3V
CL = 50 pF
M, D, P, L, R 5/
see figure 4
A Port = B Port
5V operation
CL = 50 pF
M, D, P, L, R 5/
see figure 4
A Port = B Port
3.3 V operation
CL = 50 pF
M, D, P, L, R 5/
see figure 4
A Port = B Port
3.3 V operation
CL = 50 pF
M, D, P, L, R 5/
see figure 4
01
VDD
3/
18.0
9
1.0
18.0
VDD1 = 4.5 V
and 5.5 V,
VDD2 =3.0 V
and 3.6 V
9, 10, 11
1.0
18.0
9
1.0
18.0
VDD1 = 4.5 V
and 5.5 V,
VDD2 = 4.5 V
and 5.5 V
9, 10, 11
1.0
12.0
9
1.0
12.0
VDD1 =3.13 V
and 3.6 V,
VDD2 =3.13 V
and 3.6 V
9, 10, 11
1.0
18.0
9
1.0
18.0
VDD1 =3.0 V
and 3.6 V,
VDD2 =3.0 V
and 3.6 V
9, 10, 11
1.0
18.0
9
1.0
18.0
VDD1 = 4.5 V
and 5.5 V,
VDD2 =3.13 V
and 3.6 V
9, 10, 11
1.0
18.0
9
1.0
18.0
VDD1 = 4.5 V
and 5.5 V,
VDD2 =3.0 V
and 3.6 V
9, 10, 11
1.0
18.0
9
1.0
18.0
VDD1 = 4.5 V
and 5.5 V,
VDD2 = 4.5 V
and 5.5 V
9, 10, 11
1.0
12.0
9
1.0
12.0
VDD1 =3.13 V
and 3.6 V,
VDD2 =3.13 V
and 3.6 V
9, 10, 11
1.0
18.0
9
1.0
18.0
VDD1 =3.0 V
and 3.6 V,
VDD2 =3.0 V
and 3.6 V
9, 10, 11
1.0
18.0
9
1.0
18.0
All
02, 03
02, 03
01
02, 03
02, 03
All
All
01
01
Max
1.0
All
01
Min
9, 10, 11
02, 03
01
Unit
Limits 4/
VDD1 = 4.5 V
and 5.5 V,
VDD2 =3.13 V
and 3.6 V
02, 03
01
Group A
subgroups
02, 03
02, 03
ns
ns
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
DSCC FORM 2234
APR 97
SIZE
5962-98580
A
REVISION LEVEL
D
SHEET
22
TABLE IA. Electrical performance characteristics - Continued.
Test
Propagation
delay time,
output disable,
DIRn to bus
(high
impedance)
Symbol
tPLZ
17/
Test conditions 1/ 2/
-55°C ≤ TC ≤ +125°C
For 5.0 V supply:
+4.5 V ≤ VDD1 ≤ +5.5 V
For 3.3 V supply:
+3.0 V ≤ VDD2 ≤ +3.6 V
unless otherwise specified
Device
type
B Port = 5V
A Port = 3.3V
CL = 50 pF
M, D, P, L, R 5/
see figure 4
01
B Port = 5V
A Port = 3.3V
CL = 50 pF
M, D, P, L, R 5/
see figure 4
02, 03
A Port = B Port
5V Operation
CL = 50 pF
see figure 4
Propagation
delay time,
output disable,
DIRn to bus
(high
impedance)
tPHZ
17/
01
VDD
3/
01
A Port = B Port
3.3 V operation
CL = 50 pF
M, D, P, L, R 5/
see figure 4
02, 03
B Port = 5V
A Port = 3.3V
CL = 50 pF
M, D, P, L, R 5/
see figure 4
01
B Port = 5V
A Port = 3.3V
CL = 50 pF
M, D, P, L, R 5/
see figure 4
02, 03
A Port = B Port
5V Operation
CL = 50 pF
M, D, P, L, R 5/
see figure 4
All
A Port = B Port
3.3 V operation
CL = 50 pF
M, D, P, L, R 5/
see figure 4
01
A Port = B Port
3.3 V operation
CL = 50 pF
M, D, P, L, R 5/
see figure 4
02, 03
01
20.0
9
1.0
20.0
VDD1 = 4.5 V
and 5.5 V,
VDD2 =3.0 V
and 3.6 V
9, 10, 11
1.0
20.0
9
1.0
20.0
VDD1 = 4.5 V
and 5.5 V,
9, 10, 11
1.0
15.0
9
1.0
15.0
VDD1 =3.13 V
and 3.6 V,
VDD2 =3.13 V
and 3.6 V
9, 10, 11
1.0
20.0
9
1.0
20.0
VDD1 =3.0 V
and 3.6 V,
VDD2 =3.0 V
and 3.6 V
9, 10, 11
1.0
20.0
9
1.0
20.0
VDD1 = 4.5 V
and 5.5 V,
VDD2 =3.13 V
and 3.6 V
9, 10, 11
1.0
20.0
9
1.0
20.0
VDD1 = 4.5 V
and 5.5 V,
VDD2 =3.0 V
and 3.6 V
9, 10, 11
1.0
20.0
9
1.0
20.0
VDD1 = 4.5 V
and 5.5 V,
VDD2 = 4.5 V
and 5.5 V
9, 10, 11
1.0
15.0
9
1.0
15.0
VDD1 =3.13 V
and 3.6 V,
VDD2 =3.13 V
and 3.6 V
9, 10, 11
1.0
20.0
9
1.0
20.0
VDD1 =3.0 V
and 3.6 V,
VDD2 =3.0 V
and 3.6 V
9, 10, 11
1.0
20.0
9
1.0
20.0
02, 03
01
02, 03
All
01
Max
1.0
VDD2 = 4.5 V
and 5.5 V
A Port = B Port
3.3 V operation
CL = 50 pF
M, D, P, L, R 5/
see figure 4
Min
9, 10, 11
All
All
Unit
Limits 4/
VDD1 = 4.5 V
and 5.5 V,
VDD2 =3.13 V
and 3.6 V
02, 03
M, D, P, L, R 5/
Group A
subgroup
s
02, 03
ns
ns
See footnotes on next page.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
DSCC FORM 2234
APR 97
SIZE
5962-98580
A
REVISION LEVEL
D
SHEET
23
TABLE IA. Electrical performance characteristics - Continued.
1/
Each input/output, as applicable, shall be tested at the specified temperature, for the specified limits, to the tests in table I
herein. Output terminals not designated shall be high level logic, low level logic, or open, except for all IDD tests, where the
output terminals shall be open. When performing these tests, the current meter shall be placed in the circuit such that all
current flows through the meter. For input terminals not designated, VIN = VSS or VIN ≥ 3.13 V for device type 01 and 3.0 V
for device types 02 and 03.
2/
Temperature range for device type 03 is -40°C to +125°C.
2/
This device requires both VDD1 and VDD2 power supplies for operation. The power supply will be indicated followed by the
voltage to which the power supply is set to for the given test
3/
For negative and positive voltage and current values, the sign designates the potential difference in reference to VSS and
the direction of current flow, respectively; and the absolute value of the magnitude, not the sign, is relative to the minimum
and maximum limits, as applicable, listed herein.
4/
Devices supplied to this drawing meet all levels M, D, P, L, and R of irradiation. However, these devices are only tested at
the "R" level. Pre and post irradiation values are identical unless otherwise specified in table IA. When performing post
irradiation electrical measurements for any RHA level, TA = +25°C.
5/
Guaranteed; tested on a sample of pins per device at 3.6 V, 4.5 V, and 5.5 V. Tested on all pins at 3.13 V for device type
01 and 3.0 V for device types 02 and 03.
6/
Guaranteed; tested on a sample of pins at 3.6 V. Tested on all pins at 5.5 V.
7/
Guaranteed; tested on a sample of pins at 3.13 V for device type 01 and 3.0 V for device types 02 and 03.
Tested on all pins at 4.5 V.
8/
Guaranteed; tested on a sample of pins at 3.13 V for device type 01 and 3.0 V for device types 02 and 03, and 4.5 V.
9/
Guaranteed based on characterization data but not tested.
10/
This parameter is supplied as design limit but not guaranteed or tested.
11/
No more than one output should be shorted at a time for a maximum duration of one second.
12/
Power does not include power contribution of any CMOS output sink current.
13/
Power dissipation specified per switching output.
14/
Tests shall be performed in sequence, attributes data only. Functional tests shall include the truth table and other logic
patterns used for fault detection. The test vectors used to verify the truth table shall, at a minimum, test all functions of
each input and output. All possible input to output logic patterns per function shall be guaranteed, if not tested, to the truth
table in figure 2 herein. Functional tests shall be performed in sequence as approved by the qualifying activity on qualified
devices. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH =
VIH(min + 20%, - 0%); VIL = VIL(max + 0%, - 50%), as specified herein, for TTL, CMOS, or Schmitt compatible inputs.
Devices are guaranteed to VIH(min) and VIL(max).
15/
For propagation delay tests, all paths must be tested.
16/
Guaranteed by design but not tested.
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Case outline X
FIGURE 1. Case outline
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Case outline X
Symbol
A
b
b1
c
c1
D
E
E1
E2
E3
e
k
L
Q
S1
M
N
NOTES:
1/
2/
3/
4/
5/
6/
Min
.080
.006
.006
.004
.004
.610
.370
.430
.180
.030
Inches
Nom
Max
.120
.015
.013
.010
.008
.640
.390
.470
Millimeters
Nom
Min
2.032
0.1524
0.1524
0.1016
0.1016
15.494
9.398
10.922
4.572
0.762
.025 BSC
N/A
.250
.026
.005
Max
3.048
0.381
0.3302
0.254
0.2032
16.256
9.906
11.938
0.635
N/A
.370
.045
6.35
0.6604
0.127
9.398
1.143
.0015
0.0381
48
48
All exposed metalized areas must be gold plated over electroplated nickel per MIL-PRF-38535.
The lids are electrically connected to VSS.
Lead finishes are in accordance with MIL-PRF-38535.
Dimension symbology is in accordance with MIL-PRF-38535.
Lead position and coplanarity are not measured.
ID mark symbol is vendor option: No alphanumerics. One or both ID methods may be used for pin 1 ID.
FIGURE 1. Case outline - Continued.
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Device type
Case outlines
Terminal
number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Terminal
symbol
All
X
Terminal
number
Terminal
symbol
DIR1
1B1
1B2
VSS
1B3
1B4
VDD1
1B5
1B6
VSS
1B7
1B8
2B1
2B2
VSS
2B3
2B4
VDD1
2B5
2B6
VSS
2B7
2B8
DIR2
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
OE2
2A8
2A7
VSS
2A6
2A5
VDD2
2A4
2A3
VSS
2A2
2A1
1A8
1A7
VSS
1A6
1A5
VDD2
1A4
1A3
VSS
1A2
1A1
OE1
Pin description
Terminal symbol
Description
OEn
Output Enable inputs (active low)
DIRn
Direction control inputs
nAn
Side A inputs or 3-state outputs (3.3 V Port)
nBn
Side B inputs or 3-state outputs (5.0 V Port)
FIGURE 2. Terminal connections.
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Inputs
Operation
Enable
OEn
Direction
DIRn
L
L
B data to A bus
L
H
A data to B bus
H
X
Isolation
H = High voltage level
L = Low voltage level
X = Irrelevant
Port A
Port B
Operation
3.3 Volts
5.0 Volts
Voltage Translator
5.0 Volts
5.0 Volts
Non-Translating
3.3 Volts
3.3 Volts
Non-Translating
VSS
VSS
Cold Spare
3.3 V or 5.0 V
VSS
Port B Cold Spare
NOTE:
Control signals DIRx and OEx are 5 volt tolerant inputs. When
VDD2 is at 3.3 volts, either 3.3 or 5.0 volt CMOS logic levels can
be applied to all control inputs. For proper operation, connect
power to all VDD and ground all VSS pins (i.e., no floating VDD or
VSS input pins). Tie unused inputs to VSS.
If VDD1 and VDD2 are not powered up together, then VDD2 should
be powered up first for proper control of DIRx and OEx. The
internal state of DIRx and OEx is unknown when VDD2 is not
powered, because the internal circuitry for these pins is powered
by VDD2. Until VDD2 reaches 2.75 V ±5%, control of the outputs
by DIRx and OEx cannot be guaranteed. During operation of
the part, after power up, insure VDD1 ≥ VDD2.
FIGURE 3. Truth table.
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FIGURE 4. Logic diagram.
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FIGURE 4. Logic diagram - Continued.
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FIGURE 5. Switching waveforms and test circuit.
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Notes:
1/
2/
3/
4/
VREF = 0.5VDD.
CL = 50 pF minimum or equivalent (includes test jig and probe capacitance).
ISRC is set to -1.0 mA and ISNK is set to 1.0 mA for tPHL and tPLH measurements.
Input signal from pulse generator: VIN = 0.0 V to VDD; f ≤ 10 MHz; tr = 1.0 V/ns "0.3 V/ns; tf = 1.0 V/ns "0.3 V/ns; tr
and tf shall be measured from 0.1 VDD to 0.9 VDD and from 0.9 VDD to 0.1 VDD, respectively.
FIGURE 5. Switching waveforms and test circuit - Continued.
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4. QUALITY ASSURANCE PROVISIONS
4.1 Sampling and inspection. For device classes Q and V, sampling and inspection procedures shall be in accordance with
MIL-PRF-38535 or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan
shall not affect the form, fit, or function as described herein. For device class M, sampling and inspection procedures shall be
in accordance with MIL-PRF-38535, appendix A.
4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and shall be conducted
on all devices prior to qualification and technology conformance inspection. For device class M, screening shall be in
accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection.
4.2.1 Additional criteria for device class M.
a.
Burn-in test, method 1015 of MIL-STD-883.
(1) Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision
level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall
specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified
in test method 1015.
(2) TA = +125°C, minimum.
b.
Interim and final electrical test parameters shall be as specified in table IIA herein.
4.2.2 Additional criteria for device classes Q and V.
a.
The burn-in test duration, test condition and test temperature, or approved alternatives shall be as specified in the
device manufacturer's QM plan in accordance with MIL-PRF-38535. The burn-in test circuit shall be maintained
under document revision level control of the device manufacturer's Technology Review Board (TRB) in accordance
with MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit
shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified
in test method 1015 of MIL-STD-883.
b.
Interim and final electrical test parameters shall be as specified in table IIA herein.
c.
Additional screening for device class V beyond the requirements of device class Q shall be as specified in
MIL-PRF-38535, appendix B.
4.3 Qualification inspection for device classes Q and V. Qualification inspection for device classes Q and V shall be in
accordance with MIL-PRF-38535. Inspections to be performed shall be those specified in MIL-PRF-38535 and herein for
groups A, B, C, D, and E inspections (see 4.4.1 through 4.4.4).
4.4 Conformance inspection. Technology conformance inspection for classes Q and V shall be in accordance with
MIL-PRF-38535 including groups A, B, C, D, and E inspections and as specified herein. Quality conformance inspection for
device class M shall be in accordance with MIL-PRF-38535, appendix A and as specified herein. Inspections to be performed
for device class M shall be those specified in method 5005 of MIL-STD-883 and herein for groups A, B, C, D, and E
inspections (see 4.4.1 through 4.4.4).
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TABLE IB. SEP test limits. 1/ 2/
Device
type
TA =
Temperature
±10°C
3/
All
+25°C
VDD1 = 4.5 V
Bias for
latch-up test
Effective LET
no upsets
2
[MeV/(mg/cm )]
Maximum device
cross section
LET ≥ 80
6 x 10 cm /bit
-9
2
VDD = 5.5 V
no latch-up
LET = 3/ 4/
≥ 120
1/ For SEP test conditions, see 4.4.4.4 herein.
2/ Technology characterization and model verification supplemented by in-line data may be
used in lieu of end-of-line testing. Test plan must be approved by TRB and qualifying activity.
3/ Worst case temperature is TA ≥ +125°C.
2
4/ Tested to a LET of ≤ 120 MeV/(mg/cm ), with no latch-up (SEL).
TABLE IIA. Electrical test requirements.
Test requirements
Subgroups
(in accordance with
MIL-STD-883,
method 5005, table I)
Subgroups
(in accordance with
MIL-PRF-38535, table III)
Device
class M
Device
class Q
Device
class V
Interim electrical
parameters (see 4.2)
1, 7, 9
1, 7, 9
1, 7, 9
Final electrical
parameters (see 4.2)
1/ 1, 2, 3, 7,
8, 9, 10, 11
1/ 1, 2, 3, 7,
8, 9, 10, 11
2/ 3/ 1, 2, 3, 7,
8, 9, 10, 11
Group A test
requirements (see 4.4)
1, 2, 3, 4, 5, 6,
7, 8, 9, 10, 11
1, 2, 3, 4, 5, 6,
7, 8, 9, 10, 11
1, 2, 3, 4, 5, 6,
7, 8, 9, 10, 11
Group C end-point electrical
parameters (see 4.4)
1, 2, 3, 7, 8, 9,
10, 11
1, 2, 3, 7, 8, 9,
10, 11
3/ 1, 2, 3, 7,
8, 9, 10, 11
Group D end-point electrical
parameters (see 4.4)
1, 7, 9
1, 7, 9
1, 7, 9
Group E end-point electrical
parameters (see 4.4)
1, 7, 9
1, 7, 9
1, 7, 9
1/ PDA applies to subgroups 1 and 7.
2/ PDA applies to subgroups 1, 7, and deltas.
3/ Delta limits as specified in table IIB herein shall be required where specified, and the delta
values shall be completed with reference to the zero hour electrical parameters.
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TABLE IIB. Burn-in and operating life test, Delta parameters (+25°C).
Parameters
Symbol
Delta limits
Output voltage low
VOL
±100 mV
Output voltage high
VOH
±100 mV
TABLE III. Irradiation test connections.
Device types
All
Open
13, 14, 16, 17, 19, 20,
22, 23, 37, 38, 40, 41,
43, 44, 46, 47
VDD = 5.0 V ±0.5 V
Ground
1, 2, 4, 5, 8, 10, 11, 15, 21,
25, 26, 28, 29, 32, 34, 35,
39, 45, 48
3, 6, 7, 9, 12, 18, 24,
27, 30, 31, 33, 36, 42
NOTE: Each pin except 4, 7, 10, 15, 18, 21, 28, 31, 34, 39, 42 and 45 will have a resistor of
2.49 kΩ ±5% for irradiation testing.
4.4.1 Group A inspection.
a. Tests shall be as specified in table IIA herein.
b.
For device class M, subgroups 7 and 8 tests shall be sufficient to verify the truth table in figure 3 herein. For device
classes Q and V, subgroups 7 and 8 shall include verifying the functionality of the device.
c.
CIN and COUT, shall be measured only for initial qualification and after process or design changes which may affect
capacitance. CIN and COUT shall be measured between the designated terminal and VSS at a frequency of 1 MHz. For
CIN and COUT, test all applicable pins on five devices with zero failures.
4.4.2 Group C inspection. The group C inspection end-point electrical parameters shall be as specified in table IIA herein.
4.4.2.1 Additional criteria for device class M. Steady-state life test conditions, method 1005 of MIL-STD-883:
a. Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision level
control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify
the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test
method 1005 of MIL-STD-883.
b.
TA = +125°C, minimum.
c.
Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STD-883.
4.4.2.2 Additional criteria for device classes Q and V. The steady-state life test duration, test condition and test
temperature, or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with
MIL-PRF-38535. The test circuit shall be maintained under document revision level control by the device manufacturer's TRB
in accordance with MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test
circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in
test method 1005 of MIL-STD-883.
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4.4.3 Group D inspection. The group D inspection end-point electrical parameters shall be as specified in table IIA herein.
4.4.4 Group E inspection. Group E inspection is required only for parts intended to be marked as radiation hardness
assured (see 3.5 herein).
a.
End-point electrical parameters shall be as specified in table IIA herein.
b.
For device classes Q, and V, the devices or test vehicle shall be subjected to radiation hardness assured tests as
specified in MIL-PRF-38535 for the RHA level being tested. For device class M, the devices shall be subjected to
radiation hardness assured tests as specified in MIL-PRF-38535, appendix A for the RHA level being tested. All
device classes must meet the postirradiation end-point electrical parameter limits as defined in table IA at
TA = +25°C ±5°C, after exposure, to the subgroups specified in table IIA herein.
c.
When specified in the purchase order or contract, a copy of the RHA delta limits shall be supplied.
4.4.4.1 Total dose irradiation testing. Total dose irradiation testing shall be performed in accordance with MIL-STD-883, test
method 1019, condition A, and as specified herein.
4.4.4.1.1 Accelerated aging testing. Accelerated aging testing shall be performed on all devices requiring a RHA level
greater than 5k rads (Si). The post-anneal end-point electrical parameter limits shall be as specified in table IA herein and
shall be the pre-irradiation end-point electrical parameter limits at 25°C ±5°C. Testing shall be performed at initial qualification
and after any design or process changes which may affect the RHA response of the device.
4.4.4.2 Dose rate induced latchup testing. Dose rate induced latchup testing shall be performed in accordance with test
method 1020 of MIL-STD-883 and as specified herein (see 1.5 herein). Tests shall be performed on devices, SEC, or
approved test structures at technology qualification and after any design or process changes which may affect the RHA
capability of the process.
4.4.4.4 Single event phenomena (SEP). SEP testing shall be required on class V devices (see 1.5 herein). SEP testing
shall be performed on a technology process on the Standard Evaluation Circuit (SEC) or alternate SEP test vehicle as
approved by the qualifying activity at initial qualification and after any design or process changes which may affect the upset or
latchup characteristics. The recommended test conditions for SEP are as follows:
a. The ion beam angle of incidence shall be between normal to the die surface and 60° to the normal, inclusive
(i.e. 0° ≤ angle ≤ 60°). No shadowing of the ion beam due to fixturing or package related effects is allowed.
b. The fluence shall be ≥ 100 errors or ≥ 10 ions/cm .
6
2
5
2
2
c. The flux shall be between 10 and 10 ions/cm /s. The cross-section shall be verified to be flux independent by
measuring the cross-section at two flux rates which differ by at least an order of magnitude.
d. The particle range shall be ≥ 20 micron in silicon.
e. The test temperature shall be +25°C for the upset measurements and the maximum rated operating temperature ±10°C
for the latchup measurements.
f. Bias conditions shall be defined by the manufacturer for the latchup measurements.
g. Test four devices with zero failures.
h. For SEP test limits, see table IB herein.
4.5 Methods of inspection. Methods of inspection shall be specified as follows:
4.5.1 Voltage and current. Unless otherwise specified, all voltages given are referenced to the microcircuit VSS terminal.
Currents given are conventional current and positive when flowing into the referenced terminal.
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5. PACKAGING
5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38535 for device
classes Q and V or MIL-PRF-38535, appendix A for device class M.
6. NOTES
6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications
(original equipment), design applications, and logistics purposes.
6.1.1 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a
contractor-prepared specification or drawing.
6.1.2 Substitutability. Device class Q devices will replace device class M devices.
6.2 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated with the users of record for
the individual documents. This coordination will be accomplished using DD Form 1692, Engineering Change Proposal.
6.3 Record of users. Military and industrial users should inform Defense Supply Center Columbus when a system
application requires configuration control and which SMD's are applicable to that system. DSCC will maintain a record of users
and this list will be used for coordination and distribution of changes to the drawings. Users of drawings covering
microelectronic devices (FSC 5962) should contact DSCC-VA, telephone (614) 692-0544.
6.4 Comments. Comments on this drawing should be directed to DSCC-VA , Columbus, Ohio 43216-5000, or telephone
(614) 692-0547.
6.5 Abbreviations, symbols, and definitions. The abbreviations, symbols, and definitions used herein are defined in
MIL-PRF-38535 and MIL-HDBK-1331.
6.6 Sources of supply.
6.6.1 Sources of supply for device classes Q and V. Sources of supply for device classes Q and V are listed in
QML-38535. The vendors listed in QML-38535 have submitted a certificate of compliance (see 3.6 herein) to DSCC-VA and
have agreed to this drawing.
6.6.2 Approved sources of supply for device class M. Approved sources of supply for class M are listed in MIL-HDBK-103.
The vendors listed in MIL-HDBK-103 have agreed to this drawing and a certificate of compliance (see 3.6 herein) has been
submitted to and accepted by DSCC-VA.
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APPENDIX A
A.1 SCOPE
A.1.1 Scope. This appendix establishes minimum requirements for microcircuit die to be supplied under the Qualified
Manufacturers List (QML) Program. QML microcircuit die meeting the requirements of MIL-PRF-38535 and the manufacturers
approved QM plan for use in monolithic microcircuits, multichip modules (MCMs), hybrids, electronic modules, or devices using
chip and wire designs in accordance with MIL-PRF-38534 are specified herein. Two product assurance classes consisting of
military high reliability (device class Q) and space application (device Class V) are reflected in the Part or Identification Number
(PIN). When available a choice of Radiation Hardiness Assurance (RHA) levels are reflected in the PIN.
A.1.2 PIN. The PIN shall be as shown in the following example:
5962
R
Federal
stock class
designator
\
RHA
designator
(see A.2.1)
98580
01
V
Device
type
(see A.2.2)
Device
class
designator
(see A.2.3)
/
9
Die
code
A
Die
Details
(see A.2.4)
\/
Drawing number
A.1.2.1 RHA designator. Device classes Q and V RHA identified die shall meet the MIL-PRF-38535 specified RHA levels.
A dash (-) indicates a non-RHA die.
A.1.2.2 Device type(s). The device type(s) shall identify the circuit function as follows:
Device type
Generic number
01
54ACS164245S
Radiation hardened, Schmitt 16-bit
bidirectional mult-purpose transceiver with
three-state outputs and cold sparing
02
54ACS164245S 1/
Radiation hardened, Schmitt 16-bit
bidirectional multi-purpose transceiver with
three-state outputs, cold sparing, and extended
voltage range
03
54ACS164245S 1/ 2/
Radiation hardened, Schmitt 16-bit
bidirectional multi-purpose transceiver with
three-state outputs, cold sparing, extended
voltage range, and extended industrial
temperature range of -40°C to +125°C
Circuit function
A.1.2.3 Device class designator.
Device class
Q or V
Device requirements documentation
Certification and qualification to the die requirements of MIL-PRF-38535.
_______
1/ Device types 02 and 03 have an extended voltage range.
2/ Device type 03 has an extended industrial temperature range of -40°C to +125°C.
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APPENDIX A
A.1.2.4 Die Details. The die details designation shall be a unique letter which designates the die’s physical dimensions,
bonding pad location(s) and related electrical function(s), interface materials, and other assembly related information, for each
product and variant supplied to this appendix.
A.1.2.4.1 Die Physical dimensions.
Die Type
Figure number
01, 02, 03
A-1
A.1.2.4.2 Die Bonding pad locations and Electrical functions.
Die Type
Figure number
01, 02, 03
A-1
A.1.2.4.3 Interface Materials.
Die Type
Figure number
01, 02, 03
A-1
A.1.2.4.4 Assembly related information.
Die Type
Figure number
01, 02, 03
A-1
A.1.3 Absolute maximum ratings. See paragraph 1.3 herein for details.
A.1.4 Recommended operating conditions. See paragraph 1.4 herein for details.
A.2. APPLICABLE DOCUMENTS
A.2.1 Government specifications, standards, bulletin, and handbooks. Unless otherwise specified, the following
specifications, standards, bulletin, and handbook of the issue listed in that issue of the Department of Defense Index of
Specifications and Standards specified in the solicitation, form a part of this drawing to the extent specified herein.
SPECIFICATIONS
DEPARTMENT OF DEFENSE
MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for.
STANDARDS
DEPARTMENT OF DEFENSE
MIL-STD-883 - Test Method Standard Microcircuits.
HANDBOOKS
DEPARTMENT OF DEFENSE
MIL-HDBK-103 - List of Standard Microcircuit Drawings.
(Copies of the specification, standards, bulletin, and handbook required by manufacturers in connection with specific
acquisition functions should be obtained from the contracting activity or as directed by the contracting activity).
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
DSCC FORM 2234
APR 97
SIZE
5962-98580
A
REVISION LEVEL
D
SHEET
39
APPENDIX A
A.2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the
text of this drawing shall take precedence.
A.3 REQUIREMENTS
A.3.1 Item Requirements. The individual item requirements for device classes Q and V shall be in accordance with
MIL-PRF-38535 and as specified herein or as modified in the device manufacturer’s Quality Management (QM) plan. The
modification in the QM plan shall not effect the form, fit or function as described herein.
A.3.2 Design, construction and physical dimensions. The design, construction and physical dimensions shall be as
specified in MIL-PRF-38535 and the manufacturer’s QM plan, for device classes Q and V and herein.
A.3.2.1 Die Physical dimensions. The die physical dimensions shall be as specified in A.1.2.4.1 and on figure A-1.
A.3.2.2 Die bonding pad locations and electrical functions. The die bonding pad locations and electrical functions shall be
as specified in A.1.2.4.2 and on figure A-1.
A.3.2.3 Interface materials. The interface materials for the die shall be as specified in A.1.2.4.3 and on figure A-1.
A.3.2.4 Assembly related information. The assembly related information shall be as specified in A.1.2.4.4 and on
figure A-1.
A.3.2.5 Truth table(s). The truth table(s) shall be as defined in paragraph 3.2.3 herein.
A.3.2.6 Radiation exposure circuit. The radiation exposure circuit shall be as defined within paragraph 3.2.7 of the body of
this document.
A.3.3 Electrical performance characteristics and post-irradiation parameter limits. Unless otherwise specified herein, the
electrical performance characteristics and post-irradiation parameter limits are as specified in table I of the body of this
document.
A.3.4 Electrical test requirements. The wafer probe test requirements shall include functional and parametric testing
sufficient to make the packaged die capable of meeting the electrical performance requirements in table I.
A.3.5 Marking. As a minimum, each unique lot of die, loaded in single or multiple stack of carriers, for shipment to a
customer, shall be identified with the wafer lot number, the certification mark, the manufacturer’s identification and the PIN listed
in A.1.2 herein. The certification mark shall be a “QML” or “Q” as required by MIL-PRF-38535.
A.3.6 Certification of compliance. For device classes Q and V, a certificate of compliance shall be required from a
QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see A.6.4 herein). The certificate of
compliance submitted to DSCC-VA prior to listing as an approved source of supply for this appendix shall affirm that the
manufacturer’s product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and the requirements herein.
A.3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535
shall be provided with each lot of microcircuit die delivered to this drawing.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
DSCC FORM 2234
APR 97
SIZE
5962-98580
A
REVISION LEVEL
D
SHEET
40
APPENDIX A
A.4. QUALITY ASSURANCE PROVISIONS
A.4.1 Sampling and inspection. For device classes Q and V, die sampling and inspection procedures shall be in
accordance with MIL-PRF-38535 or as modified in the device manufacturer’s Quality Management (QM) plan. The
modifications in the QM plan shall not effect the form, fit or function as described herein.
A.4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and as defined in the
manufacturer’s QM plan. As a minimum it shall consist of:
a) Wafer Lot acceptance for Class V product using the criteria defined within MIL-STD-883 test method 5007.
b) 100% wafer probe (see paragraph A.3.4 herein).
c) 100% internal visual inspection to the applicable class Q or V criteria defined within MIL-STD-883 test method 2010
or the alternate procedures allowed within MIL-STD-883 test method 5004.
A.4.3 Conformance inspection.
A.4.3.1 Group E inspection. Group E inspection is required only for parts intended to be identified as radiation assured (see
A.3.5 herein). RHA levels for device classes Q and V shall be as specified in MIL-PRF-38535. End point electrical testing of
packaged die shall be as specified in table IIA herein. Group E tests and conditions are as specified in paragraphs 4.4.4 herein.
A.5. DIE CARRIER
A.5.1 Die carrier requirements. The requirements for the die carrier shall be accordance with the manufacturer’s QM plan or
as specified in the purchase order by the acquiring activity. The die carrier shall provide adequate physical, mechanical and
electrostatic protection.
A.6. NOTES
A.6.1 Intended use. Microcircuit die conforming to this drawing are intended for use in microcircuits built in accordance with
MIL-PRF-38535 or MIL-PRF-38534 for government microcircuit applications (original equipment), design applications and
logistics purposes.
A.6.2 Comments. Comments on this appendix should be directed to DSCC-VA, Columbus, Ohio, 43216-5000 or telephone
(614)-692-0536.
A.6.3 Abbreviations, symbols and definitions. The abbreviations, symbols, and definitions used herein are defined in
MIL-PRF-38535 and MIL-HDBK-1331.
A.6.4 Sources of supply for device classes Q and V. Sources of supply for device classes Q and V are listed in
QML-38535. The vendors listed within QML-38535 have submitted a certificate of compliance (see A.3.6 herein) to DSCC-VA
and have agreed to this drawing.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
DSCC FORM 2234
APR 97
SIZE
5962-98580
A
REVISION LEVEL
D
SHEET
41
APPENDIX A
FIGURE A-1
DIE PHYSICAL DIMENSIONS
Die Size:
Die Thickness:
132.97 x 115.827 mils.
17.5 +/- 1 mils.
DIE BONDING PAD LOCATIONS AND ELECTRICAL FUNCTIONS
NOTE: Pad numbers reflect terminal numbers when placed in Case Outline X (see Figure 2).
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
DSCC FORM 2234
APR 97
SIZE
5962-98580
A
REVISION LEVEL
D
SHEET
42
APPENDIX A
INTERFACE MATERIALS
Top Metallization:
Si Al Cu
6.2kA – 7.6kA
Backside Metallization:
None.
Glassivation
Type:
Thickness:
Oxide/Nitride
9kA - 11kA
Substrate:
Epitaxial Layer on Single crystal silicon.
ASSEMBLY RELATED INFORMATION
Substrate Potential:
Tied to VSS.
Special assembly
instructions:
None.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
DSCC FORM 2234
APR 97
SIZE
5962-98580
A
REVISION LEVEL
D
SHEET
43
STANDARD MICROCIRCUIT DRAWING SOURCE APPROVAL BULLETIN
DATE: 02-05-10
Approved sources of supply for SMD 5962-98580 are listed below for immediate acquisition information only and
shall be added to MIL-HDBK-103 and QML-38535 during the next revision. MIL-HDBK-103 and QML-38535 will be
revised to include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a
certificate of compliance has been submitted to and accepted by DSCC-VA. This bulletin is superseded by the next
dated revision of MIL-HDBK-103 and QML-38535.
Standard
microcircuit drawing
PIN 1/
Vendor
CAGE
number
Vendor
similar
PIN 2/
5962-9858001QXC
65342
UT54ACS164245SUCC
5962R9858001VXC
65342
UT54ACS164245SUCCR
5962-9858001Q9A
65342
UT54ACS164245S-Q DIE
5962R9858001V9A
65342
UT54ACS164245S-V DIE
5962-9858002QXC
65342
UT54ACS164245SUCC 3/
5962R9858002VXC
65342
UT54ACS164245SUCCR 3/
5962-9858002Q9A
65342
UT54ACS164245S-Q DIE 3/
5962R9858002V9A
65342
UT54ACS164245S-V DIE 3/
5962-9858003QXC
65342
UT54ACS164245SUCC 3/ 4/
5962R9858003VXC
65342
UT54ACS164245SUCCR 3/ 4/
5962-9858003Q9A
65342
UT54ACS164245S-Q DIE 3/ 4/
5962R9858003V9A
65342
UT54ACS164245S-V DIE 3/ 4/
1/ The lead finish shown for each PIN representing a hermetic
package is the most readily available from the manufacturer
listed for that part. If the desired lead finish is not listed
contact the Vendor to determine its availability.
2/ Caution. Do not use this number for item acquisition.
Items acquired to this number may not satisfy the performance
requirements of this drawing.
3/ These parts have an extended voltage range.
4/ These parts have an extended industrial temperature range
of -40°C to +125°C.
Vendor CAGE
number
65342
Vendor name
and address
UTMC Microelectronic Systems
4350 Centennial Boulevard
Colorado Springs, CO 80907-3486
The information contained herein is disseminated for convenience only and the
Government assumes no liability whatsoever for any inaccuracies in the
information bulletin.