a LC2MOS 16-Bit, High-Speed Sampling ADCs AD7884/AD7885 FUNCTIONAL BLOCK DIAGRAMS FEATURES Monolithic Construction Fast Conversion: 5.3 s High Throughput: 166 kSPS Low Power: 250 mW APPLICATIONS Automatic Test Equipment Medical Instrumentation Industrial Control Data Acquisition Systems Robotics ⴞ3VINF ⴞ3VINS ⴞ5VINF R3 3k⍀ C1 R2 3k⍀ ⴞ5VINS AD7884 R1 5k⍀ SW1 R4 4k⍀ R6 2k⍀ AGNDS AGNDF AVDD AVSS VDD VSS R5 4k⍀ A1 SW2 9-BIT ADC VREF– O U LATCH T 16 P + U ALU T 9 9 D R I V 16 E R S DB15 DB0 A2 SW3 16-BIT ACCURATE DAC 9 TIMER The AD7884/AD7885 has its own internal oscillator which controls conversion. It runs from ±5 V supplies and needs a VREF+ of 3 V. The AD7884 is available in a 40-lead Cerdip package and in a 44-lead PLCC package. CS RD R7 2k⍀ GENERAL DESCRIPTION The AD7884/AD7885 is a 16-bit monolithic analog-to-digital converter with internal sample-and-hold and a conversion time of 5.3 µs. The maximum throughput rate is 166 kSPS. It uses a two-pass flash architecture to achieve this speed. Two input ranges are available: ± 5 V and ± 3 V. Conversion is initiated by the CONVST signal. The result can be read into a microprocessor using the CS and RD inputs on the device. The AD7884 has a 16-bit parallel reading structure while the AD7885 has a byte reading structure. The conversion result is in two’s complement code. CONTROL R8 2k⍀ VREF+F VREF+S VINV VREF– GND CONVST BUSY ⴞ3VIN AGNDS AGNDF AVDD AVSS VDD VSS R3 3k⍀ C1 R2 3k⍀ ⴞ5VINS ⴞ5VINF DGND AD7885 R1 5k⍀ R6 2k⍀ SW1 R4 4k⍀ R5 4k⍀ A1 SW2 9-BIT ADC VREF– The AD7885 is available in a 28-lead Cerdip package and the AD7885A is available in a 44-lead PLCC package. OD UR LATCH T I 16 P V + E U ALU T R 9 S DB7 9 8 DB0 A2 SW3 16-BIT ACCURATE DAC 9 TIMER CONTROL CS RD R7 2k⍀ HBEN R8 2k⍀ VREF+F VREF+S VINV VREF– GND CONVST BUSY DGND REV. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2002 (V = 5 V ⴞ 5%, V AD7884/AD7885/AD7885A–SPECIFICATIONS V +S = 3 V; AGND = DGND = GND = 0 V; f = 166 kHz. All specifications T to T , unless otherwise noted.) DD REF SAMPLE MIN SS = –5 V ⴞ 5%, MAX J Version1, 2, 3 A Version1, 2, 3 B Versions1, 2, 3 Unit 16 16 16 Bits 16 16 ± 0.1 ± 0.03 ±2 ± 0.05 ±2 ± 0.05 ±8 ± 0.1 ±8 ± 0.03 ±2 120 ±2 120 16 ± 0.0075 ± 0.03 ± 0.05 ±2 ± 0.05 ± 0.15 ±8 ± 0.03 ± 0.05 ±2 120 Bits % FSR max % FSR typ % FSR max ppm FSR/°C typ % FSR typ % FSR max ppm FSR/°C typ % FSR typ % FSR max ppm FSR/°C typ µV rms typ 78 µV rms typical in ± 3 V Input Range 82 82 –84 –84 –88 84 82 –88 –84 –88 84 82 –88 –84 –88 dB min dB typ dB max dB typ dB max Input Signal: ± 5 V, 1 kHz Sine Wave, Typically 86 dB Input Signal: ± 5 V, 12 kHz Sine Wave Input Signal: ± 5 V, 1 kHz Sine Wave Input Signal: ± 5 V, 12 kHz Sine Wave Input Signal: ± 5 V, 1 kHz Sine Wave –84 –84 –84 –84 –84 –84 dB typ dB typ fA = 11.5 kHz, fB = 12 kHz, fSAMPLE = 166 kHz fA = 11.5 kHz, fB = 12 kHz, fSAMPLE = 166 kHz 5.3 2.5 166 5.3 2.5 166 5.3 2.5 166 µs max µs max kSPS max There is an overlap between conversion and acquisition. ±5 ±3 ±4 ±5 ±3 ±4 ±5 ±3 ±4 Volts Volts mA max REFERENCE INPUT Reference Input Current ±5 ±5 ±5 mA max VREF+S = 3 V LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN4 2.4 0.8 ± 10 10 2.4 0.8 ± 10 10 2.4 0.8 ± 10 10 V min V max µA max pF max VDD = 5 V ± 5% VDD = 5 V ± 5% Input Level = 0 V to VDD 4.0 0.4 4.0 0.4 4.0 0.4 V min V max ISOURCE = 40 µA ISINK = 1.6 mA 10 15 10 15 10 15 µA max pF max 5 –5 35 30 5 –5 35 30 5 –5 35 30 V nom V nom mA max mA max ± 5% for Specified Performance ± 5% for Specified Performance Typically 25 mA Typically 25 mA 86 86 325 86 86 325 86 86 325 dB typ dB typ mW max Typically 250 mW Parameter DC ACCURACY Resolution Minimum Resolution for Which No Missing Codes Are Guaranteed Integral Nonlinearity Positive Gain Error Positive Gain Error Gain TC4 Bipolar Zero Error Bipolar Zero Error Bipolar Zero TC4 Negative Gain Error Negative Gain Error Offset TC4 Noise DYNAMIC PERFORMANCE Signal to (Noise + Distortion) Ratio Total Harmonic Distortion Peak Harmonic or Spurious Noise Intermodulation Distortion (IMD) Second Order Terms Third Order Terms CONVERSION TIME Conversion Time Acquisition Time Throughput Rate ANALOG INPUT Voltage Range Input Current LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL DB15–DB0 Floating-State Leakage Current Floating-State Output Capacitance4 POWER REQUIREMENTS VDD VSS IDD ISS Power Supply Rejection Ratio ∆Gain/∆VDD ∆Gain/∆VSS Power Dissipation Test Conditions/Comments Typically 0.003% FSR AD7885AN/BN: 0.1% typ AD7885BN: 0.2% max AD7885AN/BN: 0.1% typ AD7885BN: 0.2% max NOTES 1 Temperature ranges are as follows: J, A, B Versions: –40°C to +85°C. 2 VIN = ± 5 V. 3 The AD7885AAP has the same specs as the AD7884AP. The AD7885ABP has the same specs as the AD7884BP. 4 Sample tested to ensure compliance. Specifications subject to change without notice. –2– REV. D AD7884/AD7885 TIMING CHARACTERISTICS1, 2 (V Parameter t1 t2 t3 t4 t5 t6 2 t7 3 t8 t9 t10 t11 t12 t13 t14 DD = +5 V ⴞ 5%, VSS = –5 V ⴞ 5%, AGND = DGND = GND = 0 V. See Figures 2, 3, 4, and 5.) Limit at 25ⴗC (All Versions) Limit at TMIN, TMAX (A, B, and J Versions) Unit 50 100 0 60 0 57 5 50 40 10 25 60 60 55 55 50 100 0 60 0 57 5 50 40 80 25 60 60 70 70 Conditions/Comments CONVST Pulsewidth CONVST to BUSY Low Delay CS to RD Setup Time RD Pulsewidth CS to RD Hold Time Data Access Time After RD Bus Relinquish Time After RD ns min ns max ns min ns min ns min ns max ns min ns max ns min ns min ns min ns min ns min ns max ns max New Data Valid before Rising Edge of BUSY HBEN to RD Setup Time HBEN to RD Hold Time HBEN Low Pulse Duration HBEN High Pulse Duration Propagation Delay from HBEN Falling to Data Valid Propagation Delay from HBEN Rising to Data Valid NOTES 1 Sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. 2 t6 is measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V. 3 t7 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time, t 7, quoted in the Timing Characteristics is the true bus relinquish time of the part and as such is independent of external bus loading capacitances. Specifications subject to change without notice. 1.6mA IOL 2.1V TO OUTPUT PIN CL 100pF 200A IOH Figure 1. Load Circuit for Access Time and Bus Relinquish Time REV. D –3– AD7884/AD7885 CONVST t1 t1 CONVST CS t3 t2 t5 t4 RD t CONVERT BUSY t2 t8 t CONVERT BUSY DATA t7 OLD DATA VALID NEW DATA VALID t6 HI-Z DATA HI-Z DATA VALID Figure 2. AD7884 Timing Diagram, Using CS and RD Figure 3. AD7884 Timing Diagram, with CS and RD Permanently Low t1 CONVST t 10 t9 HBEN CS t3 t4 t5 RD t CONVERT t2 BUSY t7 t6 HI-Z DATA DATA VALID HI-Z DATA VALID DB0–DB7 HI-Z DB8–DB15 Figure 4. AD7885 Timing Diagram, Using CS and RD t1 CONVST t 11 HBEN t2 t 12 t CONVERT BUSY t8 DATA OLD DATA VALID (DB8–DB15) t 13 NEW DATA VALID (DB8–DB15) t 14 NEW DATA VALID (DB0–DB7) NEW DATA VALID (DB8–DB15) NEW DATA VALID (DB0–DB7) Figure 5. AD7885 Timing Diagram, with CS and RD Permanently Low –4– REV. D AD7884/AD7885 ORDERING GUIDE Model Linearity Temperature Range AD7884AP AD7884BP AD7885AAP AD7885ABP AD7884AQ AD7884BQ AD7885JQ AD7885AQ AD7885BQ –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C Error (% FSR) ± 0.0075 ± 0.0075 ± 0.0075 ± 0.0075 SNR (dB) Package Option 84 84 84 84 84 84 82 84 84 P-44A P-44A P-44A P-44A Q-40 Q-40 Q-28 Q-28 Q-28 NOTE P = Plastic Leaded Chip Carrier (PLCC); Q = Cerdip. ABSOLUTE MAXIMUM RATINGS 1 VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V VSS to AGND . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –7 V AVSS to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to –7 V AGND Pins to DGND . . . . . . . . . . . . –0.3 V to VDD + 0.3 V AVDD to VDD2 . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V AVSS to VSS2 . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –7 V GND to DGND . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V VINS, VINF to AGND . . . . . . . . . . VSS – 0.3 V to VDD + 0.3 V VREF+ to AGND . . . . . . . . . . . . . . VSS – 0.3 V to VDD + 0.3 V VREF– to AGND . . . . . . . . . . . . . . . VSS – 0.3 V to VDD + 0.3 V VINV to AGND . . . . . . . . . . . . . . . VSS – 0.3 V to VDD + 0.3 V Digital Inputs to DGND . . . . . . . . . . . –0.3 V to VDD + 0.3 V Digital Outputs to DGND . . . . . . . . . . –0.3 V to VDD + 0.3 V Operating Temperature Range Commercial Plastic (A, B Versions) . . . . . –40°C to +85°C Industrial Cerdip (J, A, B Versions) . . . . . . –40°C to +85°C Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300°C 28-Lead Cerdip θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 50.9°C/W θJC Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 8.3°C/W 40-Lead Cerdip θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 44.5°C/W 44-Lead PLCC θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 47.7°C/W θJC Thermal Impedance . . . . . . . . . . . . . . . . . . . . 17.5°C/W Power Dissipation (Any Package) to 75°C . . . . . . . . 1000 mW Degradation above 75°C by . . . . . . . . . . . . . . . . . . 10 mW/°C NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 If the AD7884/AD7885 is being powered from separate analog and digital supplies, AVSS should always come up before V SS. See Figure 12 for a recommended protection circuit using Schottky diodes. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7884/AD7885 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. D –5– WARNING! ESD SENSITIVE DEVICE AD7884/AD7885 PIN CONFIGURATIONS AGNDS 5 24 DB6 35 DB12 AGNDF 6 23 DB5 AGNDS 7 34 DB11 AVDD 7 AGNDF 8 33 DB10 AVDD 9 TOP VIEW AVSS 8 (Not to Scale) 21 DGND CONVST 12 17 DB0 GND 12 29 VDD VSS 13 28 DB7 CS 13 16 BUSY VSS 14 27 DB6 RD 14 15 HBEN VDD 15 26 DB5 CONVST 16 25 DB4 CS 17 24 DB3 RD 18 23 DB2 VSS 19 22 DB1 BUSY 20 21 DB0 DB10 36 35 DB9 DB8 34 NC 33 DGND VDD 15 31 DB7 VSS 16 VDD 17 30 DB6 DB5 29 18 19 20 21 22 23 24 25 26 27 28 VREF+S VREF+F 18 DB1 37 32 NC 19 DB2 DB12 DB11 14 VINV VSS 10 VDD 11 TOP VIEW (Not to Scale) 13 RD VSS 20 DB3 12 3VINS VREF GND 9 NC GND GND VSS AD7884 CONVST CS TOP VIEW 31 DB8 GND 11 (Not to Scale) 30 DGND 22 DB4 5VINS 3VINF 32 DB9 AGNDF 9 AVDD 10 AVSS 11 4 2 1 44 43 42 41 40 6 5 3 NC = NO CONNECT PIN 1 IDENTIFIER 5VINF 7 AGNDS 8 AGNDF 9 AVDD 10 AVSS 11 NC 12 GND 13 GND 14 VSS 15 38 DB7 DB6 37 NC 36 39 AD7885A 35 DB5 DB4 TOP VIEW (Not to Scale) 34 NC 33 32 DGND VDD 31 DB3 30 DB2 DB1 VSS 16 VDD 17 29 18 19 20 21 22 23 24 25 26 27 28 CONVST CS AVSS 10 AD7884 AD7885 DB13 36 DB13 6 38 39 DB4 5 5VINF PIN 1 IDENTIFIER 5VINF 7 AGNDS 8 NC 5VINS 44 43 42 41 40 –6– DB0 25 DB7 1 DB15 DB14 5VINF 4 2 3 DB3 37 DB14 4 DB2 4 5 NC NC 3VINF 6 NC NC 26 VREF+F VREF+S VREF+F 5VINS 3 NC 38 DB15 NC 3 DB0 DB1 27 VREF+S 3VINS 28 VINV NC 3VIN 2 VINV VREF– 1 39 VREF+F BUSY NC 40 VREF+S 2 BUSY NC 1 RD HBEN VINV VREF– 3VINS VREF PLCC 5VINS 3VINF CERDIP NC = NO CONNECT REV. D AD7884/AD7885 PIN FUNCTION DESCRIPTION AD7884 AD7885 AD7885A Description VINV VINV VINV VREF– VREF– VREF– ± 3 VINS _ ± 3 VINS ± 3 VINF _ ± 3 VINF – ± 3 VIN – ± 5 VINS ± 5 VINS ± 5 VINS ± 5 VINF ± 5 VINF ± 5 VINF AGNDS AGNDF AVDD AVSS GND VSS VDD CONVST CS RD AGNDS AGNDF AVDD AVSS GND VSS VDD CONVST CS RD AGNDS AGNDF AVDD AVSS GND VSS VDD CONVST CS RD – HBEN HBEN BUSY BUSY BUSY DB0–DB15 – DGND VREF+F VREF+S – DB0–DB7 DGND VREF+F VREF+S – DB0–DB7 DGND VREF+F VREF+S This pin is connected to the inverting terminal of an op amp, as in Figure 6, and allows the inversion of the supplied 3 V reference. This is the negative reference input, and it can be obtained by using an external amplifier to invert the positive reference input. In this case, the amplifier output is connected to VREF–. See Figure 6. This is the analog input sense pin for the ± 3 volt analog input range on the AD7884 and AD7885A. This is the analog input force pin for the ± 3 volt analog input range on the AD7884 and AD7885A. When using this input range, the ± 5 VINF and ± 5 VINS pins should be tied to AGND. This is the analog input pin for the ± 3 volt analog input range on the AD7885. When using this input range, the ± 5 VINF and ± 5 VINS pins should be tied to AGND. This is the analog input sense pin for the ± 5 volt analog input range on both the AD7884, AD7885 and AD7885A. This is the analog input force pin for the ± 5 volt analog input range on both the AD7884, AD7885 and AD7885A. When using this input range, the ± 3 VINF and ± 3 VINS pins should be tied to AGND. This is the ground return sense pin for the 9-bit ADC and the on-chip residue amplifier. This is the ground return force pin for the 9-bit ADC and the on-chip residue amplifier. Positive analog power rail for the sample-and-hold amplifier and the residue amplifier. Negative analog power rail for the sample-and-hold amplifier and the residue amplifier. This is the ground return for sample-and-hold section. Negative supply for the 9-bit ADC. Positive supply for the 9-bit ADC and all device logic. This asynchronous control input starts conversion. Chip Select control input. Read control input. This is used in conjunction with CS to read the conversion result from the device output latch. High Byte Enable. Active high control input for the AD7885. It selects either the high or the low byte of the conversion for reading. Busy output. The Busy output goes low when conversion begins and stays low until it is completed, at which time it goes high. Sixteen-bit parallel data word output on the AD7884. Eight-bit parallel data byte output on the AD7885. Ground return for all device logic. Reference force input. Reference sense input. The device operates from a 3 V reference. REV. D –7– AD7884/AD7885 TERMINOLOGY Integral Nonlinearity This is the deviation of the midscale transition (all 0s to all 1s) from the ideal (AGND). The AD7884/AD7885 is tested using the CCIFF standard where two input frequencies near the top end of the input bandwidth are used. In this case, the second and third order terms are of different significance. The second order terms are usually distanced in frequency from the original sine waves while the third order terms are usually at a frequency close to the input frequencies. As a result, the second and third order terms are specified separately. The calculation of the intermodulation distortion is as per the THD specification where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the fundamental expressed in dBs. Positive Gain Error Power Supply Rejection Ratio This is the deviation of the last code transition (01 . . . 110 to 01 . . . 111) from the ideal (+VREF+S – 1 LSB), after Bipolar Zero Error has been adjusted out. This is the ratio, in dBs, of the change in positive gain error to the change in VDD or VSS. It is a dc measurement. Negative Gain Error OPERATIONAL DIAGRAM This is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. Differential Nonlinearity This is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. Bipolar Zero Error An operational diagram for the AD7884/AD7885 is shown in Figure 6. It is set up for an analog input range of ± 5 V. If a ± 3 V input range is required, A1 should drive ± 3 VINS and ± 3 VINF with ± 5 VINS, ± 5 VINF being tied to system AGND. This is the deviation of the first code transition (10 . . . 000 to 10 . . . 001) from the ideal (–VREF+S + 1 LSB), after Bipolar Zero Error has been adjusted out. Signal to (Noise + Distortion) Ratio This is the measured ratio of signal to (noise + distortion) at the output of the A/D converter. The signal is the rms amplitude of the fundamental. Noise is the rms sum of all nonfundamental signals up to half the sampling frequency (fS/2), excluding dc. The ratio is dependent upon the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. The theoretical signal to (noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by: +5V –5V AVDD VDD AVSS VSS 5VINS 5VINF A1 VIN AD817 AD711 3VINS 3VINF AD7884/ AD7885 Signal to (Noise + Distortion) = (6.02N + 1.76) dB AGNDS Thus for an ideal 16-bit converter, this is 98 dB. AD817 Total Harmonic Distortion A2 Total harmonic distortion (THD) is the ratio of the rms sum of harmonics to the fundamental. For the AD7884/AD7885, it is defined as: THD (dB) = 20 log DATA OUTPUTS CONTROL INPUTS VDD = +5V AD845, AD817 OR EQUIVALENT 2 V 22 +V 32 +V 42 +V 52 +V 62 V1 AGNDF A3 6 VREF+S VREF+F AD780 10F 8 where V1 is the rms amplitude of the fundamental and V2, V3, V4, V5 and V6 are the rms amplitudes of the second through the sixth harmonics. 4 AD845, AD817 OR EQUIVALENT A4 VINV VREF– GND DGND Peak Harmonic or Spurious Noise Peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the ADC output spectrum (up to fS/2 and excluding dc) to the rms value of the fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for parts where the harmonics are buried in the noise floor, it will be a noise peak. NOTE: POWER SUPPLY DECOUPLING NOT SHOWN Figure 6. AD7884/AD7885 Operational Diagram The chosen input buffer amplifier (A1) should have low noise and distortion and fast settling time for high bandwidth applications. Both the AD711 and the AD845 are suitable amplifiers. A2 is the force, sense amplifier for AGND. The AGNDS pin should be at zero potential. Therefore, the amplifier must have a low input offset voltage and good noise performance. It must also have the ability to deal with fast current transients on the AGNDS pin. The AD817 has the required performance and is the recommended amplifier. Intermodulation Distortion With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities will create distortion products at sum and difference frequencies of mfa ± nfb where m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for which neither m or n are equal to zero. For example, the second order terms include (fa + fb) and (fa – fb), while the third order terms include (2fa + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb). If AGNDS and AGNDF are simply tied together to Star Ground instead of buffering, the SNR and THD are not significantly degraded. However, dc specifications like INL, Bipolar Zero and Gain Error will be degraded. –8– REV. D AD7884/AD7885 The required 3 V reference is derived from the AD780 and buffered by the high-speed amplifier A3 (AD845, AD817 or equivalent). A4 is a unity gain inverter which provides the –3 V negative reference. The gain setting resistors are on-chip and are factory trimmed to ensure precise tracking of VREF+. Figure 6 shows A3 and A4 as AD845s or AD817s. These have the ability to respond to the rapidly changing reference input impedance. CIRCUIT DESCRIPTION Analog Input Section The analog input section of the AD7884/AD7885 is shown in Figure 7. It contains both the input signal conditioning and sample-and-hold amplifier. Note that the analog input is truly benign. When SW1a goes open circuit to put the SHA into the hold mode, SW1b is closed. This means that the input resistors, R1 and R2 are always connected to either virtual ground or true ground. The signal at the output of A2 is proportional to the error between the first phase result and the actual analog input signal, and is digitized in the second conversion phase. This second phase begins when the 16-bit DAC and the Residue Error Amplifier have both settled. First, SW2 is turned off and SW3 is turned on. Then, the SHA section of the Residue Amplifier goes into hold mode. Next SW2 is turned off and SW3 is turned on. The 9-bit result is transferred to the output latch and ALU. An error correction algorithm now compensates for the offset inserted in the Residue Amplifier Section and errors introduced in the first pass conversion and combines both results to give the 16-bit answer. R4 4k⍀ ⴞ3V SIGNAL FROM INPUT SHA R6 2k⍀ 0 TO –3V 9-BIT ADC SW2 R5 4k⍀ 9 LATCH + ALU 16 9 VREF– A2 R3 3k⍀ SW3 RESIDUE AMP + SHA 3VINF SW1A 3VINS 5VINF 5VINS C1 R1 3k⍀ R4 4k⍀ SW1B TO 9-BIT ADC A1 A1 R2 5k⍀ R6 2k⍀ TO RESIDUE AMPLIFIER A2 16-BIT ACCURATE DAC +3V –3V 9 R5 4k⍀ R7 2k⍀ VREF– Figure 7. AD7884/AD7885 Analog Input Section When the ± 3 VINS and ± 3 VINF inputs are tied to 0 V, the input section has a gain of –0.6 and transforms an input signal of ± 5 volts to the required ± 3 volts. When the ± 5 VINS and ± 5 VINF inputs are grounded, the input section has a gain of –1 and so the analog input range is now ± 3 volts. Resistors R4 and R5, at the amplifier output, further condition the ± 3 volts signal to be 0 volt to –3 volts. This is the required input for the 9-bit A/D converter section. With SW1a closed, the output of A1 follows the input (the sample-and-hold is in the track mode). On the rising edge of the CONVST pulse, SW1a goes open circuit, and capacitor C1 holds the voltage on the output of A1. The sample-and-hold is now in the hold mode. The aperture delay time for the sampleand-hold is nominally 50 ns. A/D Converter Section The AD7884/AD7885 uses a two-pass flash technique in order to achieve the required speed and resolution. When the CONVST control input goes from low to high, the sample-and-hold amplifier goes into the hold mode and a 0 V to –3 V signal is presented to the input of the 9-bit ADC. The first phase of conversion generates the 9 MSBs of the 16-bit result and transfers these to the latch and ALU combination. They are also fed back to the 9 MSBs of the 16-bit DAC. The 7 LSBs of the DAC are permanently loaded with 0s. The DAC output is subtracted from the analog input with the result being amplified and offset in the Residue Amplifier Section. R8 2k⍀ VREF+F VREF+S VINV VREF– Figure 8. A/D Converter Section Timing and Control Section Figure 9 shows the timing and control sequence for the AD7884/ AD7885. When the part receives a CONVST pulse, the conversion begins. The input sample-and-hold goes into the hold mode 50 ns after the rising edge of CONVST and BUSY goes low. This is the first phase of conversion and takes 3.35 µs to complete. The second phase of conversion begins when SW2 is turned off and SW3 turned on. The Residue Amplifier and SHA section (A2 in Figure 8) goes into hold mode at this point and allows the input sample-and-hold to go back into sample mode. Thus, while the second phase of conversion is ongoing, the input sample-and-hold is also acquiring the input signal for the next conversion. This overlap between conversion and acquisition allows throughput rates of 166 kSPS to be achieved. CONVST FIRST PHASE 3.5s SECOND PHASE 1.8s BUSY HOLD INPUT SAMPLE SHA FIRST PHASE OF CONVERSION 1ST 9-BIT CONVERSION DAC SETTLING TIME RESIDUE AMPLIFIER SETTLING TIME TACQ 2.5s SECOND PHASE OF CONVERSION 2ND 9-BIT CONVERSION ERROR CORRECTION OUTPUT LATCH UPDATE Figure 9. Timing and Control Sequence REV. D –9– AD7884/AD7885 To do this the reference noise needs to be less than 35 µV rms. In the 100 kHz band, the AD780 noise is less than 30 µV rms, making it a very suitable reference. USING THE AD7884/AD7885 ANALOG INPUT RANGES The AD7884/AD7885 can be set up to have either a ± 3 volts analog input range or a ± 5 volts analog input range. Figures 10 and 11 show the necessary corrections for each of these. The output code is two’s complement and the ideal code table for both input ranges is shown in Table I. The buffer amplifier used to drive the device VREF+ should have low enough noise performance so as not to affect the overall system noise requirement. The AD845 and AD817 achieve this. Table I. Ideal Output Code Table for the AD7884/AD7885 Decoupling and Grounding Analog Input ⴞ3 V In Terms of FSR2 Range3 ⴞ5 V Range4 Digital Output Code Transitionl +FSR/2 – 1 LSB +FSR/2 – 2 LSBs +FSR/2 – 3 LSBs 2.999908 2.999817 2.999726 4.999847 4.999695 4.999543 011 . . . 111 to 111 . . . 110 011 . . . 110 to 011 . . . 101 011 . . . 101 to 011 . . . 100 AGND + 1 LSB AGND AGND – 1 LSB 0.000092 0.000000 –0.000092 0.000153 0.000000 –0.000153 000 . . . 001 to 000 . . . 000 000 . . . 000 to 111 . . . 111 111 . . . 111 to 111 . . . 110 –(FSR/2 – 3 LSBs) –2.999726 –(FSR/2 – 2 LSBs) –2.999817 –(FSR/2 – 1 LSB) –2.999908 –4.999543 –4.999695 –4.999847 100 . . . 011 to 100 . . . 010 100 . . . 010 to 100 . . . 001 100 . . . 001 to 100 . . . 000 NOTES 1 This table applies for V REF+S = 3 V. 2 FSR (Full-Scale Range) is 6 volts for the ± 3 V input range and 10 volts for the ± 5 V input range. 3 1 LSB on the ± 3 V range is FSR/2 16 and is equal to 91.5 µV. 4 1 LSB on the ± 5 V range is FSR/216 and is equal to 152.6 µV. The AD7884 and AD7885A have one AVDD pin and two VDD pins. They also have one AVSS pin and three VSS pins. The AD7885 has one AVDD pin, one VDD pin, one AVSS pin and one VSS pin. Figure 6 shows how a common +5 V supply should be used for the positive supply pins and a common –5 V supply for the negative supply pins. For decoupling purposes, the critical pins on both devices are the AVDD and AVSS pins. Each of these should be decoupled to system AGND with 10 µF tantalum and 0.1 µF ceramic capacitors right at the pins. With the VDD and VSS pins, it is sufficient to decouple each of these with ceramic 1 µF capacitors. AGNDS, AGNDF are the ground return points for the on-chip 9-bit ADC. They should be driven by a buffer amplifier as shown in Figure 6. If they are tied directly together and then to ground, there will be a marginal degradation in linearity performance. The GND pin is the analog ground return for the on-chip linear circuitry. It should be connected to system analog ground. The DGND pin is the ground return for the on-chip digital circuitry. It should be connected to the ground terminal of the VDD and VSS supplies. If a common analog supply is used for AVDD and VDD then DGND should be connected to the common ground point. Reference Considerations The AD7884/AD7885 operates from a ± 3 volt reference. This can be derived simply using the AD780 as shown in Figure 6. Power Supply Sequencing AVDD and VDD are connected to a common substrate and there is typically 17 Ω resistance between them. If they are powered by separate 5 V supplies, then these should come up simultaneously. Otherwise, the one that comes up first will have to drive 5 V into a 17 Ω load for a short period of time. However, the standard short-circuit protection on regulators like the 7800 series will ensure that there is no possibility of damage to the driving device. 5VINS VINV A1 5VINF 3VINS 3VINF AVSS should always come up either before or at the same time as VSS. If this cannot be guaranteed, Schottky diodes should be used to ensure that VSS never exceeds AVSS by more than 0.3 V. Arranging the power supplies as in Figure 6 and using the recommended decoupling ensures that there are no power supply sequencing issues as well as giving the specified noise performance. Figure 10. ± 5 V Input Range Connection 5VINS 5VINF 3VINS VINV A1 +5V +5V –5V –5V AVDD VDD AVSS VSS 3VINF Figure 11. ± 3 V Input Range Connections HP5082-2810 OR EQUIVALENT AD7884/AD7885 The critical performance specification for a reference in a 16-bit application is noise. The reference pk-pk noise should be insignificant in comparison to the ADC noise. The AD7884/AD7885 has a typical rms noise of 120 µV. For example a reasonable target would be to keep the total rms noise less than 125 µV. –10– Figure 12. Schottky Diodes Used to Protect Against Incorrect Power Supply Sequencing REV. D AD7884/AD7885 AD7884/AD7885 PERFORMANCE Linearity 3000 CODE FREQUENCY The linearity of the AD7884/AD7885 is determined by the on-chip 16-bit D/A converter. This is a segmented DAC which is laser trimmed for 16-bit DNL performance to ensure that there are no missing codes in the ADC transfer function. Figure 13 shows a typical INL plot for the AD7884/AD7885. 2.0 LINEARITY ERROR – LSBs VDD = +5V VSS = –5V TA = +25ⴗC 1000 1.5 0 (X – 2) 1.0 (X – 1) (X) (X + 1) (X + 2) (X + 3) CODE Figure 14. Histogram of 5000 Conversions of a DC Input 0.5 0 0 16384 32768 49152 65535 OUTPUT CODE Figure 13. AD7884/AD7885 Typical Linearity Performance Noise In an A/D converter, noise exhibits itself as code uncertainty in dc applications and as the noise floor (in an FFT, for example) in ac applications. If the noise in the converter is too high for an application, it can be reduced by oversampling and digital filtering. This involves sampling the input at higher than the required word rate and then averaging to arrive at the final result. The very fast conversion time of the AD7884/AD7885 makes it very suitable for oversampling. For example, if the required input bandwidth is 40 kHz, the AD7884/AD7885 could be oversampled by a factor of 2. This yields a 3 dB improvement in the effective SNR performance. The noise performance in the ±5 volt input range is now effectively 85 µV rms and the resultant spread of codes for 2500 conversions will be four. This is shown in Figure 15. 1500 CODE FREQUENCY In a sampling A/D converter like the AD7884/AD7885, all information about the analog input appears in the baseband from dc to 1/2 the sampling frequency. An antialiasing filter will remove unwanted signals above fS/2 in the input signal but the converter wideband noise will alias into the baseband. In the AD7884/AD7885, this noise is made up of sample-and-hold noise and A/D converter noise. The sample-and-hold section contributes 51 µV rms and the ADC section contributes 59 µV rms. These add up to a total rms noise of 78 µV. This is the input referred noise in the ± 3 V analog input range. When operating in the ± 5 V input range, the input gain is reduced to –0.6. This means that the input referred noise is now increased by a factor of 1.66 to 120 µV rms. 1000 500 0 Figure 14 shows a histogram plot for 5000 conversions of a dc input using the AD7884/AD7885 in the ± 5 V input range. The analog input was set as close as possible to the center of a code transition. All codes other than the center code are due to the ADC noise. In this case, the spread is six codes. REV. D 2000 (X – 1) (X) (X + 1) (X + 2) CODE Figure 15. Histogram of 2500 Conversions of a DC Input Using a ×2 Oversampling Ratio –11– AD7884/AD7885 Dynamic Performance MICROPROCESSOR INTERFACING With a combined conversion and acquisition time of 6 µs, the AD7884/AD7885 is ideal for wide bandwidth signal processing applications. Signal to (Noise + Distortion), Total Harmonic Distortion, Peak Harmonic or Spurious Noise and Intermodulation Distortion are all specified. Figure 16 shows a typical FFT plot of a 1.8 kHz, ± 5 V input after being digitized by the AD7884/AD7885. The AD7884/AD7885 is designed on a high speed process which results in very fast interfacing timing (Data Access Time of 57 ns max). The AD7884 has a full 16-bit parallel bus, and the AD7885 has an 8-bit wide bus. The AD7884, with its parallel interface, is suited to 16-bit parallel machines whereas the AD7885, with its byte interface, is suited to 8-bit machines. Some examples of typical interface configurations follow. AD7884 to MC68000 Interface 0 –30 fIN = 1.8kHz, ⴞ5V SINE WAVE fSAMPLE = 163kHz SNR = 87dB THD = –95dB Figure 18 shows a general interface diagram for the MC68000, 16-bit microprocessor to the AD7884. In Figure 18, conversion is initiated by bringing CSA low (i.e., writing to the appropriate address). This allows the processor to maintain control over the complete conversion process. In some cases it may be more desirable to control conversion independent from the processor. This can be done by using an external sampling timer. dB –60 –90 A23–A1 ADDRESS BUS –120 MC68000 –150 ADDRESS DECODE LOGIC CSB 2048 POINT FFT CSA CONVST CS DTACK Figure 16. AD7884/AD7885 FFT Plot AS Effective Number of Bits D15–D0 N = (SNR – 1.76)/6.02 DATA BUS DB15–DB0 Figure 18. AD7884 to MC68000 Interface Once conversion has been started, the processor must wait until it is completed before reading the result. There are two ways of ensuring this. The first way is to simply use a software delay to wait for 6.5 µs before bringing CS and RD low to read the data. 16 15 EFFECTIVE NUMBER OF BITS RD R/W The formula for SNR (see Terminology section) is related to the resolution or number of bits in the converter. Rewriting the formula, below, gives a measure of performance expressed in effective number of bits (N). AD7884 The second way is to use the BUSY output of the AD7884 to generate an interrupt in the MC68000. Because of the nature of its interrupts, the MC68000 requires additional logic (not shown in Figure 18) to allow it to be interrupted correctly. For full information on this, consult the MC68000 User’s Manual. 14 13 12 11 10 0 20 40 60 80 FREQUENCY – kHz Figure 17. Effective Number of Bits vs. Frequency The effective number of bits for a device can be calculated from its measured SNR. Figure 17 shows a typical plot of effective number of bits versus frequency for the AD7884. The sampling frequency is 166 kHz. –12– REV. D AD7884/AD7885 MEMORY READ MRDC 82288 BUS CONTROLLER CS1 CS2 CLK DECODE CIRCUITRY CLK AD7884 82284 CLOCK GENERATOR RD CS CLK CONVST DB15 8282 OR 8283 LATCH A23–A0 DB0 BUSY 80286 CPU D15–D0 8259A INTERRUPT CONTROLLER IR0–IR7 8286 OR 8287 TRANSCEIVER Figure 19. AD7884 Interfacing to Basic iAPX 286 System AD7884 to 80286 Interface AD7885 to 8088 Interface The 80286 is an advanced high performance processor with special capabilities aimed at multiuser and multitasking systems. The AD7885, with its byte (8 + 8) data format, is ideal for use with the 8088 microprocessor. Figure 20 is the interface diagram. Conversion is started by enabling CSA. At the end of conversion, data is read into the processor. The read instructions are: Figure 19 shows an interface configuration for the AD7884 to such a system. Note that only signals relevant to the AD7884 are shown. For the full 80286 configuration refer to the iAPX 286 data sheet (Basic System Configuration). MOV AX, C001 Read 8 MSBs of data MOV AX, C000 Read 8 LSBs of data In Figure 19 conversion is started by writing to a selected address and causing it CS2 to go low. When conversion is complete, BUSY goes high and initiates an interrupt. The processor can then read the conversion result. MN/MX 5V A15–A8 ADDRESS BUS IO/M ADDRESS DECODE LOGIC CSB 8088 AD7–AD0 HBEN AD7885 CONVST CS RD RD ALE CSA A0 STB 8282 DATA BUS DB7–DB0 Figure 20. AD7885 to 8088 Interface REV. D –13– AD7884/AD7885 AD7884 to ADSP-2101 Interface Stand-Alone Operation Figure 21 shows an interface between the AD7884 and the ADSP-2101. Conversion is initiated using a timer which allows very accurate control of the sampling instant. The AD7884 BUSY line provides an interrupt to the ADSP-2101 when conversion is completed. The RD pulsewidth of the processor can be programmed using the Data Memory Wait State Control Register. The result can then be read from the ADC using the following instruction: If CS and RD are tied permanently low on the AD7884, then, when a conversion is completed, output data will be valid on the rising edge of BUSY. This makes the device very suitable for stand-alone operation. All that is required to run the device is an external CONVST pulse which can be supplied by a sample timer. Figure 22 shows the AD7884 set up in this mode with the BUSY signal providing the clock for the 74HC574 3-state latches. A0 MR0 = DM (ADC) TIMER HBEN where MR0 is the ADSP-2101 MR0 register, and ADC is the AD7884 address. CONVST DB15–DB8 TIMER DMA13–DMA0 ADSP-2101 DMS DB7–DB0 ADDRESS DECODE LOGIC EN BUSY CLK CS RD CS IRQn 74HC574 AD7884 CONVST BUSY RD DMD15–DMD0 CLK AD7884 ADDRESS BUS 74HC574 RD DATA BUS DB15–DB0 Figure 21. AD7884 to ADSP-2101 Interface Figure 22. Stand-Alone Operation Digital Feedthrough from an Active Bus It is very important when using the AD7884/AD7885 in a microprocessor-based system to isolate the ADC data bus from the active processor bus while a conversion is being executed. This will yield the best noise performance from the ADC. Latches like the 74HC574 can be used to do this. If the device is connected directly to an active bus then the converter noise will typically increase by a factor of 30%. –14– REV. D AD7884/AD7885 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 28-Lead Cerdip (Q-28) 0.005 (0.13) MIN 0.100 (2.54) MAX 28 15 0.610 (15.49) 0.500 (12.70) 1 14 PIN 1 0.620 (15.75) 0.590 (14.99) 0.015 (0.38) MIN 1.490 (37.85) MAX 0.225 (5.72) MAX 0.150 (3.81) MIN 0.018 (0.46) 0.008 (0.20) 0.200 (5.08) 0.026 (0.66) 0.110 (2.79) 0.070 (1.78) SEATING 0.125 (3.18) 0.014 (0.36) 0.090 (2.29) 0.030 (0.76) PLANE 15° 0° 40-Lead Plastic DIP (Q-40) 0.005 (0.13) MIN 0.098 (2.49) MAX 40 21 0.620 (15.75) 0.510 (12.95) PIN 1 1 20 2.096 (52.23) MAX 0.070 (1.78) 0.015 (0.38) 0.225 (5.72) MAX 0.200 (5.08) 0.125 (3.18) 0.026 (0.66) 0.014 (0.36) SEATING PLANE 0.065 (1.65) 0.045 (1.14) 0.100 (2.54) BSC 0.63 (16.00) 0.59 (14.93) 15° 0° 44-Lead PLCC (P-44A) 0.180 (4.57) 0.165 (4.19) 0.048 (1.21) 0.042 (1.07) 0.048 (1.21) 0.042 (1.07) 0.056 (1.42) 0.042 (1.07) 6 7 0.025 (0.63) 0.015 (0.38) 40 39 PIN 1 IDENTIFIER 0.050 (1.27) BSC 0.021 (0.53) 0.013 (0.33) TOP VIEW (PINS DOWN) 17 0.040 (1.01) 0.025 (0.64) 0.656 (16.66) SQ 0.650 (16.51) 0.695 (17.65) SQ 0.685 (17.40) REV. D 0.032 (0.81) 0.026 (0.66) 29 28 18 0.020 (0.50) R 0.63 (16.00) 0.59 (14.99) –15– 0.110 (2.79) 0.085 (2.16) 0.018 (0.46) 0.008 (0.20) AD7884/AD7885 Revision History Location Page Data Sheet changed from REV. C to REV. D. “J” Column added to Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Cerdip added to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Edit to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 PRINTED IN U.S.A. Addition of Q-28 Outline Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 C01353–0–2/02(0) Addition of Cerdip package to GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 –16– REV. D