AS4C4M4E1 May 2001 ® 4M×4 CMOS DRAM (EDO) family Features • Organization: 4,194,304 words × 4 bits • High speed • TTL-compatible, three-state I/O • JEDEC standard package - 50/60 ns RAS access time - 25/30 ns column address access time - 12/15 ns CAS access time - 300 mil, 24/26-pin SOJ - 300 mil, 24/26-pin TSOP • 5V power supply • Latch-up current ≥ 200 mA • ESD protection ≥ 2000 volts • Industrial and commercial temperature available • Low power consumption - Active: 908 mW max - Standby: 5.5 mW max, CMOS I/O • Extended data out • Refresh - 2048 refresh cycles, 32 ms refresh interval for AS4C4M4E1 - RAS-only or CAS-before-RAS refresh Pin arrangement Pin designation 1 2 3 4 5 6 A10 A0 A1 A2 A3 VCC 7 8 9 10 11 12 TSOP 24 23 22 21 20 19 GND I/O3 I/O2 CAS OE A9 VCC I/O0 I/O1 WE RAS NC 1 2 3 4 5 6 18 17 16 15 14 13 A8 A7 A6 A5 A4 GND A10 A0 A1 A2 A3 VCC 7 8 9 10 11 12 AS4C4M4E0 VCC I/O0 I/O1 WE RAS NC AS4C4M4E0 SOJ 24 23 22 21 20 19 GND I/O3 I/O2 CAS OE A9 18 17 16 15 14 13 A8 A7 A6 A5 A4 GND Pin(s) Description A0 to A10 Address inputs RAS Row address strobe CAS Column address strobe WE Write enable I/O0 to I/O3 Input/output OE Output enable VCC Power GND Ground Selection guide Symbol AS4C4M4E1-50 AS4C4M4E1-60 Unit Maximum RAS access time tRAC 50 60 ns Maximum column address access time tCAA 25 30 ns Maximum CAS access time tCAC 12 15 ns Maximum output enable (OE) access time tOEA 13 15 ns Minimum read or write cycle time tRC 85 100 ns Minimum fast page mode cycle time tPC 25 30 ns Maximum operating current ICC1 135 120 mA Maximum CMOS standby current ICC5 2.0 2.0 mA 5/22/01; v.1.29 point> Alliance Semiconductor P. 1 of 14 Copyright © Alliance Semiconductor. All rights reserved. AS4C4M4E1 ® Functional description The AS4C4M4E1 is a high performance 16-megabit CMOS Dynamic Random Access Memories (DRAM) organized as 4,194,304 words × 4 bits. The devices are fabricated using advanced CMOS technology and innovative design techniques resulting in high speed, extremely low power and wide operating margins at component and system levels. The Alliance 16Mb DRAM family is optimized for use as main memory in PC, workstation, router and switch applications. This product features a high speed page mode operation where read and write operations within a single row (or page) can be executed at very high speed by toggling column addresses within that row. Row and column addresses are alternately latched into input buffers using the falling edge of RAS and CAS inputs respectively. Also, RAS is used to make the column address latch transparent, enabling application of column addresses prior to CAS assertion. Extended data out (EDO) read mode enables 60MHz operation using 60ns devices. In contrast to 'fast page mode' devices, data remains active on outputs after CAS is de-asserted high, giving system logic more time to latch the data. Use OE and WE to control output impedance and prevent bus contention during read-modify-write and shared bus applications. Outputs also go to high impedance at the last occurrance of RAS and CAS going high. Refresh on the 2048 address combinations of A0 to A10 must be performed every 32 ms using: • RAS-only refresh: RAS is asserted while CAS is held high. Each of the 2048 rows must be strobed. Outputs remain high impedence. • Hidden refresh: CAS is held low while RAS is toggled. Refresh address is generated internally. Outputs remain low impedence with previous valid data. • CAS-before-RAS refresh (CBR): At least one CAS is asserted prior to RAS. Refresh address is generated internally. Outputs are high-impedence (OE and WE are don't care). • Normal read or write cycles refresh the row being accessed. The AS4C4M4E1 is a available in the standard 24/26-pin plastic SOJ and 24/26-pin plastic TSOP packages. The AS4C4M4E1 operates with a single power supply of 5V ± 0.5V. It provides TTL compatible inputs and outputs. Refresh controller Logic block diagram for 2K refresh VCC GND WE CAS clock generator WE clock generator A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 Sense amp I/O0 to I/O3 OE Row decoder CAS RAS clock generator Address buffers RAS Data I/O buffers Column decoder 2048 × 2048 × 4 Array (16,777,216) Substrate bias generator Recommended operating conditions Parameter Supply voltage Input voltage Ambient operating temperature † Symbol Min Nominal Max Unit VCC 4.5 5.0 5.5 V GND 0.0 0.0 0.0 V VIH 2.4 – VCC V – 0.8 V 0 – 70 -40 – 85 VIL Commercial Industrial TA –0.5 † °C VIL min -3.0V for pulse widths less than 5 ns. Recommended operating conditions apply throughout this document unlesss otherwise specified. 5/22/01; v.1.29 point> Alliance Semiconductor P. 2 of 14 AS4C4M4E1 ® Absolute maximum ratings Parameter Symbol Min Max Unit Input voltage Vin -1.0 +7.0 V Input voltage (DQs) VDQ -1.0 VCC + 0.5 V Power supply voltage VCC -1.0 +7.0 V Storage temperature (plastic) TSTG -55 +150 °C Soldering temperature × time TSOLDER – 260 × 10 o Power dissipation PD – 1 W Short circuit output current Iout – 50 mA C × sec DC electrical characteristics -50 Parameter Symbol Test conditions Input leakage current IIL Output leakage current -60 Min Max Min Max Unit 0V ≤ Vin ≤ +5.5V, Pins not under test = 0V -5 +5 -5 +5 µA IOL DOUT disabled, 0V ≤ Vout ≤ +5.5V -5 +5 -5 +5 µA Operating power supply current ICC1 RAS, CAS Address cycling; tRC=min – 135 – 120 mA TTL standby power supply current ICC2 RAS = CAS ≥ VIH – 2.0 – 2.0 mA Average power supply current, RAS refresh mode or CBR ICC3 RAS cycling, CAS ≥ VIH, tRC = min of RAS low after CAS low. – 120 – 110 mA 1 EDO page mode average ICC4 power supply current RAS = VIL, CAS address cycling: tHPC = min – 130 – 120 mA 1, 2 CMOS standby power supply current ICC5 RAS = CAS = VCC - 0.2V – 2.0 – 2.0 mA VOH IOUT = -5.0 mA 2.4 – 2.4 – V VOL IOUT = 4.2 mA – 0.4 – 0.4 V ICC6 RAS or CAS cycling, tRC = min – 120 – 110 mA Output voltage CAS before RAS refresh current 5/22/01; v.1.29 point> Alliance Semiconductor Notes 1,2 P. 3 of 14 AS4C4M4E1 ® AC parameters common to all waveforms -50 -60 Symbol Parameter Min Max Min Max Unit Notes tRC Random read or write cycle time 80 – 100 – ns tRP RAS precharge time 30 – 40 – ns tRAS RAS pulse width 50 10K 60 10K ns tCAS CAS pulse width 8 10K 10 10K ns tRCD RAS to CAS delay time 15 35 15 43 ns 6 tRAD RAS to column address delay time 12 25 12 30 ns 7 tRSH CAS to RAS hold time 10 – 10 – ns tCSH RAS to CAS hold time 40 – 50 – ns tCRP CAS to RAS precharge time 5 – 5 – ns tASR Row address setup time 0 – 0 – ns tRAH Row address hold time 8 – 10 – ns tT Transition time (rise and fall) 1 50 1 50 ns 4,5 tREF Refresh period – 32 – 32 ms 16 tCP CAS precharge time 8 – 10 – ns tRAL Column address to RAS lead time 25 – 30 – ns tASC Column address setup time 0 – 0 – ns tCAH Column address hold time 8 10 – ns Read cycle -50 Symbol Parameter tRAC -60 Min Max Min Max Unit Access time from RAS – 50 – 60 ns 6 tCAC Access time from CAS – 12 – 15 ns 6,13 tAA Access time from address – 25 – 30 ns 7,13 tRCS Read command setup time 0 – 0 – ns tRCH Read command hold time to CAS 0 – 0 – ns 9 tRRH Read command hold time to RAS 0 – 0 – ns 9 5/22/01; v.1.29 point> Alliance Semiconductor Notes P. 4 of 14 AS4C4M4E1 ® Write cycle -50 Symbol Parameter tWCS -60 Min Max Min Max Unit Notes Write command setup time 0 – 0 – ns 11 tWCH Write command hold time 10 – 10 – ns 11 tWP Write command pulse width 10 – 10 – ns tRWL Write command to RAS lead time 10 – 10 – ns tCWL Write command to CAS lead time 8 – 10 – ns tDS Data-in setup time 0 – 0 – ns 12 tDH Data-in hold time 8 – 10 – ns 12 Read-modify-write cycle -50 -60 Symbol Parameter Min Max Min Max Unit Notes tRWC Read-write cycle time 113 – 135 – ns tRWD RAS to WE delay time 67 – 77 – ns 11 tCWD CAS to WE delay time 32 – 35 – ns 11 tAWD Column address to WE delay time 42 – 47 – ns 11 Refresh cycle -50 Symbol Parameter tCSR -60 Min Max Min Max Unit CAS setup time (CAS-before-RAS) 5 – 5 – ns 3 tCHR CAS hold time (CAS-before-RAS) 8 – 10 – ns 3 tRPC RAS precharge to CAS hold time 0 – 0 – ns tCPT CAS precharge time (CBR counter test) 10 10 – ns 5/22/01; v.1.29 point> Alliance Semiconductor Notes P. 5 of 14 AS4C4M4E1 ® Hyper page mode cycle -50 -60 Symbol Parameter Min Max Min Max Unit tCPWD CAS precharge to WE delay time 45 – 52 – ns tCPA Access time from CAS precharge – 28 – 35 ns tRASP RAS pulse width 50 100K 60 100K ns tDOH Previous data hold time from CAS 5 – 5 – ns tREZ Output buffer turn off delay from RAS 0 13 0 15 ns tWEZ Output buffer turn off delay from WE 0 13 0 15 ns tOEZ Output buffer turn off delay from OE 0 13 0 15 ns tHPC Hyper page mode cycle time 20 – 25 – ns tHPRWC Hyper page mode RMW cycle 47 – 56 – ns tRHCP RAS hold time from CAS 30 – 35 – ns Notes 13 Output enable -50 Symbol Parameter tCLZ -60 Min Max Min Max Unit CAS to output in Low Z 0 – 0 – ns tROH RAS hold time referenced to OE 8 – 10 – ns tOEA OE access time – 13 – 15 ns tOED OE to data delay 13 – 15 – ns tOEZ Output buffer turnoff delay from OE 0 13 0 15 ns tOEH OE command hold time 10 – 10 – ns tOLZ OE to output in Low Z 0 – 0 – ns tOFF Output buffer turn-off time 0 13 0 15 ns 5/22/01; v.1.29 point> Alliance Semiconductor Notes 8 8 8,10 P. 6 of 14 AS4C4M4E1 ® Notes 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 ICC1, ICC3, ICC4, and ICC6 are dependent on frequency. ICC1 and ICC4 depend on output loading. Specified values are obtained with the output open. An initial pause of 200 µs is required after power-up followed by any 8 RAS cycles before proper device operation is achieved. In the case of an internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 8 initialization cycles are required after extended periods of bias without clocks (greater than 8 ms). AC Characteristics assume tT = 2 ns. All AC parameters are measured with a load equivalent to two TTL loads and 100 pF, VIL (min) ≥ GND and VIH (max) ≤ VCC. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL. Operation within the tRCD (max) limit insures that tRAC (max) can be met. tRCD (max) is specified as a reference point only. If tRCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC. Operation within the tRAD (max) limit insures that tRAC (max) can be met. tRAD (max) is specified as a reference point only. If tRAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA. Assumes three state test load (5 pF and a 380 Ω Thevenin equivalent). Either tRCH or tRRH must be satisfied for a read cycle. tOFF (max) defines the time at which the output achieves the open circuit condition; it is not referenced to output voltage levels. tOFF is referenced from rising edge of RAS or CAS, whichever occurs last. tWCS, tWCH, tRWD, tCWD and tAWD are not restrictive operating parameters. They are included in the datasheet as electrical characteristics only. If tWS ≥ tWS (min) and tWH ≥ tWH (min), the cycle is an early write cycle and data out pins will remain open circuit, high impedance, throughout the cycle. If tRWD ≥ tRWD (min), tCWD ≥ tCWD (min) and tAWD ≥ tAWD (min), the cycle is a read-write cycle and the data out will contain data read from the selected cell. If neither of the above conditions is satisfied, the condition of the data out at access time is indeterminate. These parameters are referenced to CAS leading edge in early write cycles and to WE leading edge in read-write cycles. Access time is determined by the longest of tCAA or tCAC or tCPA tASC ≥ tCP to achieve tPC (min) and tCPA (max) values. These parameters are sampled and not 100% tested. These characteristics apply to AS4C4M4E1 5V devices. AC test conditions - Access times are measured with output reference levels of VOH = 2.4V and VOL = 0.4V, VIH = 2.4V and VIL = 0.8V - Input rise and fall times: 2 ns +3.3V R1 = 828Ω Dout 50 pF* R2 = 295Ω *including scope and jig capacitance GND Figure A: Equivalent output load (AS4LC4M4E1) Key to switching waveforms Rising input 5/22/01; v.1.29 point> Falling input Alliance Semiconductor Undefined output/don’t care P. 7 of 14 AS4C4M4E1 ® Read waveform tRC tRAS tRCD tRSH tRP RAS tCSH tCRP tCAH tCAS tASC tRCS CAS tRAD Address tRAL tRAH tASR Row address Column address tRRH tRCH WE tROH tROH tWEZ OE tOEZ tRAC tAA tOFF (see note 11) tOEA tCAC tREZ tCLZ DQ Data out tOLZ Early write waveform tRC tRAS tRP RAS tCSH tRSH tCRP tRCD tCAS CAS tRAD tRAL tASC tASR Address tRAH tCAH Row address Column address tCWL tRWL tWP tWCS tWCH WE OE tDS DQ 5/22/01; v.1.29 point> tDH Data in Alliance Semiconductor P. 8 of 14 AS4C4M4E1 ® Write waveform OE controlled tRC tRAS tRP RAS tCSH tCRP tRSH tCAS tRCD CAS tRAL tRAD tRAH tASR tASC tCAH Row address Address Column address tRWL tCWL tWP WE tOEH OE tDS tOED tDH Data in DQ Read-modify-write waveform tRWC tRAS tRP RAS tCAS tCRP tRCD tRSH tCSH CAS tAR tRAL tRAD tRAH tASR Address tASC tCAH Row address Column address tRWD tRWL tAWD tRCS WE tCWL tCWD tOEA tOEZ tWP tOED OE tRAC tAA tCAC tCLZ Data out DQ tDS tDH Data in tOLZ 5/22/01; v.1.29 point> Alliance Semiconductor P. 9 of 14 AS4C4M4E1 ® EDO page mode read waveform tRASP tRP RAS tRHCP tCSH tCRP tRCD tCAS tCP tRSH tHPC CAS tAR tRAL tRAD tASR Address tRAH tASC Row tCAH Col address Col address Col address tRCS tRCH tRRH WE tOEA tOEA OE tRAC tCPA tCLZ tCAC tAA DQ tOEZ tOEZ tOFF tCPA Data out Data out tOLZ Data out tCLZ tCLZ EDO page mode early write waveform tRASP tRAH tRWL RAS tCRP tRCD tPC tCSH tCAS CAS tCP tWCS tRSH tRAL tAR tASR Address tCAH tASC tRAD Col address Row address Col address Col address tCWL tWP tWCH tOEH WE OE tHDR tOED tDH tDS DQ 5/22/01; v.1.29 point> Data in Data In Alliance Semiconductor Data in P. 10 of 14 AS4C4M4E1 ® EDO page mode read-modify-write waveform tRASP tRP RAS tHPRWC tCSH tRCD tCAS tCP tCRP CAS tRAD tASR tRAH tASC Address tASC tCAH Row ad Col ad Col ad tRWD tRCS tRAL tASC tCAH tCAH Col address tCPWD tCWL tCWD tCWD tRWL tCWD tAWD tCWL tAWD tWP WE tOEA tOEZ tOED tOEA OE tAA tDH tRAC tCPA tDS tDS tCLZ tCLZ tCAC tCLZ tCAC DQ Data in tCAC Data in Data out Data out Data in Data out CAS before RAS refresh waveform WE = A = VIH or VIL tRC tRP tRAS RAS tRPC tCHR tCP tCSR CAS OPEN DQ RAS only refresh waveform WE = OE = VIH or VIL tRC tRAS tRP RAS tCRP tRPC CAS tASR Address 5/22/01; v.1.29 point> tRAH Row address Alliance Semiconductor P. 11 of 14 AS4C4M4E1 ® Hidden refresh waveform (read) tRC tRC tRAS tRP tRAS tRP RAS tCRP tCHR tRCD tRSH tCRP CAS tAR tRAD tCAH tRAH tASC tASR Row Address Col address tRCS tRRH WE tOEA OE tRAC tOFF tAA tCAC tCLZ tOEZ Data out DQ Hidden refresh waveform (write) tRC tRAS tRP RAS tCRP tRCD tRSH tCHR CAS tAR tRAD tRAL tRAH tASR Address tASC tCAH Row address Col address tRWL tWCR tWP tWCS tWCH WE tDS tDH tDHR DQ Data in OE 5/22/01; v.1.29 point> Alliance Semiconductor P. 12 of 14 AS4C4M4E1 ® CAS before RAS refresh counter test waveform tRAS tRSH tRP RAS CAS tCSR tCHR tCPT tCAS tRAL tASC tCAH Address Col address tAA tCAC tCLZ Read cycle DQ tOFF tOEZ Data out tRRH tRCH tRCS WE tROH tOEA OE tRWL tCWL tWP tWCH Write cycle tWCS WE tDH tDS DQ Data in OE tRWL tWP tRCS tCWD tAWD tCWL Read-Write cycle WE tOEA tOED OE t AA tCLZ tCAC DQ 5/22/01; v.1.29 point> tDH tOEZ tDS Data out Alliance Semiconductor Data in P. 13 of 14 AS4C4M4E1 ® Capacitance 15 ƒ = 1 MHz, Ta = Room temperature Parameter Input capacitance DQ capacitance Symbol Signals Test conditions Max Unit CIN1 A0 to A10 Vin = 0V 5 pF CIN2 RAS, CAS, WE, OE Vin = 0V 7 pF CDQ DQ0 to DQ3 Vin = Vout = 0V 7 pF AS4C4M4E1 ordering information Package \ RAS access time 50 ns 60 ns Plastic SOJ, 300 mil, 24/26-pin 5V AS4C4M4E1-50JC AS4C4M4E1-50JI AS4C4M4E1-60JC AS4C4M4E1-60JI Plastic TSOP, 300 mil, 24/26-pin 5V AS4C4M4E1-50TC AS4C4M4E1-50TI AS4C4M4E1-60TC AS4C4M4E1-60TI AS4C4M4E1 family part numbering system AS4 C 4M4 E1 –XX X DRAM prefix C = 5V CMOS 4M×4 E1=2K refresh RAS access time Package: Temperature range J = SOJ 300 mil, 24/26 C=Commercial, 0°C to 70°C T = TSOP 300 mil, 24/26 I=Industrial, -40°C to 85°C 5/22/01; v.1.29 point> Alliance Semiconductor X P. 14 of 14 © Copyright Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. 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