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• Organization: 4,194,304 words × 4 bits
• High speed
- 50/60 ns RAS access time
- 25/30 ns column address access time
- 12/15 ns CAS access time
• Low power consumption
- Active: 495 mW max
- Standby: 5.5 mW max, CMOS I/O
• Fast page mode
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AS4C4M4F1Q
62-
• Refresh
- 2048 refresh cycles, 32 ms refresh interval for
AS4C4M4F1Q
- RAS-only or CAS-before-RAS refresh
• TTL-compatible, three-state I/O
• 4 separate CAS pins allow for separate I/O operation
• JEDEC standard package
- 300 mil, 28-pin SOJ
- 300 mil, 28-pin TSOP
• Latch-up current ≥ 200 mA
• ESD protection ≥ 2000 V
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Pin(s)
Description
A0 to A11
Address inputs
RAS
Row address strobe
CAS0 to CAS3
Column address strobe
WE
Write enable
I/O0 to I/O3
Input/output
OE
Output enable
VCC
Power
GND
Ground
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Symbol
AS4C4M4F1Q-50
AS4C4M4F1Q-60
Unit
Maximum RAS access time
tRAC
50
60
ns
Maximum column address access time
tCAA
25
30
ns
Maximum CAS access time
tCAC
12
15
ns
Maximum output enable (OE) access time
tOEA
13
15
ns
Minimum read or write cycle time
tRC
85
100
ns
Minimum fast page mode cycle time
tPC
20
24
ns
Maximum operating current
ICC1
135
120
mA
Maximum CMOS standby current
ICC5
2.0
2.0
mA
3/22/02; v.1.3
Alliance Semiconductor
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The AS4C4M4F1Q is a high performance 16-megabit CMOS Dynamic Random Access Memory (DRAM) device that is organized as 4,194,304
words × 4 bits. The device is fabricated using advanced CMOS technology and innovative design techniques resulting in high speed, extremely
low power and wide operating margins at component and system levels. The Alliance 16Mb DRAM family is optimized for use as main
memory in PCs, workstations, routers and switch applications.
The device features a high speed page mode operation where read and write operations within a single row (or page) can be executed at very
high speed by toggling column addresses within that row. Row and column addresses are alternately latched into input buffers using the falling
edge of RAS and CAS inputs respectively. Four individual CAS pins allow for separate I/O operation which enables the device to operate in
parity mode. Also, RAS is used to make the column address latch transparent, enabling application of column addresses prior to CAS assertion.
Refresh on the 2048 address combinations of A0 to A10 must be performed every 32 ms using:
• RAS-only refresh: RAS is asserted while CAS is held high. Each of the 2048 rows must be strobed. Outputs remain high impedence.
• Hidden refresh: CAS is held low while RAS is toggled. Refresh address is generated internally. Outputs remain low impedence with previous
valid data.
• CAS-before-RAS refresh (CBR): CAS is asserted prior to RAS. Refresh address is generated internally.
Outputs are high-impedence (OE and WE are don't care).
• Normal read or write cycles refresh the row being accessed.
The AS4C4M4F1Q is available in the standard 28-pin plastic SOJ and 28-pin plastic TSOP packages. The AS4C4M4F1Q operates with a single
power supply of 5V ± 0.5V and provides TTL compatible inputs and outputs.
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Parameter
Supply voltage
Input voltage
Ambient operating temperature
Symbol
Min
Nominal
Max
Unit
VCC
4.5
5.0
5.5
V
GND
0.0
0.0
0.0
V
VIH
2.4
–
VCC
V
VIL
–0.5†
–
0.8
V
TA
0
70
°C
†V min -3.0V for pulse widths less than 5 ns. Recommended operating conditions apply throughout this document unlesss otherwise specified.
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3/22/02; v.1.3
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Parameter
Symbol
Min
Max
Unit
Input voltage
Vin
-1.0
+7.0
V
Input voltage (DQs)
VDQ
-1.0
VCC + 0.5
V
Power supply voltage
VCC
-1.0
+7.0
V
Storage temperature (plastic)
TSTG
-55
+150
Soldering temperature × time
°C
oC
TSOLDER
–
260 × 10
Power dissipation
PD
–
1
W
Short circuit output current
Iout
–
50
mA
× sec
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Parameter
Symbol Test conditions
-60
Min
Max
Min
Max
Unit
Notes
Input leakage current IIL
0V ≤ Vin ≤ +5.5V,
Pins not under test = 0V
-5
+5
-5
+5
µA
Output leakage
current
IOL
DOUT disabled, 0V ≤ Vout ≤ +5.5V
-5
+5
-5
+5
µA
Operating power
supply current
ICC1
RAS, CAS Address cycling; tRC=min
–
135
–
120
mA
TTL standby power
supply current
ICC2
RAS = CAS ≥ VIH
–
2.0
–
2.0
mA
Average power supply
current, RAS refresh ICC3
mode or CBR
RAS cycling, CAS ≥ VIH,
tRC = min of RAS low after XCAS
low.
–
120
–
110
mA
1
Fast page mode
average power supply ICC4
current
RAS = VIL, CAS,
address cycling: tHPC = min
–
130
–
120
mA
1, 2
CMOS standby power
ICC5
supply current
RAS = CAS = VCC - 0.2V
–
2.0
–
2.0
mA
Output voltage
CAS before RAS
refresh current
3/22/02; v.1.3
VOH
IOUT = -5.0 mA
2.4
–
2.4
–
V
VOL
IOUT = 4.2 mA
–
0.4
–
0.4
V
ICC6
RAS, CAS cycling, tRC = min
–
120
–
110
mA
Alliance Semiconductor
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-60
Symbol Parameter
Min
Max
Min
Max
Unit
Notes
tRC
Random read or write cycle time
80
–
100
–
ns
tRP
RAS precharge time
30
–
40
–
ns
tRAS
RAS pulse width
50
10K
60
10K
ns
tCAS
CAS pulse width
8
10K
10
10K
ns
tRCD
RAS to CAS delay time
15
35
15
43
ns
6
tRAD
RAS to column address delay time
12
25
12
30
ns
7
tRSH
CAS to RAS hold time
10
–
10
–
ns
tCSH
RAS to CAS hold time
40
–
50
–
ns
tCRP
CAS to RAS precharge time
5
–
5
–
ns
tASR
Row address setup time
0
–
0
–
ns
tRAH
Row address hold time
8
–
10
–
ns
tT
Transition time (rise and fall)
1
50
1
50
ns
4,5
tREF
Refresh period
–
32
–
32
ms
16
tCP
CAS precharge time
8
–
10
–
ns
tRAL
Column address to RAS lead time
25
–
30
–
ns
tASC
Column address setup time
0
–
0
–
ns
tCAH
Column address hold time
8
10
–
ns
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Symbol Parameter
-60
Min
Max
Min
Max
Unit
Notes
tRAC
Access time from RAS
–
50
–
60
ns
6
tCAC
Access time from CAS
–
12
–
15
ns
6,13
tAA
Access time from address
–
25
–
30
ns
7,13
tRCS
Read command setup time
0
–
0
–
ns
tRCH
Read command hold time to CAS
0
–
0
–
ns
9
tRRH
Read command hold time to RAS
0
–
0
–
ns
9
3/22/02; v.1.3
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Symbol Parameter
-60
Min
Max
Min
Max
Unit
Notes
tWCS
Write command setup time
0
–
0
–
ns
11
tWCH
Write command hold time
10
–
10
–
ns
11
tWP
Write command pulse width
10
–
10
–
ns
tRWL
Write command to RAS lead time
10
–
10
–
ns
tCWL
Write command to CAS lead time
8
–
10
–
ns
tDS
Data-in setup time
0
–
0
–
ns
12
tDH
Data-in hold time
8
–
10
–
ns
12
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-50
-60
Symbol Parameter
Min
Max
Min
Max
Unit
Notes
tRWC
Read-write cycle time
113
–
135
–
ns
tRWD
RAS to WE delay time
67
–
77
–
ns
11
tCWD
CAS to WE delay time
32
–
35
–
ns
11
tAWD
Column address to WE delay time
42
–
47
–
ns
11
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-50
Symbol Parameter
-60
Min
Max
Min
Max
Unit
Notes
tCSR
CAS setup time (CAS-before-RAS)
5
–
5
–
ns
3
tCHR
CAS hold time (CAS-before-RAS)
8
–
10
–
ns
3
tRPC
RAS precharge to CAS hold time
0
–
0
–
ns
tCPT
CAS precharge time
(CBR counter test)
10
10
–
ns
3/22/02; v.1.3
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Symbol
Parameter
tCPA
Access time from CAS precharge
tRASP
-60
Min
Max
Min
Max
–
28
–
35
RAS pulse width
50
100K
60
100K
tPC
Read-write cycle time
30
–
35
–
tCP
CAS precharge time (fast page)
10
–
10
–
tPCM
Fast page mode RMW cycle
80
–
85
–
tCRW
Page mode CAS pulse width (RMW)
12
–
15
–
Unit
Notes
13
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-50
Symbol
Parameter
tCLZ
-60
Min
Max
Min
Max
Unit
CAS to output in Low Z
0
–
0
–
ns
tROH
RAS hold time referenced to OE
8
–
10
–
ns
tOEA
OE access time
–
13
–
15
ns
tOED
OE to data delay
13
–
15
–
ns
tOEZ
Output buffer turnoff delay from OE
0
13
0
15
ns
tOEH
OE command hold time
10
–
10
–
ns
tOLZ
OE to output in Low Z
0
–
0
–
ns
tOFF
Output buffer turn-off time
0
13
0
15
ns
3/22/02; v.1.3
Alliance Semiconductor
Notes
8
8
8,10
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9
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14
15
16
ICC1, ICC3, ICC4, and ICC6 are dependent on frequency.
ICC1 and ICC4 depend on output loading. Specified values are obtained with the output open.
An initial pause of 200 µs is required after power-up followed by any 8 RAS cycles before proper device operation is achieved. In the case of an internal
refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 8 initialization cycles are required after
extended periods of bias without clocks (greater than 8 ms).
AC Characteristics assume tT = 2 ns. All AC parameters are measured with a load equivalent to two TTL loads and 50 pF, VIL (min) ≥ GND and VIH (max)
≤ VCC.
VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL.
Operation within the tRCD (max) limit insures that tRAC (max) can be met. tRCD (max) is specified as a reference point only. If tRCD is greater than the
specified tRCD (max) limit, then access time is controlled exclusively by tCAC.
Operation within the tRAD (max) limit insures that tRAC (max) can be met. tRAD (max) is specified as a reference point only. If tRAD is greater than the
specified tRAD (max) limit, then access time is controlled exclusively by tAA.
Assumes three state test load (5 pF and a 380 Ω Thevenin equivalent).
Either tRCH or tRRH must be satisfied for a read cycle.
tOFF (max) defines the time at which the output achieves the open circuit condition; it is not referenced to output voltage levels. tOFF is referenced from
rising edge of RAS or CAS, whichever occurs last.
tWCS, tWCH, tRWD, tCWD and tAWD are not restrictive operating parameters. They are included in the datasheet as electrical characteristics only.
If tWS ≥ tWS (min) and tWH ≥ tWH (min), the cycle is an early write cycle and data out pins will remain open circuit, high impedance, throughout the
cycle. If tRWD ≥ tRWD (min), tCWD ≥ tCWD (min) and tAWD ≥ tAWD (min), the cycle is a read-write cycle and the data out will contain data read from the
selected cell. If neither of the above conditions is satisfied, the condition of the data out at access time is indeterminate.
These parameters are referenced to CAS leading edge in early write cycles and to WE leading edge in read-write cycles.
Access time is determined by the longest of tCAA or tCAC or tCPA
tASC ≥ tCP to achieve tPC (min) and tCPA (max) values.
These parameters are sampled and not 100% tested.
These characteristics apply to AS4C4M4F1Q 5V devices.
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- Access times are measured with output reference levels of VOH =
2.4V and VOL = 0.4V,
VIH = 2.4V and VIL = 0.8V
- Input rise and fall times: 2 ns
+5V
R1 = 828Ω
Dout
50 pF*
R2 = 295Ω
*including scope
and jig capacitance
GND
Figure A: Equivalent output load
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Rising input
3/22/02; v.1.3
Falling input
Alliance Semiconductor
Undefined output/don’t care
P. 7 of 14
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tRC
tRAS
tRCD
tRSH
tRP
RAS
tCSH
tCRP
tCAH
tCAS
tASC
tRCS
CAS
tRAD
tRAH
tASR
Address
tRAL
Row address
Column address
tRRH
tRCH
WE
tROH
tROH
tWEZ
OE
tOEZ
tRAC
tAA
tOFF (see note 11)
tOEA
tCAC
tREZ
tCLZ
DQ
Data out
tOLZ
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tRC
tRAS
tRP
RAS
tCSH
tRSH
tCRP
tRCD
tCAS
CAS
tRAD
tRAL
tASC
tASR
Address
tRAH
tCAH
Row address
Column address
tCWL
tRWL
tWP
tWCS
tWCH
WE
OE
tDS
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3/22/02; v.1.3
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3/22/02; v.1.3
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Parameter
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Symbol
Input capacitance
DQ capacitance
Signals
Test conditions
Max
Unit
CIN1
A0 to A9
Vin = 0V
5
pF
CIN2
RAS, WE, OE, CAS0, CAS1, CAS2, CAS3
Vin = 0V
7
pF
CDQ
DQ0 to DQ3
Vin = Vout = 0V
7
pF
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Package \ RAS access time
Plastic SOJ, 300 mil, 28-pin
5V
Plastic TSOP, 300 mil, 28-pin
50 ns
60 ns
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AS4C4M4F1Q-60JC
AS4C4M4F1Q-50TC
AS4C4M4F1Q-60TC
$6&0)4IDPLO\SDUWQXPEHULQJV\VWHP
AS4
C
DRAM
prefix
C = 5V CMOS
3/22/02; v.1.3
4M4
F1
–XX
X
C
4M×4
F1=2K refresh
RAS access
time
Package:
J = SOJ 300 mil, 28
T = TSOP 300 mil, 28
Commercial temperature
range, 0°C to 70 °C
Alliance Semiconductor
P. 14 of 14
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