ETC AT76C711

Features
• AVR® Microcontroller
• Clock Generator Provides CPU Rates up to 24 MHz
• Programmable UART with 16-byte FIFOs at the Receiver Side (1), with a Maximum Rate
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
of 921K Baud
Programmable SPI Interface
Full-speed USB Function Controller
2K Bytes of SRAM for Data, Stack and Program Variables
2K Bytes of Dual-port RAM, Shared among the USB, UART and AVR
8K x 16-bit SRAM for Program Execution
Internal ROM for the Bootstrap Loader
One USB Control Endpoint
Six USB Programmable Endpoints (up to 64 Bytes) with Double-buffered FIFOs for
Back-to-back Transfers
One 8-bit Timer/Counter
One 16-bit Timer/Counter
External and Internal Interrupt Sources
Programmable Watchdog Timer
Independent UART BRG Oscillator
64-lead TQFP Package and BGA Package
3.3V Operation
AVR®-based
Bridge between
Full-speed USB
and Fast Serial
Asynchronous
Interfaces
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
AT76C711
Summary
P_RX
P_TX
GND
VCC
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
VCC
GND
TEST2
ECK
TCK
TP
LC
VCC
GND
DP
DM
SUSP
GND
VCC
PM0
PM1
PC0
PC1
PC2
PC3
RST
PB0_T0
PB1_T1
PB2_ICP
PB3
PB4_SS
PB5_MOSI
PB6_MISO
PB7_SCK
VCC
LFT
GND
XTAL1
XTAL2
TEST1
PSDIN
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
NC
VCC
GND
PD7_INT1
PD6_INT0
PD5
PD4
PD3
PD2
PD1_SOUT
PD0_SIN
UXTAL0
UXTAL1
GND
LFTU
VCC
Pin Configuration (TQFP)
Rev. 1643ES–USB–06/03
Note: This is a summary document. A complete document is available on
our web site at www.atmel.com.
1
Description
The Atmel AT76C711 is a compound USB device designed to provide a high-speed
USB interface to devices that need to communicate with a host through fast serial links,
like UARTs and IrDA interfaces. It is based on the AVR-enhanced RISC architecture
and consists of a USB function interface with a devoted DMA controller for fast data
transfers between the buffers of the USB endpoints and a shared DPRAM of 2K bytes,
2K bytes SRAM for data, stack and program variables, a Synchronous Peripheral Interface (SPI), a UART supporting a maximum rate of 921K baud with DMA channels for
data transfers to/from the DPRAM and an 8K x 16-bit SRAM for microcode execution.
An IrDA controller is also provided, attached to a second UART module, and is able to
communicate with an IrDA transceiver with a maximum rate of 1.2 Mbps. An internal
ROM contains the bootstrap loader which reads the instructions from an external serial
DataFlash® of Atmel AT45 Series and stores them into the on-chip program SRAM.
Alternatively, microcode can be stored in the program SRAM using the slave program
mode while the chip is in the reset state.
The USB Hardware block consists of a USB transceiver, the SIE, endpoint controllers
and an interface to the microcontroller. The USB Hardware interfaces to the USB host at
the packet level. The microcontroller firmware handles the higher-level USB protocol
layers that are not processed by the USB Hardware and in addition, it performs the
peripheral control functions.
The device is suitable for applications where minimization of power dissipation is
required, since there are no power-consumable transactions with external parallel
devices.
Block Diagram
Program
Memory
Controller
Osc
Clock
Generator
IrDA 1.0
EncDec
UART
1
Timers
SRAM
WD
General-Purpose I/O
AVR Core
USB
Address
Decoder
2
SPI
DPRAM
DMA
Controller
UART0
AT76C711
1643ES–USB–06/03
AT76C711
Applications
The AT76C711 can be used in applications where peripherals supporting fast serial
asynchronous or synchronous transfer of data have to communicate with a host or other
peripherals through a high-speed serial link, like USB. A typical application of
AT76C711 and its functional diagram are shown in Figures 1 and 2.
Typical areas of AT76C711 usage are:
•
Connection of Network Interface Cards (NICs) to a host system
•
Wireless communications
•
Bridging of microcontrollers with different types of serial interfaces
•
USB to UART bridge
•
USB to IrDA bridge
•
IrDA to UART bridge
•
Packet adaptation of network protocol packets to USB requirements
Figure 1. Typical AT76C711 Application
UART
USB
AT76C
711
Network
Adaptor
RF
Trsc
RF
Trsc
Network
Adaptor
Printer
Desktop System
Figure 2. Functional Diagram
S/U
PROGRAM MEMORY
CONTROLLER
Debug
ROM
16K x 16-bit
SRAM
CLOCK
Osc
IrDA 1.0
EncDec
Clock
Generator
UART
1
Program Bus
AVR Core
SRAM
Timers
2K x 8-bit
WD
SUSP
Data
Interrupt Lines
DP
DM
USB
RAM Address Bus & Bi-directional Data Bus
TDMAC,
RDMAC, UINT
Address & Control Bus for AVR Register File Programming
RST
TXRDY
RXRDY
UINT
Address
Decoder
/
DPRAM
2K x 8-bit
DMA
Controller
SPI
USART
0
UART
Osc
USCLK
DATA PORT REGISTERS - PORT DIRECTION REGISTERS DRIVERS/BUFFERS
XTAL1 XTAL2 LFT
PA0/SIN1/IrRx
PA1/SOUT1/IrT
PA2
PA3
PA4
PA5
PA6
PA7
PB0/T0
PB1/T1
PB2/INT0
PB3/INT1
PB4/SS
PB5/MOSI
PB6/MISO
PB7/SCK
PC0-3
PD0/SIN0
PD1/SOUT0
PD2/RTS0
PD3/CTS0
PD4/DSR0
PD5/DTR0
PD6
PD7
UXTALO
UXTALI
LFTU
3
1643ES–USB–06/03
Pin Summary – Pin Assignment in Alphabetical Order
Type:
Pin #
TQFP
Pin #
BGA
Signal
Type
Pin #
TQFP
Pin #
BGA
Signal
Type
Pin #
TQFP
Pin #
BGA
Signal
23
H4
DM
B
44
D6
PA7
B
58
C5
PD4
B
22
H3
DP
B
2
B1
PB0_T0
B
59
B4
PD5
B
33
H8
ECK
I
3
C3
PB1_T1
B
60
C4
PD6_INT0
B
19
F3
LC
I
4
C2
PB2_ICP
B
61
A3
PD7_INT1
B
14
E2
LFT
I
5
D2
PB3
B
16
G2
PSDIN
I
50
A7
LFTU
I
6
C1
PB4_SS
B
1
A1
RST
I
*
***
GND
V
7
D1
PB5_MOSI
B
27
28
G5,
F5
PM0,
PM1
I
64
B2
NC
8
D4
PB6_MISO
B
24
E4
SUSP
O
48
B7
P_IRX
I
9
E1
PB7_SCK
B
17
H1
TCK
I
47
B8
P_ITX
O
29
H6
PC0
B
15
G1
TEST1
I
37
E7
PA0
B
30
G6
PC1
B
34
G8
TEST2
I
38
F8
PA1
B
31
H7
PC2
B
18
H2
TP
I
39
E8
PA2
B
32
G7
PC3
B
**
****
VCC
V
40
E5
PA3
B
54
A6
PD0_SIN
B
51
B6
UXTALI
I
41
D8
PA4
B
55
A5
PD1_SOUT
B
52
B5
UXTALO
O
42
E6
PA5
B
56
D5
PD2
B
11
F1
XTAL1
I
43
D7
PA6
B
57
A4
PD3
B
12
F2
XTAL2
O
Notes:
4
I = Input, O = Output, OD = Output, Open Drain, B = Bi-directional, V = Power Supply, Ground
1.
2.
3.
4.
Type
(*) GND - TGFP: 12, 21, 25, 35, 46, 51, 62.
(**) VCC - TQFP: 10, 20, 24, 36, 45, 49, 63.
(***) GND - BGA: B3, C6, C7, E3, F6, H5, G4
(****) VCC - BGA: A2, A8, C8, F7, F4, G3, D3
AT76C711
1643ES–USB–06/03
AT76C711
Pin Summary – Pin Assignment in Numerical Order
Type:
I = Input, O = Output, OD = Output, Open Drain, B = Bi-directional, V = Power Supply, Ground
Pin #
TQFP
Pin #
BGA
Type
Pin #
TQFP
Pin #
BGA
Type
Pin #
TQFP
Pin #
BGA
1
A1
RST
I
23
H4
DM
B
45
C8
VCC
V
2
B1
PB0_T0
B
24
E4
SUSP
O
46
C7
GND
V
3
C3
PB1_T1
B
25
H5
GND
V
47
B8
P_ITX
O
4
C2
PB2_ICP
B
26
F4
VCC
V
48
B7
P_IRX
I
5
D2
PB3
B
27
G5
PM0
I
49
A8
VCC
V
6
C1
PB4_SS
B
28
F5
PM1
I
50
A7
LFTU
I
7
D1
PB5_MOSI
B
29
H6
PC0
B
51
C6
GND
V
8
D4
PB6_MISO
B
30
G6
PC1
B
52
B6
UXTALI
I
9
E1
PB7_SCK
B
31
H7
PC2
B
53
B5
UXTALO
O
10
D3
VCC
V
32
G7
PC3
B
54
A6
PD0_SIN
B
11
E2
LFT
I
33
H8
ECK
I
55
A5
PD1_SOUT
B
12
E3
GND
V
34
G8
TEST2
I
56
D5
PD2
B
13
F1
XTAL1
I
35
F6
GND
V
57
A4
PD3
B
14
F2
XTAL2
O
36
F7
VCC
V
58
C5
PD4
B
15
G1
TEST1
I
37
E7
PA0
B
59
B4
PD5
B
16
G2
PSDIN
I
38
F8
PA1
B
60
C4
PD6_INT0
B
17
H1
TCK
I
39
E8
PA2
B
61
A3
PD7_INT1
B
18
H2
TP
I
40
E5
PA3
B
62
B3
GND
V
19
F3
LC
I
41
D8
PA4
B
63
A2
VCC
V
20
G3
VCC
V
42
E6
PA5
B
64
B2
NC
V
21
G4
GND
V
43
D7
PA6
B
22
H3
DP
B
44
D6
PA7
B
Signal
Signal
Signal
Type
5
1643ES–USB–06/03
Signal Description (1)
Type:
I = Input, O = Output, OD = Output, Open Drain, B = Bi-directional, V = Power Supply, Ground
Name
Type
Description
Program Memory Controller Signals
PM0, PM1
I
Configuration pins
PSDIN
I
Program Serial Data-In: In slave program mode, this signal carries the serial program data that
are samples with the positive edge of TCK.
TP
I
When RST is active (low), a high level of this signal, for at least two TCK pulses, forces the
program address generator.
LC
I
Load Complete: A transition from low to high denotes the completion of program data transfer
from the external device. The AVR will start executing instructions from the internal SRAM as
soon as the RST goes high.
TCK
I
A clock signal for sampling PSDIN input.
PA[0:7]
B
Port A, PA0 through PA7 – 8-bit bi-directional port.
PB[0:7]
B
Port B, PB0 through PB7 – 8-bit bi-directional port. PB0, PB1, PB2, PB4 through PB7 are dualfunction as shown below:
Port
Alternate Function
PB0
Timer/Counter0 clock input
PB1
Timer/Counter1 clock input
PB2
(ICP) Input Capture Pin for Timer/Counter1
PB4
(SS) SPI slave port select input
PB5
(MOSI) SPI slave port select input
PB6
(MISO) SPI master data-in, slave data-out
PB7
(SCK) SPI master clock out, slave clock in
PC[0:3]
B
Port C, PC0 through PC3 – 4-bit output port.
PD[0:7]
B
Port D, PD0 through PD7 – 8-bit bi-directional I/O port. PD0, PD1 also serve as the data lines for
the asynchronous serial port as listed below:
Port
Alternate Function
PD0
(SIN) Serial Data-In (I): This pin provides the serial receive data input to 16550 UART.
The SIN signal will be a logic “1” during reset, idle (no data). During the local loopback mode, the
SIN input pin is disabled and SOUT data is internally connected to the UART SIN input.
PD1
(SOUT) Serial Data Out (O): This pin provides the serial transmit data from the 16550
UART. The SOUT signal will be a logic “1” during reset, idle (no data).
PD6
(INT0) External Interrupt0 source
PD7
(INT1) External Interrupt1 source
B
Upstream Plus USB I/O – DP and DM form the differential signal pin pair connected to the host
controller or an upstream hub.
DM
B
Upstream Minus USB I/O
SUSP
O
Suspend: This output pin is deactivated (high) during normal operation. It is used to signal the
host microcontroller that AT76C711 has received USB suspend signaling. This pin will stay
asserted while AT76C711 is in the suspend mode. This pin is deactivated whenever a USB
resume signaling is detected on DP and DM.
Port Signals
USB Serial Interface
DP
6
AT76C711
1643ES–USB–06/03
AT76C711
Signal Description (Continued)(1)
Type:
I = Input, O = Output, OD = Output, Open Drain, B = Bi-directional, V = Power Supply, Ground
Name
Type
Description
Test Signals
TEST1
I
Test signal for clocks (used in production phase only – normally tied to high)
TEST2
I
Test signal for monitoring internal signal levels using the four data ports (used in production
phase only – normally tied to high)
ECK
I
Clock pulse for activating various test modes when TEST2 is active
P_ITX
O
Infrared Data Out: This pin provides the serial transmit data from the IrDA codec to external IR
Data Transceiver. This function is activated when the IrDA interface is enabled from PERIPHEN
I/O Register.
P_IRX
I
Infrared Data-In: This pin provides the serial receive data input from the external IR Data
Transceiver to IrDA codec. This function is activated when the IrDA interface is enabled from
PERIPHEN I/O Register.
GND
V
Ground
VCC
V
3.3V power supply
RST
I
Reset: A low on this pin for two machine cycles, while the oscillator is running, resets the device.
XTAL1
I
Oscillator Input: Input to the inverting oscillating amplifier. A 12 MHz clock oscillator should be
applied.
XTAL2
O
Oscillator Output: Output of the inverting oscillator amplifier.
LFT
I
Master clock PLL LFT pin
UXTALI
I
UART BRG Oscillator Input. Input to the UART oscillator amplifier.
UXTALO
O
UART BRG Oscillator Output. Output of the UART oscillator amplifier.
LFTU
I
UART clock PLL LFT pin
IrDA Interface
Other Signals
Note:
1. Any signal with an OVERLINE indicates that it is an active low signal.
7
1643ES–USB–06/03
64C1 – LFBGA
Z
0.10 4X
0.12 Z
X
A
A1 BALL PAD CORNER
A1
D
b
Y
Ø0.15 M Z X Y
Ø0.08 M Z
E
SEATING PLANE
A2
TOP VIEW
SIDE VIEW
A1 BALL PAD CORNER
e
8
7
6
5
4
3
2
1
COMMON DIMENSIONS
(Unit of Measure = mm)
A
B
1.20 REF
C
D
SYMBOL
E
D
F
E
MIN
NOM
MAX
NOTE
8.00 BSC
8.00 BSC
G
H
e
1.20 REF
BOTTOM VIEW
Notes:
–
–
1.70
3
A1
0.25
–
–
3
A2
0.85
–
–
e
b
0.80 BSC
0.45
0.50
0.55
4
1. This drawing is for general information only. Refer to JEDEC Drawing
MO-205, Variation BA, for proper dimensions, tolerances, datums, etc.
2. Array as seen from the bottom of the package.
3. Dimension A includes standoff height A1, package body thickness, and lid height,
but does not include attached features.
4. Dimension b is measured at the maximum ball diameter, parallel to primary
datum C.
R
8
A
2325 Orchard Parkway
San Jose, CA 95131
TITLE
64C1, 64-ball (8 x 8 Array),0.80 mm Pitch, 8.0 x 8.0 x 1.70 mm,
2-layer, Low Profile, Fine-Pitch, Ball Grid Array Package (LFBGA)
11/7/02
DRAWING NO.
64C1
REV.
A
AT76C711
1643ES–USB–06/03
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© Atmel Corporation 2003.
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Printed on recycled paper.
1643ES–USB–06/03
xM