[ /Title (CD54 HC405 1, CD74 HC405 1, CD74 HCT40 51, CD74 HC405 2, Data sheet acquired from Harris Semiconductor SCHS122G CD54/74HC4051, CD54/74HCT4051, CD54/74HC4052, CD74HCT4052, CD54/74HC4053, CD74HCT4053 High-Speed CMOS Logic Analog Multiplexers/Demultiplexers November 1997 - Revised July 2003 Features Ordering Information • Wide Analog Input Voltage Range . . . . . . . . . . ±5V Max PART NUMBER • Low “On” Resistance - 70Ω Typical (VCC - VEE = 4.5V) - 40Ω Typical (VCC - VEE = 9V) • Low Crosstalk between Switches TEMP. RANGE (oC) PACKAGE CD54HC4051F3A -55 to 125 16 Ld CERDIP CD54HC4052F3A -55 to 125 16 Ld CERDIP CD54HC4053F3A -55 to 125 16 Ld CERDIP CD54HCT4051F3A -55 to 125 16 Ld CERDIP • Fast Switching and Propagation Speeds CD74HC4051E -55 to 125 16 Ld PDIP • “Break-Before-Make” Switching CD74HC4051M -55 to 125 16 Ld SOIC • Wide Operating Temperature Range . . -55oC to 125oC CD74HC4051M96 -55 to 125 16 Ld SOIC CD74HC4051NSR -55 to 125 16 Ld SOP CD74HC4051PWR -55 to 125 16 Ld TSSOP CD74HC4052E -55 to 125 16 Ld PDIP CD74HC4052M -55 to 125 16 Ld SOIC CD74HC4052M96 -55 to 125 16 Ld SOIC CD74HC4052NSR -55 to 125 16 Ld SOP CD74HC4052PW -55 to 125 16 Ld TSSOP CD74HC4052PWR -55 to 125 16 Ld TSSOP CD74HC4053E -55 to 125 16 Ld PDIP CD74HC4053M -55 to 125 16 Ld SOIC CD74HC4053M96 -55 to 125 16 Ld SOIC CD74HC4053NSR -55 to 125 16 Ld SOP CD74HC4053PW -55 to 125 16 Ld TSSOP CD74HC4053PWR -55 to 125 16 Ld TSSOP • CD54HC/CD74HC Types - Operation Control Voltage . . . . . . . . . . . . . . 2V to 6V - Switch Voltage . . . . . . . . . . . . . . . . . . . . . . . 0V to 10V - High Noise Immunity . . . NIL = 30%, NIH = 30% of VCC, VCC = 5V • CD54HCT/CD74HCT Types - Operation Control Voltage . . . . . . . . . . . 4.5V to 5.5V - Switch Voltage . . . . . . . . . . . . . . . . . . . . . . . 0V to 10V - Direct LSTTL Input Logic Compatibility . . . VIL = 0.8V Max, VIH = 2V Min - CMOS Input Compatibility . . . . . II ≤ 1µA at VOL, VOH Description These devices are digitally controlled analog switches which utilize silicon gate CMOS technology to achieve operating speeds similar to LSTTL with the low power consumption of standard CMOS integrated circuits. These analog multiplexers/demultiplexers control analog voltages that may vary across the voltage supply range (i.e. VCC to VEE). They are bidirectional switches thus allowing any analog input to be used as an output and vice-versa. The switches have low “on” resistance and low “off” leakages. In addition, all three devices have an enable control which, when high, disables all switches to their “off” state. CD74HCT4051E -55 to 125 16 Ld PDIP CD74HCT4051M -55 to 125 16 Ld SOIC CD74HCT4051M96 -55 to 125 16 Ld SOIC CD74HCT4052E -55 to 125 16 Ld PDIP CD74HCT4052M -55 to 125 16 Ld SOIC CD74HCT4052M96 -55 to 125 16 Ld SOIC CD74HCT4053E -55 to 125 16 Ld PDIP CD74HCT4053M -55 to 125 16 Ld SOIC CD74HCT4053M96 -55 to 125 16 Ld SOIC CD74HCT4053PWR -55 to 125 16 Ld TSSOP NOTE: When ordering, use the entire part number. The suffixes 96 and R denote tape and reel. CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, Texas Instruments Incorporated 1 ’HC4051, ’HCT4051, ’HC4052, CD74HCT4052, ’HC4053, CD74HCT4053 Pinouts CD54HC4051, CD54HCT4051 (CERDIP) CD74HC4051 (PDIP, SOIC, SOP, TSSOP) CD74HCT4051 (PDIP, SOIC) TOP VIEW A4 1 16 VCC A6 2 15 A2 A 3 14 A1 A7 4 13 A0 A5 5 12 A3 E 6 11 S0 VEE 7 10 S1 GND 8 9 S2 CHANNEL IN/OUT COM OUT/IN CHANNEL IN/OUT CD54HC4052 (CERDIP) CD74HC4052 (PDIP, SOIC, SOP, TSSOP) CD74HCT4052 (PDIP, SOIC) TOP VIEW B0 1 16 VCC B2 2 15 A2 COM OUT/IN BN 3 14 A1 CHANNEL IN/OUT B3 4 13 AN COM OUT/IN B1 5 12 A0 E 6 11 A3 VEE 7 10 S0 GND 8 9 S1 CHANNEL IN/OUT CHANNEL IN/OUT CHANNEL IN/OUT ADDRESS SELECT CD54HC4053 (CERDIP) CD74HC4053 (PDIP, SOIC, SOP, TSSOP) CD74HCT4053 (PDIP, SOIC, TSSOP) TOP VIEW B1 1 16 VCC B0 2 15 BN COM OUT/IN C1 3 14 AN COM OUT/IN COM OUT/IN CN 4 13 A1 IN/OUT C0 5 12 A0 E 6 11 S0 VEE 7 10 S1 GND 8 9 S2 CHANNEL IN/OUT 2 CHANNEL IN/OUT CHANNEL IN/OUT ’HC4051, ’HCT4051, ’HC4052, CD74HCT4052, ’HC4053, CD74HCT4053 Functional Diagram of HC/HCT4051 CHANNEL IN/OUT VCC A7 A6 A5 A4 A3 A2 A1 A0 16 4 2 5 1 12 15 14 13 TG TG S0 11 TG S1 TG 10 BINARY TO 1 OF 8 DECODER WITH ENABLE LOGIC LEVEL CONVERSION S2 3 TG 9 TG TG E 6 TG 8 7 GND VEE TRUTH TABLE HC/HCT4051 INPUT STATES ENABLE S2 S1 S0 “ON” CHANNELS L L L L A0 L L L H A1 L L H L A2 L L H H A3 L H L L A4 L H L H A5 L H H L A6 L H H H A7 H X X X None X = Don’t care 3 A COMMON OUT/IN ’HC4051, ’HCT4051, ’HC4052, CD74HCT4052, ’HC4053, CD74HCT4053 Functional Diagram of ’HC4052, CD74HCT4052 A CHANNELS IN/OUT VCC A3 A2 A1 A0 11 15 14 12 16 TG TG TG S1 S0 BINARY TO 1 OF 4 DECODER WITH ENABLE LOGIC LEVEL CONVERSION 9 TG 13 COMMON A OUT/IN TG 3 COMMON B OUT/IN 10 TG E 6 TG TG 8 7 1 5 2 4 GND VEE B0 B1 B2 B3 B CHANNELS IN/OUT TRUTH TABLE ’HC4052, CD74HCT4052 INPUT STATES ENABLE S1 S0 “ON” CHANNELS L L L A0, B0 L L H A1, B1 L H L A2. B2 L H H A3, B3 H X X None X = Don’t care 4 ’HC4051, ’HCT4051, ’HC4052, CD74HCT4052, ’HC4053, CD74HCT4053 Functional Diagram of ’HC4053, CD74HCT4053 BINARY TO 1 OF 2 DECODERS WITH ENABLE VCC LOGIC LEVEL CONVERSION 16 IN/OUT C1 C0 B1 B0 A1 A0 3 5 1 2 13 12 TG S0 11 S1 10 14 A COMMON OUT/IN 15 B COMMON OUT/IN 4 C COMMON OUT/IN TG TG TG S2 TG 9 TG E 6 8 7 GND VEE TRUTH TABLE ’HC4053, CD74HCT4053 INPUT STATES ENABLE S0 S1 S2 “ON” CHANNELS L L L L C0, B0, A0 L H L L C0, B0, A1 L L H L C0, B1, A0 L H H L C0, B1, A1 L L L H C1, B0, A0 L H L H C1, B0, A1 L L H H C1, B1, A0 L H H H C1, B1, A1 H X X X None X = Don’t care 5 ’HC4051, ’HCT4051, ’HC4052, CD74HCT4052, ’HC4053, CD74HCT4053 Absolute Maximum Ratings Thermal Information (Note 2) Package Thermal Impedance, θJA (see Note 1): E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67oC/W M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73oC/W NS (SOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64oC/W PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . 108oC/W Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC DC Supply Voltage, VCC - VEE . . . . . . . . . . . . . . . . . -0.5V to 10.5V DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V DC Supply Voltage, VEE . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.5V to -7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Switch Diode Current, IOK For VI < VEE -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . .±20mA DC Switch Current, (Note 2) For VI > VEE -0.5V or VI < VCC + 0.5V . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA DC VEE Current, IEE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20mA NOTE: 1. The package thermal impedance is calculated in accordance with JESD 51-7. Recommended Operating Conditions For maximum reliability, nominal operating conditions should be selected so that operation is always within the following ranges PARAMETER MIN MAX UNITS 2 6 V 4.5 5.5 V 2 10 V 0 -6 V DC Input Control Voltage, VI GND VCC V Analog Switch I/O Voltage, VIS VEE VCC V Operating Temperature, TA -55 125 oC 2V 0 1000 ns 4.5V 0 500 ns 6V 0 400 ns Supply Voltage Range (For TA = Full Package Temperature Range), VCC (Note 2) CD54/74HC Types CD54/74HCT Types Supply Voltage Range (For TA = Full Package Temperature Range), VCC - VEE CD54/74HC Types, CD54/74HCT Types (See Figure 1) Supply Voltage Range (For TA = Full Package Temperature Range), VEE (Note 3) CD54/74HC Types, CD54/74HCT Types (See Figure 2) Input Rise and Fall Times, tr, tf CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 2. All voltages referenced to GND unless otherwise specified.. 3. In certain applications, the external load resistor current may include both VCC and signal line components. To avoid drawing VCC current when switch current flows into the transmission gate inputs, the voltage drop across the bidirectional switch must not exceed 0.6V (calculated from rON values shown in Electrical Specifications table). No VCC current will flow through RL if the switch current flows into terminal 3 on the HC/HCT4051; terminals 3 and 13 on the HC/HCT4052; terminals 4, 14 and 15 on the HC/HCT4053. Recommended Operating Area as a Function of Supply Voltages 8 VCC - GND (V) VCC - GND (V) 8 6 HCT HC 4 2 0 0 2 4 6 8 10 6 HCT 2 0 12 VCC - VEE (V) HC 4 0 -2 -4 -6 -8 VEE - GND (V) FIGURE 1. FIGURE 2. 6 ’HC4051, ’HCT4051, ’HC4052, CD74HCT4052, ’HC4053, CD74HCT4053 DC Electrical Specifications TEST CONDITIONS PARAMETER VIS (V) VI (V) AMBIENT TEMPERATURE, TA VEE (V) 25oC -40oC - 85oC -55oC - 125oC VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS 2 1.5 - - 1.5 - 1.5 - V 4.5 3.15 - - 3.15 - 3.15 0 V 6 4.2 - - 4.2 - 4.2 - V 2 - - 0.5 - 0.5 - 0.5 V 4.5 - - 1.35 - 1.35 - 1.35 V 6 - - 1.8 - 1.8 - 1.8 V 0 4.5 - 70 160 - 200 - 240 Ω 0 6 - 60 140 - 175 - 210 Ω -4.5 4.5 - 40 120 - 150 - 180 Ω 0 4.5 - 90 180 - 225 - 270 Ω 0 6 - 80 160 - 200 - 240 Ω -4.5 4.5 - 45 130 - 162 - 195 Ω 0 4.5 - 10 - - - - - Ω 0 6 - 8.5 - - - - - Ω -4.5 4.5 - 5 - - - - - Ω 0 6 - - ±0.1 - ±1 - ±1 µA -5 5 - - ±0.1 - ±1 - ±1 µA 0 6 - - ±0.1 - ±1 - ±1 µA -5 5 - - ±0.2 - ±2 - ±2 µA 0 6 - - ±0.2 - ±2 - ±2 µA -5 5 - - ±0.4 - ±4 - ±4 µA VCC or GND 0 6 - - ±0.1 - ±1 - ±1 µA VCC or GND 0 6 - - 8 - 80 - 160 µA -5 5 - - 16 - 160 - 320 µA HC TYPES High Level Input Voltage, VIH Low Level Input Voltage, VIL On Resistance, rON IO = 1mA, (Figure 11) VCC or VEE VIL or VIH VCC to VEE Maximum On Resistance Between any Two Channels, ∆rON Switch On/Off Leakage Current, IIZ 1 and 2 Channels 4053 4 Channels 4052 8 Channels For Switch Off: When VIS = VCC, VOS = VEE; When VIS = VEE, VOS = VCC For Switch On: All Applicable Combinations of VIS and VOS Voltage Levels VIL or VIH 4051 Control Input Leakage Current, IIL Quiescent Device Current, ICC IO = 0 When VIS = VEE, VOS = VCC When VIS = VCC, VOS = VEE 7 ’HC4051, ’HCT4051, ’HC4052, CD74HCT4052, ’HC4053, CD74HCT4053 DC Electrical Specifications (Continued) TEST CONDITIONS VIS (V) PARAMETER VI (V) AMBIENT TEMPERATURE, TA VEE (V) VCC (V) 25oC -40oC - 85oC -55oC - 125oC MIN TYP MAX MIN MAX MIN MAX UNITS HCT TYPES High Level Input Voltage, VIH 4.5 to 5.5 2 - - 2 - 2 - V Low Level Input Voltage, VIL 4.5 to 5.5 - - 0.8 - 0.8 - 0.8 V 0 4.5 - 70 160 - 200 - 240 Ω - - - - - - - - - Ω -4.5 4.5 - 40 120 - 150 - 180 Ω 0 4.5 - 90 180 - 225 - 270 Ω - - - - - - - - - Ω -4.5 4.5 - 45 130 - 162 - 195 Ω 0 4.5 - 10 - - - - - Ω - - - - - - - - - Ω -4.5 4.5 - 5 - - - - - Ω 0 6 - - ±0.1 - ±1 - ±1 µA -5 5 - - ±0.1 - ±1 - ±1 µA 0 6 - - ±0.1 - ±1 - ±1 µA -5 5 - - ±0.2 - ±2 - ±2 µA 0 6 - - ±0.2 - ±2 - ±2 µA -5 5 - - ±0.4 - ±4 - ±4 µA On Resistance, rON IO = 1mA, (Figure 15) VCC or VEE VIL or VIH VCC to VEE Maximum On Resistance Between any Two Channels, ∆rON Switch On/Off Leakage Current, IIZ 1 and 2 Channels 4053 4 Channels 4052 8 Channels For Switch Off: When VIS = VCC, VOS = VEE; When VIS = VEE, VOS = VCC For Switch On: All Applicable Combinations of VIS and VOS Voltage Levels VIL or VIH 4051 Control Input Leakage Current, IIL - (Note 4) - 5.5 - - ±0.1 - ±1 - ±1 µA Quiescent Device Current, ICC IO = 0 When VIS = VEE, VOS = VCC VCC or GND 0 5.5 - - 8 - 80 - 160 µA -4.5 5.5 - - 16 - 160 - 320 µA 4.5 to 5.5 - 100 360 - 450 - 490 µA Additional Quiescent Device Current Per Input Pin: 1 Unit Load When VIS = VCC, VOS = VEE ∆ICC (Note 5) VCC 2.1 NOTES: 4. Any voltage between VCC and GND. 5. For dual supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. HCT Input Loading Table INPUT UNIT LOADS (NOTE) 4051, 4053 All 0.5 4052 All 0.4 TYPE NOTE: Unit load is ∆ICC limit specified in DC Specifications table, e.g., 360mA max. at 25oC. 8 ’HC4051, ’HCT4051, ’HC4052, CD74HCT4052, ’HC4053, CD74HCT4053 Switching Specifications VCC = 5V, TA = 25oC, Input tr, tr = 6ns TYPICAL 4051 4052 4053 CL (pF) HC HCT HC HCT HC HCT UNITS Switch IN to OUT, tPHL, tPLH 15 4 4 4 4 4 4 ns Switch Turn-Off (S or E), tPHZ, tPLZ 15 19 19 21 21 18 18 ns Switch Turn-On (S or E), tPZH, tPZL 15 19 23 27 29 18 20 ns - 50 52 74 76 38 42 pF PARAMETER Propagation Delay Power Dissipation Capacitance, CPD (Note 6) NOTE: 6. CPD is used to determine the dynamic power consumption, per package. PD = CPD VCC2 fI + ∑ (CL + CS) VCC2 fO fO = output frequency fI = input frequency CL = output load capacitance CS = switch capacitance VCC = supply voltage Switching Specifications CL = 50pF, Input tr, tr = 6ns AMBIENT TEMPERATURE, TA 25oC -40oC - 85oC HC PARAMETER Propagation Delay, Switch In to Out, tPLH, tPHL Maximum Switch Turn “Off” Delay from S or E to Switch Output tPHZ, tPLZ 4051 4052 4053 HCT HC -55oC - 125oC HCT HC HCT VEE (V) VCC (V) MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN 0 2 - 60 - - - 75 - - - 90 - - ns 0 4.5 - 12 - 12 - 15 - 15 - 18 - 18 ns 0 6 - 10 - - - 13 - - - 15 - - ns -4.5 4.5 - 8 - 8 - 10 - 10 - 12 - 12 ns 0 2 - 225 - - - 280 - - - 340 - - ns 0 4.5 - 45 - 45 - 56 - 56 - 68 - 68 ns 0 6 - 38 - - - 48 - - - 57 - - ns -4.5 4.5 - 32 - 32 - 40 - 40 - 48 - 48 ns 0 2 - 250 - - - 315 - - - 375 - - ns 0 4.5 - 50 - 50 - 63 - 63 - 75 - 75 ns 0 6 - 43 - - - 54 - - - 65 - - ns -4.5 4.5 - 38 - 38 - 48 - 48 - 57 - 57 ns 0 2 - 210 - - - 265 - - - 315 - - ns 0 4.5 - 42 - 44 - 53 - 55 - 63 - 66 ns 0 6 - 36 - - - 45 - - - 54 - - ns -4.5 4.5 - 29 - 31 - 36 - 39 - 44 - 47 ns 9 MAX UNITS ’HC4051, ’HCT4051, ’HC4052, CD74HCT4052, ’HC4053, CD74HCT4053 Switching Specifications CL = 50pF, Input tr, tr = 6ns (Continued) AMBIENT TEMPERATURE, TA 25oC -40oC - 85oC HC PARAMETER Maximum Switch Turn “On” Delay from S or E to Switch Output tPZL, tPZH 4051 4052 4053 Input (Control) Capacitance, CI HCT HC -55oC - 125oC HCT HC HCT VEE (V) VCC (V) MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN 0 2 - 225 - - - 280 - - - 340 - - ns 0 4.5 - 45 - 55 - 56 - 69 - 68 - 83 ns 0 6 - 38 - - - 48 - - - 57 - - ns -4.5 4.5 - 32 - 39 - 40 - 49 - 48 - 59 ns 0 2 - 325 - - - 405 - - - 490 - - ns 0 4.5 - 65 - 70 - 81 - 68 - 98 - 105 ns 0 6 - 55 - - - 69 - - - 83 - - ns -4.5 4.5 - 46 - 48 - 58 - 60 - 69 - 72 ns 0 2 - 220 - - - 275 - - - 330 - - ns 0 4.5 - 44 - 48 - 55 - 60 - 66 - 72 ns 0 6 - 37 - - - 47 - - - 56 - - ns -4.5 4.5 - 31 - 34 - 39 - 43 - 47 - 51 ns - - - 10 - 10 - 10 - 10 - 10 - 10 pF Analog Channel Specifications MAX UNITS Typical Values at TA = 25oC PARAMETER TEST CONDITIONS Switch Input Capacitance, CI Common Output Capacitance, CCOM Minimum Switch Frequency Response at -3dB, fMAX (Figures 12, 14, 16) See Figure 3 (Notes 7, 8) HC/HCT TYPES VEE (V) VCC (V) HC/ HCT UNITS All - - 5 pF 4051 - - 25 pF 4052 - - 12 pF 4053 - - 8 pF 145 MHz 165 MHz 4053 200 MHz 4051 180 MHz 185 MHz 200 MHz 4051 4052 4052 4053 10 -2.25 -4.5 2.25 4.5 ’HC4051, ’HCT4051, ’HC4052, CD74HCT4052, ’HC4053, CD74HCT4053 Analog Channel Specifications Typical Values at TA = 25oC PARAMETER Crosstalk Between any Two Switches (Note 10) TEST CONDITIONS See Figure 4 (Notes 8, 9) HC/ HCT UNITS N/A dB (TBE) dB 4053 (TBE) dB 4051 N/A dB (TBE) dB (TBE) dB HC/HCT TYPES VEE (V) VCC (V) 4051 4052 4052 -2.25 -4.5 2.25 4.5 4053 Sinewave Distortion E or S to Switch Feedthrough Noise See Figure 5 See Figure 6 (Notes 8, 9) All -2.25 2.25 0.035 % All -4.5 4.5 0.018 % 4051 4052 mV -2.25 2.25 (TBE) 4053 mV 4051 mV 4052 -4.5 4.5 (TBE) 4053 Switch “OFF” Signal Feedthrough (Figures 13, 15, 17) See Figure 7 (Notes 8, 9) -73 dB -65 dB 4053 -64 dB 4051 -75 dB -67 dB -66 dB 4052 4053 7. Adjust input voltage to obtain 0dBm at VOS for fIN = 1MHz. 8. VIS is centered at (VCC - VEE)/2. 9. Adjust input for 0dBm. 10. Not applicable for HC/HCT4051. 11 mV mV 4051 4052 NOTES: mV -2.25 -4.5 2.25 4.5 ’HC4051, ’HCT4051, ’HC4052, CD74HCT4052, ’HC4053, CD74HCT4053 Test Circuits and Waveforms VCC VIS R 0.1µF INPUT SWITCH ON VOS1 C R fIS = 1MHz SINEWAVE R = 50Ω C = 10pF VCC VOS SWITCH ON VIS 0.1µF VCC /2 VCC 50Ω dB METER 10pF R VCC /2 SWITCH OFF VCC /2 VOS2 R dB METER C VCC /2 FIGURE 3. FREQUENCY RESPONSE TEST CIRCUIT FIGURE 4. CROSSTALK BETWEEN TWO SWITCHES TEST CIRCUIT E VCC VCC VI = VIH SINEWAVE VIS 10µF VIS SWITCH ON fIS = 1kHz TO 10kHz SWITCH ALTERNATING ON AND OFF tr, tf ≤ 6ns fCONT = 1MHz 50% DUTY CYCLE 600Ω VOS 10kΩ 50pF VCC /2 DISTORTION METER VCC /2 FIGURE 5. SINEWAVE DISTORTION TEST CIRCUIT fIS ≥ 1MHz SINEWAVE R = 50Ω C = 10pF VC = VIL VOS SWITCH OFF VIS VOS 600Ω 50pF SCOPE VCC /2 FIGURE 6. CONTROL TO SWITCH FEEDTHROUGH NOISE TEST CIRCUIT VCC 0.1µF VP-P VOS R R VCC /2 VCC /2 C dB METER FIGURE 7. SWITCH OFF SIGNAL FEEDTHROUGH 12 ’HC4051, ’HCT4051, ’HC4052, CD74HCT4052, ’HC4053, CD74HCT4053 Test Circuits and Waveforms (Continued) VCC tr = 6ns tf = 6ns 90% 50% 10% SWITCH INPUT tPLH tPHL VEE 90% 50% 10% SWITCH OUTPUT FIGURE 8A. 6ns 6ns 6ns 90% E OR Sn 50% E OR Sn 10% tPLZ tPLZ OUTPUT LOW TO OFF 10% tPZH SWITCH ON SWITCH OFF 50% 10% tPZH 90% OUTPUT HIGH TO OFF 50% 50% SWITCH ON SWITCH ON GND tPZL tPHZ 90% OUTPUT HIGH TO OFF 3V 0.3 GND 50% tPHZ 6ns 2.7 1.3 tPZL OUTPUT LOW TO OFF tf tr VCC FIGURE 8B. HC TYPES SWITCH OFF SWITCH ON FIGURE 8C. HCT TYPES FIGURE 8. SWITCH PROPAGATION DELAY, TURN-ON, TURN-OFF TIMES VEE FOR tPLZ AND tPZL VCC FOR tPHZ AND tPZH RL = 1kΩ VCC FOR tPLZ AND tPZL CL 50pF VEE FOR tPHZ AND tPZH TG IN OUT IN OUT TG 50pF FIGURE 9. SWITCH ON/OFF PROPAGATION DELAY TEST CIRCUIT FIGURE 10. SWITCH IN TO SWITCH OUT PROPAGATION DELAY TEST CIRCUIT 13 ’HC4051, ’HCT4051, ’HC4052, CD74HCT4052, ’HC4053, CD74HCT4053 Typical Performance Curves 120 ON RESISTANCE (Ω) 100 80 VCC - VEE = 4.5V 60 VCC - VEE = 6V 40 VCC - VEE = 9V 20 1 2 3 4 5 6 INPUT SIGNAL VOLTAGE (V) 7 8 9 FIGURE 11. TYPICAL ON RESISTANCE vs INPUT SIGNAL VOLTAGE 0 0 VCC = 4.5V GND = -4.5V VEE = -4.5V RL = 50Ω PIN 12 TO 3 -2 -20 VCC = 2.25V GND = -2.25V VEE = -2.25V RL = 50Ω PIN 12 TO 3 -40 -4 -6 dB dB VCC = 2.25V GND = -2.25V VEE = -2.25V RL = 50Ω PIN 12 TO 3 -60 VCC = 4.5V GND = -4.5V VEE = -4.5V RL = 50Ω PIN 12 TO 3 -80 -8 -10 10K 100K 1M FREQUENCY (Hz) 10M -100 10K 100M FIGURE 12. CHANNEL ON BANDWIDTH (HC/HCT4051) 100K 1M FREQUENCY (Hz) 10M 100M FIGURE 13. CHANNEL OFF FEEDTHROUGH (HC/HCT4051) 0 0 VCC = 4.5V GND = -4.5V VEE = -4.5V RL = 50Ω PIN 4 TO 3 -2 -4 -40 dB dB VCC = 2.25V GND = -2.25V VEE = -2.25V RL = 50Ω PIN 4 TO 3 -6 VCC = 2.25V GND = -2.25V VEE = -2.25V RL = 50Ω PIN 4 TO 3 -20 -60 VCC = 4.5V GND = -4.5V VEE = -4.5V RL = 50Ω PIN 4 TO 3 -80 -8 -10 10K 100K 1M FREQUENCY (Hz) 10M -100 10K 100M FIGURE 14. CHANNEL ON BANDWIDTH (HC/HCT4052) 100K 1M FREQUENCY (Hz) 10M 100M FIGURE 15. CHANNEL OFF FEEDTHROUGH (HC/HCT4052) 14 ’HC4051, ’HCT4051, ’HC4052, CD74HCT4052, ’HC4053, CD74HCT4053 Typical Performance Curves (Continued) 0 0 VCC = 2.25V GND = -2.25V VEE = -2.25V RL = 50Ω PIN 5 TO 4 -20 VCC = 4.5V GND = -4.5V VEE = -4.5V RL = 50Ω PIN 5 TO 4 -2 -40 dB dB -1 VCC = 4.5V GND = -4.5V VEE = -4.5V RL = 50Ω PIN 5 TO 4 -60 VCC = 2.25V GND = -2.25V VEE = -2.25V RL = 50Ω PIN 5 TO 4 -3 -4 10K 100K 1M FREQUENCY (Hz) 10M -80 -100 10K 100M FIGURE 16. CHANNEL ON BANDWIDTH (HC/HCT4053) 100K 1M FREQUENCY (Hz) 10M 100M FIGURE 17. CHANNEL OFF FEEDTHROUGH (HC/HCT4053) 15 MECHANICAL MPDI002C – JANUARY 1995 – REVISED DECEMBER 20002 N (R-PDIP-T**) PLASTIC DUAL-IN-LINE PACKAGE 16 PINS SHOWN PINS ** 14 16 18 20 A MAX 0.775 (19,69) 0.775 (19,69) 0.920 (23,37) 1.060 (26,92) A MIN 0.745 (18,92) 0.745 (18,92) 0.850 (21,59) 0.940 (23,88) MS-100 VARIATION AA BB AC DIM A 16 9 0.260 (6,60) 0.240 (6,10) 1 C AD 8 0.070 (1,78) 0.045 (1,14) 0.045 (1,14) 0.030 (0,76) D D 0.325 (8,26) 0.300 (7,62) 0.020 (0,51) MIN 0.015 (0,38) Gauge Plane 0.200 (5,08) MAX Seating Plane 0.010 (0,25) NOM 0.125 (3,18) MIN 0.100 (2,54) 0.430 (10,92) MAX 0.021 (0,53) 0.015 (0,38) 0.010 (0,25) M 14/18 PIN ONLY 20 pin vendor option D 4040049/E 12/2002 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001, except 18 and 20 pin minimum body lrngth (Dim A). D. The 20 pin end lead shoulder width is a vendor option, either half or full width. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 MECHANICAL DATA MSOI002B – JANUARY 1995 – REVISED SEPTEMBER 2001 D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 8 PINS SHOWN 0.020 (0,51) 0.014 (0,35) 0.050 (1,27) 8 0.010 (0,25) 5 0.008 (0,20) NOM 0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,81) Gage Plane 1 4 0.010 (0,25) 0°– 8° A 0.044 (1,12) 0.016 (0,40) Seating Plane 0.010 (0,25) 0.004 (0,10) 0.069 (1,75) MAX PINS ** 0.004 (0,10) 8 14 16 A MAX 0.197 (5,00) 0.344 (8,75) 0.394 (10,00) A MIN 0.189 (4,80) 0.337 (8,55) 0.386 (9,80) DIM 4040047/E 09/01 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). Falls within JEDEC MS-012 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-150 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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