CLC446 400MHz, 50mW Current-Feedback Op Amp General Description Features The National CLC446 is a very high speed unity-gain-stable current-feedback op amp that is designed to deliver the highest levels of performance from a mere 50mW quiescent power. It provides a very wide 400MHz bandwidth, a 2000V/µs slew rate and 900ps rise/fall times. The CLC446 achieves its superior speed-vs-power using an advanced complementary bipolar IC process and National’s currentfeedback architecture. The CLC446 is designed to drive video loads with very low differential gain and phase errors (0.02%, 0.03˚). Combined with its very low power (50mW), the CLC446 makes an excellent choice for NTSC/PAL video switchers and routers. With its very quick edge rates (900ps) and high slew rate (2000V/µs), the CLC446 also makes an excellent choice for high speed, high resolution component RGB video systems. The CLC446 makes an excellent low power, high resolution A/D converter driver with its very fast 9ns settling time (to 0.1%) and low harmonic distortion. The combination of high performance and low power make the CLC446 useful in many high speed general purpose applications. Its current-feedback architecture maintains consistent performance over a wide gain range and signal levels. DC gain and bandwidth can be set independently. Also, either maximally flat AC response or linear phase response can be emphasized. n n n n n n n 400MHz bandwidth (AV = +2) 5mA supply current 0.02%, 0.03˚ differential gain, phase 2000V/µs slew rate 9ns settling to 0.1% 0.05dB gain flatness to 100MHz −65/−78dBc HD2/HD3 Applications n n n n n n n High resolution video A/D driver Medical imaging Video switchers & routers RF/IF amplifier Communications Instrumentation Non-Inverting Frequency Response (AV = +2) DS012730-1 Connection Diagram DS012730-89 Pinout DIP & SOIC © 2001 National Semiconductor Corporation DS012730 www.national.com CLC446 400MHz, 50mW Current-Feedback Op Amp February 2001 CLC446 Typical Application DS012730-23 Elliptic-Function Low Pass Filter Ordering Information Package Temperature Range Industrial Part Number Package Marking 8-pin plastic DIP −40˚C to +85˚C CLC446AJP CLC446AJP N08E 8-pin plastic SOIC −40˚C to +85˚C CLC446AJE CLC446AJE M08A www.national.com 2 NSC Drawing Lead Solder Duration (+300˚C) ESD Rating (human body model) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage Output Current Common Mode Input Voltage Maximum Junction Temperature Storage Temperature Range 10 sec 1000V Operating Ratings ± 6V ± 48mA ± VCC Thermal Resistance Package MDIP SOIC +150˚C −65˚C to +150˚C (θJC) 70˚C/W 60˚C/W (θJA) 125˚C/W 140˚C/W Electrical Characteristics AV = +2, VCC = ± 5V, RL = 100Ω, Rf = 249Ω; unless specified Symbol Parameter Ambient Temperature Conditions Typ CLC446AJ Min/Max (Note 2) Units +25˚C +25˚C o to 70˚C −40 to 85˚C VO < 0.2VPP 400 340 300 300 MHz VO < 2.0VPP 280 210 190 190 MHz ± 0.05 ± 0.2 ± 0.2 ± 0.2 dB 0.2 0.5 0.8 0.8 deg Frequency Domain Response -3dB Bandwidth Gain Flatness VO < 2.0VPP Linear Phase Dev. VO < 2.0VPP < 100MHz < 100MHz Differential Gain NTSC, RL = 150Ω 0.02 0.04 0.04 0.04 % Differential Phase NTSC, RL = 150Ω 0.03 0.05 0.05 0.05 deg Rise and Fall Time 2V Step 0.9 1.4 1.5 1.6 ns Settling Time to ± 0.1% 2V Step 9 13 15 15 ns Overshoot 2V Step 6 15 18 18 % Slew Rate 2V Step, ± 0.5V 2000 1400 1300 1200 V/µs Time Domain Response Crossing Distortion And Noise Response 2nd Harmonic Distortion 3rd Harmonic Distortion 2VPP,5MHz −65 −59 −58 −58 dBc 2VPP,20MHz −55 −48 −48 −48 dBc 2VPP,50MHz −54 −43 −42 −42 dBc 2VPP, 5MHz −78 −70 −68 −68 dBc 2VPP,20MHz −70 −62 −60 −60 dBc 2VPP,50MHz −50 −45 −42 −42 dBc Voltage (eni) > 1MHz 3.8 4.8 5.0 5.1 nV/ Non-Inverting Current (ibn) > 1MHz 2.0 2.6 2.8 3.3 pA/ Inverting Current (ibi) > 1MHz 16 19 20 21 pA/ 2 7 10 11 mV 17 - 25 35 µV/C˚ 3 12 25 25 µA 30 - 90 130 nA/C˚ Equivalent Input Noise Static, DC Performance Input Offset Voltage (Note 3) Average Drift Input Bias Current (Note 3) Non-Inverting Average Drift Input Bias Current (Note 3) Inverting Average Drift 10 22 30 35 µA 26 - 75 85 nA/C˚ 45 43 43 dB Power Supply Rejection Ratio DC 52 Common Mode Rejection Ratio DC RL = ∞ 48 44 42 42 dB 4.8 5.8 6.2 6.2 mA Supply Current (Note 3) 3 www.national.com CLC446 Absolute Maximum Ratings (Note 1) CLC446 Electrical Characteristics (Continued) AV = +2, VCC = ± 5V, RL = 100Ω, Rf = 249Ω; unless specified Symbol Parameter Conditions Typ Min/Max (Note 2) Units Miscellaneous Performance Input Resistance Non-Inverting 1.5 1.0 0.85 0.70 MΩ Input Capacitance Non-Inverting 1 2 2 2 pF Input Range Common-Mode RL 100Ω ± 2.6 ± 2.8 ± 3.0 ± 2.4 ± 2.8 ± 2.9 ± 2.3 ± 2.6 V Output Voltage Range ± 2.8 ± 3.1 ± 3.2 2.8 V 48 48 48 48 mA 0.04 0.1 0.1 0.1 Ω RL = ∞ Output Current Output Resistance, Closed Loop DC V Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation. Note 2: Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined from tested parameters. Note 3: AJ-level: spec. is 100% tested at +25˚C. Typical Performance Characteristics (VCC = ± 5, AV = +2, Rf =249Ω, RL =100Ω; unless specified) Non-Inverting Frequency Response Inverting Frequency Response DS012730-2 Frequency Response vs. RL DS012730-3 Frequency Response vs. RO DS012730-4 www.national.com DS012730-5 4 CLC446 Typical Performance Characteristics (VCC = ± 5, AV = +2, Rf =249Ω, RL =100Ω; unless specified)) (Continued) Frequency Response vs. CL Recommended RS vs. CL DS012730-6 DS012730-21 Small Signal Pulse Response Large Signal Pulse Response DS012730-16 DS012730-17 Equivalent Input Noise 2nd Harmonic Distortion DS012730-7 DS012730-8 5 www.national.com CLC446 Typical Performance Characteristics (VCC = ± 5, AV = +2, Rf =249Ω, RL =100Ω; unless specified)) (Continued) 3rd Harmonic Distortion Differential Gain and Phase (3.58MHz) DS012730-18 DS012730-9 2nd Harmonic Distortion vs. POUT 3rd Harmonic Distortion vs. POUT DS012730-19 VOS, IBN, and IBI vs. Temperature DS012730-20 Short Term Settling Time DS012730-22 www.national.com DS012730-10 6 CLC446 Typical Performance Characteristics (VCC = ± 5, AV = +2, Rf =249Ω, RL =100Ω; unless specified)) (Continued) Long Term Settling Time DS012730-11 The denominator of the equation above is approximately 1 at low frequencies. Near the −3dB corner frequency, the interaction between Rf and Z(jω) dominates the circuit performance. Increasing Rf does the following: Application Division CLC446 Operation The CLC446 has a current-feedback architecture built in an advanced complementary bipolar process. The key features of current-feedback are: • • • • • • Decreases loop-gain • Decreases bandwidth • Lowers pulse response overshoot • Reduces gain peaking • Affects frequency response phase linearity CLC446 Design Information The following topics will supply you with: • Design parameters, formulas and techniques • Interfaces • Application circuits • Layout techniques • SPICE model information DC Gain (non-inverting) The non-inverting DC voltage gain for the configuration shown in Figure 1 is AC bandwidth is independent of voltage gain Unity-gain stability Frequency response may be adjusted with Rf High slew rate Low variation in performance for a wide range of gains, signal levels and loads • Fast settling Current-feedback operation can be explained with a simple model. The voltage gain for the circuits in Figure 1 and Figure 2 is approximately: where: • • • • AV is the DC voltage gain Rf is the feedback resistor The normalized gain plots in the Typical Performance Characteristics section show different feedback resistors (Rf) for different gains. These values of Rf are recommended for obtaining the highest bandwidth with minimal peaking. The resistor Rt provides DC bias for the non-inverting input. For AV < 5, use linear interpolation on the nearest AV values to calculate the recommended value of Rf. For AV ≥5, the minimum recommended Rf is 200Ω. Select Rg to set the DC gain: Z(jω) is the CLC446’s open-loop transimpedance gain is the loop-gain 7 www.national.com CLC446 Application Division The normalized gain plots in the Typical Performance Characteristics section show different feedback resistors (Rf) for different gains. These values of Rf are recommended for obtaining the highest bandwidth with minimal peaking. The resistor Rt provides DC bias for the non-inverting input. (Continued) DC gain accuracy is usually limited by the tolerance of Rf and Rg. For |AV| < 5, use linear interpolation on the nearest AV values to calculate the recommended value of Rf. For |AV| ≥ 5, the minimum recommended Rf is 200Ω. Select Rg to set the DC gain: At large gains, Rg becomes small and will load the previous stage. This can be solved by driving Rg with a low impedance buffer like the CLC111, or increasing Rf and Rg. See the AC Design (small signal bandwidth) sub-section for the tradeoffs. DC gain accuracy is usually limited by the tolerance of Rf and Rg. DC Gain (transimpedance) DS012730-29 Figure 3 shows a transimpedance circuit where the current Iin is injected at the inverting node. The current source’s output resistance is much greater than Rf. The DC transimpedance gain is: FIGURE 1. Non-Inverting Gain DC Gain (unity gain buffer) The recommended Rf for unity gain buffers is 453Ω. Rg is left open. Parasitic capacitance at the inverting node may require a slight increase of Rf to maintain a flat frequency response. DC Gain (inverting) The inverting DC voltage gain for the configuration shown in Figure 2 is AV = − Rf/Rg The recommended Rf is 453Ω. Parasitic capacitance at the inverting node may require a slight increase of Rf to maintain a flat frequency response. DC gain accuracy is usually limited by the tolerance of Rf. DS012730-30 FIGURE 2. Inverting Gain DS012730-32 FIGURE 3. Transimpedance Gain www.national.com 8 The DC offset model shown in Figure 6 is used to calculate the output offset voltage. The equation for output offset voltage is: (Continued) DC Design (level shifting) Figure 4 shows a DC level shifting circuit for inverting gain configurations. Vref produces a DC output level shift of The current offset terms, IBN and IBI, do not track each other. The specifications are stated in terms of magnitude only. Therefore, the terms Vos,IBN, and IBI can have either polarity. Matching the equivalent resistance seen at both input pins does not reduce the output offset voltage. which is independent of the DC output produced by VIN. Rt Vin Rg Vref Rref IBN + Vo CLC446 Req1 Rf + Vos - IBI + CLC446 Rf Vo RL DS012730-24 FIGURE 4. Level Shifting Circuit Req2 DC Design (single supply) Figure 5 is a typical single supply circuit. R1 and R2 from a voltage divider that sets the non-inverting input DC voltage. This circuit has a DC gain of 1. A low frequency zero is set by Rg and C2. The coupling capacitor C1 isolates its DC bias point from the previous stage. Both capacitors make high pass response; high frequency gain is determined by Rf and Rg. DS012730-28 FIGURE 6. DC Offset Model DC Design (output loading) RL, Rf, and Rg load the op amp output. The equivalent load seen by the output in Figure 6 is: RL(eq) = RLi (Rf+Req2), non-inverting gain RL(eq) = RL i Rf, inverting gain VCC VCC R1 Vin + C1 RL(eq) needs to be large enough so that the minimum output current can produce the required output voltage swing. AC Design (small signal bandwidth) The CLC446 current-feedback amplifier bandwidth is a function of the feedback resistor (Rf), not of the DC voltage gain (AV). The bandwidth is approximately proportional to Vo CLC446 R2 Rf As a rule, if Rf doubles, the bandwidth is cut in half. Other AC specifications will also be degraded. Decreasing Rf from the recommended value increases peaking, and for very small values of Rf oscillation will occur. Rg C2 AC Design (minimum slew rate) Slew rate influences the bandwidth of large signal sinusoids. To determine an approximate value of slew rate necessary to support a large sinusoid, use the following equation: SR ≅5 x f x Vpeak DS012730-25 FIGURE 5. Single Supply Circuit The complete gain equation for the circuit in Figure 5 is: where Vpeak is the peak output sinusoidal voltage. The slew rate of the CLC446 in inverting gains is always higher than in non-inverting gains. AC Design (linear phase/constant group delay) The recommended value of Rf produces minimal peaking and a reasonably linear phase response. To improve phase linearity when |Av| < 5, increases Rf approximately 50% over its recommended value. Some adjustment of Rf may be needed to achieve phase linearity for your application. See the AC Design (small signal bandwidth) a sub-section for other effects of changing Rf. where s = jω τ1 = (R11\R1) x C1 τ2 = Rg x C2 DC Design (DC offsets) 9 www.national.com CLC446 Application Division CLC446 Application Division In non-inverting gain applications, Rg is connected directly to ground. The resistors R1, R2, R6, and R7 are equal to the characteristic impedance, Z0 of the transmission line or cable. Use R3 to isolate the amplifier from reactive loading caused by the transmission line, or by parasitics. (Continued) Propagation delay is approximately equal to group delay. Group delay is related to phase by this equation: In inverting gain applications, R3 is connected directly to ground. The resistor R4, R6, and R7 are equal to Z0. The parallel combination of R5 and Rg is also equal to Z0. where θ(f) is the phase in degrees. Linear phase implies constant group delay. The technique for achieving linear phase also produces a constant group delay. AC Design (peaking) Peaking is sometimes observed with the recommended Rf. If a small increase in Rf does not solve the problem, then investigate the possible causes and remedies listed below. The input and output matching resistors attenuate the signal by a factor of 2, therefore additional gain is needed. Use C6 to match the output transmission line over a greater frequency range. It compensates for the increase of the op amp’s output impedance with frequency. Thermal Design To calculate the power dissipation for the CLC446, follow these steps: 1. Calculate the no-load op amp power: Pamp = ICC (VCC-VEE) j Capacitance across Rf –Do not place a capacitor across Rf –Use a resistor with low parasitic capacitance for Rf j A capacitive load 2. Calculate the output stage’s RMS power: Po = (VCC - Vload) Iload, where Vload and Iload are the RMS voltage and current across the external load. 3. Calculate the total op amp RMS power: Pt = Pamp + Po –Use a series resistor between the output and a capacitive load (see the Recommended Rs vs. CL plot) j Long traces and/or lead lengths between Rf and the CLC446 –Keep these traces as short as possible For non-inverting and transimpedance gain configurations: To calculate the maximum allowable ambient temperature, solve the following equation: Tamb = 150 − Pt θJA where θJA is the thermal resistance from junction to ambient in ˚C/W, and Tamb is in ˚C. The Package Thermal Resistance section contains the thermal resistance for various packages. Dynamic Range (input/output protection) ESD diodes are present on all connected pins for protection from static voltage damage. For a signal that may exceed the supply voltages, we recommend using diode clamps at the amplifier’s input to limit the signals to less than the supply voltages. Dynamic Range (input/output levels) The Electrical Characteristics section specifies the Common-Mode Input Range and Output Voltage Range; these voltage ranges scale with the supplies. Output Current also specified in the Electrical Characteristics section. Unity gain applications are limited by the Common-Mode Input Range. At greater non-inverting gains, the Output Voltage Range becomes the limiting factor. Inverting gain applications are limited by the Output Voltage Range. For transimpedance gain applications, the sum of the input currents injected at the inverting input pin of the op amp needs to be: j Extra capacitance between the inverting pin and gound (Cg) –See the Printed Circuit Board Layout sub-section below for suggestions on reducing Cg –Increase Rf if peaking is still observed after reducing Cg For inverting gain configurations: j Inadequate ground plane at the non-inverting pin and/or long traces between non-inverting pin and grouns –Place a 50 to 100Ω resistor between the non-inverting pin and ground (see Rt in Figure 2) Capacitive Loads Capacitive loads, such as found in A/D converters, require a series resistor (Rs) in the output to improve settling performance. The Recommended Rs vs. CL plot in the Typical Performance Characteristics section provides the information for selecting this resistor. Using a resistor in series with a reactive load will also reduce the load’s effect on amplifier loop dynamics. For instance, driving coaxial cables without an output series resistor may cause peaking or oscillation. Transmission Line Matching One method for matching the characteristic impedance of a transmission line is to place the appropriate resistor at the input or output of the amplifier. Figure 7 shows the typical circuit configurations for matching transmission lines. where Vmax is the Output Voltage Range (see the DC Gain (transimpedance) sub-section for details. The equivalent output load needs to be large enough so that the minimum output current can produce the required output voltage swing. See the DC Design (output loading ) sub-section for details. Dynamic Range (noise) In RF applications, noise is frequently specified as Noise Figure (NF). This allows the calculation of signal to noise ratio into a defined load. Figure 8 plots the NF for a CLC446 at a gain of 10, and with a feedback resistor Rf of 100Ω. The minimum NF (3.9dB) occurs when the source impedance equals 1600Ω. DS012730-12 FIGURE 7. Transmission Line Matching www.national.com 10 Dynamic Range (distortion) (Continued) The distortion plots in the Typical Performance Characteristics section show distortion as a function of load resistance, frequency, and output amplitude. Distortion places an upper limit on the CLC446’s dynamic range. Realized output distortion is highly dependent upon the external circuit. Some of the common external circuit choices that can improve distortion are: • Short and equal return paths from the load to the supplies • • • De-coupling capacitors of the correct value • • • Use a ground plane • tantalum capacitors of about 6.8µF for large signal current swings or improved power supply noise rejection; we recommend a minimum of 2.2 µF for any circuit • Minimize trace and lead lengths for components between the inverting and output pins • Remove ground plane underneath the amplifier package and 0.1” (3mm) from all input/output pads Higher load resistance A lower ratio of the output voltage swing to power supply voltage Printed Circuit Board Layout High Frequency op amp performance is strongly dependent on proper layout, proper resistive termination and adequate power supply decoupling. The most important layout points to follow are: DS012730-13 FIGURE 8. Noise Figure vs. Source Resistance Bypass power supply pins with: ceramic capacitors of about 0.1µF placed less than 0.1” (3mm) from the pin • For prototyping, use flush-mount printed circuit board pins; never use high profile DIP sockets Evaluation Board Separate evaluation boards are available for prototyping and measurements. Additional information is available in the evaluation board literature. Low Noise Composite Amp With Input Matching The composite amp shown in Figure 10 eliminates the need for a matching resistor to ground at the input. By connecting two amplifiers in series, the first non-inverting and the second inverting, an overall inverting gain is realized. The feedback resistor (Rf) closes the loop, and generates a set input resistance (Rin) that can be matched to Rs. Rf generates less noise than a matching resistor to ground at the input. DS012730-33 FIGURE 9. Noise Model The CLC446 noise model in Figure 9 is used to develop this equation for NF: where: • • • Rs is the source resistance at the non-inverting input There is no matching resistor from the input to ground eni, ibn, and ibi are the voltage and current noise density terms (see the Electrical Characteristics section) • • Rf is the feedback resistor, and Rg is the gain-setting resistor To achieve a low Noise Figure while matching the source, use a matching transformer or the Low Noise Composite Amp With Input Matching circuit found in the CLC446 Applications section. DS012730-46 FIGURE 10. Composite Amplifier The input resistance and DC voltage gain of the amplifier are: 11 www.national.com CLC446 Application Division CLC446 Application Division Filter type = Elliptic (Continued) Filter order (n) = 3 Passband ripple = 0.18dB Minimum stopband attenuation (Amin)= 37.44dB Cutoff frequency = 10MHz (at 0.18dB attenuation) These choices produce the following results: -3dB frequency = 12.7MHz Stopband corner frequency = 29.3MHz 2. Find the pole and zero locations. Reference gave the following for our filter: Pole 1: α = 0.38621 Pole 2: αo = 0.88668 Match the source resistance by setting: RinR = s. The voltage noise produced by Rf, referred to the source Vs is: Zero 1: β = 1.13897 Zero 2: ω∞ = 3.3505 3. Denormalize the frequency by multiplying by the cutoff frequency (ωo) in radians/second. For our filter we have: The noise of a simple input matching resistor connected to ground can be calculated by setting G to 0 in this equation. Thus, this circuit reduces the thermal noise power produced by the matching resistor by a factor of (1+G). Rectifier Circuit Wide bandwidth rectifier circuits have many applications. Figure 11 shows a 200MHz wideband full-wave rectifier circuit using a CLC446 and a CLC522 amplifier. Schottky or PIN diodes are used for D1 and D2. They produce an active half-wave rectifier whose signals are taken at the feedback diode connection. The CLC522 takes the difference of the two half-wave rectified signals, producing a full-wave rectifier. The CLC522 is used at a gain of 5 to achieve high differential bandwidth. For best high frequency performance, maintain low parasitic capacitance from the diodes D1 and D2 to ground, and from the input of the CLC522 to ground. Cutoff frequency: ωo = 2π(10MHz) = 62.832 x 106rad/s Pole 1: α' = ωoα = 24.266 x 106rad/s Pole 2: αo' = ωoαo = 55.712 x 106rad/s Zero 1: β' = ωoβ = 21.052 x 106rad/s Zero 2: ω∞' = ωoω∞ = 71.564 x 106rad/s 4. Calculate these intermediate coefficients used in Reference . For this design, a = 0.64226, b = 7.7612 and c = 75.556 x 106. 5. Set the following resistance and capacitance scaling factors: R = an arbitrary value C = an arbitrary value We chose C = 47pF and R = 1.00kΩ 6. Calculate the capacitor, resistor and gain (K) values using these equations: DS012730-14 FIGURE 11. Full-Wave Rectifier Elliptic Low-pass, Anti-aliasing Filter Elliptic filters are often used in anti-aliasing applications. If there is noise or undesired signals at frequencies above 1/2 the sampling rate of an A/D converter, then these signals are aliased down into the operating frequency range, degrading the signal of interest. To filter out these undesired signal components, place a low pass filter in front of the A/D converter. The Typical Application depicted on the front page is a 10MHz, third-order elliptic filter. It has a voltage-controlled, voltage source (VCVS) topology using a CLC446. To calculate the component values for this filter, do the following: 1. Select the filter approximation function for your application (see References ). For this design we choose: www.national.com 12 CLC446 Application Division (Continued) For this design, the calculated values are: C1 = 47pF, C2 = 91pF, C3 = C4 = 23.5pF, C5 = 17.95pF, R1 = R2 = 202.1Ω, R3 = 101.1Ω, R4 = 3190Ω, R5 = 1000Ω and K = 4.928. 7. Select the feedback resistor (Rf) and gain setting resistor (Rg values to obtain a non-inverting voltage gain of AV = K. See the DC Gain (non-inverting) sub-section for details on selecting these values. Figure 12 shows the ideal response of this filter. Some methods to bring actual performance closer to this ideal are: • Compensate for op amp delay effects (pre-distortion) • Adjust for parasitic capacitances in the layout • Use components with small tolerances • Add trim capacitors DS012730-15 FIGURE 12. Ideal Elliptic Filter Frequency Response References  Anatol I. Zverev, Handbook of FILTER SYNTHESIS, John Wiley & Sons 1967, p. 177  Arthur B. Williams and Fred J. Taylor, Electronic Filter Design Handbook, McGraw Hill, 1995, pp. 3-29 to 3-31. 13 www.national.com CLC446 Physical Dimensions inches (millimeters) unless otherwise noted 8-Pin SOIC NS Package Number M08A 8-Pin MDIP NS Package Number N08E www.national.com 14 CLC446 400MHz, 50mW Current-Feedback Op Amp Notes LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: [email protected] www.national.com National Semiconductor Europe Fax: +49 (0) 180-530 85 86 Email: [email protected] Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: [email protected] National Semiconductor Japan Ltd. Tel: 81-3-5639-7560 Fax: 81-3-5639-7507 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.