CLC505 High Speed, Programmable Supply Current, Monolithic Op Amp General Description For more information, visit http://www.national.com/mil The CLC505 is a monolithic, high speed op amp with a unique combination of high performance, low power consumption, and flexibility of application. The supply current is programmable over a 10 to 1 continuous range with a single resistor, Rp. This feature enables the amplifier to be used in a wide variety of high performance applications. Typical performance at any supply current is exceptional: Features Parameter Supply Current (ICC) 9mA Units 3.4mA 1mA −3dB Bandwidth 150 100 50 MHz Settling Time 12 14 35 nsec Slew Rate 1700 1200 n 10mW power consumption with 50MHz BW n Single resistor programming of supply current n 3.4mA ICC provides 100MHz bandwidth and 14ns settling (0.05%) n Fast disable capability n 0.04% differential gain at ICC = 3.4mA n 0.06% differential phase at ICC = 3.4mA Applications n 800 V/µsec n Output Current 45 25 7 mA n n The CLC505’s combination of high performance, low power n consumption, and large signal performance makes the CLC505 ideal for a wide variety of remote site equipment applications, such as battery powered test instrumentation and communications gear. Some other power applications are video switching matrices, ATE, and phased-array radar systems. The CLC505 has been designed for ease of use and has been specified to ensure design confidence and final system predictability. The product performance is specified for 1mA, 3mA ad 9mA supply current. The CLC505 is available in 8-pin Dip SOIC packages offered for the industrial temperature range. Enhanced Solutions (Military/Aerospace) SMD Number: contact factory Space level versions also available. Low power battery applications Remote site instrumentation Mobile communications gear Video switching matrix Phased-array radar Large-Signal Pulse Response DS012755-37 Connection Diagram DS012755-33 Pinout DIP & SOIC Ordering Information Package Temperature Range Industrial Part Number Package Marking NSC Drawing 8-pin plastic DIP −40˚C to +85˚C CLC505AJP CLC505AJP N08E 8-pin plastic SOIC −40˚C to +85˚C CLC505AJE CLC505AJE M08A © 2001 National Semiconductor Corporation DS012755 www.national.com CLC505 High Speed, Programmable Supply Current, Monolithic Op Amp January 2001 CLC505 Absolute Maximum Ratings (Note 1) Junction Temperature Operating Temperature Storage Temperature Range Lead Solder Duration (+300˚C) ESD rating (human body model) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. ± 7V Supply Voltage (VCC) IOUT Output is short circuit protected to ground, but maximum reliability will be maintained if IOUT does not exceed... Common Mode Input Voltage Differential Input Voltage +150˚C −40˚C to +85˚C −65˚C to +150˚C 10 sec 2000V Operating Ratings Thermal Resistance (SOIC) θJC θJA 60mA ± VCC 10V 60˚C/W 140˚C/W Electrical Characteristics AV = +6, VCC = ± 5V, Rf = 1000Ω, Cp = 100pF; unless specified Symbol Parameter Ambient Temperature Conditions CLC505AJ Typ Max/Min Ratings (Note 2) Units +25˚C −40˚C +25˚C +85˚C VOUT < 2VPP 150 VOUT < 5VPP 135 > 115 > 95 > 100 > 80 MHz -3dB Large Signal > 115 > 95 Gain Flatness VOUT < 2VPP < 0.4 < 0.6 < 1.0 < 1.0 < 0.3 < 0.5 < 1.0 < 1.0 < 0.4 < 0.6 < 1.3 < 1.2 dB < 3.0 < 3.7 < 16 < 3.0 < 3.7 < 16 < 3.5 < 4.4 < 16 < 15 > 1000 < 12 > 1200 < 15 > 1200 < −45 < −55 < −45 < −55 dBc Frequency Domain Response SSBW LSBW -3dB Bandwidth GFPL Peaking GFPH Peaking GFR Rolloff LPD Linear Phase Deviation < 25/20/10MHz (Note 7) > 25/20/10MHz (Note 7) < 50/40/20MHz (Note 7) 0.2 DC to 50/40/20MHz (Note 7) 0.6 0 0 MHz dB dB deg Time Domain Response TRS Rise and Fall Time TRL 2V Step 2.3 5V Step 2.6 TSP Settling time to 0.1/0.05/0.05% (Note 7) 2V Step 12 OS Overshoot 2V Step 5 SR Slew Rate (AV +2) 1700 ns ns ns % V/µs Distortion And Noise Response HD2 HD3 2nd Harmonic Distortion 2VPP,20/10/5MHz (Note 7) −50 3rd Harmonic Distortion 2VPP,20/10/5MHz (Note 7) −65 < −40 < −55 −156 < −154 < −154 < −153 dBm (1Hz) 50 < 65 < 65 < 70 µV dBc Equivalent Input Noise SNF Noise Floor > 1MHz INV Integrated Noise 1MHz to 200/200/100MHz (Note 7) DG Differential Gain (Note 6) 0.04 - - - % DP Differential Phase (Note 6) 0.06 - - - deg < ± 12.8 < ± 50 < ± 8.0 < ± 14 < ± 50 mV µV/˚C < ± 36 < ± 225 < ± 18 < ± 18 < ± 100 nA/˚C < ± 60 < ± 275 < ± 38 - < ± 40 < ± 125 nA/˚C > 45 > 45 > 48 > 48 > 45 > 45 Static, DC Performance VIO Input Offset Voltage (Note 3) 2 DVIO Average Temperature Coefficient 30 IBN Input Bias Current (Note 3) DIBN Average Temperature Coefficient IBI Input Bias Current (Note 3) DIBI Average Temperature Coefficient 80 PSRR Power Supply Rejection Ratio 50 CMRR Common Mode Rejection Ratio 50 www.national.com Non Inverting 8 80 Inverting 10 2 - - µA µA dB dB CLC505 Electrical Characteristics (Continued) AV = +6, VCC = ± 5V, Rf = 1000Ω, Cp = 100pF; unless specified Symbol Parameter Conditions Typ Max/Min Ratings (Note 2) Units Static, DC Performance ICC Supply Current (Note 3) No Load, Quiescent 9 < 11 < 11 < 12 mA 1200 > 400 <2 < 1.2 > ± 2.8 > ± 1.5 > ± 20 > 800 <2 < 0.3 > ± 3.0 > ± 1.8 > ± 36 > 1600 <2 < 0.2 > ± 3.0 > ± 2.0 > ± 36 kΩ Miscellaneous Performance RIN Non-Inverting Input Resistance CIN Capacitance 1 RO Output Impedence At DC VO Output Voltage Range No Load 0.2 CMIR Common Mode Input Range For Rated Performance IO Output Current −40˚C to +85˚C ± 3.3 ± 2.2 ± 45 pF ohm V V mA Electrical Characteristics AV = +6, VCC = ± 5V, Rf = 1000Ω, CP = 100pF; unless specified SUPPLY CURRENT ICC (TYP) = 3.4mA Rp =100kΩ, RL = 500Ω Symbol Typ SUPPLY CURRENT ICC (TYP) = 1mA Rp = 300kΩ, RL =1000Ω Max & Min Ratings Typ Max & Min Ratings Units +25˚C −40˚C +25˚C +85˚C +25˚C −40˚C +25˚C +85˚C SSBW 100 > 65 > 40 < 0.3 < 0.5 < 1.3 < 1.2 < 5.4 < 8.8 < 22 < 12 > 800 < −45 < −55 < −152 > 30 80 > 80 > 50 < 0.2 < 0.4 < 1.0 < 1.0 < 4.4 < 7.0 < 22 < 10 > 800 < −45 < −55 < −153 50 LSBW 33 –1 0 7 < 0.2 < 0.3 < 1.0 < 0.5 < 12 9 –1 35 −152 < 70 <8 > 500 < −40 < −55 < −150 > 35 > 20 < 0.1 < 0.2 < 1.0 < 0.5 < 10 < 18 < 60 <5 > 600 < −45 < −55 < −150 > 30 > 18 < 0.2 < 0.3 < 1.3 < 1.0 < 12 < 20 < 60 <8 > 600 < −45 < −55 < −149 HD3 −65 SNF −155 > 80 > 50 < 0.3 < 0.5 < 1.0 < 1.0 < 4.4 < 7.0 < 22 < 12 > 700 < −40 < −55 < −153 INV 56 < 70 < 70 < 80 55 < 70 < 70 < 80 µV DG 0.04 – – – 0.1 – – – % deg GFPL 0 GFPH 0 GFR 0.2 LPD 0.5 TRS 3.5 TRL 4.4 TSP 14 OS 2 SR 1200 HD2 −55 0 0.5 0.2 0 800 −55 −65 DP 0.06 – – – 0.1 – – – VIO 3 < ± 7.0 IBN 2 DIBN 30 IBI 4 DIBI 40 PSRR 50 CMRR 50 ICC 3.4 RIN 3000 CIN 1 RO 0.2 VO ± 3.3 ± 2.2 < ± 13.0 < ± 75 < ± 5.0 < ± 32 < ± 10.0 < ± 38 > 45 > 45 < 1.4 > 2500 <2 < 3.0 > ± 2.5 > ± 1.5 < ± 7.0 40 < ± 13 < ± 60 < ±6 < ± 50 < ± 15 < ± 60 > 45 > 45 < 4.2 > 4000 <2 < 0.2 > ± 3.0 > ± 2.0 3 DVIO < ± 11.8 < ± 60 < ± 12 < ± 75 < ± 22 < ± 100 > 45 > 45 < 3.8 > 1000 <2 < 1.6 > ± 2.8 > ± 1.5 < ± 14.5 < ± 75 < ± 2.5 < ± 30 < ± 8.0 < ± 35 > 45 > 45 < 1.4 > 10000 <2 < 0.5 > ± 3.0 > ± 2.0 CMIR – < ±6 – < ± 14 – > 48 > 48 < 3.8 > 2000 <2 < 0.5 > ± 2.7 > ± 1.8 50 1 10 2 20 50 50 1.0 7500 1 0.5 ± 3.3 ± 2.2 3 – < ± 2.5 – < ± 7.0 – > 48 > 48 < 1.3 > 5000 <2 < 1.0 > ± 3.0 > ± 1.8 MHz MHz dB dB dB deg ns ns ns % V/µs dBc dBc dBm (1Hz) mV µV/˚C µA nA/˚C µA nA/˚C dB dB mA kΩ pF Ω V V www.national.com CLC505 Electrical Characteristics (Continued) AV = +6, VCC = ± 5V, Rf = 1000Ω, CP = 100pF; unless specified SUPPLY CURRENT ICC (TYP) = 3.4mA Rp =100kΩ, RL = 500Ω IO IO ± 25 ± 25 > ± 10 > ±9 > ± 18 > ± 18 SUPPLY CURRENT ICC (TYP) = 1mA Rp = 300kΩ, RL =1000Ω > ± 18 > ± 18 ±7 ±7 > ± 3.0 > ± 2.5 > ±5 > ±5 > ±5 > ±5 mA mA Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation. Note 2: Max/min ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined from tested parameters. Note 3: AJ-level: spec. is 100% tested at +25˚C = 3.4mA & parameter is 100% @ 25˚C in die form @ ICC = 1mA, 3.4mA and 9mA. Note 4: Not applicable due to output current limitations. Note 5: See Text on the back page of data sheet. Note 6: Differential gain and phase is characterized with a 1VPP equivalent video signal, 0-100 IREPP, 40IREpp, and 0IRE = 0V at the load resistor and 3.58 MHz. Note 7: xx/yy/zz MHz indicates that the CLC505 is specified at xxMHz for ICC = 9mA, yyMHz for Icc = 3.4mA, and zzMHz for Icc = 1 mA. Conditions are different for the three supply currents: ICC RL ROUT AV 9mA 3.4mA 75Ω 75Ω +2 500Ω 0Ω 1mA +6 1000Ω 0Ω +6 Typical Performance Characteristics (TA = 25˚C, AV = +6, VCC = ± 5V, Rf = 1000Ω, VH = +3V, Cp = 100pF) ICC 9mA, RL 250Ω Non-Inverting Gain Circuit ICC 3.4mA, RL 500Ω Non-Inverting Gain Circuit DS012755-1 www.national.com DS012755-2 4 (TA = 25˚C, AV = +6, VCC = ± 5V, Rf = 1000Ω, VH = +3V, Cp = 100pF)) (Continued) ICC 1mA, RL 1000Ω Non-Inverting Gain Circuit Inverting Frequency Response DS012755-4 DS012755-3 Inverting Frequency Response Inverting Frequency Response DS012755-5 Large Signal Frequency Response DS012755-6 Large Signal Frequency Response DS012755-7 DS012755-8 5 www.national.com CLC505 Typical Performance Characteristics CLC505 Typical Performance Characteristics (TA = 25˚C, AV = +6, VCC = ± 5V, Rf = 1000Ω, VH = +3V, Cp = 100pF)) (Continued) Large Signal Frequency Response Equivalent Input Noise DS012755-9 DS012755-10 Equivalent Input Noise Equivalent Input Noise DS012755-11 CMRR and PSRR DS012755-12 CMRR and PSRR DS012755-13 www.national.com DS012755-14 6 (TA = 25˚C, AV = +6, VCC = ± 5V, Rf = 1000Ω, VH = +3V, Cp = 100pF)) (Continued) CMRR and PSRR ICC 9mA, RL 250Ω 2nd Harmonic Distortion DS012755-15 ICC 34mA, RL 500Ω 2nd Harmonic Distortion DS012755-16 ICC 1mA, RL 1000Ω 2nd Harmonic Distortion DS012755-17 3rd Harmonic Distortion DS012755-18 3rd Harmonic Distortion DS012755-19 DS012755-20 7 www.national.com CLC505 Typical Performance Characteristics CLC505 Typical Performance Characteristics (TA = 25˚C, AV = +6, VCC = ± 5V, Rf = 1000Ω, VH = +3V, Cp = 100pF)) (Continued) 3rd Harmonic Distortion Bandwidth vs. Load Capacitance DS012755-22 DS012755-21 Bandwidth vs. Load Capacitance Bandwidth vs. Load Capacitance DS012755-23 Recommended RS vs. Load Capacitance DS012755-24 Recommended RS vs. Load Capacitance DS012755-25 www.national.com DS012755-26 8 (TA = 25˚C, AV = +6, VCC = ± 5V, Rf = 1000Ω, VH = +3V, Cp = 100pF)) (Continued) Recommended RS vs. Load Capacitance Settling Time DS012755-27 DS012755-28 Settling Time Settling Time DS012755-29 ICC 9mA, RL 250Ω Small-Signal Pulse Response DS012755-30 ICC 34mA, RL 500Ω Small-Signal Pulse Response DS012755-34 DS012755-35 9 www.national.com CLC505 Typical Performance Characteristics CLC505 Typical Performance Characteristics (TA = 25˚C, AV = +6, VCC = ± 5V, Rf = 1000Ω, VH = +3V, Cp = 100pF)) (Continued) ICC 1mA, RL 1000Ω Small-Signal Pulse Response Large-Signal Pulse Response DS012755-37 DS012755-36 Large-Signal Pulse Response Large-Signal Pulse Response DS012755-38 I CC vs. RP DS012755-39 I CC vs. IP DS012755-40 DS012755-41 www.national.com 10 (TA = 25˚C, AV = +6, VCC = ± 5V, Rf = 1000Ω, VH = +3V, Cp = 100pF)) (Continued) Bandwidth vs. ICC Maximum Output Current vs. ICC DS012755-42 DS012755-43 Offset Voltage vs. ICC Slew Rate vs. ICC DS012755-45 DS012755-44 Non-Inverting Bias Current vs. ICC Inverting Bias Current vs. ICC DS012755-46 DS012755-47 11 www.national.com CLC505 Typical Performance Characteristics CLC505 Typical Performance Characteristics (TA = 25˚C, AV = +6, VCC = ± 5V, Rf = 1000Ω, VH = +3V, Cp = 100pF)) (Continued) Differential Gain and Phase vs. Load DS012755-48 Application Information DS012755-32 FIGURE 2. Recommended Inverting Gain Circuit Description The CLC505 is a programmable-supply current, current-feedback operational amplifier. Supply current and consequently dynamic performance can be easily adjusted by selecting the value of a single external resistor (Rp). DS012755-31 FIGURE 1. Recommended Non-Inverting Gain Circuit www.national.com 12 Rp is connected from pin 8 to −VCC and VCC =+/−3V. Now calculate Rp under new conditions: (Continued) Selecting an Operating Point Rp =[(+VCC−1.6V)−(−VCC)]/Ip The operating point is determined by the supply current, which in turn is determined by current (Ip) flowing out of pin 8. As the supply current is reduced the following effects will be observed: Rp =[(+3V−1.6V)−(−3V)]/26µA Specification Bandwidth Rise TIme Rp =169kΩ The CLC505 will have performance similar to Rp = 300kΩ shown on the datasheet, but with 40% less power dissipation due to the reduced supply voltages. (The op amp will also have a more restricted common-mode range and output swing.) This calculation is approximate and a prudent design would include substantial performance margin for max/min limits. Dynamic Shutdown Capability The CLC505 may be powered on and off very quickly by controlling the voltage applied to Rp. If Rp is connected between pin 8 and the output of a CMOS gate powered from ± 5V supplies, the gate can be used to turn the amplifier on and off. This is shown in Figure 3 below: Effect as ICC Decreases Decreases increases Output Drive Decreases Input Bias Current Decreases Input Impedance Increases (see source impedance discussion) Both the specification pages and the plot pages illustrate these effects to help make the supply current vs. performance tradeoff. Performance is specified and tested at ICC =1mA, 3.4mA, and 9mA as indicated in the datasheet. (Note some test conditions and especially the load resistance are different for the three supply current settlings.) The performance plots show typical performance for all three supply currents levels. When making the supply current vs. performance tradeoff, it is first a good idea to see if one of the standard operating points (ICC = 9mA, 3.4mA, or 1mA) fits the application. If it does, performance guaranteed on the specification pages will apply directly to your application. In addition, the value of Rp may be obtained directly from the specification page. The following discussion will assist in selecting ICC for applications that cannot operate at one of the specified supply current settlings. Use the typical performance plots for critical specifications to select the best ICC. Now interpolate between the values of ICC in the plots & specification tables to estimate the max/min values in the application. From the selected value of ICC the “programming current” (Ip) may be easily calculated: IP =ICC/39 DS012755-49 FIGURE 3. Dynamic Control of Power Consumption When the gate output is switched from high to low, the CLC505 will turn on. In the off state, the supply current typically reduces to 0.2mA or less. The speed with which the CLC505 turns on or off is limited by the capacitance at pin 8. To improve switching time, a speed up capacitor from the gate output to pin 8 is recommended. The value of this capacitor will depend on the total capacitance connected to pin 8 and is best established experimentally. Turn-on and turn-off times of 100ns to 200ns are achievable with ordinary CMOS gates. Example: An open collector logic device is used to dynamically control the power dissipation of the circuit. Here, the desired connection for Rp is from pin 8 to the open collector logic device. The plot of ICC vs Ip in the plot pages shows this relationship graphically. Knowing Ip leads to a direct calculation of Rp. Rp = [(+VPP−1.6)−Vn]/ Ip Rp =8.4/Ip (for +VCC =+5V and Vn =−5V) Vn is the voltage externally applied to Rp. (Throughout the data sheet and in most applications, Vn and −VCC are −5V.) The term (+VCC−1.6V) is the voltage at pin 8. DS012755-50 Now standard VCC, VEE and Rp does not have to be connected to −VCC. In applications where non-standard supply voltages are used or when there is a need to power down the op amp via digital logic control. The value of Rp is adjusted accordingly. First, an operating point needs to be determined from the plots & specifications as discussed above. From this, Ip is obtained. Ip, in concert with the available Vn determines Rp. Example An application requires that VCC = ± 3V and performance in the 1mA operating point range. The required Ip can therefore be determined as follows: Ip =26µA FIGURE 4. Controlling Power on State with TTL Logic When the logic gate goes low, the CLC505 is turned on. Performance desired is that given for ICC = 3.4mA under standard conditions. From the ICC vs. Ip plot, Ip = 84µA. Then calculating Rp: Rp =[(+VCC−1.6V)−(V n)]/Ip Rp =[(+5V−1.6V)−(0)]84µA Rp =40kΩ 13 www.national.com CLC505 Application Information CLC505 Application Information At ICC = 1mA and ICC = 3.4mA, the CLC505 is less capable of driving a 150Ω load due to output current limitations. For this reason lighter loads are used and the termination resistor is omitted. The gain and load resistance for ICC = 3.4mA are AV = +6 and RL = 500Ω and for ICC = 1mA; AV = +6 and RL = 1kΩ. (Continued) Slew Rate The rapid turn on and off ability of the CLC505 is not recommended for signal isolation applications (such as multiplexing). While the power dissipation of the amplifier drops in the off state, the amplifier may still have some gain at low frequencies. Causing feed through in multiplex application. The performance desired is that given for ICC = 3.4mA under standard conditions. From the ICC vs. Ip plot, Ip =84µA. Is obtained now calculating Rp: Slew rate limiting is a nonlinear response which occurs in amplifiers when the output voltage swing cannot change as rapidly as the applied input signal. The CLC505 has been designed to avoid slew rate limiting in most circuit configurations. The large signal (5VPP) bandwidth of 80MHz at ICC = 3.4mA, is only slightly less than the 100MHz small signal bandwidth. The result is a low distortion, linear system for both small and large signals over the required system frequency range. The CLC505 reaches slew rate limits only for small non-inverting gains. In other words, slew rate limiting is constrained by common mode voltage swings at the input. The large signal frequency response plot at a gain of +2 was a break in the response, which indicates that a slew rate limit has been reached. Note also that the frequency response plots at a gain of +21 for large and small signal responses are nearly identical. Differential Gain and Phase Differential gain and phase are measurements useful primarily in composite video channels. They are measured by monitoring the gain and phase changes of a high frequency carrier (3.58MHz typically) as the output of the amplifier is swept over a range of DC voltages. Specifications for the CLC505 include differential gain and phase. Test signals based on a 1VPP video level. Test conditions used are the following: DC sweep range: 0 to 100 IRE units (black to white) Carrier: 3.58MHz at 40 IRE units peak to peak The amplifier conditions are significantly different for the three values of supply current specified. At ICC = 9mA, the amplifier is specified for a gain of +2 and 150Ω load (for a backmatched 75Ω system). IRE amplitudes at ICC = 9mA, are referred to the 75Ω load resistor. www.national.com Source Impedance For best results, source impedance in the non-inverting circuit configuration (see Figure 1) should be kept below 5kΩ. Above 5kΩ it is possible for oscillation to occur, depending on other circuit board parasitics. For high signal source impedances, a resistor with a value of less than 5kΩ may be used to terminate the non-inverting input to ground. Feedback Resistor In current-feedback op amps, the value of the feedback resistor plays a major role in determining amplifier dynamics. It is important to select the correct value. The CLC505 provides optimum performance with a 1kΩ feedback resistor. Selection of an incorrect value can lead to severe rolloff in frequency response, (if the resistor value is too large) or peaking or oscillation, (if the value is too low.) Printed Circuit Layout As with any high frequency device, a good PCB layout will enhance performance. Ground plane construction and good power supply bypassing close to the package are critical to achieving full performance. In the non-inverting configuration, the amplifier is sensitive to stray capacitance to ground at the inverting input. Hence, the inverting node connections should be small with minimal coupling to the ground plane. Shunt capacitance across the feedback resistor should not be used to compensate for this effect. Precision buffed resistors (PRP8351 series from Precision Resistive Products) with low parasitic reactances were used to develop the data sheet specifications. Precision carbon composition resistors will also yield excellent results. Standard spirally-trimmed RN55D metal film resistors will work with a slight decrease in bandwidth due to their reactive nature at high frequencies. Evaluation PC boards (part number 730013 for through-hole and 730027 for SOIC) for the CLC505 are available. 14 CLC505 Physical Dimensions inches (millimeters) unless otherwise noted 8-Pin SOIC NS Package Number M08A 8-Pin MDIP NS Package Number N08E 15 www.national.com CLC505 High Speed, Programmable Supply Current, Monolithic Op Amp Notes LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 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