a FEATURES Pin Compatible 12-Bit and 10-Bit Versions 12-Bit/10-Bit 6 MSPS A/D Converter Integrated Triple Correlated Double Sampler 3-Channel, 2 MSPS Color Mode 13 – 43 Analog Programmable Gain Amplifier Pixel-Rate Digital Gain Adjustment Pixel-Rate Digital Offset Adjustment Internal Voltage Reference No Missing Codes Guaranteed Microprocessor-Compatible Control Interface +3.3 V/+5 V Digital I/O Compatibility Low Power CMOS: 500 mW 64-Pin PQFP Surface Mount Package Complete 12-Bit/10-Bit 6 MSPS CCD/CIS Signal Processors AD9807/AD9805 FUNCTIONAL BLOCK DIAGRAM PIXEL PIXEL OFFSET GAIN VREF AD9807/AD9805 VINR GAIN REGISTERS RED CDS 8-10 12-10 PGA REF GREEN 12-10 VING CDS VINB PGA MUX – ADC X DOUT CSB BLUE CDS PGA INPUT OFFSET ODD EVEN RD MPU MPU PORT PORT CONFIG REGS WR A2 A1 A0 CDSCLK1 CDSCLK2 PRODUCTION DESCRIPTION The AD9807 and AD9805 are complete CCD/CIS imaging decoders and signal processors on a single monolithic integrated circuit. The input of the AD9807/AD9805 allows direct ac coupling of the charge-coupled device (CCD) or contact image sensor (CIS) output(s). The AD9807/AD9805 includes all the circuitry to perform three-channel correlated double sampling (CDS) and programmable gain adjustment of the CCD output; a 12-bit or 10-bit analog-to-digital converter (ADC) quantizes the analog signal. After digitization, the on-board digital signal processor (DSP) circuitry allows pixel rate offset and gain correction. The DSP also corrects odd/even CCD register imbalance errors. A parallel control bus provides a simple interface to 8-bit microcontrollers. The AD9807/AD9805 comes in a space saving 64-pin plastic quad flatpack (PQFP) and is specified over the commercial (0°C to +70°C) temperature range. By disabling the CDS, the AD9807/AD9805 are also suitable for non-CCD applications, or applications that do not require CDS, such as CIS signal processing. PRODUCT HIGHLIGHTS The AD9807/AD9805 offers a complete, single chip CCD imaging front end in a 64-pin plastic quad flatpack (PQFP). ADCCLK On-Chip CDS—An integrated 3-channel correlated double sampler allows easy ac coupling directly from the CCD sensor outputs. Additionally, the CDS reduces low frequency noise and reset feedthrough. On-Chip Voltage Reference—The AD9807/AD9805 includes a 2 V bandgap reference that allows the input range of the device to be configured for input spans up to 4 V. 6 MSPS A/D Converter—A highly linear 12-bit or 10-bit A/D converter sequentially digitizes the red, green and blue CDS outputs ensuring no missing code performance. The user may also configure the AD9807/AD9805 for single channel operation. Digital Gain & Offset Correction—Pixel rate digital gain and offset correction blocks allow precise repeatable correction of imaging system error sources. Digital I/O Compatibility—The AD9807/AD9805 offers +3.3 V/+5 V logic level compatibility. Pin-Compatible 12-Bit and 10-Bit Versions—The AD9807 is also offered in a pin-compatible 10-bit version, the AD9805, allowing upgrade-ability and simplifying design issues across different scanner models. On-Chip PGA—The AD9807/AD9805 includes a 3-channel analog programmable gain amplifier; it is programmable from 1× to 4× in 16 increments. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 World Wide Web Site: http://www.analog.com Fax: 617/326-8703 © Analog Devices, Inc., 1997 AD9807–SPECIFICATIONS ANALOG SPECIFICATIONS (TMIN to TMAX with AVDD = +5.0 V, DVDD = +5.0 V, fADCCLK = 6 MSPS, fCDSCLK1 = 2 MSPS, fCDSCLK2 = 2 MSPS, PGA Gain = 1 unless otherwise noted) Parameter Min RESOLUTION CONVERSION RATE 3-Channel Mode With CDS 1-Channel Mode With CDS1 DC ACCURACY Integral Nonlinearity (INL)2 Differential Nonlinearity (DNL)2 No Missing Codes Unipolar Offset Error (@ +25°C) Gain Error (@ +25°C) 12 Typ Max Bits 6 6 1.5 0.4 MSPS MSPS 0.75 12 0.4 1.2 ANALOG INPUTS Full-Scale Input Span Input Limits3 Input Capacitance Input Bias Current Input Referred Noise 0.0625 AVSS – 0.3 V PSRR (AVDD = +5 V ± 0.25 V) INTERNAL VOLTAGE REFERENCE 1 V Output Tolerance (@+25°C) 2 V Output Tolerance (@+25°C) POWER SUPPLIES Operating Voltages AVDD DVDD Operating Current AVDD DVDD POWER CONSUMPTION TEMPERATURE RANGE Operating Units 4 AVDD + 0.3 LSB LSB Bits Guaranteed % FSR % FSR 10 0.01 0.3 V p-p V pF µA LSB rms 0.06 % FSR +4.75 +4.75 73 16.6 450 0 ± 15 ± 30 mV mV +5.25 +5.25 V V 86 20 530 mA mA mW +70 °C NOTES 1 Blue and green channels. Red channel conversion rate for 1-channel mode is 5 MSPS. 2 Measured with 4 V p-p input range. 3 Input signals exceeding these limits are subject to excessive overvoltage recovery times. Specifications subject to change without notice. (TMIN to TMAX with AVDD = +5.0 V, DVDD = +5.0 V, fADCCLK = 6 MSPS, fCDSCLK1 = 2 MSPS, fCDSCLK2 = 2 MSPS, DIGITAL SPECIFICATIONS C = 20 pF, unless otherwise noted) L Parameter Symbol Min LOGIC INPUTS High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Capacitance VIH VIL IIH IIL CIN 2.0 LOGIC OUTPUTS High Level Output Voltage (IOH = 50 µA) High Level Output Voltage (IOH = 0.5 mA) Low Level Output Voltage (IOL = 50 µA) Low Level Output Voltage (IOL = –0.6 mA) Output Capacitance VOH VOH VOL VOL COUT 4.5 2.4 Typ Max 0.8 10 10 10 4.9 0.1 0.4 5 Units V V µA µA pF V V V V pF Specifications subject to change without notice. –2– REV. 0 AD9805–SPECIFICATIONS ANALOG SPECIFICATIONS AD9807/AD9805 (TMIN to TMAX with AVDD = +5.0 V, DVDD = +5.0 V, fADCCLK = 6 MSPS, fCDSCLK1 = 2 MSPS, fCDSCLK2 = 2 MSPS, PGA Gain = 1 unless otherwise noted) Parameter Min RESOLUTION CONVERSION RATE 3-Channel Mode With CDS 1-Channel Mode With CDS1 DC ACCURACY Integral Nonlinearity (INL)2 Differential Nonlinearity (DNL)2 No Missing Codes Unipolar Offset Error (@ +25°C) Gain Error (@ +25°C) 10 Typ Max Bits 6 6 MSPS MSPS 1.0 0.5 10 0.6 1.2 ANALOG INPUTS Full-Scale Input Span Input Limits3 Input Capacitance Input Bias Current Input Referred Noise 0.0625 AVSS – 0.3 V PSRR (AVDD = +5 V ± 0.25 V) INTERNAL VOLTAGE REFERENCE 1 V Output Tolerance (@ +25°C) 2 V Output Tolerance (@ +25°C) POWER SUPPLIES Operating Voltages AVDD DVDD Operating Current AVDD DVDD POWER CONSUMPTION TEMPERATURE RANGE Operating Units 4 AVDD + 0.3 LSB LSB Bits Guaranteed % FSR % FSR 10 0.01 0.1 V p-p V pF µA LSB rms 0.06 % FSR +4.75 +4.75 73 16.6 450 0 ± 15 ± 30 mV mV +5.25 +5.25 V V 86 20 530 mA mA mW +70 °C NOTES 1 Blue and green channels. Red channel conversion rate for 1-channel mode is 5 MSPS. 2 Measured with 4 V p-p input range. 3 Input signals exceeding these limits are subject to excessive overvoltage recovery times. Specifications subject to change without notice. (TMIN to TMAX with AVDD = +5.0 V, DVDD = +5.0 V, fADCCLK = 6 MSPS, fCDSCLK1 = 2 MSPS, fCDSCLK2 = 2 MSPS, DIGITAL SPECIFICATIONS C = 20 pF, unless otherwise noted) L Parameter Symbol Min LOGIC INPUTS High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Capacitance VIH VIL IIH IIL CIN 2.0 LOGIC OUTPUTS High Level Output Voltage (IOH = 50 µA) High Level Output Voltage (IOH = 0.5 mA) Low Level Output Voltage (IOL = 50 µA) Low Level Output Voltage (IOL = –0.6 mA) Output Capacitance VOH VOH VOL VOL COUT 4.5 2.4 Max 0.8 10 10 10 4.9 0.1 0.4 5 Specifications subject to change without notice. REV. 0 Typ –3– Units V V µA µA pF V V V V pF AD9807/AD9805 TIMING SPECIFICATIONS (T MIN to TMAX with AVDD = +5.0 V, DVDD = +5.0 V, unless otherwise noted) Parameter Symbol Min CLOCK PARAMETERS 3-Channel Conversion Rate 1-Channel Conversion Rate CDSCK1 Pulse Width CDSCK1 Pulse Width CDSCK2 Pulse Width CDSCK2 Pulse Width CDS Clocks Digital Quiet Time CDSCK2 Falling to CDSCK1 Rising CDSCK2 Falling to CDSCK1 Rising CDSCK1 Falling to CDSCK2 Rising CDSCK1 Falling to CDSCK2 Rising ADCCLK Rising to CDSCK1 Falling ADCCLK Pulse Width ADCCLK Period ADCCLK Period (Red Single Channel Mode) 3-Channel Settling Time 1-Channel Settling Time (B and G Only) ADCCLK Rising to Control Data Setup ADCCLK Rising to Control Data Hold STRTLN Rising, Falling Setup STRTLN Rising, Falling Hold Aperture Delay tCRA tCRB tC1A tC1B tC2A tC2B tQ tC2C1A tC2C1B tC1C2A tC1C2B tC1AD tACLK tCP tCP2 tSTL1 tSTL2 tGOS tGOH tS tH tAD 500 166 30 30 30 30 20 80 40 20 20 35 50 166 200 60 30 15 15 15 15 10 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns REGISTER WRITE/READ Address Setup Time Address Hold Time Data Setup Time Data Hold Time Chip Select Setup Time Chip Select Hold Time Write Pulse Width Read Pulse Width Read To Data Valid tAS tAH tDS tDH tCSS tCSH tPWW tPWR tDD 15 15 15 15 15 15 25 50 40 ns ns ns ns ns ns ns ns ns tOD tEDV tHZ 15 5 DATA OUTPUT Output Delay 3-State to Data Valid Output Enable High to 3-State Latency Typ Max 15 Units ns ns ns ADCCLK Cycles 6 Table I. Output Controls CSB RDB WRB OEB 0 0 0 x 0 0 1 x 0 1 0 0 DOUT X Q X MPU 0 1 0 1 0 1 1 0 0 1 1 1 1 x x 0 1 x x 1 D X MPU Z Q Z ADC LEGEND: x = Don't Care X = Unknown (Not Recommended) Q = Outputs D = Inputs Z = 3-State –4– REV. 0 AD9807/AD9805 DVSS DVDD A2 A1 GAIN<1> GAIN<0> GAIN<3> GAIN<2> GAIN<5> GAIN<4> GAIN<7> GAIN<6> GAIN<9> GAIN<8> GAIN<11> GAIN<10> PIN CONFIGURATION 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 AVDD 1 AVSS 2 CAPT 3 A0 DOUT<11> 46 DOUT<10> 48 PIN 1 IDENTIFIER 47 CAPT 4 CAPB 5 45 44 CAPB 6 VREF 7 42 DOUT<7>/MPU<7> DOUT<6>/MPU<6> 41 DRVDD 43 AD9807 CML 8 VINR 9 TOP VIEW (Not to Scale) DOUT<9> DOUT<8> DRVSS DOUT<5>/MPU<5> 38 DOUT<4>/MPU<4> 40 AVSS 10 VING 11 39 AVSS 12 37 VINB 13 AVSS 14 AVDD 15 36 DOUT<3>/MPU<3> DOUT<2>/MPU<2> DOUT<1>/MPU<1> DOUT<0>/MPU<0> 33 OEB 35 34 STRTLN 16 WRB DVSS DVDD CSB RDB OFFSET<1> OFFSET<0> OFFSET<4> OFFSET<3> OFFSET<2> OFFSET<5> ADCCLK OFFSET<7> OFFSET<6> CDSCLK1 CDSCLK2 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PIN DESCRIPTIONS Pin No. Pin Name Type Description 1, 15 2, 10, 12, 14 3, 4 5, 6 7 8 9 11 13 16 17 18 19 28, 52 29, 51 20 21–26 27 30 31 32 33 34 35–39, 42 40 41 43 44–46 47 48, 49, 50 53 54–63 64 AVDD AVSS CAPT CAPB VREF CML VINR VING VINB STRTLN CDSCLK1 CDSCLK2 ADCCLK DVSS DVDD OFFSET<7> OFFSET<6:1> OFFSET<0> CSB RDB WRB OEB DOUT<0>/MPU<0> DOUT<1:6>/MPU<1:6> DRVSS DRVDD DOUT<7>/MPU<7> DOUT<8:10> DOUT<11> A0, A1, A2 GAIN<0> GAIN<1:10> GAIN<11> P P AO AO AO AO AI AI AI DI DI DI DI P P DI DI DI DI DI DI DI DIO DIO P P DIO DO DO DI DI DI DI +5 V Analog Supply. Analog Ground. Reference Decoupling. See Figure 22. Reference Decoupling. Internal Reference Output. Decouple with 10 µF + 0.1 µF. Internal Bias Voltage. Decouple with 0.1 µF. Analog Input, Red. Analog Input, Green. Analog Input, Blue. STRTLN. Indicates beginning of scan line. CDS Reset Clock Pulse Input. CDS Data Clock Pulse Input. A/D Sample Clock Input. Digital Ground. +5 V Digital Supply. Pixel Rate Offset Coefficient Inputs. Most Significant Bit. Pixel Rate Offset Coefficient Inputs. Pixel Rate Offset Coefficient Inputs. Least Significant Bit. Chip Select. Active Low. Read Strobe. Active Low. Write Strobe. Active Low. Output Enable. Active Low. Data Output LSB/Register Input LSB Data Outputs/Register Inputs. Digital Driver Ground Digital Driver Supply Data Output/Register Input MSB. Data Outputs. Data Output MSB. Register Select Pins. Pixel Rate Gain Coefficient Input. LSB. Pixel Rate Gain Coefficient Inputs. Pixel Rate Gain Coefficient Input. MSB. TYPE: AI = Analog Input; AO = Analog Output; DI = Digital Input; DO = Digital Output; DIO = Digital Input/Output; P = Power. REV. 0 –5– AD9807/AD9805 DVSS DVDD A2 A1 NC NC GAIN<1> GAIN<0> GAIN<3> GAIN<2> GAIN<5> GAIN<4> GAIN<7> GAIN<6> GAIN<9> GAIN<8> PIN CONFIGURATION 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 AVDD 1 A0 DOUT<9> 46 DOUT<8> 48 PIN 1 IDENTIFIER AVSS 2 CAPT 3 CAPT 4 47 45 CAPB 5 44 CAPB 6 VREF 7 42 DOUT<5>/MPU<7> DOUT<4>/MPU<6> 41 DRVDD 43 AD9805 CML 8 VINR 9 TOP VIEW (Not to Scale) DOUT<7> DOUT<6> DRVSS DOUT<3>/MPU<5> 38 DOUT<2>/MPU<4> 40 AVSS 10 VING 11 39 AVSS 12 37 VINB 13 AVSS 14 AVDD 15 36 DOUT<1>/MPU<3> DOUT<0>/MPU<2> 35 MPU<1> 34 MPU<0> 33 OEB STRTLN 16 WRB DVSS DVDD CSB RDB OFFSET<1> OFFSET<0> OFFSET<4> OFFSET<3> OFFSET<2> OFFSET<5> ADCCLK OFFSET<7> OFFSET<6> NC = NO CONNECT CDSCLK1 CDSCLK2 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PIN DESCRIPTIONS Pin No. Pin Name Type Description 1, 15 2, 10, 12, 14 3, 4 5, 6 7 8 9 11 13 16 17 18 19 28, 52 29, 51 20 21–26 27 30 31 32 33 34 35 36 37–39, 42 40 41 43 44–46 47 48, 49, 50 53, 54 55 56–63 64 AVDD AVSS CAPT CAPB VREF CML VINR VING VINB STRTLN CDSCLK1 CDSCLK2 ADCCLK DVSS DVDD OFFSET<7> OFFSET<6:1> OFFSET<0> CSB RDB WRB OEB MPU<0> MPU<1> DOUT<0>/MPU<2> DOUT<1:4>/MPU<3:6> DRVSS DRVDD DOUT<5>/MPU<7> DOUT<6:8> DOUT<9> A0, A1, A2 NC GAIN<0> GAIN<1:8> GAIN<9> P P AO AO AO AO AI AI AI DI DI DI DI P P DI DI DI DI DI DI DI DIO DIO DIO DIO P P DIO DO DO DI +5 V Analog Supply. Analog Ground. Reference Decoupling. See Figure 22. Reference Decoupling. Internal Reference Output. Decouple with 10 µF + 0.1 µF. Internal Bias Voltage. Decouple with 0.1 µF. Analog Input, Red. Analog Input, Green. Analog Input, Blue. STRTLN. Indicates beginning of scan line. CDS Reset Clock Pulse Input. CDS Data Clock Pulse Input. A/D Sample Clock Input. Digital Ground. +5 V Digital Supply. Pixel Rate Offset Coefficient Inputs. Most Significant Bit. Pixel Rate Offset Coefficient Inputs. Pixel Rate Offset Coefficient Inputs. Least Significant Bit. Chip Select. Active Low. Read Strobe. Active Low. Write Strobe. Active Low. Output Enable. Active Low. Register Input-Output LSB. Register Input-Output. Data Output LSB/Register Input-Output. Data Output/Register Input-Output. Digital Driver Ground. Digital Driver Supply. Data Output/Register Input-Output MSB. Data Outputs. Data Output MSB. Register Select Pins. No Connection. Pixel Rate Gain Coefficient Input LSB. Pixel Rate Gain Coefficient Inputs. Pixel Rate Gain Coefficient Input MSB. DI DI DI TYPE: AI = Analog Input; AO = Analog Output; DI = Digital Input; DO = Digital Output; DIO = Digital Input/Output; P = Power. –6– REV. 0 AD9807/AD9805 ABSOLUTE MAXIMUM RATINGS* With Respect to Parameter AVDD AVSS AVSS AVDD DVDD DVSS AGND DVSS AVDD DVDD Clock Input DVSS Digital Outputs DVSS AIN, VREF AVSS Junction Temperature Storage Temperature Lead Temperature (10 sec) DEFINITIONS OF SPECIFICATIONS INTEGRAL NONLINEARITY Min Max Units –0.5 –6.5 –0.5 –0.3 –6.5 –0.5 –0.5 –0.3 +6.5 +0.5 +6.5 +0.3 +6.5 DVDD + 0.5 AVDD + 0.3 AVDD + 0.3 +150 +150 +300 Volts Volts Volts Volts Volts Volts Volts Volts °C °C °C –65 *Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. ORDERING GUIDE Model Temperature Range Package Description Package Option* AD9807JS AD9805JS 0°C to +70°C 0°C to +70°C PQFP PQFP S-64 S-64 *S = Plastic Quad Flatpack. Linearity error refers to the deviation of each individual code from a line drawn from “negative full scale” through “positive full scale.” The point used as “negative full scale” occurs 1/2 LSB before the first code transition. “Positive full scale” is defined as a level 1 1/2 LSB beyond the last code transition. The deviation is measured from the middle of each particular code to the true straight line. DIFFERENTIAL LINEARITY ERROR (DNL, NO MISSING CODES) An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Thus every code must have a finite width. Guaranteed no missing codes to 12-bit resolution indicates that all 4096 codes, respectively, must be present over all operating ranges. UNIPOLAR OFFSET ERROR In the unipolar mode, the first transition should occur at a level 1/2 LSB above analog common. Unipolar offset is defined as the deviation of the actual from that point. The unipolar offset temperature coefficient specifies the maximum change of the transition point over temperature, with or without external adjustments. GAIN ERROR The last transition should occur for an analog value 1 1/2 LSB below the nominal full scale. Gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between first and last code transitions. POWER SUPPLY REJECTION Power Supply Rejection specifies the maximum full-scale change from the initial value with the supplies at the various limits. APERTURE DELAY Aperture delay is a timing measurement between the sampling clocks and the CDS. It is measured from the falling edge of the CDSCLK2 input to when the input signal is held for conversion in CDS mode. In non-CDS mode, it is the falling edge of CDSCLK1. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9807/AD9805 feature proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. 0 –7– WARNING! ESD SENSITIVE DEVICE AD9807/AD9805 ANALOG INPUTS R0, G0, B0 tAD R1, G1, B1 Rn, Gn, Bn tAD STRTLN tC1C2A tC1A tCRA tC2C1A tS tH CDSCLK1 tC2A tC1AD CDSCLK2 tSTL1 tACLK tACLK ADCCLK R G B R G B R G tCP2 GAIN<n:0> OFFSET<m:0> R0 G0 B tGOH tGOS B0 R1 G1 B1 Figure 1a. 3-Channel CDS-Mode Clock Timing ANALOG INPUTS R0, G0, B0 R1, G1, B1 Rn, Gn, Bn (0V) tAD STRTLN tCRA tC2A tS tH CDSCLK1 tACLK tACLK tSTL1 ADCCLK tCP tGOS tGOH GAIN<n:0> OFFSET<m:0> Figure 1b. 3-Channel SHA-Mode Clock Timing ANALOG INPUTS PIXEL 0 tAD PIXEL 1 PIXEL n tAD STRTLN tC1B tC1C2B tCRB tC2C1B tS tH CDSCLK1 tC2B CDSCLK2 tACLK tACLK tSTL2 ADCCLK tGOS tCP GAIN<n:0> OFFSET<m:0> G0 tGOH G2 G1 Figure 1c. 1-Channel CDS-Mode Clock Timing (for B and G Only) –8– REV. 0 AD9807/AD9805 ANALOG INPUTS PIXEL 0 tAD PIXEL 1 PIXEL n tAD STRTLN tC1B tC1C2B tCRB tC2C1B tS tH CDSCLK1 tC2B CDSCLK2 tC1AD tACLK tACLK tSTL1 ADCCLK tCP2 GAIN<n:0> OFFSET<m:0> tGOS G0 G1 tGOH G2 Figure 1d. 1-Channel CDS-Mode Clock Timing (Red Channel) ANALOG INPUTS R0, G0, B0 R1, G1, B1 Rn, Gn, Bn (0V) tAD STRTLN tC2B tCRB tS tH CDSCLK1 tACLK tSTL2 tACLK ADCCLK tCP GAIN<n:0> OFFSET<m:0> tGOH tGOS G0 G2 G1 Figure 1e. 1-Channel SHA-Mode Clock Timing (for Blue and Green Channels) ANALOG INPUTS R0, G0, B0 R1, G1, B1 Rn, Gn, Bn (0V) tAD STRTLN tC2B tCRB tS tH tSTL1 CDSCLK1 tACLK tACLK ADCCLK tCP2 GAIN<n:0> OFFSET<m:0> tGOS G0 G1 Figure 1f. 1-Channel SHA-Mode Clock Timing (Red Channel) REV. 0 –9– tGOH AD9807/AD9805 ANALOG INPUTS R0, G0, B0 R1, G1, B1 Rn, Gn, Bn STRTLN CDSCLK1 tQ CDSCLK2 tQ tQ R ADCCLK G B R G B R G B tGOH tQ tGOS GAIN<n:0> OFFSET<m:0> R0 G0 B0 R1 G1 B1 Figure 1g. CDS Clocks Digital Quiet Time OEB CSB tAS tAH A0, A1, A2 tCSS tCSH WRB tPWW MPU<7:0> tDS tDH Figure 2. Write Timing CSB tAS tAH A0, A1, A2 tCSH RDB tPWR tCSS tDH MPU<7:0> tDD Figure 3. Read Timing –10– REV. 0 AD9807/AD9805 OFFSET<M:0> VREF AD9807/AD9805 RED VINR GAIN<N:0> PGA CDS BANDGAP REFERENCE 8-10 12-10/10-8 OEB I/O GREEN DIGITAL 12 VING 12-BIT/10-BIT A/D MUX PGA CDS 3 12 DIGITAL 12 – X SUBTRACTOR MULTIPLIER DOUT<11:0>/MPU<7:0> INPUT OFFSET REGISTER VINB BLUE CONFIGURATION REGISTER PGA CDS R G B CDSCLK1 12 8 CSB R RODD REVEN G GODD GEVEN B BODD BEVEN RDB MPU PORT WRB A2 CONFIGURATION REGISTER 2 A1 A0 CDSCLK2 STRTLN ADCCLK Figure 4. Block Diagram 7 6 5 4 3 2 1 0 REGISTER OVERVIEW MPU Port Map Table II shows the MPU Port Map. The MPU Port Map is accessed through pins A0, A1 and A2 of the AD9807/AD9805, and provides the decoding scheme for the various registers of the AD9807/AD9805. When writing or reading from any of the registers, the appropriate bits must be applied to A0–A2. 8X FULL SCALE 4X FULL SCALE 2X FULL SCALE 10-BIT GAIN, 10-BIT OFFSET 11-BIT GAIN, 9-BIT OFFSET 12-BIT GAIN, 8-BIT OFFSET COLOR0 Table II. MPU Port Map Format A2 A1 A0 Register 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Configuration Register Configuration Register 2 PGA Gain Register Odd Offset Register Even Offset Register Input Offset Register RESERVED Bayer Mode Configuration Register/AD9807 The Configuration Register controls three functions: a color pointer, gain and offset pin configurations, and digital gain scaling. Figure 5 shows the AD9807 Configuration Register. Bits 0–2 control the digital scaling function. Setting a bit makes the corresponding condition true. Resetting Bits 0–2 disables and bypasses the digital multiplier. Bits 3–5 control the gain and offset pin distribution. Resetting Bits 3–5 disables and bypasses the digital subtracter and sets the gain word width to 12. Setting any bit makes the corresponding condition true. For example, if Bit 3 is set, the 2 LSBs of the gain word become the 2 MSBs of the offset word. If Bit 4 is set, the LSB of the gain word becomes MSB of the offset word. Bits 6 and 7 direct register data written to the MPU<7:0> bus to the appropriate red, green or blue register. COLOR1 Figure 5. AD9807 Configuration Register Format Configuration Register/AD9805 The Configuration Register controls three functions: a color pointer, gain and offset pin configurations, and digital gain scaling. Figure 6 shows the AD9805 Configuration Register. Bits 0–2 control the digital scaling function. Setting a Bit makes the corresponding condition true. Resetting Bits 0–2 disables and bypasses the digital multiplier. Bits 3–5 control the gain and offset pin distribution. Resetting Bits 3–5 disables and bypasses the digital subtracter and sets the gain word width to 10. Setting any bit makes the corresponding condition true. If Bit 3 is set, the 2 LSBs of the gain word become the 2 MSBs of the offset word. If Bit 4 is set, the LSB of the gain word becomes MSB of the offset word. Bits 6 and 7 direct register data written to the MPU<7:0> bus to the appropriate red, green or blue register. 7 6 5 4 3 2 1 0 8X FULL SCALE 4X FULL SCALE 2X FULL SCALE 8-BIT GAIN, 10-BIT OFFSET 9-BIT GAIN, 9-BIT OFFSET 10-BIT GAIN, 8-BIT OFFSET COLOR0 COLOR1 Figure 6. AD9805 Configuration Register Format REV. 0 –11– AD9807/AD9805 Input Offset Registers Color Pointer Both the AD9807 and the AD9805 use Bits 6 and 7 in the Configuration Register to direct data to the corresponding internal registers. Table III shows the mapping of Bits 6 and 7 to their corresponding color. The Input Offset Registers control the amount of analog offset applied to the analog inputs prior to the PGA portion of the AD9807/AD9805; there is one Input Offset Register for each color. Figure 8 shows the Input Offset Register format. The offset range may be varied between –80 mV and 20 mV. The data format for the Input Offset Registers is straight binary coding. An all “zeros” data word corresponds to –80 mV. An all “ones” data word corresponds to 20 mV. The offset is variable in 256 steps. The contents of the color pointer in the Configuration Register at the time an Input Offset Register is written indicates the color for which that offset setting applies. Table III. Color Pointer Map Bit 7 Bit 6 Color Register 0 0 1 1 0 1 0 1 Red Green Blue RESERVED 7 Configuration Register 2 Configuration Register 2 controls several functions: color/black and white selection, CDS enabling, A/D Reference Control and Input Clamp Mode. Figure 7 shows the AD9807 and AD9805 Configuration Register 2 format. Setting Bit 0 enables the three internal CDS blocks of the AD9807/AD9805. Resetting Bit 0 disables the internal CDS blocks, configuring the part for SHA operation. Setting Bit 1 places the AD9807/AD9805 in single-channel (black & white) mode. In this mode, only one of the three input channels is used. The color bits in the configuration register at the time of the last write indicate the particular channel used. Resetting Bit 1 places the AD9807/AD9805 in color mode and all three input channels are enabled. Bits 2-4 control the full-scale input span of the A/D. Setting Bit 2 results in a 4 V p-p input span. Setting Bit 3 results in a 2 V p-p full-scale input span. Setting Bit 4 results in a full-scale span set by an external reference connected to the VREF pin of the AD9807/ AD9805 (Full Scale = 2 × VREF). Resetting Bits 2, 3 or 4 disables that particular mode. Bits 6 and 7 select the desired clamp mode (see Figure 17). Table IV shows the truth table for clamp mode functionality. Line clamp mode allows control of the input switch (S1) via CDSCLK1 only while STRTLN is reset. Pixel clamp mode allows control of the input switch (S1) via CDSCLK1 regardless of the state of STRTLN. No clamp mode disables the input switch (S1) regardless of the selected mode of CDS operation. Bit 6 Clamp Mode 0 0 1 1 0 1 0 1 Line Clamp Pixel Clamp No Clamp RESERVED 5 4 3 2 1 0 ANALOG OFFSET (LSB) ANALOG OFFSET ANALOG OFFSET ANALOG OFFSET ANALOG OFFSET ANALOG OFFSET ANALOG OFFSET ANALOG OFFSET (MSB) Figure 8. Input Offset Registers Format PGA Gain Registers Bits 0–3 of the PGA Gain Registers control the amount of gain applied to the analog inputs prior to the A/D conversion portion of the AD9807/AD9805; there is one PGA Gain Register for each channel. Figure 9 shows the PGA Gain Register format. The gain range may be varied between 1 and 4. The data format for the PGA Gain Registers is straight binary coding. An all “zeros” data word corresponds to an analog gain of 1. An all “ones” data word corresponds to an analog gain of 4. The gain is variable in 16 steps (see Figure 16). The contents of the color pointer in the Configuration Register at the time a PGA Gain Register is written indicates the color for which that gain setting applies. Bits 4–7 of the PGA Gain Registers are reserved. Table IV. Clamp Mode Truth Table Bit 7 6 7 6 5 4 3 2 1 0 PGA0 PGA1 PGA2 PGA3 RESERVED RESERVED 7 6 5 4 3 2 1 RESERVED 0 RESERVED Figure 9. PGA Gain Registers Format CDSEN BLACK & WHITE ADC FULL SCALE = 4V ADC FULL SCALE = 2V EXTERNAL REFERENCE SET TO 0 CLAMP MODE SELECT CLAMP MODE SELECT Figure 7. AD9807/AD9805 Configuration Register 2 Format Odd, Even Offset Registers The Odd and Even Offset Registers provide a means of digitally compensating the odd and even offset error (Register Imbalance) typical of multiplexed CCD imagers; there is one Odd and one Even Offset Register for each color. Figure 10 shows the AD9807/AD9805 Odd and Even Offset Register Formats. The data format for the Odd and Even Offset Registers is twos complement. The offsets may be varied between positive –12– REV. 0 AD9807/AD9805 127 LSBs and negative 128 LSBs. The offset is variable in 1 LSB increments (see Table V). The contents of the color pointer in the Configuration Register at the time an Odd or Even Register is written indicates the color for which that offset setting applies. 7 6 5 4 3 2 1 0 O/E OFFSET (LSB) O/E OFFSET O/E OFFSET O/E OFFSET O/E OFFSET O/E OFFSET O/E OFFSET O/E OFFSET (MSB) Figure 10. Odd and Even Offset Registers Format Table V. Odd/Even Offset Register Coding Odd/Even Register Contents Offset Value 0111 1111 . . . 0000 0001 0000 0000 1111 1111 . . . 1000 0000 +127 LSB . . . +1 LSB 0 LSB –1 LSB . . . –128 LSB DATA BUSES GAIN<n:0>—The GAIN data bus gives the user access to the internal digital multiplier. Data from the GAIN bus is latched into the appropriate internal registers in accordance with the timing shown in Figure 1. Note that the GAIN data must be valid on the rising edges of ADCCLK. The contents of the register become one multiplicand of the digital multiplier; the output data from the digital subtracter is the other multiplicand. The AD9807/AD9805 provide a variable word length for the GAIN data word. Based on the setting in the Configuration Register, the GAIN data word may be 10, 11 or 12 bits wide (8, 9 or 10 bits wide for the AD9805). The data format for the GAIN data bus is straight binary coding. An all “zeros” data word always corresponds to a gain setting of 1×. An all “ones” data word corresponds to a gain setting dependent on Bits 0–2 of the Configuration Register. The gain is variable in 1024, 2048, or 4096 (256, 512 or 1024 for the AD9805) increments depending on the width of GAIN data word. OFFSET<m:0> The OFFSET data bus gives the user access to the internal digital subtracter. Data from the OFFSET bus is latched into the appropriate internal registers in accordance with the timing shown in Figure 1. Note that the OFFSET data must be valid on the rising edges of ADCCLK. The contents of the register become the subtrahend; the output data from the A/D converter REV. 0 (after odd/even correction) is the other input. The AD9807/ AD9805 provide a variable word length for the OFFSET data word. Based on the setting in the Configuration Register, the OFFSET data word may be 8, 9 or 10 bits wide. The data format for the OFFSET data bus is straight binary coding. An all “zeros” data word corresponds to an offset value of 0 LSBs. An all “ones” data word subtracts an offset value of 256, 512 or 1024 LSBs, depending on the width of OFFSET data word. The offset is variable in 256, 512 or 1024 increments. DOUT<n:0>—The DOUT data bus is bidirectional. CMOS compatible digital data is available as an output on the DOUT bus. Data is coded in straight binary format. When CSB and either WRB or RDB are applied to the AD9807/AD9805, the DOUT data bus becomes an input/output port for the register data, shown as MPU<7:0>. The timing and latency for the DOUT data bus are given in Figures 11 through 15. FUNCTIONAL OVERVIEW It is possible to operate the AD9807/AD9805 in one of five modes: 3-Channel Operation with CDS, 3-Channel SHA Operation, 1-Channel Operation with CDS, 1-Channel SHA Operation and 2-Channel Bayer Mode. A description of each of the five modes follows. 3-Channel Operation with CDS This mode of the AD9807/AD9805 enables simultaneous sampling of a triple output CCD. The CCD waveforms are ac coupled to the VINR, VING and VINB pins of the AD9807/ AD9805 where they are automatically biased at an appropriate voltage level using the on-chip clamp; the inputs may alternatively be dc coupled if they have already been appropriately level shifted. The internal CDSs take two samples of the incoming pixel data: the first samples (CDSCLK1) are taken during the reset time while the second samples (CDSCLK2) are taken during the video, or data, portion of the input pixels. The offsets of the three input channels are modified by the values stored in the input offset registers. The voltage differences of the reset levels and video levels are inverted and amplified by the PGAs; the settings in the corresponding PGA Gain Registers determine the gains of the PGAs. These outputs from the PGAs are then routed through a high speed multiplexer to a 12-bit A/D converter (10-bit for AD9805) for digitization; the multiplexer cycles between the red, green and then blue channels. After digitization, the data is modified by the amount indicated in the Odd and Even Offset Registers. A digital subtracter allows additional pixel rate offset modification of each color based on the values written to the OFFSET data bus. Finally, a digital multiplier allows pixel rate gain modification of each color based on the values written to the GAIN data bus. Latency for the red, green and blue channels is 6 ADCCLK cycles (9 cycles for the gain and offset bus; see Figure 12). The STRTLN signal indicates the first red, green and blue pixels in a scan line, and the red channel is always the first pixel digitized. The state of STRTLN is evaluated on the rising edges of ADCCLK. When STRTLN is low, the internal circuitry is reset on the next rising edge of ADCCLK; the multiplexer is switched to the red channel and the odd/even circuitry is configured to expect even pixels. After STRTLN goes high, the first set of pixels is assumed to be even. Consecutive sets of pixels (red, green and blue) are assumed to alternate between odd and even pixel sets. –13– AD9807/AD9805 3-Channel SHA Operation This mode of the AD9807/AD9805 enables 3-channel simultaneous sampling; it differs from the CDS sampling mode in that the CDS functions are replaced with sample-and-hold amplifiers (SHAs). CDSCLK1 becomes the sample-and-hold clock; CDSCLK2 is tied to ground. The input is sampled on the falling edge of CDSCLK1. The input signals must be either dc coupled and level shifted, or dc restored prior to driving the VINR, VING, and VINB pins of the AD9807/AD9805 (clamp mode must be disabled). The input signal in this mode is ground-referenced. The offsets of the three input channels are modified by the values stored in the input offset registers. The part does not invert the input signals prior to amplification by the PGAs; the settings in the corresponding PGA Gain Registers determine the gains of the PGAs. These outputs from the PGAs are then routed through a high speed multiplexer to a 12-bit A/D converter (10-bit for AD9805) for digitization; the multiplexer cycles between the red, green and then blue channels. After digitization, the data is modified by the amount indicated in the Odd and Even Offset Registers. A digital subtracter allows additional pixel rate offset modification of each color based on the values written to the OFFSET data bus. Finally, a digital multiplier allows pixel rate gain modification of each color based on the values written to the GAIN data bus. Latency for the red, green and blue channels is 6 ADCCLK cycles (9 cycles for the gain and offset bus; see Figure 13). The STRTLN signal indicates the first red, green and blue pixels in a scan line and the red channel is always the first pixel digitized. The state of STRTLN is evaluated on the rising edges of ADCCLK. When STRTLN is low, the internal circuitry is reset on the next rising edge of ADCCLK; the multiplexer is switched to the red channel and the odd/even circuitry is configured to expect even pixels. After STRTLN goes high, the first set of pixels is assumed to be even. Consecutive sets of pixels (red, green and blue) are assumed to alternate between odd and even pixel sets. 1-Channel Operation with CDS This mode of the AD9807/AD9805 enables single-channel, or monochrome, sampling. The CCD waveform is ac coupled to either the VINR, VING, and VINB pin of the AD9807/AD9805 where it is biased at an appropriate voltage level using the onchip clamp; the input may alternatively be dc coupled if it has already been appropriately level shifted. Bits 6 and 7 in the Configuration Register select the desired input. The internal CDS takes two samples of the incoming pixel data: the first sample (CDSCLK1) is taken during the reset time while the second sample (CDSCLK2) is taken during the video, or data, portion of the input pixel. The offset of the input signal is modified by the value stored in the input offset register. The voltage difference of the reset level and video level is inverted and amplified by the PGA; the setting in the corresponding PGA Gain Register determines the gain of the PGA. The output from the PGA is then routed through a high-speed multiplexer to a 12-bit A/D converter (10-bit for AD9805) for digitization; the multiplexer does not cycle in this mode. After digitization, the data is modified by the amount indicated in the Odd and Even Offset Registers. A digital subtracter allows additional pixel rate offset modification of the signal based on the values written to the OFFSET data bus. Finally, a digital multiplier allows pixel rate gain modification of the signal based on the values written to the GAIN data bus. Latency is 6 ADCCLK cycles (7 cycles for the gain and offset bus; see Figure 14). The state of STRTLN is evaluated on the rising edges of ADCCLK. When STRTLN is low, the internal circuitry is reset on the next rising edge of ADCCLK; the odd/even circuitry is configured to expect an even pixel. After STRTLN goes high, the first pixel is assumed to be even. Consecutive pixels (red, green or blue) are assumed to alternate between odd and even. The blue and green channels are recommended for single channel operation to achieve the maximum sampling rate; if using red, invert ADCCLK as shown in Figure 1d. 1-Channel SHA Operation This mode of the AD9807/AD9805 enables single-channel, or monochrome sampling; it differs from the CDS monochrome sampling mode in that the CDS function is replaced with a sample-and-hold amplifier (SHA). CDSCLK1 becomes the sample-and-hold clock; CDSCLK2 is tied to ground. The input is sampled on the falling edge of CDSCLK1. The input waveform would typically be either dc coupled and level shifted, or dc restored prior to driving either the VINR, VING and VINB pins of the AD9807/AD9805 (clamp mode must be disabled). Bits 6 and 7 in the Configuration Register select the desired input. The input signal in this mode is ground referenced. The input signal is not inverted prior to amplification by the PGA; the setting in the corresponding PGA Gain Register determines the gain of the PGA. The offset of the input signal is modified by the value stored in the input offset register. This signal is then routed through a high speed multiplexer to a 12-bit A/D converter (10-bit for AD9805) for digitization; the multiplexer does not cycle in this mode. After digitization, the data is modified by the amount indicated in the Odd and Even Offset Registers. A digital subtracter allows additional pixel rate offset modification of the signal based on the values written to the OFFSET data bus. Finally, a digital multiplier allows pixel rate gain modification of the signal based on the values written to the GAIN data bus. Latency is 6 ADCCLK cycles (7 cycles for gain and offset; see Figure 15). The state of STRTLN is evaluated on the rising edges of ADCCLK. When STRTLN is low, the internal circuitry is reset on the next rising edge of ADCCLK; the odd/even circuitry is configured to expect an even pixel. After STRTLN goes high, the first pixel is assumed to be even. Consecutive pixels (red, green or blue) are assumed to alternate between odd and even. The blue and green channels are recommended for single channel operation to achieve the maximum sampling rate; if using red, invert ADCCLK as shown in Figure 1f. 2-Channel Bayer Mode Operation with CDS This mode of the AD9807/AD9805 enables Bayer Mode. The CCD waveform is ac coupled to both the VING and VINB pins of the AD9807/AD9805 where it is biased at an appropriate voltage level using the on-chip clamp; the input may alternatively be dc coupled if it has already been appropriately level shifted. The internal CDS takes two samples of the incoming pixel data: the first sample (CDSCLK1) is taken during the reset time while the second sample (CDSCLK2) is taken during the video, or data, portion of the input pixel. The offset of the input signal is modified by the value stored in the input offset register. The voltage difference of the reset level and video level –14– REV. 0 AD9807/AD9805 This feature has been included to accommodate the use of the part with an area CCD (Bayer Mode). The mode is initiated by writing a one to the LSB of the register at Address 7 (see Figure 21). The write to enable the mode should be performed when the STRTLN input is inactive (low) and the ADCCLK is running. The first pixel after an active edge on STRTLN will be a green pixel. All pixels in Bayer Mode are even and use the even offset registers. The line will continue alternating GRGRGR pixels until STRTLN goes inactive. The next line will be BGBGBG pixels (the first pixel after the active STRTLN edge being blue). Line type will then alternate between GRGRGR and BGBGBG type. To reset the next line to GRGRGR type at the start of the next frame/image, rewrite the Bayer mode enable bit to a one during the inactive STRTLN period. All red and blue pixels pass through the blue channel of the part and use the blue PGA and offset registers. To use a different offset/PGA gain value the register must be written to between lines. Green pixels on either line type pass through the green channel. is inverted and amplified by the PGA; the setting in the corresponding PGA Gain Register determines the gain of the PGA. The output from the PGA is then routed through a high speed multiplexer to a 12-bit A/D converter (10-bit for AD9805) for digitization; the multiplexer does cycle in this mode. After digitization, the data is modified by the amount indicated in the Even Offset Registers. A digital subtracter allows additional pixel rate offset modification of the signal based on the values written to the OFFSET data bus. Finally, a digital multiplier allows pixel rate gain modification of the signal based on the values written to the GAIN data bus. Latency is 6 ADCCLK cycles (7 cycles for the gain and offset bus; see Figure 14). The state of STRTLN is evaluated on the rising edges of ADCCLK. When STRTLN is low, the internal circuitry is reset on the next rising edge of ADCCLK; the odd/even circuitry is configured to expect even pixels. ADCCLK tOD DATA<11:0> tHZ tEDV OEB Figure 11. Digital Output Timing PIXEL n RIN, GIN, BIN PIXEL n+1 R, G, B PIXEL n+2 R, G, B R, G, B CDSCLK1 CDSCLK2 ADCCLK R G B DATA<11:0> GAIN<n:0> GAIN<m:0> R (n) G (n) B (n) R G B R R (n–2) G (n–2) B (n–2) R (n–1) R (n+1) G (n+1) B (n+1) R (n+2) G G (n–1) G (n+2) Figure 12. DOUT Latency, 3-Channel CDS Mode REV. 0 –15– B B (n–1) B (n+2) R (n) R (n+3) AD9807/AD9805 PIXEL n RIN, GIN, BIN PIXEL n+1 R, G, B PIXEL n+2 R, G, B R, G, B CDSCLK1 ADCCLK R G B R DATA<11:0> G R (n–2) GAIN<n:0> GAIN<m:0> R (n) G (n) B (n) R (n+1) B G (n–2) G (n+1) R B (n–2) B (n+1) G R (n–1) R (n+2) B G (n–1) G (n+2) B (n–1) B (n+2) R (n) R (n+3) Figure 13. DOUT Latency, 3-Channel SHA Mode PIXEL n PIXEL n+1 PIXEL n+2 RIN, GIN, BIN CDSCLK1 CDSCLK2 ADCCLK DATA<11:0> D (n–8) GAIN<n:0> OFFSET<m:0> D (n–7) D (n–6) G (n+1) G (n) D (n–4) D (n–5) G (n+2) G (n+3) Figure 14. DOUT Latency, 1-Channel CDS Mode PIXEL n PIXEL n+1 PIXEL n+2 RIN, GIN, BIN CDSCLK1 ADCCLK DATA<11:0> GAIN<n:0> OFFSET<m:0> D (n–7) G (n) D (n–6) G (n+1) D (n–5) G (n+2) D (n–4) G (n+3) Figure 15. DOUT Latency, 1-Channel SHA Mode –16– REV. 0 AD9807/AD9805 where GAIN<n:0> is the decimal representation of the GAIN bus data bits, Y = 4096 for the AD9807, Y = 1024 for the AD9805, and X equals 1, 3 or 7 depending on Bits 0–2 in the Configuration Register. Calculating Overall Gain The overall gain for the AD9807/AD9805 can accommodate a wide range of input voltage spans. The total gain is a composite of analog gain (from the PGAs), digital gain (from the digital multiplier) and the input span setting for the A/D (2 V or 4 V). To determine the overall gain setting for the AD9807/AD9805, always multiply the PGA gain setting by the digital gain setting. In addition, the 2 V/4 V reference option can effectively provide analog gain for input signals less than 2 V p-p. Overall Transfer Function The overall transfer function for the AD9807 can be calculated as follows: ADC OUT = Overall Gain = Analog Gain × Digital Gain For example, with the PGA gain equal to 1 (gain setting equals all “zeros”) and the digital multiplier equal to 1, the minimum gain equals 1. With these settings, input signals can be as large as 2 V or 4 V depending on the reference setting. Alternatively, with the PGA gain equal to 4 (gain setting equals all “ones”) and the digital multiplier equal to 8, the maximum gain equals 32. With the A/D reference span set to 2 V, an input signal span as small as 62.5 mV p-p will produce a digital output spanning from all “zeros” to all “ones.” For ranges between 62.5 mV and 4 V, see the Digital Gain and Analog Gain sections of the data sheet. Analog Gain [(V IN ± InputOffset ) × PGA Gain 2 ×V REF ] × 4096 DOUT = [ADCOUT + Offset Register – Offset Bus][Digital Gain] Choosing the Input Coupling Capacitors Because of the dc offset present at the output of CCDs, it is likely that these outputs will require some form of dc restoration to be compatible with the input requirements of the AD9807/AD9805. To simplify input level shifting, a dc blocking capacitor may be used in conjunction with the internal biasing circuits of the AD9807/AD9805 to accomplish the necessary dc restoration. Figure 17 shows the equivalent analog input for the VINR, VING and VINB inputs. The transfer function of the PGA is: Analog Input = 4 15 − x 1+ 3 × 15 AD9807/AD9805 4pF I BIAS C V IN 4.0 12 3.5 10 3.0 8 CDS CDSCLK1 where x is the decimal representation of the settings in the PGA gain register. Figure 16 shows the graph of this transfer function on both a linear and logarithmic scale. The transfer function is approximately linear in dB. STRTLN S1 CONFIG REG 2<7> 4pF 5kΩ V BIAS CONFIG REG 2<0> CONFIG REG 2<6> 2.5 6 GAIN (dB) 2.0 GAIN – dB GAIN CDSCLK2 GAIN 1.5 2 1.0 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PGA GAIN SETTING Figure 16. PGA Transfer Function Digital Gain The digital multiplier section of the AD9807/AD9805 allows the user to apply gain in addition to that afforded by the analog PGA. The minimum gain of the digital multiplier is always 1. The user sets the maximum gain of the digital multiplier to be 8, 4, or 2 with Bits 0–2 in the Configuration Register. (The max gain is the same for all three channels.) The digital gain applied to the output from the digital subtracter is calculated using the equation: Gain < n:0 > Digital Gain = 1+ ×X Y REV. 0 Figure 17. Equivalent Analog Inputs (VINR, VING, and VINB) 4 Enabling CDS functionality and Line Clamp Mode with Bits 0, 6 and 7 in Configuration Register 2 allows switch S1 to turn on when STRTLN is low and CDSCLK1 goes high. This connects a 5 kΩ biasing resistor to the inputs. This arrangement acts to bias the average level of the input signal at voltage, VBIAS. The voltage, VBIAS, changes depending on the selected PGA gain setting. Specifically, for gain settings from 0 to 5, VBIAS equals 4 V; for gain settings from 10 to 15, VBIAS equals 3 V. For gain settings between 5 and 10, VBIAS decreases linearly from 4 V to 3 V. The size of the coupling capacitor is dependent on several factors including signal swing, allowable droop, and acquisition time. The following procedure shows how to determine the recommended range of capacitors. Calculating CMAX The maximum capacitor value is largely dependent on the degree of accuracy and how quickly the input signal must be level-shifted into the valid input range of the degree of accuracy. Other factors affecting the speed of the capacitor charging or –17– AD9807/AD9805 discharging include the amount of time that input switch S1 is turned on, the input impedance of the AD9807/AD9805 and the output impedance of the circuit driving the coupling capacitor. The impedance of the drive circuit, ROUT, the input impedance of the AD9807/AD9805, RIN, and the desired charging time, tACQ, are all known quantities. Note that tACQ may not necessarily occur over a continuous period of time; it may actually be an accumulation of discrete charging periods. This is typical where CDSCLK1 is asserted only during the reset levels of the pixels. In this case, the quantity, m × T, may be substituted for tACQ, where m is the number of periods CDSCLK1 is asserted and T is the period of the assertion. Given these quantities, the maximum value for the input coupling capacitor is computed from the equation: C MAX ≅ With dV = 1.2 volts, a clamp accuracy of 100 mV should be sufficient (VE =100 mV), but this value can be adjusted. The amount of time available to charge up the input capacitor, TACQ, will equal the period of CDSCLK1 (when the clamp switch is closed) times the number of optical black pixels. With a pixel rate of 2 MHz, CDSCLK1 would typically be around 100 ns wide, giving TACQ =1800 ns or 1.8 µs. The input impedance of the AD9807 is 5K, and the input bias current is 10 nA. Assume the source impedance driving the AD9807 is low (ROUT = 0). CMAX = (1.8 µs/5K) × (1/ln (1.5/0.1)) = 133 pF CMIN = (10 nA/1.2) × 5000 × 500 ns = 21 pF Note that a capacitor larger than 133 pF would still work, it would just take several lines to charge the input capacitor up to the full VC level. Another option to lengthen TACQ is by clocking the CCD and CDSCLK1 while the transport motor moves the scanner carriage. This would extend TACQ to several hundred µs or more, meaning that only very fine adjustment would be needed during the limited number of optical black pixels. t ACQ V / ln C RIN + ROUT V E where VC is the required voltage change across the coupling capacitor and VE is the maximum tolerable error voltage. VC is calculated by taking the difference between the CCD’s reset level and the internal bias level of the AD9807/AD9805. VE is the level of accuracy to which the input capacitor must be charged and is system dependent. Usually the allowable droop of the capacitor voltage is taken into account. This is discussed below. For example, if the CCD output can droop up to 1 volt without affecting the accuracy of the CDS, then clamping to within about one tenth of the allowable droop (100 mV) should be sufficient in most cases. Example 2 Calculating CMIN Determining CMIN is a function of the amount of allowable voltage droop. It is important that the signals at the inputs of the AD9807/AD9805 remain within the supply voltage limits so the CDSs are able to accurately digitize the difference between the reset level and the video level. Assuming the input voltages are initially biased at the correct levels, the input bias current of the AD9807/AD9805 inputs will discharge the input coupling capacitors resulting in voltage droop. After taking into account any droop, the peaks of the input signal must remain within the required voltage limits of AD9807/AD9805 inputs. Specifically, CMIN is a function of the maximum allowable droop, dV, in one scan line, the number of pixels across one scan line, n, the period of one pixel, t, and the input bias current of the AD9807/AD9805, IBIAS. CMIN is calculated from the equation: I C MIN = BIAS × n × t dV A 7926 pixel CCD running at 2 MHz has a reset level of 6 volts, an output voltage of 2.9 volts and 80 optical black pixels. Using the AD9807 with an input span of 4 volts and a PGA gain of 1.25, VBIAS = 4 volts. The maximum required voltage change on the capacitor, VC, is 2 volts and the maximum amount of droop dV for one line is 1.1 volts. TACQ will be 80 × 100 ns or 8 µs, and VE = 100 mV should be sufficient. Again, RIN = 5K, ROUT = 0, and IBIAS = 10 nA. CMAX = (8 µs/5K) × (1/ln (2/0.1)) ≅ 534 pF CMIN = (10 nA/1.1) × (7926) × (500 ns) = 36 pF Again, a larger capacitor may be used if several lines are allowed for to initially charge up the cap, or if the CCD and CDSCLK1 are clocked during the moving of the scanner carriage. Generating 3-Channel Timing from a 16 3 Master Clock Generating the required signals for CDSCLK1, CDSCLK2 and ADCCLK is easily accomplished with a master clock running 16 × the desired per channel pixel rate (i.e., 2 MSPS pixel rate requires 32 MHz master clock). The timing diagram shown in Figure 18 meets all the minimum and maximum timing specifications. Note that a 16 × master clock using only rising edges was chosen instead of using both edges of an 8 × rate clock to ensure immunity to duty cycle variations. 500ns Some examples are given below showing the typical range of capacitor values. MASTER (32MHz) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Example 1 A 5000 pixel CCD running at a 2 MHz (t = 500 ns) has a reset level of 4.5 volts and an output voltage of 1.8 volts. The number of optical black pixels available at the start of a line is 18. Using the AD9807/AD9805 with an input span of 4 volts and a PGA gain of 2 gives a VBIAS of 3 volts. If the input signal is clamped to 3 volts during the optical black pixels, the required voltage change on the input capacitor, VC, equals (4.5 – 3) or 1.5 volts and the maximum droop allowable during one line, dV, will be (3 – 1.8) or 1.2 volts before the signal droops below 0 volts. –18– CDSCLK1 CDSCLK2 ADCCLK Figure 18. Timing Scheme Using 16 × Master Clock REV. 0 AD9807/AD9805 Power-On Initialization and Calibration Sequence When the AD9807/AD9805 is powered on, the following sequence should be used to initialize the part to a known state. The digital gain and offset buses are disabled until the calibration sequence. The Bayer mode register must be written to and set to zero if this mode is not going to be used. To calibrate the AD9807/AD9805 for a particular scan, use the following sequence. SET PGA GAIN(S) (INPUT OFFSET = 0mV) SCAN DARK LINE CHANGE POINTER WRITE TO CONFIGURATION REGISTER SET DIGITAL GAIN RANGE TO 000 SET GAIN/OFFSET BUS SIZE TO 000 SET COLOR POINTER COMPUTE PIXEL OFFSETS SET INPUT OFFSET WRITE TO PGA GAIN REGISTER SET TO GAIN OF ONE (0000) SET ODD/EVEN OFFSET WRITE TO INPUT OFFSET REGISTER SET TO 0mV (11001100) YES YES SET ANOTHER COLOR ? SET ANOTHER COLOR ? NO SET GAIN/OFFSET BUS SIZE NO WRITE TO CONFIGURATION 2 REGISTER SET CDS OR SHA OPERATION SET 3-CHANNEL OR 1-CHANNEL MODE SET ADC FULL-SCALE RANGE SET CLAMP MODE SET EXTERNAL PIXEL OFFSET VECTORS SCAN WHITE LINE WRITE TO BAYER MODE REGISTER SET MODE ON OR OFF COMPUTE PIXEL GAINS OPTIONAL READBACK FROM REGISTERS YES Figure 19. Initialization ADJUST PGA GAIN(S) ? NO SET DIGITAL GAIN RANGE Figure 20. Calibration REV. 0 –19– AD9807/AD9805 Grounding and Decoupling SET PGA AND INPUT OFFSET FOR GREEN PIXELS USING THE GREEN REGISTERS SET PGA AND INPUT OFFSET FOR RED PIXELS USING THE BLUE REGISTERS BRING STRTLN LOW WRITE A "1" TO THE LSB OF THE BAYER REGISTER APPLY AT LEAST ONE ADCCLK CYCLE BRING STRTLN HIGH THE FIRST PIXEL IS GREEN CHANGE GAIN AND OFFSET FOR RED PIXELS WITH BLUE REGISTERS THE SECOND PIXEL IS RED, ALTERNATING GRGR... BRING STRTLN LOW AT THE END OF THE LINE Figure 22 shows the recommended decoupling capacitors and ground connections for the AD9807/AD9805. Notice that all of the power and ground connections are common for the analog and digital portions of the chip. This would be the best way to connect the device on a board containing a large number of digital components. By treating the AD9807/AD9805 as an analog component, the on-board digital circuitry is considered “quiet digital” and the digital supply pins are connected to the clean analog supply and analog ground plane. For this technique to work well, it is important that the digital supply pins be well decoupled to the analog ground plane and that the digital outputs of the AD9807/AD9805 are buffered to minimize the digital drive current. The buffers would be referred to the digital supply and ground. This scheme is preferable to tying the digital portion of the AD9807/AD9805 to a noisy digital ground and power plane, capacitively coupling noise to the analog circuitry within the device. The AD9807/AD9805 evaluation boards use this grounding method, shown in Figures 26 and 27. If a minimum amount of digital circuitry exists on the board, it is possible that the power and ground connections of the AD9807 can be separated; be sure to maintain a single point connection between the two ground planes at the AD9807/AD9805. 0.1µF YES 1 0.1µF 2 0.1µF 3 4 + NO 10µF 0.1µF CHANGE THE PGA AND INPUT OFFSET OF BLUE REGISTERS FOR BLUE PIXELS 5 6 0.1µF + BRING STRTLN HIGH 10µF 7 0.1µF 0.1µF 8 10 12 THE FIRST PIXEL IS BLUE 14 0.1µF THE SECOND PIXEL IS GREEN, ALTERNATING BGBG... 51 52 +5 NEXT LINE GRGR AGAIN (NEW FRAME) ? +5 15 DVSS AVDD AVSS CAPT CAPT CAPB CAPB AD9807/AD9805 (PINS OMITTED FOR CLARITY) REF CML DRVDD AVSS DRVSS 41 +5 0.1µF 40 AVSS AVSS AVDD DVSS DVDD DVSS DVDD 28 29 +5 0.1µF +5 BRING STRTLN LOW AT THE END OF THE LINE Figure 22. Figure 21. Bayer Mode Operation –20– REV. 0 AD9807/AD9805 CIS Application CIS START PULSE Unlike many other integrated circuit CCD signal processors, the AD9807/AD9805 can easily be implemented in imaging systems that do not use a CCD. By disabling the input clamp and the CDS blocks, any dc coupled signal within the input limits of the part can be digitized. Figure 23 shows a typical block diagram of the AD9807 used with a color CIS module, in this case Dyna Image Corporation’s DL100*. The three color output signals are dc coupled into the AD9807. The Dyna CIS module’s output levels are around 70 mV to 500 mV dark to bright, well within the input range of the AD9807. The AD9807 is configured for 3-channel SHA operation through the MPU registers. Timing used with the Dyna DL100 is shown in Figure 24; the CIS output levels are sampled on the falling edge of CDSCLK1. The digital ASIC shown can be implemented in a variety of ways: it could include the MPU interface and timing generator, as well as memory for the output data and pixel gain and offset correction vectors. 12 RED VINR GREEN VING BLUE VINB CIS CLOCKS CIS OUTPUT STRTLN ADCCLK CDSCLK1 Figure 24. CIS Application Timing Signals EVALUATION BOARDS The AD9807 and AD9805 evaluation boards are designed to provide an easy interface to a standard PC, simplifying the task of evaluating the performance of the AD9807/AD9805 with an existing imaging system. The system level block diagram shown in Figure 25 illustrates the basic evaluation setup for the AD9807 (the AD9805 is the same). The user needs to supply the analog input signals (such as outputs from a CCD), the AD9807/AD9805’s clock signals, a power supply and a printer cable to connect the evaluation board to the PC’s parallel port. Software is included to allow the user to easily accomplish three major tasks: first, configure the AD9807/AD9805 in one of several operating modes (1 Channel, 3 Channel, CDS or SHA mode, etc.), second, acquire output data from the part and third, download pixel gain and offset correction data to the evaluation board and enable pixel rate shading and offset correction. PIXEL GAIN CORRECTION GAIN<11:0> CIS CIS CLOCK OUTPUT DATA 12 DOUT<11:0> MPU<7:0> AD9807 A2, A1, A0 OEB, WRB STRTLN, RDB, CSB CDSCLK1, ADCCLK OFFSET<7:0> 3 7 8 8 MPU INTERFACE PIXEL OFFSET CORRECTION Figures 26 and 27 show the signal routing and decoupling for the AD9807 evaluation board. DIGITAL ASIC TIMING GENERATOR The evaluation boards are designated with the part numbers AD9807-EB and AD9805-EB. Figure 23. CIS Application Diagram (Power, Ground, and Decoupling Omitted) +5V VOLT POWER SUPPLY AD9807 EVALUATION BOARD ANALOG INPUTS RED VINR GREEN VING BLUE VINB 8 OFFSET AD9807 12 DOUT MPU I/O MPU CONTROL CLOCK INPUTS 12 GAIN 8 7 FIFO BUFFERS, LATCHES, AND CONTROL LOGIC 8 CLOCKS STRTLN CDSCLK1 4 CDSCLK2 ADCCLK Figure 25. Evaluation System Block Diagram *All trademarks are properties of their respective holders. REV. 0 –21– PRINTER CABLE PC PARALLEL PORT AD9807/AD9805 AVDD +5VD DVDD C21 0.1µF + C18 C26 0.1µF 10µF 12 GAIN + C25 10µF AVSS C15 0.1µF DVDD A2 A1 PL JP1 TP7 C2 0.01µF B6 R6 50Ω PL C11 0.1µF JP2 AVDD CDS1 C3 0.01µF B7 A1 A2 DVDD G(0) DVSS G(1) G(2) G(3) G(4) G(5) G(6) G(7) G(8) G(9) D(5) D(4) D(3) D(2) D(1) D(0) OEB 47 D11 46 45 D10 44 D8 43 D7 D9 42 D6 41 40 C13 0.1µ 39 DVDD D5 38 37 D4 36 D2 35 D1 D3 D0 34 OEB 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PL JP3 C14 0.1µF R5 50Ω DRVSS 48 WRB TP6 RDB R7 50Ω CSB B5 DRVDD AD9807 DVDD C4 0.1µF TP5 DVSS C27 0.1µF D(6) OFF(0) + D(7) OFF(1) C28 10µF C1 0.01µF D(8) OFF(2) TP5 D(9) OFF(3) C6 10µF OFF(4) + D(10) OFF(5) C7 0.1µF C10 0.1µF D(11) AVSS 3 CAPT 4 CAPT 5 CAPB 6 CAPB 7 REF 8 CML 9 VINR 10 AVSS 11 VING 12 AVSS 13 VINB 14 AVSS 15 AVDD 16 ST_LIN OFF(6) 2 AD9807 DATABUS A0 AVDD OFF(7) C8 0.1µF 1 G(10) C12 0.1µF ADCLK AVDD G(11) TP15 TP16 CDS2 TP13 TP14 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 STARTLINE TP9 STARTLINE 8 OFFSET B1 R4 50Ω DVDD PL TP10 CDS1 B2 R3 50Ω PL TP11 CDS2 B3 R2 50Ω PL TP12 ADC B4 R1 50Ω PL ADCCLK Figure 26. AD9807 Evaluation Board (Digital Circuitry Omitted) –22– REV. 0 AD9807/AD9805 +C6 +C28 C13 C12 C7 C8 C10 C15 C27 C4 C11 C14 Figure 27. Suggested Capacitor Placement for Single-Side Component Layout REV. 0 –23– AD9807/AD9805 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 64-Terminal PQFP (S-64) 0.093 (2.35) MAX 0.041 (1.03) 0.029 (0.73) 64 1 C2196–12–1/97 0.687 (17.45) 0.667 (16.95) 0.555 (14.10) 0.547 (13.90) 0.472 (12.0) BSC 49 48 PIN 1 0.472 (12.0) BSC 0.555 (14.10) 0.547 (13.90) 0.687 (17.45) 0.667 (16.95) SEATING PLANE TOP VIEW (PINS DOWN) STANDOFF 0.010 (0.25) 16 17 0.009 (0.23) 0.005 (0.13) 33 32 0.031 (0.80) 0.018 (0.45) BSC 0.012 (0.30) 0.083 (2.10) 0.077 (1.95) PRINTED IN U.S.A. 7° 0° –24– REV. 0