ETC EM78P451

EM78P451
OTP ROM
1. GENERAL DESCRIPTION
The EM78P451 is an 8-bit microprocessor designed and developed with low-power, high speed CMOS
technology. Its operational kernel is implemented with RISC-like architecture and is available in the mask
ROM version. The one time programmable (OTP) version is flexible, both in mass production or
engineering test stages. OTP provide users with unlimited volume with favorable price opportunities. This
device is equipped with the Serial Peripheral Interface (SPI) function and an easy-implemented RS-232.
The EM78P451 is very suitable for wired communication. Only 58 easy-to-learn instructions are needed
and user’s program can be emulated with EMC In-Circuit Emulator (ICE).
This specification is subject to change without prior notice.
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EM78P451
OTP ROM
2. FEATURES
• Operating voltage range: 2.3V~5.5V.
• Operating temperature range: 0°C~70°C.
• Operating frequency rang (base on 2 clocks ):
* Crystal mode: DC~20MHz at 5V, DC~8MHz at 3V, DC~4MHz at 2.3V.
* RC mode: DC~4MHz at 5V, DC~4MHz at 3V, DC~4MHz at 2.3V.
• Low power consumption:
* Less then 3 mA at 5V/4MHz
* Typically 10 µA during sleep mode
• Serial Peripheral Interface (SPI) available.
• 4K × 13 bits on chip ROM (EM78P451).
• 11 special function registers.
• 140× 8 bits on chip general-purposed registers.
• 5 bi-directional I/O ports (35 I/O pins).
• 3 LED direct sinking pins with internal serial resistors.
• Built-in RC oscillator with external serial resistor, ±10% variation.
• Built-in power-on reset.
• 5 stacks for subroutine nesting.
• 8-bit real time clock/counter (TCC) with overflow interrupt.
• Two machine clocks or four machine clocks per instruction cycle.
• Power down mode.
• Programmable wake up from sleep circuit on I/O ports.
• Programmable free running on-chip watchdog timer.
• 12 wake-up pins.
• 2 open-drain pins.
• 2 R-option pins.
• 32 programmable pull-high input pins.
• Packages:
* 40 pin DIP 600mil
: EM78P451P.
* 44 pin QFP
: EM78P451AQ.
This specification is subject to change without prior notice.
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OTP ROM
• Four types of interrupts.
* External interrupt (/INT).
* SPI transmission completed interrupt.
* TCC overflow interrupt.
* Timer1 comparator match interrupt.
This specification is subject to change without prior notice.
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OTP ROM
3. PIN ASSIGNMENT
36
P 7 1
35
P 7 2
34
P 6 7
P90
1
33
P71
33
P 6 6
P91
32
31
P72
32
2
3
P 6 5
4
30
P66
5
29
P65
28
P64
P63
7
8
27
26
P52
9
25
P61
P53
P54
10
24
P60
11
23
P87
P51
13
28
P 6 1
P 5 3
14
27
P 6 0
P 5 4
15
26
P 8 7
P 5 5
16
25
P 8 6
P 5 6
17
24
P 8 5
P 5 7
18
23
P 8 4
P 8 0
19
22
P 8 3
P 8 1
20
21
P 8 2
37
P50
P 6 2
P 5 2
EM78P451AQ
SS/P95
P62
P 8 6 22
29
P 6 3
P67
6
P 8 5 21
12
30
P 6 4
P 8 4 20
P 5 1
11
31
P 8 3 19
P 5 0
10
P 8 2 18
S S / P 9 5
SDI/P92
SDO/P93
SCK/P94
17
9
NC
S C K / P 9 4
P 8 1 16
8
P 8 0 15
S D O / P 9 3
P 5 7 14
7
P 5 5 12
6
P 5 6 13
P 9 1
S D I / P 9 2
P 7 0
34 P 7 0
5
35 N C
P 9 0
NC
37
36 N C
4
38 V D D
V D D
C L K
39 R - O S C I
38
40 O S C O
3
41 V S S
R - O S C I
D A T A
43 D A T A
O S C O
39
42 I N T
40
2
44 C L K
1
I N T
E M 7 8 P 4 5 1 P / W M
V S S
Fig. 1 Pin Assignment
Table 1 Pin description
Symbol
Pin No.
Type
R-OSCI
39
I
OSCO
40
O
5~10
I/O
P80~P87 19~26
I/O
P70~P72 37~35
I/O
CLK
4
I/O
DATA
3
I/O
P90~P95
P60~P67 27~34
I/O
P50~P57 11~18
I/O
VDD
VSS
/INT
38
1
2
I
Function Description
* In XTAL mode: Crystal input; In internal C, external R mode: 56Kohm±5%
pull high for 1.8432MHz.
* In XTAL mode: Crystal output; In RC mode: Instruction clock output.
* General bi-directional I/O port. All of its pins can be pulled-high by software.
P90 and P91 are pin-change wake up pins.
* General bi-directional I/O port. All of its pins can be pulled-high by software.
P80 and P81 are also used as the R-option pins.
* LED direct-driving pin with internal serial resistor used as output and is
software defined.
* By connecting P74 and P76 together.
* P74 can be pulled-high by software and it is also a pin-change wake up pin.
* P76 can be defined as an open-drain output.
* By connecting P75 and P77 together.
* P75 can be pulled-high by software and it is also a pin-change wake up pin.
* P77 can be defined as an open-drain output.
* General bi-directional port. All of its pins can be pulled-high by software, and
pin-change wake up pins.
* General bi-directional I/O port. All of its pins can be pulled-high individually
by software.
* Power supply pin.
* Ground pin.
* An interrupt schmitt-triggered pin.
This specification is subject to change without prior notice.
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OTP ROM
SDI
SDO
SCK
/SS
7
8
9
10
I/O
I/O
I/O
I/O
* The function of interrupt triggers at the falling edge.
* Users can enable it by software. The internal pull-up resistor is around 50K
ohms.
* Serial data in for SPI
* Serial data out for SPI.
* Serial clock for SPI.
* /Slave select for SPI.
This specification is subject to change without prior notice.
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OTP ROM
4. FUNCTION DESCRIPTION
WDT Timer
WDT
Time-out
P C
STACK 1
STACK 2
Prescaler
STACK 3
Oscillator/
/INT
Timming
STACK 4
ROM
STACK 5
Control
Interrupt
Instruction
Control
Register
R1(TCC)
ALU
Instruction
Sleep
RAM
Decoder
&
Wake Up
Control
R3
ACC
TMR1
R4
DATA & CONTROL BUS
IOC5
IOC6
IOC7
R5
R6
R7
P P PP P P PP
5 5 55 5 5 55
0 1 23 4 5 67
P P P PP P P P
6 6 6 66 6 6 6
0 1 2 34 5 6 7
P
7
0
P
7
1
IOC9
IOC8
R8
P
7
2
P P PP P PP P
8 8 88 8 88 8
0 1 23 4 56 7
R9
SPI
ENGIN
P P P P
9 9 9 9
0 1 2 3
/ /
S S
D D
P P
9 5
4 5
/ /
S /
C S
I O K S
Fig. 2 Functional Block Diagram
4.1 Operational Registers
1. R0 (Indirect Address Register)
R0 is not a physically implemented register. It is used as an indirect addressing pointer. Any
instruction using R0 as register actually accesses data pointed by the RAM Select Register (R4).
2. R1 (TCC)
• Increased by the instruction cycle clock.
• Written and read by program as any other register.
3. R2 (Program Counter) & Stack
• R2 and the hardware stacks are 12 bits wide.
• The structure is depicted in Fig. 3.
This specification is subject to change without prior notice.
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OTP ROM
• Generates 4K × 13 on-chip ROM addresses to the relative programming instruction codes. One
program page is 1024 words long.
• All the R2 bits are set to "1"s as a RESET condition occurs.
• "JMP" instruction allows direct loading of the lower 10 program counter bits. Thus, "JMP" allows
jump to any location on one page.
• "CALL" instruction loads the lower 10 bits of the PC, and then PC+1 is pushed into the stack. Thus,
the subroutine entry address can be located anywhere within a page
• "RET" ("RETL k", "RETI") instruction loads the program counter with the contents at the top of stack.
• "MOV R2, A" allows the loading of an address from the "A" register to the lower 8 bits of PC, and the
ninth and tenth bits (A8~A9) of PC are cleared.
• "ADD R2, A" allows a relative address be added to the current PC, and the ninth and tenth bits of PC
are cleared.
• Any instruction that is written to R2 (e.g. "ADD R2, A", "MOV R2, A", "BC R2,6",⋅⋅⋅⋅⋅) (except "TBL")
will cause the ninth and tenth bits (A8~A9) of PC to be cleared. Thus, the computed jump is limited
to the first 256 locations of any program page.
• "TBL" allows a relative address be added to the current PC (R2+A→R2), and contents of the ninth
and tenth bits (A8~A9) of PC are not changed. Thus, the computed jump can be on the second (or
third, 4th) 256 locations on one program page.
• In case of EM78P451, the most significant bits (A10~A11) will be loaded with the contents of bits
PS0~PS1 in the status register (R3) upon the execution of a "JMP", "CALL", or any other
instructions which writes to R2.
• All instructions are single instruction cycle (fclk/2 or fclk/4) except for the instruction that would
change the contents R2. Such instruction will need one more instruction cycle.
CALL
PC
A11A10
A9A8
A7
~
A0
RET
RETL
RETI
00
400
7FF
10
Stack 3
Stack 4
Page 0
0 0 1 : H a r e w a r e i nt e r r u p t l o c a t i o n
002:Software interrupt (INT instruction) location
Page 1
FFF:Reset location
800
BFF
11
Stack 2
Stack 5
000
3FF
01
Stack 1
Page 2
C00
FFF
Page 3
Fig. 3 Program Counter Organization
This specification is subject to change without prior notice.
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EM78P451
OTP ROM
4. R3 (Status Register)
7
GP
6
PS1
5
PS0
4
T
3
P
2
Z
1
DC
0
C
• Bit 0 (C) Carry flag
• Bit 1 (DC) Auxiliary carry flag
• Bit 2 (Z) Zero flag. Set to "1" if the result of an arithmetic or logic operation is zero.
• Bit 3 (P) Power down bit. Set to 1 during power on or by a "WDTC" command and reset to 0 by a
"SLEP" command.
• Bit 4 (T) Time-out bit. Set to 1 with the "SLEP" and the "WDTC" commands, or during power up and
reset to 0 with WDT timeout.
• Bits 5 (PS0) ~ 6 (PS1) Page select bits. PS0~PS1 are used to pre-select a program memory page.
When executing a "JMP", "CALL", or other instructions which causes the program counter to be
changed (e.g. MOV R2, A), PS0~PS1 are loaded into the 11th and 12th bits of the program counter
where it selects selecting one of the available program memory pages. Note that RET (RETL, RETI)
instruction does not change the PS0~PS1 bits. That is, the return will always be to the page from
where the subroutine was called, regardless of the current setting of PS0~PS1 bits. PS1 bit is not
used (read as "0") and cannot be modified in EM78P451.
PS1
0
0
1
1
PS0
0
1
0
1
Program memory page [Address]
Page 0 [000-3FF]
Page 1 [400-7FF]
Page 2 [800-BFF]
Page 3 [C00-FFF]
• Bit 7 (GP) General read/write bit.
5. R4 (RAM Select Register)
• Bits 0~5 are used to select the registers (address: 00~3F) in the indirect addressing mode.
• Bits 6~7 determine which bank is activated among the 4 banks.
• If no indirect addressing is used, the RSR is used as an 8-bit general-purposed read/writer register.
• See the configuration of the data memory in Fig. 4.
6. R5~R8 (Port 5 ~ Port8)
• Four general 8 bits I/O registers
• Both P74 and P76 read or write data from the DATA pin, while both P75 and P77 read or write data
from the CLK pin.
7. R9 (Port9)
• A general 6-bit I/O register. The values of the two most significant bits are read as "0".
This specification is subject to change without prior notice.
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EM78P451
OTP ROM
00
R0
01
R1 (TCC)
02
R2 (PC)
STACK 0
03
R3 (Status)
STACK 1
04
R4 (RSR)
STACK 2
05
R5 (Port 5)
STACK 3
IOC5
06
R6 (Port 6)
STACK 4
IOC6
07
R7 (Port 7)
IOC7
08
R8 (Port 8)
IOC8
09
R9 (Port 9)
IOC9
0A
RA
0B
RB
0C
RC
IOCC
0D
RD
IOCD
0E
RE
IOCE
0F
RF
IOCF
10
11
16x8
Common
Register
1E
1F
00
01
10
11
20
21
31x8
Bank
Register
31x8
Bank
Register
31x8
Bank
Register
31x8
Bank
Register
(Bank 0)
(Bank 1)
(Bank 2)
(Bank 3)
3E
3F
R3F
Fig. 4 Data memory configuration
This specification is subject to change without prior notice.
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OTP ROM
8. RA (SPIRB: SPI Read Buffer)
Address
Name
0X0A SPIRB/RA
Bit 7
SRB7
Bit 6
SRB6
Bit 5
SRB5
Bit 4
SRB4
Bit 3
SRB3
Bit 2
SRB2
Bit 1
SRB1
• SRB7~SRB0 are the 8-bit data when complete transmission by SPI.
9. RB (SPIWB: SPI Write Buffer)
Address
Name
0x0B SPIWB/RB
Bit 7
SWB7
Bit 6
SWB6
Bit 5
SWB5
Bit 4
SWB4
Bit 3
SWB3
Bit 2
SWB2
Bit 1
SWB1
Bit 0
SWB0
Bit 1
RBFIF
Bit 0
RBF
• SWB7~SWB0 are the 8-bit data that are waiting for transmission by SPI.
10. RC (SPIS: SPI Status Segister)
Address
0x0C
Name
SPIS/RC
Bit 7
--
Bit 6
--
Bit 5
--
Bit 4
TM1IF
Bit 3
OD3
Bit 2
OD4
• TM1IF (bit 4):
1 = In timer1 mode, receiving completed, and an interrupt occurs if enabled.
0 = In timer1 mode, receiving not completed yet, and an interrupt does not occur.
• OD3 (bit 3): Open-Drain Control bit
1 = Open-drain enable for SDO,
0 = Open-drain disable for SDO.
• OD4 (bit 2): Open-Drain Control bit
1 = Open-drain enable for SCK,
0 = Open-drain disable for SCK.
• RBFIF (bit 1):Read Buffer Full Interrupt Flag
1 = Receiving completed, SPIRB is fully exchanged, and an interrupt occurs if enabled.
0 = Receiving not completed yet; and SPIRB has not fully exchanged.
• RBF (bit 0): Read Buffer Full flag
1 = Receiving completed; SPIRB is fully exchanged.
0 = Receiving not completed yet, and SPIRB has not fully exchanged.
11. RD (SPIC: SPI Control Register)
Address
0x0D
Name
SPIC/RD
Bit 7
CES
Bit 6
SPIE
Bit 5
SRO
Bit 4
SSE
Bit 3
-
Bit 2
SBRS2
Bit 1
Bit 0
SBRS1 SBRS0
• CES (bit 7): Clock Edge Select bit
1 = Data shifts out on falling edge, and shifts in on rising edge. Data is on hold during the high level.
0 = Data shifts out on rising edge, and shifts in on falling edge. Data is on hold during the low level.
• SPIE (bit 6): SPI Enable bit
1= Enable SPI mode
This specification is subject to change without prior notice.
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OTP ROM
0= Disable SPI mode
• SRO (bit 5): SPI Read Overflow bit
1 = A new data is received while the previous data is still being held in the SPIB register. In this
situation, the data in SPIS register will be destroyed. To avoid setting this bit, users had better read
SPIRB register even if only the transmission is implemented.
0 = No overflow.
<Note>:
This can only occur in slave mode.
• SSE (bit 4): SPI Shift Enable bit
1 = Start to shift, and keep on 1 while the current byte is still being transmitted.
0 = Reset as soon as the shifting is complete, and the next byte is ready to shift.
<Note>: This bit will reset to 0 at every one-byte transmission by the hardware
• SBRS (bit 2~bit 0): SPI Baud Rate Select bits
SPI baud rate table is illustrated in SPI section in later pages.
12. RE (TMR1: Timer1 register)
Address
0X0E
Name
Bit 7
TMR1/RE TMR17
Bit 6
TMR16
Bit 5
TMR15
Bit 4
TMR14
Bit 3
TMR13
Bit 2
TMR12
Bit 1
Bit 0
TMR11 TMR10
• TMR17~TMR10 is bit set of timer1 register and it increases until the value matches PWP and then,
it resets to 0.
13. RF (PWP: Pulse width preset register)
Address Name
0x0F PWP/RF
Bit 7
PWP7
Bit 6
PWP6
Bit 5
PWP5
Bit 4
PWP4
Bit 3
PWP3
Bit 2
PWP2
Bit 1
PWP1
Bit 0
PWP0
• PWP7~PWP0 is bit set of pulse width preset in advance for the desired width of baud clock.
14. R20~R3E (General Purpose Register)
• RA~R1F, and R20~R3E (including Banks 0~3) are general-purpose registers.
15. R3F (Interrupt Status Register)
Address Name
0x3F ISR/R3F
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
TM1IF
Bit 2
SPIIF
Bit 1
EXIF
Bit 0
TCIF
• Bit 0 (TCIF) the flag of the TCC overflow interrupt. Set as TCC overflow; flag cleared by software.
• Bit 1 (EXIF) External interrupt flag. Set by falling edge on /INT pin, flag cleared by software
• Bit 2 (SPIIF) SPI interrupt flag. Set by data transmission complete, flag cleared by software.
• Bit 3 (TM1IF) Timer1 interrupt flag. Set by the comparator at Timer1 application, flag cleared by
software.
• Bits 2~7 are not used and read as “0”.
This specification is subject to change without prior notice.
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OTP ROM
• "1" means interrupt request, "0" means non-interrupt.
• R3F can be cleared by instruction, but cannot be set by instruction.
• IOCF is the interrupt mask register.
• Note that to read R3F will result to "logic AND" of R3F and IOCF.
4.2 Special Purpose Registers
1. A (Accumulator)
• Internal data transfer, or instruction operand holding.
• A non-addressable register.
2. CONT (Control Register)
7
/PHEN
6
/INT
5
-
4
-
3
PAB
2
PSR2
1
PSR1
0
PSR0
• Bit 7 (/PHEN) I/O pin pull-high enable flag.
0: For P60~P67, P74~P75 and P90~P95, the pull-high function is enabled.
1: The pull-high function is disabled.
• Bit 6 (INT) An interrupt enable flag cannot be written by the CONTW instruction.
0: interrupt masked by the DISI instruction.
1: interrupt enabled by the ENI or RETI instruction.
• Bit4, 5 Not used, and to be read as “0”.
• Bit 3 (PAB) Prescaler assignment bit.
0: TCC
1: WDT
• Bit 0 (PSR0) ~ Bit 2 (PSR2) TCC/WDT prescaler bits.
PSR2
0
0
0
0
1
1
1
1
PSR1
0
0
1
1
0
0
1
1
PSR0
0
1
0
1
0
1
0
1
TCC Rate
1:2
1:4
1:8
1:16
1:32
1:64
1:128
1:256
WDT Rate
1:1
1:2
1:4
1:8
1:16
1:32
1:64
1:128
• Bits 0~3, and 7 of the CONT register are readable and writable.
3. IOC5 ~ IOC9 (I/O Port Control Register)
• "1" put the relative I/O pin into high impedance, while "0" put the relative I/O pin as output.
This specification is subject to change without prior notice.
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OTP ROM
• Both P74 and P76 should not be defined as output pins at the same time. This also applies to both
P75 and P77.
• Only the lower 6 bits of the IOC9 register are used.
4. IOCC (T1CON: Timer1 control register)
Address
Name
0x0C T1CON/IOCC
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
TM1E
Bit 1
TM1P1
Bit 0
TM1P0
• TM1E (bit2): Timer1 Function Enable bit
1 = Enable timer1 function.
0 = Disable timer1 function as default.
• TM1P (bit1~bit0): Timer1 Prescaler bit
Timer1 prescaler table for FOSC will be illustrated in the Section on Timer1 in later pages.
5. IOCD (Pull-high Control Register)
7
S7
6
-
5
-
4
-
3
/PU9
2
/PU8
1
/PU6
0
/PU5
• The default values of /PU5, /PU6, /PU8, and /PU9 are one, which means the pull-high function is
disabled.
• /PU6 and /PU9 are “AND” gating with /PHEN, that is, when each one is written as “0” pull high is
enabled.
• S7 defines the driving ability of the P70-P72.
0: Normal output.
1: Enhance the driving ability of LED.
6. IOCE (WDT Control Register)
7
-
6
ODE
5
WDTE
4
SLPC
3
ROC
2
-
1
-
0
/WUE
• Bit 0 (/WUE) Control bit used to enable the wake-up function of P60~P67, P74~P75, and P90~P91.
0: Enable the wake-up function.
1: Disable the wake-up function.
The /WUE bit can be read and written.
• Bit 3 (ROC) ROC is used for the R-option. Setting ROC to "1" will enable the status of R-option pins
(P80, P81) to be read by the controller. Clearing ROC will disable the R-option function. Otherwise,
the R-option function is introduced. Users must connect the P81 pin or/and P80 pin to VSS by a
560KΩ external resistor (Rex). If Rex is connected/disconnected with VDD, the status of P80 (P81)
will be read as "0"/"1" (refer to Fig. 7(b)). The ROC bit can be read and written.
This specification is subject to change without prior notice.
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OTP ROM
• Bit 4 (SLPC) This bit is set by hardware at the falling edge of wake-up signal and is cleared in
software. SLPC is used to control the oscillator operation. The oscillator is disabled (oscillator is
stopped, and the controller enters the SLEEP2 mode) on the high-to-low transition and is enabled
(the controller is awakened from SLEEP2 mode) on low-to-high transition. In order to ensure the
stable output of the oscillator, once the oscillator is enabled again, there is a delay for approximately
18 ms (oscillator start-up timer (OST)) before the next program instruction is executed. The OST is
always activated by wake-up from sleep mode whether the Code Option bit ENWDT is "0" or not.
After waking up, the WDT is enabled if Code Option ENWDT is "1". The block diagram of SLEEP2
mode and wake-up caused by input triggered is depicted in Fig. 5. The SLPC bit can be read and
written.
• Bit 5 (WDTE) Control bit used to enable Watchdog timer.
The WDTE bit can be used only if ENWDT, the CODE Option bit, is "1". If the ENWDT bit is "1", then
WDT can be disabled/enabled by the WDTE bit.
0: Disable WDT.
1: Enable WDT.
The WDTE bit is not used if ENWDT, the CODE Option bit ENWDT, is "0". That is, if the ENWDT bit
is "0", WDT is always disabled no matter what the WDTE bit is.
The WDTE bit can be read and written.
• Bit 6 (ODE) Open-drain control bit.
0: Both P76 and P77 are normally I/O pins.
1: Both P76 and P77 pins have the open-drain function inside.
The ODE bit can be read and written.
• Bits 1~2, and 7 Not used.
7. IOCF (Interrupt Mask Register)
7
-
6
-
5
-
4
-
3
TM1IE
2
SPIIE
1
EXIE
0
TCIE
• Bit 0 (TCIE) TCIF interrupt enable bit.
0: disable TCIF interrupt
1: enable TCIF interrupt
• Bit 1 (EXIE) EXIF interrupt enable bit.
0: disable EXIF interrupt
1: enable EXIF interrupt
• Bit 2 (SPIIE) SPI interrupt enable bit.
0: disable SPI interrupt
This specification is subject to change without prior notice.
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OTP ROM
1: enable SPI interrupt
• Bit 3 (TM1IE) TM1IE interrupt enable bit.
0: disable TM1IE interrupt
1: enable TM1IE interrupt
• Bits 4~7 Not used.
• Individual interrupt is enabled by setting its associated control bit in IOCF to "1".
• The IOCF Register could be read and written.
/WUE
Oscillator
Enable
Disable
/WUE
Reset
Q
Q
Clear
P D
R
CLK
C
L
VCC
Set
/WUE
8
from S/W
P60~P67
VCC
/WUE
/PHEN
4
P74~P75, P90~P91
Fig. 5 Block Diagram of Sleep Mode and Wake-up Circuits on I/O Ports
This specification is subject to change without prior notice.
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4.3 TCC/WDT Presacler
An 8-bit counter is available as prescaler for the TCC or WDT. The prescaler is available for either the
TCC or WDT only at any given time, and the PAB bit of CONT register is used to determine the
prescaler assignment. The PSR0~PSR2 bits determine the prescale ratio. The prescaler is cleared
each time the instruction is written to TCC under TCC mode. The WDT and prescaler, when assigned to
WDT mode, are cleared by the WDTC or SLEP instructions. Fig. 6 depicts the circuit diagram of
TCC/WDT.
• R1(TCC) is an 8-bit timer/counter. TCC will increase by one at every instruction cycle (without
prescaler).
• The watchdog timer is a free running on-chip RC oscillator. The WDT will keep running even when the
oscillator driver has been turned off (i.e. in sleep mode). During normal operation or sleep mode, a
WDT time-out (if enabled) will cause the device to reset. The WDT can be enabled or disabled any
time during the normal mode by software programming (if Code Option bit ENWDT is "1"). Refer to
WDTE bit of IOCE register. Without presacler, the WDT time-out period is approximately 18 ms 1.
4.4 I/O Ports
The I/O registers, from Port 5 to Port 9, are bi-directional tri-state I/O ports. P60~P67, P74~P75, and
P90~P91 provide internal pull-high. P60~P67, P74~P75, and P90~P95 provide
programmable
wake-up function through software. P76~P77 can have open-drain output by software control. P80~P81
are the R-option pins which are enabled by software. When the R-option function is used, it is
recommended that P80 and P81 are used as output pins. During R-option enabled state, P80 and P81
must be programmed as input pins. If an external resistor is connected to P80 (P81) for the R-option
function, the current consumption should be taken as an important factor in the applications for low
power consideration.
The I/O ports can be defined as "input" or "output" pins by the I/O control registers (IOC5~IOC9) under
program control. The I/O registers and I/O control registers are both readable and writable. The I/O
interface circuit is shown in Fig. 7. Note that the reading path source of input and output pins is different
when reading the I/O port.
1
NOTE: Vdd = 5V, set up time period = 16.2ms ± 5%
Vdd = 3V, set up time period = 18.0ms ± 5%
This specification is subject to change without prior notice.
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Data Bus
CLK(=Fosc/2)
1
M
U
X
SYNC
TCC(R1)
2 cycles
0
TCC overflow interrupt
PAB
0
WDT
1
M
U
X
8- b i t C o u n t e r
PSR0~PSR2
8 - to - 1 MUX
0
WDTE
1
PAB
MUX
(in IOCE)
WDT timeout
Fig. 6 Block Diagram of TCC WDT
PCRD
Q
P
D
R
Q
C
L
Q
P
R
CLK
PCWR
IOD
PORT
D
C CLK
Q
0
1
M
U
X
PDWR
L
PDRD
Fig. 7 (a) The Circuit of I/O Port and I/O Control Register
This specification is subject to change without prior notice.
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PCRD
VCC
ROC
Weakly
Pull-up
P
D
R
CLK
Q C
L
PORT
Q
Q
P
R D
C CLK
Q L
0
Rex*
1
M
U
X
PCWR
IOD
PDWR
PDRD
*The Rex is 560K ohm external resistor
Fig.7(b) The Circuit of I/O Port with R-option (P80, P81)
4.5 SERIAL PERIPHERAL INTERFACE MODE
1. Overview & Features
Overview:
Figures 8, 9, and 10 show how EM78P451 communicates with other devices through SPI module.
If EM78P451 is a master controller, it sends clock through the SCK pin. A couple of 8-bit data are
transmitted and received at the same time. However, if EM78P451is defined as a slave, its SCK
pin could be programmed as an input pin. Data will continue to be shifted based on both the clock
rate and the selected edge.
Features:
• Operation in either Master mode or Slave mode,
• Three-wire or four-wire synchronous communication; that is, full duplex
• Programmable baud rates of communication,
• Programming clock polarity, (RD bit7)
• Interrupt flag available for the read buffer full,
This specification is subject to change without prior notice.
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• Up to 8 MHz ( maximum ) bit frequency,
SDO
SPIR Reg
Reg
SPIR
SPIW
SPIW Reg
Reg
/SS
SDI
SPIS Reg
SPI Module
Module
SPI
Bit 7
SCK
Master Device
Slave Device
Fig. 8 SPI Master/Slave Communication
SDI
SDO
SCK
/SS
Vdd
Master
P50
P51
P52
P53
SDO
SDI
SCK
/SS
SDO
SDI
SCK
/SS
SDO
SDI
SCK
/SS
SDO
SDI
SCK
/SS
Slave Device 1
Slave Device 2
Slave Device 3
Slave Device 4
Fig. 9 The SPI Configuration of Single-Master and Multi-Slave
This specification is subject to change without prior notice.
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SDI
SDO
SCK
/SS
SDI
SDO
SCK
/SS
Master1
or
Slave1
Master2
or
P50
Slave6
P51
P50
P51
P52
P53
P52
P53
SDI
SDO
Slave 4 for Master1/2
SCK
/SS
SDO
/SS
Slave 3 for Master 1/2
SDI
SCK
SDO
SDI
SCK
/SS
SDO
SDI
SCK
/SS
Slave 2 for master 1
Slave 5 for Master 2
Fig. 10 The SPI Configuration of Single-Master and Multi-Slave
This specification is subject to change without prior notice.
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2. SPI Function Description
Read
RBF
RBFI
Write
SPIR
SE
reg
SPIW reg
Set to 1
Buffer Full Detector
shift right
SPIS reg
P92/SDI
bit 0
bit 7
SPIC reg
P93/SDO
Edge
Select
SBR0 ~SBR2
P95/ /SS
SBR2~SBR0
8
/ SS
Tsco
Noise
Filter
Clock Select
2
Prescaler
4, 8, 16, 32, 64
Edge
Select
P94/SCK
TMR1/2
SPIC bit6
Fig. 11 SPI Block Diagram
SPI
SPI Read Register
(0X0A)
/SS
SPI Write Register
(0X0B)
8-1 MUX
SPI Mode Select
Register
SDO
SDI
Shift Clock
SPI Shift Buffer
FOSC
2 1 0
SPIC
7~0
SPIWB
1 0
7 6 4 1 0
T1CON
SPIC
SPIS
2
4
INTC
SPIC
7~0
SPIRB
DATA BUS
Fig. 12 The Function Block Diagram of SPI Transmission
This specification is subject to change without prior notice.
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The following describes the function of each block and explains how to carry out the SPI
communication with the signals depicted in Fig.11 and Fig.12:
• P92/SDI:
Serial Data In.
• P93/SDO: Serial Data Out.
• P94/SCK: Serial Clock.
• P95//SS:
/Slave Select (Option). This pin (/SS) may be required during a slave mode.
• RBF:
Set by Buffer Full Detector, and reset in software.
• RBIF:
Set by Buffer Full Detector, and reset in software.
• Buffer Full Detector: Sets to 1 when an 8-bit shifting is completed.
• SSE:
Loads the data in SPIS register, and begin to shift
• SPIS reg.: Shifting byte in and out. The MSB is shifted first. Both the SPIS register and the SPIW
register are loaded at the same time. Once data are written, SPIS starts transmission / reception.
The received data will be moved to the SPIR register as the shifting of the 8-bit data is completed.
The RBF (Read Buffer Full) flag and the RBFI(Read Buffer Full Interrupt) flag are then set.
• SPIR reg.: Read buffer. The buffer will be updated as the 8-bit shifting is completed. The data must
be read before the next reception is completed. The RBF flag is cleared as the SPIR register reads.
• SPIW reg.: Write buffer. The buffer will deny any attempt to write until the 8-bit shifting is
completed.
The SSE bit will be kept in 1 if the communication is still undergoing. This flag must be cleared as the
shifting is completed. Users can determine if the next write attempt is available.
• SBRS2~SBRS0:
Programming the clock frequency/rates and sources.
• Clock Select: Selecting either the internal or external clock as the shifting clock.
• Edge Select:
Selecting the appropriate clock edges by programming the CES bit
3. SPI Signal & Pin Description
The detailed functions of the four pins, SDI, SDO, SCK, and /SS, which are shown in Fig. 9, are as
follows:
SDI/P92 (Pin 7):
• Serial Data In,
• Receive serially, the Most Significant Bit (MSB) first, Least Significant Bit (LSB) last,
• Defined as high-impedance, if not selected,
• Program the same clock rate and clock edge to latch on both the master and slave devices,
This specification is subject to change without prior notice.
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• The received byte will update the transmitted byte,
• Both the RBF and RBFIF bits (located in Register 0x0C) will be set as the SPI operation is
completed.
• Timing is shown in Fig.13 and14.
SDO/P93 (Pin 8):
• Serial Data Out,
• Transmit serially; the Most Significant Bit (MSB) first, Least Significant Bit (LSB) last,
• Program the same clock rate and clock edge to latch on both the master and slave devices,
• The received byte will update the transmitted byte,
• The CES (located in Register 0x0D) bit will be reset, as the SPI operation is completed.
• Timing is shown in Fig.13 and 14.
SCK/P94 (Pin 9):
• Serial Clock
• Generated by a master device
• Synchronize the data communication on both the SDI and SDO pins
• The CES (located in Register 0x0D) is used to select the edge to communicate.
• The SBR0~SBR2 (located in Register 0x0D) is used to determine the baud rate of
communication
• The CES, SBR0, SBR1, and SBR2 bits have no effect in the slave mode
• Timing is show in Fig.13 and 14
/SS/P95 (Pin 10):
• Slave Select; negative logic,
• Generated by a master device to signify the slave(s) to receive data,
• Goes low before the first cycle of SCK appears, and remains low until the last (eighth) cycle is
completed,
• Ignores the data on the SDI and SDO pins while /SS is high, because the SDO is no longer
driven.
• Timing is shown in Fig.13 and Fig. 14.
This specification is subject to change without prior notice.
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4. Programmed the related registers
As the SPI mode is defined, the related registers of this operation are shown in Table 2 and Table 3.
Table 2 Related Control Registers of the SPI Mode
Address
Name
0x0D
*SPIC/RD
0x0F INTC/IOCF
Bit 7
CES
--
Bit 6
SPIE
--
Bit 5
SRO
--
Bit 4
SSE
--
Bit 3
-TM1IE
Bit 2
SBR2
SPIIE
Bit 1
SBR1
EXIE
Bit 0
SBR0
TCIE
• SPIC: SPI Control Register.
• CES (bit 7): Clock Edge Select bit
1 = Data shifts out on falling edge, and shifts in on rising edge. Data is on hold during the high level.
0 = Data shifts out on rising edge, and shifts in on falling edge. Data is on hold during the low level.
• SPIE (bit 6):SPI Enable bit
1 = Enable SPI mode
0 = Disable SPI mode
• SRO (bit 5):SPI Read Overflow bit
1 = A new data is received while the previous data is still being on hold in the SPIB register. Under
this condition, the data in SPIS register will be destroyed. To avoid setting this bit, users should read
the SPIRB register even if the transmission is implemented only.
0 = No overflow.
<Note>:This can only occur under slave mode.
• SSE (bit 4):SPI Shift Enable bit
1 = Start to shift, and stays on 1 while the current byte continues to transmit.
0 = Reset as soon as the shifting is completed and the next byte is ready to shift.
<Note>:
This bit can be reset by hardware only.
• SBRS (bit 2~0): SPI Baud Rate Select Bits
SBRS2 (Bit 2)
0
0
0
0
1
1
1
1
<Note>
SBRS1 (Bit 1)
0
0
1
1
0
0
1
1
SBRS0 (Bit 0)
0
1
0
1
0
1
0
1
Mode
Master
Master
Master
Master
Master
Slave
Slave
Master
Baud Rate
Fsco/2
Fsco/4
Fsco/8
Fsco/16
Fsco/32
/SS enable
/SS disable
TMR1/2
In master mode, /SS is disable.
• INTC: Interrupt control register
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• Bit 3 (TM1IE) TM1IE interrupt enable bit.
0: disable TM1IE interrupt
1: enable TM1IE interrupt
• Bit 2 (SPIIE) SPI interrupt enable bit.
0: disable SPI interrupt
1: enable SPI interrupt
• Bit 1 (EXIE) EXIF interrupt enable bit.
0: disable EXIF interrupt
1: enable EXIF interrupt
• Bit 0 (TCIE) TCIF interrupt enable bit.
0: disable TCIF interrupt
1: enable TCIF interrupt
Table 3 Related Status/Data Registers of the SPI Mode
Address
0X0A
0x0B
0x0C
Name
SPIRB/RA
SPIWB/RB
SPIS/RC
Bit 7
SRB7
SWB7
0
Bit 6
SRB6
SWB6
0
Bit 5
SRB5
SWB5
0
Bit 4
SRB4
SWB4
TM1IF
Bit 3
SRB3
SWB3
OD3
Bit 2
SRB2
SWB2
OD4
Bit 1
SRB1
SWB1
RBFIF
Bit 0
SRB0
SWB0
RBF
• SPIRB: SPI Read Buffer. Once the serial data is received completely, it will load to SPIRB from
SPISR. The RBF bit and the RBFIF bit in the SPIS register will be set also.
• SPIWB: SPI Write Buffer. As a transmitted data is loaded, the SPIS register stands by and start to
shift the data when sensing SCK edge with SSE set to “1”.
• SPIS: SPI Status register
• TM1IF (bit 4):Timer1 interrupt flag.
• OD3 (bit 3):Open-Drain Control bit (P93)
1 = Open-drain enable for SDO,
0 = Open-drain disable for SDO.
• OD4 (bit 2):Open Drain-Control bit (P94)
1 = Open-drain enable for SCK,
0 = Open-drain disable for SCK.
• RBFIF (bit 1):Read Buffer Full Interrupt flag
1 = Receive is completed, SPIB is full, and an interrupt occurs if enabled.
0 = Receive is ongoing, SPIB is empty.
• RBF (bit 0):Read Buffer Full flag
1 = Receive is completed, SPIB is full.
This specification is subject to change without prior notice.
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0 = Receive is ongoingt, SPIB is empty.
5. SPI Mode Timing
The edge of SCK is selected by programming bit CES. The waveform shown in Fig.13 is applicable
regardless of whether the EM78P451 is under master or slave mode with /SS disabled. However, The
waveform in Fig. 14 can only be implemented in slave mode with /SS enabled.
Fig. 13 SPI Mode with /SS Disable
Fig. 14
This specification is subject to change without prior notice.
SPI Mode with /SS Enable
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6. Software Application of SPI
Example for SPI:
For Master
ORG 0X0
SETTING:
CLRA
IOW 0X05
;SET PORT5 OUTPUT
IOW 0X06
;SET PORT6 OUTPUT
MOV 0X05,A
MOV A,@0B11001111 ;SET PRESCALER FOR WDT
CONTW
MOV A,@0B00010001 ;DISABLE WAKEUP FUNCTION
IOW 0X0E
MOV A,@0B00000000 ;DISABLE INTERRUPT
IOW 0X0F
MOV A,@0X07
;SDI INPUT AND SDO, SCK
OUTPUT
IOW 0X09
MOV A,@0B10000000 ;CLEAR RBF AND RBFIF FLAG
MOV 0X0C,A
MOV A,@0B11100000 ;SELECT CLOCK EDGE AND ENABLE SPI
MOV 0X0D,A
START:
WDTC
BC 0X0C,1
;CLEAR RBFIF FLAG
MOV A,@0XFF
MOV 0X05,A
;SHOW A SIGNAL AT PORT5
MOV 0X0A,A
;MOVE FF AT READ BUFFER
MOV A,@0XAA
;MOVE AA AT WRITE BUFFER
MOV 0X0B,A
BS 0X0D,4
;START TO SHIFT SPI DATA
NOP
JBC 0X0D,4
;POLLING LOOP FOR CHECKING SPI TRANSMISSION COMPLETED
JMP $-2
This specification is subject to change without prior notice.
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BC 0X03,2
CALL DELAY
;TO CATCH THE DATA FROM SLAVER
MOV A,0X0A
XOR A,@0X5A
;COMPARE THE DATA FROM SLAVER
JBS 0X03,2
JMP START
FLAG:
MOV A,@0X55
;SHOW THE SIGNAL WHEN RECEIVING CORRECT DATA FROM SLAVER
MOV 0X05,A
CALL DELAY
JMP START
DELAY:
; (USER’S PROGRAM)
EOP
ORG 0XFFF
JMP SETTING
This specification is subject to change without prior notice.
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For Slaver
ORG 0X0
INITI:
JMP INIT
ORG 0X2
INTERRUPT:
;INTERRUPT ADDRESS
MOV A,@0X55
MOV 0X06,A
;SHOW A SIGNAL AT PORT 6 WHEN ENTERING INTERRUPT
MOV A,@0B11100110 ;ENABLE SPI, /SS
DISABLED
MOV 0X0D,A
BS 0X0D,4
;KEEP SSE AT 1 TO WAIT FOR SCK SIGNAL IN ORDER TO SHIFT DATA
MOV A,@0X00
;MOVE 00 TO WRITE BUFFER IN ORDER TO KEEP MASTER’S READ BUFFER AS 00
MOV 0X0B,A
BS 0X0D,4
;KEEP SSE AT 1 TO WAIT FOR SCK SIGNAL IN ORDER TO SHIFT DATA
NOP
JBC 0X0D,4
;POLLING LOOP FOR CHECKING SPI TRANSMISSION COMPLETED
JMP $-2
BS 0X0D,4
;KEEP SSE AT 1 TO WAIT FOR SCK SIGNAL IN ORDER TO SHIFT DATA
BC 0X03,2
MOV A,0X0A
MOV 0X06,A
;READ MASTER’S DATA FROM READ BUFFER
XOR A,@0XAA
;CHECK PASS SIGNAL FROM READ BUFFER
JBS 0X03,2
JMP $-6
JMP SPI
ORG 0X30
INIT:
CLRA
IOW 0X05
IOW 0X06
MOV 0X05,A
MOV 0X06,A
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MOV A,@0XFF
IOW 0X08
MOV A,@0B11001111 ;SET PRESCALER FOR WDT
CONTW
MOV A,@0B00010001 ;DISABLE WAKEUP FUNCTION
IOW 0X0E
MOV A,@0B00000010 ;ENABLE EXTERNAL INTERRUPT
IOW 0XF
ENI
MOV A,@0B00110111
IOW 0X09
BC 0X3F,1
;CLEAR RBFIF FLAG
NOP
JBS 0X3F,1
;POLLING LOOP FOR CHECKING INTERRUPT OCCURENCE
JMP $-2
JMP INTERRUPT
SPI:
BS 0X0D,4
;KEEP SSE ENABLED AS LONG AS POSSIBLE
WDTC
MOV A,@0X0F
;SHOW A SIGNAL WHEN ENTERING SPI LOOP
MOV 0X06,A
JBC 0X08,1
;CHOOSE P81 AS A SIGNAL BUTTON
JMP SPI
MOV A,@0X5A
;MOVE 5A INTO WRITE BUFFER WHEN P81 BUTTON IS PUSHED
MOV 0X0B,A
NOP
JBC 0X0D,4
;POLLING LOOP FOR CHECKING SPI TRANSMISSION COMPLETED
JMP $-2
BS 0XD,4
NOP
NOP
MOV A,@0XF0
;DISPLAY AT PORT6 WHEN P81 BUTTON IS PUSHED
MOV 0X06,A
MOV A,@0X00
;SEND A SIGNAL TO MASTER TO PREVENT INFINITE LOOP
This specification is subject to change without prior notice.
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MOV 0X0B,A
NOP
JBC 0X0D,4
JMP $-2
BS 0X0D,4
BS 0X0C,7
BC 0X0C,1
NOP
JMP SPI
DELAY:
; (USER’S PROGRAM)
EOP
ORG 0XFFF
JMP INITI
This specification is subject to change without prior notice.
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4.6 Timer 1
1. Overview
Timer1(TMR1) is an eight-bit clock counter with a programmable prescaler. It is designed for the SPI
module as a baud rate clock generator. TMR1 can be read and written and cleared on any reset
conditions. If employed, it can be turned down for power saving by setting TMR1EN bit [T1CON<2>]
to 0.
2. Function description
Fig. 15 shows TIMER1 block diagram. Each signal and block is described as follows:
Fig. 15 TIMER1 Block Diagram
• OSC/4:
Input clock.
• Prescaler: Option of 1:1, 1:4, 1:8, and 1:16 defined by T1P1 and T1P02 (T1CON<1, 0>). It is
cleared when a value is written to TMR1 or T1CON, and during any kind of reset as well.
• PWP: Pulse width preset register. The desired width of baud clock is written in advance.
• TMR1: Timer 1 register. TMR1 increases until it matches with PWP, and then resets to 0. If it is
chosen optionally in the SPI mode, its output is fed as a shifting clock.
• Comparator: To change the output status while a match occurs. The TMR1IF flag will be set at the
same time.
3. Programmed the related registers
The related registers of the defining TMR1 operation are shown in Table 4 and Table 5
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Table 4 Related Control Registers of the TMR1
Address
Name
0x0C
SPIS/RC
0x0F
INTC/IOCF
Bit 7
0
0
Bit 6
0
0
Bit 5
0
0
Bit 4
TM1IF
0
Bit 3
OD3
TM1IE
Bit 2
OD4
SPIIE
Bit 1
RBFIF
EXIE
Bit 0
RBF
TCIE
Bit 4
TMR14
PWP4
0
Bit 3
TMR13
PWP3
0
Bit 2
TMR12
PWP2
TM1E
Bit 1
TMR11
PWP1
TM1P1
Bit 0
TMR10
PWP0
TM1P0
Table 5 Related Status/Data Registers ofTMR1
Address
Name
Bit 7
0X0E
TMR1/RE
TMR17
0x0F
PWP/RF
PWP7
0x0C T1CON/IOCC
0
Bit 6
TMR16
PWP6
0
Bit 5
TMR15
PWP5
0
• TMR1: Timer1 Register
TMR17~TMR10 is bit set of Timer1 register and it increases until the value matches PWP and then
it reset to 0.
• PWP: Pulse Width Preset Register
PWP7~PWP0 is bit set of pulse width preset for the desired width of baud clock in advance.
• T1CON: Timer1 Control Register
TM1E (bit2): Timer1 enable bit
TM1P1 and TM1P0 (bit1~0): Timer1 prescaler for FSCO
TM1P1
TM1P0
Prescaler Rate
0
0
1:1
0
1
1:4
1
0
1:8
1
1
1:16
This specification is subject to change without prior notice.
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4.7 RESET and Wake-up
A RESET is initiated by
(1) Power on reset, or
(2) WDT timeout. (if enabled)
VDD
D
Oscillator
Q
CLK
CLK
CLR
Poweron Reset
Voltage
Detector
WDTE
Setup
Time
WDT timeout
WDT
Reset
Fig. 16 Block Diagram of Reset
The device is kept in a RESET condition for a period of approx. 18ms 1 (one oscillator start-up timer
period) after the reset is detected and Fig.16 is the block diagram of reset. Once the RESET occurs,
the following functions are performed.
• The oscillator is running, or will be started.
• The Program Counter (R2) is set to all "1".
• When power is switched on, bits 5~6 of R3 and the upper 2 bits of R4 are cleared.
• All I/O port pins are configured as input mode (high-impedance state).
• The Watchdog timer and prescaler are cleared.
• The Watchdog timer is enabled if Code Option bit ENWDT is "1".
• The CONT register is set to all "1" except bit 6 (INT flag).
• Bits 3,6 of IOCE register are cleared, bits 0,4~5 of IOCE register are set to "1".
1
NOTE: Vdd = 5V, set up time period = 16.2ms ± 5%
Vdd = 3V, set up time period = 18.0ms ± 5%
This specification is subject to change without prior notice.
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• Bits 0 of R3F and bits 0 of IOCF registers are cleared.
The sleep mode (power down) is achieved by executing the SLEP instruction (named as SLEEP1
MODE). While entering sleep mode, the WDT (if enabled) is cleared but keeps on running. The
controller is awakened by WDT timeout (if enabled), and it will cause the controller to reset. The T and
P flags of R3 are used to determine the source of the reset (wake-up).
In addition to the basic SLEEP1 MODE, EM78P451 has another sleep mode (caused by clearing
"SLPC" bit of IOCE register, designated as SLEEP2 MODE). In the SLEEP2 MODE, the controller
can be awakened by(a) Any one of the wake-up pins is set to “0.” (refer to Fig.17). Upon waking, the controller will
continue to execute the program in-line. In this case, before entering SLEEP2 MODE, the wake-up
function of the trigger sources (P60~P67, P74~P75, and P90~P91)should be selected (e.g. input
pin) and enabled (e.g. pull-high, wake-up control). One caution should be noted is that after waking
up, the WDT is enabled if Code Option bit ENWDT is "1". The WDT operation (to be enabled or
disabled) should be appropriately controlled by software after waking up.
(b) WDT time-out (if enabled). On wake-up, will cause the controller reset.
Table 6 The Summary of the Initialized Values for Registers
Address
Name
N/A
IOC5
N/A
IOC6
N/A
IOC7
N/A
IOC8
N/A
IOC9
N/A
CONT
Reset Type
Bit 7
Bit 6
Bit Name
C57
C56
Power-On
1
1
/RESET and WDT
1
1
Wake-Up from Pin Change
P
P
Bit Name
C67
C66
Power-On
1
1
/RESET and WDT
1
1
Wake-Up from Pin Change
P
P
Bit Name
C77
C76
Power-On
1
1
/RESET and WDT
1
1
Wake-Up from Pin Change
P
P
Bit Name
C87
C86
Power-On
1
1
/RESET and WDT
1
1
Wake-Up from Pin Change
P
P
Bit Name
C97
C96
Power-On
1
1
/RESET and WDT
1
1
Wake-Up from Pin Change
P
P
Bit Name
/PHEN /INT
Power-On
1
0
/RESET and WDT
1
P
Wake-Up from Pin Change
P
P
Bit Name
-
This specification is subject to change without prior notice.
35
Bit 5
C55
1
1
P
C65
1
1
P
C75
1
1
P
C85
1
1
P
C95
1
1
P
1
1
P
-
Bit 4
C54
1
1
P
C64
1
1
P
C74
1
1
P
C84
1
1
P
C94
1
1
P
1
1
P
-
Bit 3
C53
1
1
P
C63
1
1
P
C73
1
1
P
C83
1
1
P
C93
1
1
P
PAB
1
1
P
-
Bit 2
Bit 1
Bit 0
C52
C51
C50
1
1
1
1
1
1
P
P
P
C62
C61
C60
1
1
1
1
1
1
P
P
P
C72
C71
C70
1
1
1
1
1
1
P
P
P
C82
C81
C80
1
1
1
1
1
1
P
P
P
C92
C91
C90
1
1
1
1
1
1
P
P
P
PSR2 PSR1 PSR0
1
1
1
1
1
1
P
P
P
2002/03/01
EM78P451
OTP ROM
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
R0(IAR)
Power-On
U
U
U
U
U
U
U
U
/RESET and WDT
P
P
P
P
P
P
P
P
Wake-Up from Pin Change
P
P
P
P
P
P
P
P
Bit Name
R1(TCC)
Power-On
0
0
0
0
0
0
0
0
/RESET and WDT
0
0
0
0
0
0
0
0
Wake-Up from Pin Change
P
P
P
P
P
P
P
P
Bit Name
R2(PC)
Power-On
1
1
1
1
1
1
1
1
/RESET and WDT
1
1
1
1
1
1
1
1
Wake-Up from Pin Change
**P
**P
**P
**P
**P
**P
**P
**P
Bit Name
GP
PS1
PS0
T
P
Z
DC
C
R3(SR)
Power-On
0
0
0
t
t
U
U
U
/RESET and WDT
0
0
0
t
t
P
P
P
Wake-Up from Pin Change
P
P
P
t
t
P
P
P
Bit Name
RSR.1 RSR.0
R4(RSR)
Power-On
0
0
U
U
U
U
U
U
/RESET and WDT
0
0
P
P
P
P
P
P
Wake-Up from Pin Change
P
P
P
P
P
P
P
P
Bit Name
P57
P56
P55
P54
P53
P52
P51
P50
R5(P5)
Power-On
U
U
U
U
U
U
U
U
/RESET and WDT
P
P
P
P
P
P
P
P
Wake-Up from Pin Change
P
P
P
P
P
P
P
P
Bit Name
P67
P66
P65
P64
P63
P62
P61
P60
R6(P6)
Power-On
U
U
U
U
U
U
U
U
/RESET and WDT
P
P
P
P
P
P
P
P
Wake-Up from Pin Change
P
P
P
P
P
P
P
P
Bit Name
P77
P76
P75
P74
P73
P72
P71
P70
R7(P7)
Power-On
U
U
U
U
U
U
U
U
/RESET and WDT
P
P
P
P
P
P
P
P
Wake-Up from Pin Change
P
P
P
P
P
P
P
P
Bit Name
P87
P86
P85
P84
P83
P82
P81
P80
R8(P8)
Power-On
U
U
U
U
U
U
U
U
/RESET and WDT
P
P
P
P
P
P
P
P
Wake-Up from Pin Change
P
P
P
P
P
P
P
P
Bit Name
P97
P96
P95
P94
P93
P92
P91
P90
R9(P9)
Power-On
U
U
U
U
U
U
U
U
/RESET and WDT
P
P
P
P
P
P
P
P
Wake-Up from Pin Change
P
P
P
P
P
P
P
P
Bit Name
SRB7 SRB6 SRB5 SRB4 SRB3 SRB2 SRB1 SRB0
RA(SPIRB)
Power-On
U
U
U
U
U
U
U
U
/RESET and WDT
P
P
P
P
P
P
P
P
Wake-Up from Pin Change
P
P
P
P
P
P
P
P
Bit Name
SWB7 SWB6 SWB5 SWB4 SWB3 SWB2 SWB1 SWB0
RB(SPIWB)
Power-On
U
U
U
U
U
U
U
U
/RESET and WDT
P
P
P
P
P
P
P
P
Wake-Up from Pin Change
P
P
P
P
P
P
P
P
ENSD
Bit Name
OBDC IBDC
TIIF
OD3 OD4 RBFIF RBF
O
RC(SPIS)
Power-On
0
0
0
0
0
0
0
0
/RESET and WDT
0
0
0
0
0
0
0
0
Wake-Up from Pin Change
P
P
P
P
P
P
P
P
SBRS SBRS SBRS
Bit Name
CES SPIE SRO SPISE
2
1
0
This specification is subject to change without prior notice.
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OTP ROM
0x0D
RD(SPIC)
Power-On
/RESET and WDT
Wake-Up from Pin Change
Bit Name
0x0E
RE(TMR1)
0x0F
RF(PWP)
0x3F
R3F(ISR)
0x0C
IOCC
0x0D
IOCD
0x0E
IOCE
0x0F
IOCF
0x10~0x3E
GPR
Power-On
/RESET and WDT
Wake-Up from Pin Change
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin Change
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin Change
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin Change
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin Change
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin Change
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin Change
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin Change
0
0
0
0
0
0
0
0
0
0
0
0
0
0
P
P
P
P
P
P
P
TMR1 TMR1 TMR1 TMR1 TMR1 TMR1 TMR1
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
P
P
P
P
P
P
P
PWP7 PWP6 PWP5 PWP4 PWP3 PWP2 PWP1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
P
P
P
P
P
P
P
T1IF SPIIF EXIF
U
U
U
U
0
0
0
U
U
U
U
0
0
0
U
U
U
U
P
P
P
T1E T1P1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
P
P
P
P
P
P
P
S7
/PU9 /PU8 /PU6
1
1
1
1
1
1
1
1
1
1
1
1
1
1
P
P
P
P
P
P
P
ODE WTE SLPC ROC
U
0
1
1
0
U
U
U
0
1
1
0
U
U
U
P
1
1
P
U
U
T1IE SPIIE EXIE
U
U
U
U
0
0
0
U
U
U
U
0
0
0
U
U
U
U
P
P
P
U
U
U
U
U
U
U
P
P
P
P
P
P
P
P
P
P
P
P
P
P
0
0
P
TMR1
0
0
0
P
PWP0
1
1
P
TCIF
0
0
P
T1P0
0
0
P
/PU5
1
1
P
/WUE
1
1
P
TCIE
0
0
P
U
P
P
** To execute the next instruction after the ”SLPC” bit status of IOCE register being on high-to-low transition.
X: Not used.
U: Unknown or don’t care.P: Previous value before reset.
t: Check Table 7
The Status of RST, T, and P of STATUS Register
A RESET condition is initiated by the following events:
1. A power-on condition,
2. Watchdog timer time-out.
The values of T and P, listed in Table 7 are used to check how the processor wakes up.
Table 8 shows the events that may affect the status of T and P.
This specification is subject to change without prior notice.
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OTP ROM
Table 7 The Values of RST, T and P After RESET
Reset Type
Power on
WDT during Operating mode
WDT wake-up during SLEEP1 mode
WDT wake-up during SLEEP2 mode
Wake-Up on pin change during SLEEP2 mode
T
1
0
0
0
P
P
1
P
0
P
P
*P: Previous value before reset
Table 8 The Status of RST, T and P Being Affected by Events
Event
Power on
WDTC instruction
WDT time-out
SLEP instruction
Wake-Up on pin change during SLEEP2 mode
T
1
1
0
1
P
P
1
1
*P
0
P
*P: Previous value before reset
4.8 Interrupt
The EM78P451 has the following interrupts.
1. /TCC overflow interrupt
2. External interrupt (/INT)
3. Serial Peripheral Interface (SPI) transmission completed interrupt.
4. Timer1 comparator completed interrupt.
R3F is the interrupt status register, which records the interrupt request in flag bit. IOCF is the interrupt
mask register. Global interrupt is enabled by ENI instruction and is disabled by DISI instruction. When
one of the interrupts (if enabled) is generated, will cause the next instruction to be fetched from address
001H. Once in the interrupt service routine the source of the interrupt can be determined by polling the
flag bits in the R3F register. The interrupt flag bit must be cleared by software before leaving the
interrupt service routine and enabling interrupts to avoid recursive interrupts.
The flag in the Interrupt Status Register (R3F) is set regardless of the status of its mask bit or the
execution of ENI instruction. Note that reading R3F will obtain the output of logic AND of R3F and IOCF
(refer to Fig. 17). The RETI instruction exits interrupt routine and enables the global interrupt (execution
of ENI instruction).
When an interrupt is generated by INT instruction (if enabled), it causes the next instruction to be
This specification is subject to change without prior notice.
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EM78P451
OTP ROM
fetched from address 002H.
IRQn
P Q
R
CLK C
L Q
D
/IRQn
R3F
ENI/DISI
Q
Q
RESET
interrupt
IRQm
RFRD
P
D
R
C CLK
L
IOD
IOCFWR
IOCF
IOCFRD
RFWR
Fig. 17 Interrupt Input Circuit
4.9 Oscillator
1. Oscillator Modes
The EM78P451 can operate in four different oscillator modes. There are high XTAL (HXT) oscillator
mode, low XTAL (LXT) oscillator mode, External RC oscillator mode (ERC), and Internal C、External
R oscillator modes. User can select one of them by programming MS, RCT, IRC, HLF and HLP in the
Code Option Register. Table 9 depicts how these three modes are defined.
Table 9 Oscillator Modes by MS, IRC, RCT.
Mode
High XTAL Oscillator
Low XTAL Oscillator
External RC Oscillator
External R and Internal C Oscillator
MS
1
1
0
0
IRC
X
X
1
1
RCT
X
X
1
0
HLF
1
0
X
X
HLP
X
0
X
X
<Note> X: Don’t care
2. Crystal Oscillator/Ceramic Resonators (XTAL)
EM78P451 can be driven by an external clock signal through the OSCI pin as shown in Fig 18 below.
In the most applications, pin OSCI and pin OSCO is connected with a crystal or ceramic resonator to
generate oscillation. Fig 19 depicts such circuit. Table 10 provides the recommended values of C1
This specification is subject to change without prior notice.
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OTP ROM
and C2. Since each resonator has its own attribute, user should refer to its specification for
appropriate values of C1 and C2. RS, a serial resistor may be necessary for AT strip cut crystal or low
frequency mode.
OSCI
Ext. Clock
OSCO
EM78P451
Fig. 18 Circuit for External Clock Input
C1
OSCI
EM78P451
XTAL
OSCO
RS
C2
Fig. 19 Circuit for Crystal/Resonator
Table 10 Capacitor Selection Guide for Crystal Oscillator Ceramic Resonators
Oscillator Type
Frequency Mode
Ceramic Resonator
HXT
LXT
Crystal Oscillator
HXT
This specification is subject to change without prior notice.
Frequency
455 KHz
1.0 MHz
2.0 MHz
4.0 MHz
32.768 KHz
100 KHz
200 KHz
455 KHz
1.0 MHz
2.0 MHz
4.0 MHz
40
C1 (pF)
10~150
40~80
20~40
10~30
25
25
25
20~40
15~30
15
15
C2 (pF)
10~150
40~80
20~40
10~30
15
25
25
20~150
15~30
15
15
2002/03/01
EM78P451
OTP ROM
330
330
C
OSCI
7404
7404
7404
EM78P451
XTAL
Fig. 20 Circuit for Crystal/Resonator-Series Mode
4.7K
10K
VDD
OSCI
7404
7404
EM78P451
10K
XTAL
C1
C2
Fig. 21 Circuit for Crystal/Resonator-Parallel Mode
3. RC Oscillator Mode
For some applications that do not need a very precise timing calculation, the RC oscillator (Fig 22 &
Fig 23) offers a lot of cost savings. Nevertheless, it should be noted that the frequency of the RC
oscillator is influenced by the supply voltage, the values of the resistor (Rext), the capacitor (Cext),
and even by the operation temperature. Moreover, the frequency also changes slightly from one chip
to another due to the manufacturing process variation.
In order to maintain a stable system frequency, the values of the Cext should not be less than 20pF,
and that the value of Rext should not be greater than 1 M ohm. If they cannot be kept in this range, the
frequency is easily affected by noise, humidity, and leakage.
The smaller the Rext in the RC oscillator, the faster its frequency will be. On the contrary, for very low
This specification is subject to change without prior notice.
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OTP ROM
Rext values, for instance, 1 KΩ, the oscillator becomes unstable because the NMOS cannot
discharge the current of the capacitance correctly.
Based on the reasons above, it must be kept in mind that all of the supply voltage, the operation
temperature, the components of the RC oscillator, the package types, the way the PCB is layout, will
affect the system frequency.
VCC
Rext
OSCI
Cext
EM78P451
Fig. 22 Circuit for External RC Oscillator Mode
VCC
Rext
OSCI
EM78P451
Fig. 23 Circuit for External R, Internal C Oscillator Mode
Calibrate frequency of External RC oscillator (For reference only)
C ext
20pF
100pF
R ext
3.3K
5.1K
10K
100K
3.3K
5.1K
10K
100K
This specification is subject to change without prior notice.
Fosc @5.0V,25℃
3.4MHz
2.2MHz
1.3MHz
144KHz
1.39MHz
935KHz
500KHz
54.5KHz
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OTP ROM
3.3K
5.1K
10K
100K
300pF
740KHz
490KHz
255KHz
28KHz
Internal C, external R Table (For reference only)
External R (Ohm)
Fosc @5.0V, 25℃ (Hz)
10K
15K
20K
30K
12M
7.7M
5.7M
3.65M
51K
100K
150K
200K
2.24M
1.14M
749K
559K
510K
2M
3.3M
214K
56K
32.8K
4.10. Code Option Register :
Address
0xFFF
12
MS
11
10
ENWDT CLKS
9
PTB
8
HLF
7
RCT
6
HLP
5
4
DEL0 DEL1
3
ID3
2
ID2
1
ID1
0
ID0
• Bit 12 (MS): Oscillator type selection.
0: RC type
1: XTAL type
• Bit 11 (ENWDT): Watchdog Timer enabled.
0: Enable
1: Disable
• Bit 10 (CLKS): Clocks of each instruction cycle.
0: Two clocks
1: Four clocks
• Bit 9 (PTB): Protect bit.
0: Protect enabled
1: Protect disabled
• Bit 8 (HLF): XTAL frequency selection.
0: Low frequency (32.768KHz)
1: High frequency
This bit is useful only when Bit 12 (MS) is 1. When MS is 0, HLF must be 0.
This specification is subject to change without prior notice.
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OTP ROM
• Bit 7 (RCT): Resistor Capacitor.
0: internal RC
1: external RC
• Bit 6 (HLP): Power consumption selection.
0: Low power
1: High power
• Bit 5 ~ Bit 4: DEL1 and DEL0 (SDI) input delay time options.
DEL 1
1
0
1
DEL 0
1
1
0
Delay time
0 ns
50 ns
100 ns
• Bit3~0 (ID): User’s ID code.
• Procedures to configure the RC oscillators by programming the option code:
i. Enable External RC oscillator:
MS (0) -> IRC (1) -> RCT (1)
ii. Enable External R and Internal C oscillator:
•MS (0) -> IRC (1) -> RCT (0)
4.11 Instruction Set
Each instruction in the instruction set is a 13-bit word divided into an OP code and one or more
operands. All instructions are executed within one single instruction cycle (consisting of 2 oscillator
periods), unless the program counter is changed by(a) Executing the instruction "MOV R2,A", "ADD R2,A", "TBL", or any other instructions that write to
R2 (e.g. "SUB R2,A", "BS R2,6", "CLR R2", ⋅⋅⋅⋅).
(b) execute CALL, RET, RETI, RETL, JMP, Conditional skip (JBS, JBC, JZ, JZA, DJZ, DJZA) which
were tested to be true.
Under these cases, the execution takes two instruction cycles.
In addition, the instruction set has the following features:
(1). Every bit of any register can be set, cleared, or tested directly.
(2). The I/O register can be regarded as general register. That is, the same instruction can operate
on I/O register.
The symbol "R" represents a register designator that specifies which one of the registers (including
operational registers and general purpose registers) is to be utilized by the instruction. Bits 6 and 7 in
R4 determine the selected register bank. "b" represents a bit field designator that selects the value for
This specification is subject to change without prior notice.
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OTP ROM
the bit located in the register "R" and affects operation. "k" represents an 8 or 10-bit constant or literal
value.
HEX
0000
0001
0002
0003
0004
000r
0010
0011
0012
MNEMONIC
NOP
DAA
CONTW
SLEP
WDTC
IOW R
ENI
DISI
RET
0 0000 0001 0011
0013
RETI
0 0000 0001 0100
0 0000 0001 rrrr
0014
001r
CONTR
IOR R
0 0000 0010 0000
0020
TBL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
00rr
0080
00rr
01rr
01rr
01rr
01rr
02rr
02rr
02rr
02rr
03rr
03rr
03rr
03rr
04rr
04rr
04rr
04rr
05rr
05rr
05rr
05rr
MOV R,A
CLRA
CLR R
SUB A,R
SUB R,A
DECA R
DEC R
OR A,R
OR R,A
AND A,R
AND R,A
XOR A,R
XOR R,A
ADD A,R
ADD R,A
MOV A,R
MOV R,R
COMA R
COM R
INCA R
INC R
DJZA R
DJZ R
0 0110 00rr rrrr
06rr
RRCA R
0 0110 01rr rrrr
06rr
RRC R
0 0110 10rr rrrr
06rr
RLCA R
0 0110 11rr rrrr
06rr
RLC R
0 0111 00rr rrrr
07rr
SWAPA R
0
0
0
0
0
0
0
0
0
INSTRUCTION BINARY
0000 0000 0000
0000 0000 0001
0000 0000 0010
0000 0000 0011
0000 0000 0100
0000 0000 rrrr
0000 0001 0000
0000 0001 0001
0000 0001 0010
0000
0000
0000
0001
0001
0001
0001
0010
0010
0010
0010
0011
0011
0011
0011
0100
0100
0100
0100
0101
0101
0101
0101
01rr
1000
11rr
00rr
01rr
10rr
11rr
00rr
01rr
10rr
11rr
00rr
01rr
10rr
11rr
00rr
01rr
10rr
11rr
00rr
01rr
10rr
11rr
rrrr
0000
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
This specification is subject to change without prior notice.
OPERATION
No Operation
Decimal Adjust A
A → CONT
0 → WDT, Stop oscillator
0 → WDT
A → IOCR
Enable Interrupt
Disable Interrupt
[Top of Stack] → PC
[Top of Stack] → PC,
Enable Interrupt
CONT → A
IOCR → A
R2+A → R2,
Bits 8~9 of R2 unchanged
A→ R
0→A
0→R
R-A → A
R-A → R
R-1 → A
R-1 → R
A ∨ VR → A
A ∨ VR → R
A&R→A
A&R→R
A⊕ R → A
A⊕ R → R
A+R→A
A+R→R
R→A
R→R
/R → A
/R → R
R+1 → A
R+1 → R
R-1 → A, skip if zero
R-1 → R, skip if zero
R(n) → A(n-1),
R(0) → C, C → A(7)
R(n) → R(n-1),
R(0) → C, C → R(7)
R(n) → A(n+1),
R(7) → C, C → A(0)
R(n) → R(n+1),
R(7) → C, C → R(0)
R(0-3) → A(4-7),
R(4-7) → A(0-3)
45
STATUS AFFECTED
None
C
None
T,P
T,P
None <Note1>
None
None
None
None
None
None <Note1>
Z,C,DC
None
Z
Z
Z,C,DC
Z,C,DC
Z
Z
Z
Z
Z
Z
Z
Z
Z,C,DC
Z,C,DC
Z
Z
Z
Z
Z
Z
None
None
C
C
C
C
None
2002/03/01
EM78P451
OTP ROM
HEX
07rr
07rr
07rr
0xxx
0xxx
0xxx
0xxx
MNEMONIC
SWAP R
JZA R
JZ R
BC R,b
BS R,b
JBC R,b
JBS R,b
1 00kk kkkk kkkk
1kkk
CALL k
1
1
1
1
1
1
1
1
1
1kkk
18kk
19kk
1Akk
1Bkk
1Ckk
1Dkk
1E02
1Fkk
JMP k
MOV A,k
OR A,k
AND A,k
XOR A,k
RETL k
SUB A,k
INT
ADD A,k
0
0
0
0
0
0
0
INSTRUCTION BINARY
0111 01rr rrrr
0111 10rr rrrr
0111 11rr rrrr
100b bbrr rrrr
101b bbrr rrrr
110b bbrr rrrr
111b bbrr rrrr
01kk
1000
1001
1010
1011
1100
1101
1110
1111
kkkk kkkk
kkkk kkkk
kkkk kkkk
kkkk kkkk
kkkk kkkk
kkkk kkkk
kkkk kkkk
0000 0010
kkkk kkkk
OPERATION
R(0-3) ↔ R(4-7)
R+1 → A, skip if zero
R+1 → R, skip if zero
0 → R(b)
1 → R(b)
if R(b)=0, skip
if R(b)=1, skip
PC+1 → [SP],
(Page, k) → PC
(Page, k) → PC
k→A
A∨ k→ A
A&k→A
A⊕ k→ A
k → A, [Top of Stack] → PC
k-A → A
PC+1 → [SP], 002H → PC
k+A → A
STATUS AFFECTED
None
None
None
None <Note2>
None <Note3>
None
None
None
None
None
Z
Z
Z
None
Z,C,DC
None
Z,C,DC
<Note1> This instruction is applicable to IOC5 ~ IOC9, IOCD~IOCF only.
<Note2> This instruction is not recommended for RF operation.
<Note3> This instruction cannot operate on R3F.
This specification is subject to change without prior notice.
46
2002/03/01
EM78P451
OTP ROM
4.12 Timing Diagrams
AC Test Input/Output Waveform
2.4
2.0
2.0
TEST POINTS
0.8
0.8
0.4
AC Testing : Input is driven at 2.4V for logic "1",and 0.4V for logic "0".Timing measurements are
made at 2.0V for logic "1",and 0.8V for logic "0".
RESET Timing (CLK="0")
NOP
Instruction 1
Executed
CLK
/RESET
Tdrh
TCC Input Timing (CLKS="0")
Tins
CLK
TCC
Ttcc
This specification is subject to change without prior notice.
47
2002/03/01
EM78P451
OTP ROM
5. ABSOLUTE MAXIMUM RATING
Items
Temperature under bias
Storage temperature
Input voltage
Output voltage
Operating Frequency (2clk)
Rating
to
to
to
to
to
0°C
-65°C
-0.3V
-0.3V
DC
This specification is subject to change without prior notice.
48
70°C
150°C
+6.0V
+6.0V
20MHz
2002/03/01
EM78P451
OTP ROM
6. ELECTRICAL CHARACTERISTICS
(1) DC Characteristic
(Ta=0°C~70°C, VDD=5V±5%, VSS=0V)
Symbol
FXT
FRC
IIL
VIH1
VIL1
VIHX1
VILX1
VIH2
VIL2
VIHX2
VILX2
VOH1
VOH2
VOH3
VOL1
VOL2
VOL3
Parameter
XTAL VDD to 2.3V
XTAL VDD to 3V
XTAL VDD to 5V
RC VDD to 2.3V
RC VDD to 3V
RC VDD to 5V
Input Leakage Current
Input High Voltage VDD=5V)
Input Low Voltage (VDD=5V)
Clock Input High Voltage
(VDD=5V)
Clock Input Low Voltage
(VDD=5V)
Input High Voltage(VDD=3V)
Input Low Voltage (VDD=3V)
Clock Input High Voltage
(VDD=3V)
Clock Input Low Voltage
(VDD=3V)
Output High Voltage
(Ports 5,6,8, P74~P77,
P90~P92,P95~P97,and
PF5~PF7)
Output High Voltage
(P70~P72)
Output High Voltage
(P93/SDO,P94/SCK)
Output Low Voltage
(Ports 5,6,8, P74~P77,
P90~P92,P95~P97,and
PF5~PF7))
Condition
Two clocks
Two clocks
Typ
VIN = VDD, VSS
Max
4
8
20
4
4
4
±1
2.0
0.8
OSCI
2.5
S7=1(IOCD Register bit7),
IOH = -7.0mA
S7=0(IOCD Register bit7),
IOH = -7.0mA
IOH = -5.0mA
0.4
V
2.4
Output Low Voltage
(P93/SDO, P94/SCK)
IOL = 7.0mA
49
V
V
2.4
V
2.4
2.4
V
IOL = 5.0mA
S7=1(IOCD Register bit7),
IOH = 10.0mA
S7=0(IOCD Register bit7),
IOH = 10.0mA
µA
V
V
V
V
0.6
2
MHz
V
1.5
OSCI
IOH = -8.0mA
MHz
1.0
1.5
OSCI
Unit
V
OSCI
Output Low Voltage
(P70~P72)
This specification is subject to change without prior notice.
Min
DC
DC
DC
DC
DC
DC
0.4
0.4
V
0.8
V
0.4
0.4
V
2002/03/01
EM78P451
OTP ROM
VOL4
IPH
IPH2
Output Low Voltage
(P74~P77)
Pull-high current
Pull-high current
(P74,P75)
ISB
Power down current
ICC
Operating supply current
IOL = 15.0mA
Pull-high active, input pin at VSS
0.4
-50
Pull-high active, input pin at VSS
-100
-240
1
µA
mA
All input and I/O pin at VDD, output
pin floating, WDT enabled
/RESET="High",
Fosc=1.84324MHz (CK2="0"),
output pin floating
10
µA
3
mA
(2) AC Characteristic
(Ta=0°C~70°C, VDD=5V±5%, VSS=0V)
Symbol
Dclk
Tins
Ttcc
Twdt
Tdrh
Parameter
Input CLK duty cycle
Instruction cycle time
(CK2="0")
TCC input period
Watchdog timer period
Device reset hold period
Conditions
Min
45
RC Type
500
Typ
50
(Tins+20)/N*
Ta=25°C
Ta=25°C
18
181
Max
55
Unit
%
DC
ns
ns
ms
ms
N= selected prescaler ratio.
1
NOTE: Vdd = 5V, set up time period = 16.2ms ± 5%
Vdd = 3V, set up time period = 18.0ms ± 5%
This specification is subject to change without prior notice.
50
2002/03/01
EM78P451
OTP ROM
7. Application Circuit
EM78P451
This specification is subject to change without prior notice.
51
2002/03/01
EM78P451
OTP ROM
APPENDIX
Package Types:
OTP MCU
EM78P451P
EM78P451AQ
Package Type
DIP
QFP
This specification is subject to change without prior notice.
Pin Count
40
44
52
Package Size
600 mil
2002/03/01