www.fairchildsemi.com FMS7857 Phase Locked Loop Clock Driver Features Frequency Range of 60 to 170 MHz 10 outputs at 2.5 Volts Less than 100 pS of Output to Output Skew Less than 60 pS of Cycle to Cycle Jitter Dedicated Power Down pin Power Supply at 2.5V ± 0.2V Commercial Temperature Range Available in 48 pin TSSOP Description FMS7857 is a zero delay clock buffer designed for high fan out applications. It has ten outputs with one dedicated output for feedback. All the outputs are connected to VDD at 2.5 Volts. To reduce ground bounce noise, the Phase Locked Loop (PLL) has a dedicated power supply pin (AVDD). For normal When the input frequency falls below a suggested detection frequency (less than 20 MHz), FMS7857 will enter the power down mode. FMS7857 is available in 48 pin TSSOP in commercial temperature range. Block Diagram VDD Q0 Q0 Q1 Q1 PWRDWN Q2 Q2 CONTROL LOGIC Q3 Q3 Q4 Q4 Q5 Q5 Q6 Q6 MUX CLK CLK PLL Q7 Q7 Q8 Q8 FBIN FBIN Q9 Q9 FBOUT FBOUT AVDD ADVANCED INFORMATION describes products that are not in full production at the time of printing. Specifications are based on design goals and limited characterization. They may change without notice. Contact Fairchild Semiconductor for current information. REV. 0.0.5 6/19/00 Advanced Information • • • • • • • • operation, AVDD must be connected to 2.5 Volts. In this mode, the PLL will compare the phase and frequency between the incoming clock and the feedback pin. First, it will adjust the frequency to the desired value, and then, the phase. The PLL has wide enough bandwidth to track any incoming clock with modulation of ±1% of the clock period. When AVDD is connected to GND, FMS7857 will be in clock buffer mode. In this mode, the PLL is shut off and the clock is bypassed for test proposes. Power down mode, when connected to GND, will shut the PLL off and all the outputs will be tri-stated. PRODUCT SPECIFICATION FMS7857 Pin Assignments Advanced Information 48 TSSOP GND Q0 Q0 VDD Q1 Q1 GND GND Q2 Q2 VDD VDD CLK CLK VDD AVDD AGND GND Q3 Q3 VDD Q4 Q4 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 FMS7857 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 GND Q5 Q5 VDD Q6 Q6 GND GND Q7 Q7 VDD PWRDWN FBIN FBIN VDD FBOUT FBOUT GND Q8 Q8 VDD Q9 Q9 GND Pin Description Pin Name Pin # Pin Type Description GND 1, 7, 8, 18, 24, 25, 31, 41, 42, 48 PWR Ground Connection. Connect all ground pins to the common system ground plane. VDD 4, 11, 12, 15, 21, 28, 34, 38, 45 PWR Power Connection. Power supply for all the outputs. Q(0:9) 3,5,10,20,22,27,29,3 9,44,46 OUT Clock Outputs. Clock outputs 0:9 are buffer clocks of input. Q(0:9) 2, 6, 9, 19, 23, 26, 30, 40, 43, 47 OUT Inverted Clock Outputs. Clock outputs 0:9 are buffer clocks of input. 37 IN Power Down. When low, all outputs are in high impedance, and PLL is shut off. Normal operation when asserted high. FBOUT/ FBOUT 32, 33 OUT FBIN/FBIN 36, 35 IN Feedback Clock Input.PLL feedback input. The user connects it to FBOUT to FBIN and FBOUT to FBIN. 16 PWR Power Connection. Power supply for PLL. Connect to 3.3V. When low, PLL is bypassed and CLK/CLK is directly connect to all the outputs. In this mode, the chip is a buffer. 13, 14 IN 17 PWR PWRDWN AVDD CLK/CLK AGND 2 Feedback Clock Output. Dedicated pin for FBIN. For proper operation, FBOUT/FBOUT must be connect of FBIN/FBIN, respectively. Input Clock. Input of PLL supplied by the user. Analog Ground Connection. Connect to common ground plane. REV. 0.0.5 6/19/00 FMS7857 PRODUCT SPECIFICATION Table 1. Functionality Table Outputs PLL Inputs AVDD PWRDWN CLK CLK Q(0:9) Q(0:9) FBOUT FBOUT PLL GND H L H L H L H Bypassed/Off GND H H L H L H L Bypassed/Off X L L H Z Z Z Z Off X L H L Z Z Z Z Off 2.5 V H L H L H L H On 2.5 V H H L H L H L On 2.5 V X Z Z Z Z Off <20 MHz <20 MHz Advanced Information REV. 0.0.5 6/19/00 3 PRODUCT SPECIFICATION FMS7857 Absolute Maximum Ratings Symbol Parameter Ratings Units VDD, VIN Voltage on any pin with respect to ground -0.5 to 4.6 V TSTG Storage Temperature -65 to 150 °C TB Ambient Temperature -55 to 125 °C TA Operating Temperature 0 to 70 °C Stresses greater than those listed in the table may cause permanent damage to the device. These represent a stress rating only. Operation of the device at these or any other conditions above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may effect reliability. Advanced Information DC Electrical Characteristics TA = 0 to 70°C; Supply Voltage 2.5 V ± 0.2V(unless otherwise stated) Parameter Symbol Input Low Voltage Conditions VIL MIN MAX Units VSS – 0.3 0.8 V 2.0 VDD + 0.3 V 0.5 V Input High Voltage VIH Output Low Voltage VOL IOL= 12 mA Output High Voltage VOH IOH= –12 mA 2.0 TYP V Input Low Current IIL VIN= 0 -10 10 µA Input High Current IIH VIN= VDD -10 10 µA Supply Current IDD PWRDWN = CLK < 20 MHz = 0 TBD Freq. = 133MHz; CL = 16 pF TBD Clock Stabilization(1) Input Capacitance(1) Output Capacitance(1) TSTAB From VDD = 2.5 V to 1% Target 100 µA mA 0.1 mS CI VDD = 2.5; VIN = 2.5V or GND 2 pF CO VDD = 2.5; VOUT = 2.5V or GND 3 pF Note: 1. Guaranteed by design, not subject to 100% production testing. AC Electrical Characteristics TA = 0 to 70°C; Supply Voltage VDD = 2.5V ± 0.2V, CL = 16 pF (unless otherwise stated) Parameter Symbol Clock Input Duty Cycle(1) Input Frequency Output Frequency Static Phase Error(1) Input to Output Delay(1) (1) Output Clock Skew Rise Time(1) (1) Fall Time MAX Units 40 60 % FIN 60 170 MHz FOUT 60 170 MHz TSK1 -50 50 pS 5.0 nS DT_IN Conditions PWRDWN = VDD; CLKIN > 20 MHz TSK2 AVDD = 0V; Clock Mode TSK3 VTH = VDD/2; (window) MIN 1.5 TYP 3.5 100 pS TR 20–80% 0 1.0 1.5 ns 1.0 1.5 ns TF 20–80% Duty Cycle(1) DT VTH = VDD/2 49 51 % Jitter (Cycle-Cycle)(1) TJIT VTH = VDD/2 -75 75 pS Note: 1. Guaranteed by design, not subject to 100% production testing. 4 REV. 0.0.5 6/19/00 FMS7857 PRODUCT SPECIFICATION Parameter Measurement Information Cycle-to-Cycle Jitter Yx, FBOUT Yx, FBOUT Tcycle n Tcycle n+1 Tjit = Tcycle n – Tcycle n+1 Static Phase Error Advanced Information CLK CLK FBIN FBIN Tsk1 Output to Output Skew Yx Yx Yx, FBOUT Yx, FBOUT Tsk3 REV. 0.0.5 6/19/00 5 PRODUCT SPECIFICATION FMS7857 Mechanical Dimensions 48-pin TSSOP Inches Advanced Information Symbol Min. Max. Min. A A1 B C D E e H — 0.002 0.007 0.47 0.006 0.006 nom 0.488 0.496 0.236 0.244 0.020 BSC 0.311 0.327 — 1.20 0.05 0.15 0.17 0.27 0.15 nom 12.40 12.60 6.00 6.20 0.50 BSC 7.90 8.30 L M 0.018 0.45 α ccc Notes: Millimeters 0.011 0.327 2. Falls within JEDEC MO-153. 0.75 0.001 nom 0° 8° 0.25 nom 0° 8° — — 0.004 1. Body dimensions do not include mold protrusion not to exceed 0.15. Max. 0.10 D E H C A1 A B e SEATING PLANE –C– LEAD COPLANARITY α L M ccc C 6 REV. 0.0.5 6/19/00 PRODUCT SPECIFICATION FMS7857 Ordering Information Product Number Packag FMS7857MTDT TSSOP-48 Advanced Information FMS7857MTD Tape & Reel DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com 6/19/00 0.0m 003 Stock#DS3007857 2000 Fairchild Semiconductor Corporation