a FEATURES Supports DOCSIS Standard for Reverse Path Transmission Gain Programmable in 0.75 dB Steps Over a 59.45 dB Range Low Distortion at 61 dBmV Output –57 dBc SFDR at 21 MHz –55 dBc SFDR at 42 MHz Output Noise Level –48 dBmV in 160 kHz Maintains 75 ⍀ Output Impedance Transmit Enable and Transmit Disable Modes Upper Bandwidth: 100 MHz (Full Gain Range) 5 V Supply Operation Supports SPI Interfaces 5 V CATV Line Driver Fine Step Output Power Control AD8325 FUNCTIONAL BLOCK DIAGRAM VCC (7 PINS) R1 VIN+ AD8325 VOUT+ DIFF OR SINGLE INPUT AMP VIN– BYP ATTENUATION CORE VERNIER POWER AMP VOUT– ZOUT DIFF = 75⍀ 8 DECODE R2 ZIN (SINGLE) = 800⍀ ZIN (DIFF) = 1.6k⍀ 8 DATA LATCH POWER-DOWN LOGIC 8 SHIFT REGISTER APPLICATIONS Gain-Programmable Line Driver DOCSIS High-Speed Data Modems Interactive Cable Set-Top Boxes PC Plug-in Cable Modems General-Purpose Digitally Controlled Variable Gain Block DATEN DATA CLK GND (11 PINS) TXEN SLEEP GENERAL DESCRIPTION The AD8325 is a low-cost, digitally controlled, variable gain amplifier optimized for coaxial line driving applications such as cable modems that are designed to the MCNS-DOCSIS upstream standard. An 8-bit serial word determines the desired output gain over a 59.45 dB range resulting in gain changes of 0.7526 dB/LSB. Distortion performance of –57 dBc is achieved with an output level up to 61 dBmV at 21 MHz bandwidth. A key performance and cost advantage of the AD8325 results from the ability to maintain a constant 75 Ω output impedance during Transmit Enable and Transmit Disable conditions. In addition, this device has a sleep mode function that reduces the quiescent current to 4 mA. VOUT = 62dBmV @ MAX GAIN –52 VOUT = 61dBmV @ MAX GAIN DISTORTION – dBc The AD8325 comprises a digitally controlled variable attenuator of 0 dB to –59.45 dB, which is preceded by a low noise, fixed gain buffer and is followed by a low distortion high power amplifier. The AD8325 accepts a differential or single-ended input signal. The output is specified for driving a 75 Ω load, such as coaxial cable. –50 –54 –56 –58 –60 VOUT = 60dBmV @ MAX GAIN –62 VOUT = 59dBmV @ MAX GAIN –64 5 15 25 35 45 55 FUNDAMENTAL FREQUENCY – MHz 65 Figure 1. Worst Harmonic Distortion vs. Gain Control The AD8325 is packaged in a low-cost 28-lead TSSOP, operates from a single 5 V supply, and has an operational temperature range of –40°C to +85°C. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2001 (T = 25ⴗC, V = 5 V, R = 75 ⍀, V AD8325–SPECIFICATIONS a 1:1 transformer with an insertion loss of 0.5 dB @ 10 MHz unless otherwise noted.) A S L IN (differential) = 31 dBmV, VOUT measured through 1 Parameter INPUT CHARACTERISTICS Specified AC Voltage Noise Figure Input Resistance Conditions Min Output = 61 dBmV, Max Gain Max Gain, f = 10 MHz Single-Ended Input Differential Input OUTPUT CHARACTERISTICS Bandwidth (–3 dB) Bandwidth Roll-Off Bandwidth Peaking Output Noise Spectral Density 1 dB Compression Point Differential Output Impedance OVERALL PERFORMANCE Second Order Harmonic Distortion Third Order Harmonic Distortion Adjacent Channel Power Gain Linearity Error Output Settling Due to Gain Change (TGS) Due to Input Change Isolation in Transmit Disable Mode Gain Code = 79 Dec Gain Code = 0 Dec 58.45 59.45 29.2 30.0 –30.25 –29.45 0.7526 Unit dBmV dB Ω Ω pF 60.45 dB 30.8 dB –28.65 dB dB/LSB All Gain Codes f = 65 MHz f = 65 MHz Max Gain, f = 10 MHz 100 1.6 0 –33 Min Gain, f = 10 MHz –48 Transmit Disable Mode, f = 10 MHz –68 Max Gain, f = 10 MHz Transmit Enable and Transmit Disable Modes 18.5 75 ± 20% MHz dB dB dBmV in 160 kHz dBmV in 160 kHz dBmV in 160 kHz dBm Ω f = 21 MHz, VOUT = 61 dBmV @ Max Gain f = 42 MHz, VOUT = 61 dBmV @ Max Gain f = 65 MHz, VOUT = 61 dBmV @ Max Gain f = 21 MHz, VOUT = 61 dBmV @ Max Gain f = 42 MHz, VOUT = 61 dBmV @ Max Gain f = 65 MHz, VOUT = 61 dBmV @ Max Gain Adjacent Channel Width = Transmit Channel Width = 160 KSYM/SEC f = 10 MHz, Code to Code –70 –67 –60 –57 –55 –54 –53.8 dBc dBc dBc dBc dBc dBc dBc ± 0.3 dB Min to Max Gain Max Gain, VIN = 31 dBmV Max Gain, TXEN = 0 V, f = 42 MHz, VIN = 31 dBmV 60 30 –33 ns ns dBc 300 40 3 50 ns ns mV p-p mV p-p POWER CONTROL Transmit Enable Settling Time (TON) Max Gain, VIN = 0 V Transmit Disable Settling Time (TOFF) Max Gain, VIN = 0 V Between Burst Transients2 Equivalent Output = 31 dBmV Equivalent Output = 61 dBmV POWER SUPPLY Operating Range Quiescent Current Max 31 13.8 800 1600 2 Input Capacitance GAIN CONTROL INTERFACE Gain Range Maximum Gain Minimum Gain Gain Scaling Factor Typ Transmit Enable Mode (TXEN = 1) Transmit Disable Mode (TXEN = 0) Sleep Mode OPERATING TEMPERATURE RANGE 4.75 123 30 2 –40 5 133 35 4 5.25 140 10 7 V mA mA mA +85 °C NOTES 1 TOKO 617DB-A0070 used for above specifications. MACOM ETC-1-IT-15 can be substituted. 2 Between Burst Transients measured at the output of a 42 MHz diplexer. Specifications subject to change without notice. –2– REV. 0 AD8325 LOGIC INPUTS (TTL/CMOS-Compatible Logic) (DATEN, CLK, SDATA, TXEN, SLEEP, V Parameter Min Logic “1” Voltage Logic “0” Voltage Logic “1” Current (VINH = 5 V) CLK, SDATA, DATEN Logic “0” Current (VINL = 0 V) CLK, SDATA, DATEN Logic “1” Current (VINH = 5 V) TXEN Logic “0” Current (VINL = 0 V) TXEN Logic “1” Current (VINH = 5 V) SLEEP Logic “0” Current (VINL = 0 V) SLEEP 2.1 0 0 –600 50 –250 50 –250 TIMING REQUIREMENTS CC Typ Max Unit 5.0 0.8 20 –100 190 –30 190 –30 V V nA nA µA µA µA µA (Full Temperature Range, VCC = 5 V, TR = TF = 4 ns, fCLK = 8 MHz unless otherwise noted.) Parameter Min Clock Pulsewidth (TWH) Clock Period (TC) Setup Time SDATA vs. Clock (TDS) Setup Time DATEN vs. Clock (TES) Hold Time SDATA vs. Clock (TDH) Hold Time DATEN vs. Clock (TEH) Input Rise and Fall Times, SDATA, DATEN, Clock (TR, TF) 16.0 32.0 5.0 15.0 5.0 3.0 Typ TDS VALID DATA WORD G1 MSB. . . .LSB SDATA VALID DATA WORD G2 TC TWH CLK TES TEH 8 CLOCK CYCLES DATEN GAIN TRANSFER (G1) GAIN TRANSFER (G2) TOFF TXEN TGS TON ANALOG OUTPUT SIGNAL AMPLITUDE (p-p) Figure 2. Serial Interface Timing VALID DATA BIT SDATA MSB MSB-1 TDS MSB-2 TDH CLK Figure 3. SDATA Timing REV. 0 = 5 V: Full Temperature Range) –3– Max Unit 10 ns ns ns ns ns ns ns AD8325 PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS* Supply Voltage +VS Pins 5, 9, 10, 19, 20, 23, 27 . . . . . . . . . . . . . . . . . . . . . . 6 V Input Voltages Pins 25, 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 0.5 V Pins 1, 2, 3, 6, 7 . . . . . . . . . . . . . . . . . . . . . –0.8 V to +5.5 V Internal Power Dissipation TSSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.9 W Operating Temperature Range . . . . . . . . . . . –40°C to +85°C Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Lead Temperature, Soldering 60 seconds . . . . . . . . . . . 300°C *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DATEN 1 28 SDATA 2 27 VCC CLK 3 26 VIN– GND 4 25 VIN+ VCC 5 24 GND TXEN 6 SLEEP 7 GND 8 VCC AD8325 GND 23 VCC 22 GND TOP VIEW (Not to Scale) 21 BYP 9 20 VCC VCC 10 19 VCC GND 11 18 GND GND 12 17 GND GND 13 16 GND OUT– 14 15 OUT+ ORDERING GUIDE Model Temperature Range Package Description JA Package Option AD8325ARU AD8325ARU-REEL AD8325-EVAL –40°C to +85°C –40°C to +85°C 28-Lead TSSOP 28-Lead TSSOP Evaluation Board 67.7°C/W* 67.7°C/W* RU-28 RU-28 *Thermal Resistance measured on SEMI standard 4-layer board. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8325 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Description 1 DATEN 2 SDATA 3 CLK 4, 8, 11, 12, 13, 16, 17, 18, 22, 24, 28 5, 9, 10, 19, 20, 23, 27 6 7 GND Data Enable Low Input. This port controls the 8-bit parallel data latch and shift register. A Logic 0-to-1 transition transfers the latched data to the attenuator core (updates the gain) and simultaneously inhibits serial data transfer into the register. A 1-to-0 transition inhibits the data latch (holds the previous gain state) and simultaneously enables the register for serial data load. Serial Data Input. This digital input allows for an 8-bit serial (gain) word to be loaded into the internal register with the MSB (Most Significant Bit) first. Clock Input. The clock port controls the serial attenuator data transfer rate to the 8-bit masterslave register. A Logic 0-to-1 transition latches the data bit and a 1-to-0 transfers the data bit to the slave. This requires the input serial data word to be valid at or before this clock transition. Common External Ground Reference. VCC Common Positive External Supply Voltage. A 0.1 µF capacitor must decouple each pin. TXEN SLEEP 14 15 21 25 OUT– OUT+ BYP VIN+ 26 VIN– Logic “0” disables transmission. Logic “1” enables transmission. Low Power Sleep Mode. Logic 0 enables Sleep mode, where ZOUT goes to 400 Ω and supply current is reduced to 4 mA. Logic 1 enables normal operation. Negative Output Signal. Positive Output Signal. Internal Bypass. This pin must be externally ac-coupled (0.1 µF cap). Noninverting Input. DC-biased to approximately VCC/2. Should be ac-coupled with a 0.1 µF capacitor. Inverting Input. DC-biased to approximately VCC/2. Should be ac-coupled with a 0.1 µF capacitor. –4– REV. 0 Typical Performance Characteristics–AD8325 34 VOUT = 61dBmV @ MAX GAIN CL= 0pF CL= 10pF 31 VCC GAIN – dB TOKO 617DB–A0070 1:1 0.1F VIN– VIN RL 75⍀ OUT– AD8325 165⍀ 28 CL= 20pF CL= 50pF 25 VCC TOKO617DB–A0070 1:1 OUT+ VIN+ 0.1F GND 0.1F VIN– 22 OUT– OUT+ VIN+ GND VIN 165⍀ CL RL 75⍀ 0.1F 19 TPC 1. Basic Test Circuit 1 100 TPC 4. AC Response for Various Cap Loads –30 0.5 f = 10MHz TXEN = 1 OUTPUT NOISE – dBmV IN 160kHz f = 10MHz 0 GAIN ERROR – dB 10 FREQUENCY – MHz f = 5MHz –0.5 f = 42MHz –1.0 –1.5 –34 –38 –42 –46 f = 65MHz –50 –2.0 0 10 20 30 50 60 40 GAIN CONTROL – Decimal 70 80 TPC 2. Gain Error vs. Gain Control 0 8 40 48 56 24 32 GAIN CONTROL – Decimal 16 72 80 TPC 5. Output Referred Noise vs. Gain Control 0 40 79D TXEN = 0 VIN = 31dBmV 30 –20 20 10 MAX GAIN 46D ISOLATION – dB GAIN – dB 64 0 23D –10 –20 –40 –60 00D –30 MIN GAIN –80 –40 –50 0.1 1 10 FREQUENCY – MHz 100 –100 0.1 1000 TPC 3. AC Response REV. 0 1 10 FREQUENCY – MHz 100 1000 TPC 6. Isolation in Transmit Disable Mode vs. Frequency –5– AD8325 180 –55 170 VOUT = 62dBmV @ MAX GAIN 160 TXEN = 0 IMPEDANCE – ⍀ DISTORTION – dBc –60 VOUT = 61dBmV @ MAX GAIN 150 –65 TXEN = 1 TOKO 617DB–A0070 1:1 VCC 140 VOUT = 60dBmV @ MAX GAIN 0.1F VIN– 130 –70 120 0.1F GND –75 15 25 35 45 55 FUNDAMENTAL FREQUENCY – MHz RL 75⍀ VIN+ VOUT = 59dBmV @ MAX GAIN 5 OUT– OUT+ ZIN 165⍀ 110 65 1 TPC 7. Second Order Harmonic Distortion vs. Frequency for Various Output Levels 100 10 FREQUENCY – MHz TPC 10. Input Impedance vs. Frequency –50 90 VOUT = 62dBmV @ MAX GAIN –52 85 VOUT = 61dBmV @ MAX GAIN 80 IMPEDANCE – ⍀ DISTORTION – dBc –54 –56 –58 –60 TXEN = 1 75 70 TXEN = 0 65 VOUT = 60dBmV @ MAX GAIN –62 60 VOUT = 59dBmV @ MAX GAIN –64 5 15 25 35 45 55 FUNDAMENTAL FREQUENCY – MHz 55 65 TPC 8. Third Order Harmonic Distortion vs. Frequency for Various Output Levels 10 FREQUENCY – MHz 100 TPC 11. Output Impedance vs. Frequency –10 –50 FO = 42MHz VOUT = 61dBmV @ MAX GAIN –55 DISTORTION – dBc 1 –20 CH PWR ACP UP ACP LOW 12.3dBm –54.02dB –53.79dB CU1 CU1 –30 –40 HD3 –60 –50 –60 –65 –70 –70 –80 –90 –75 –80 HD2 0 10 20 40 50 60 30 GAIN CONTROL – Dec Code –100 70 C11 –110 CENTER 21MHz 80 TPC 9. Harmonic Distortion vs. Gain Control C11 C0 C0 75kHz/DIV SPAN 750kHz TPC 12. Adjacent Channel Power –6– REV. 0 AD8325 APPLICATIONS General Application with a transformer, the stated gain values already take into account the losses associated with the transformer. The AD8325 is primarily intended for use as the upstream power amplifier (PA) in DOCSIS (Data Over Cable Service Interface Specifications) certified cable modems and CATV set-top boxes. Upstream data is modulated in QPSK or QAM format, and done with DSP or a dedicated QPSK/QAM modulator. The amplifier receives its input signal from the QPSK/QAM modulator or from a DAC. In either case the signal must be low-pass filtered before being applied to the amplifier. Because the distance from the cable modem to the central office will vary with each subscriber, the AD8325 must be capable of varying its output power by applying gain or attenuation to ensure that all signals arriving at the central office are of the same amplitude. The upstream signal path contains components such as a transformer and diplexer that will result in some amount of power loss. Therefore, the amplifier must be capable of providing enough power into a 75 Ω load to overcome these losses without sacrificing the integrity of the output signal. The gain transfer function is as follows: AV = 30.0 dB – (0.7526 dB × (79 – CODE)) for 0 ≤ CODE ≤ 79 where AV is the gain in dB and CODE is the decimal equivalent of the 8-bit word. Valid gain codes are from 0 to 79. Figure 4 shows the gain characteristics of the AD8325 for all possible values in an 8-bit word. Note that maximum gain is achieved at Code 79. From Code 80 through 127, the 5.25 dB of attenuation from the vernier stage is being applied over every eight codes, resulting in the sawtooth characteristic at the top of the gain range. Because the eighth bit is a “don’t care” bit, the characteristic for codes 0 through 127 repeats from Codes 128 through 255. 30 25 20 Operational Description SPI Programming and Gain Adjustment Gain programming of the AD8325 is accomplished using a serial peripheral interface (SPI) and three digital control lines, DATEN, SDATA, and CLK. To change the gain, eight bits of data are streamed into the serial shift register through the SDATA port. The SDATA load sequence begins with a falling edge on the DATEN pin, thus activating the CLK line. With the CLK line activated, data on the SDATA line is clocked into the serial shift register Most Significant Bit (MSB) first, on the rising edge of each CLK pulse. Because only a 7-bit shift register is used, the MSB of the 8-bit word is a “don’t care” bit and is shifted out of the register on the eighth clock pulse. A rising edge on the DATEN line latches the contents of the shift register into the attenuator core resulting in a well controlled change in the output signal level. The serial interface timing for the AD8325 is shown in Figures 2 and 3. The programmable gain range of the AD8325 is –29.45 dB to +30 dB and scales 0.7526 dB per least significant bit (LSB). Because the AD8325 was characterized REV. 0 15 10 GAIN – dB The AD8325 is composed of four analog functions in the powerup or forward mode. The input amplifier (preamp) can be used single-endedly or differentially. If the input is used in the differential configuration, it is imperative that the input signals are 180 degrees out of phase and of equal amplitudes. This will ensure proper gain accuracy and harmonic performance. The preamp stage drives a vernier stage that provides the fine tune gain adjustment. The 0.7526 dB step resolution is implemented in the vernier stage and provides a total of approximately 5.25 dB of attenuation. After the vernier stage, a DAC provides the bulk of the AD8325’s attenuation (9 bits or 54 dB). The signals in the preamp and vernier gain blocks are differential to improve the PSRR and linearity. A differential current is fed from the DAC into the output stage, which amplifies these currents to the appropriate levels necessary to drive a 75 Ω load. The output stage utilizes negative feedback to implement a differential 75 Ω output impedance. This eliminates the need for external matching resistors needed in typical video (or video filter) termination requirements. 5 0 –5 –10 –15 –20 –25 –30 0 32 64 96 128 160 GAIN CODE – Decimal 192 224 256 Figure 4. Gain vs. Gain Code Input Bias, Impedance, and Termination The VIN+ and VIN– inputs have a dc bias level of approximately VCC/2, therefore the input signal should be ac-coupled. The differential input impedance is approximately 1600 Ω while the single-ended input impedance is 800 Ω. If the AD8325 is being operated in a single-ended input configuration with a desired input impedance of 75 Ω, the VIN+ and VIN– inputs should be terminated as shown in Figure 5. If an input impedance other than 75 Ω is desired, the values of R1 and R2 in Figure 5 can be calculated using the following equations: ZIN = R1800 R2 = Z IN R1 ZIN = 75⍀ – R1 = 82.5⍀ AD8325 + R2 = 39.2⍀ Figure 5. Single-Ended Input Termination –7– AD8325 input and output traces should be kept as short and symmetrical as possible. In addition, the input and output traces should be kept far apart in order to minimize coupling (crosstalk) through the board. Following these guidelines will improve the overall performance of the AD8325 in all applications. Output Bias, Impedance, and Termination The differential output pins VOUT+ and VOUT– are also biased to a dc level of approximately VCC/2. Therefore, the outputs should be ac-coupled before being applied to the load. This is accomplished with a 1:1 transformer as seen in the typical applications circuit of Figure 6. The transformer also converts the output signal from differential to single-ended, while maintaining a proper impedance match to the line. The differential output impedance of the AD8325 is internally maintained at 75 Ω, regardless of whether the amplifier is in transmit enable mode (TXEN = 1) or transmit disable mode (TXEN = 0). If the output signal is being evaluated on standard 50 Ω test equipment, a 75 Ω to 50 Ω pad must be used to provide the test circuit with the correct impedance match. Initial Power-Up When the 5 V supply is first applied to the VCC pins of the AD8325, the gain setting of the amplifier is indeterminate. Therefore, as power is first applied to the amplifier, the TXEN pin should be held low (Logic 0) thus preventing forward signal transmission. After power has been applied to the amplifier, the gain can be set to the desired level by following the procedure in the SPI Programming and Gain Adjustment section. The TXEN pin can then be brought from Logic 0 to 1, enabling forward signal transmission at the desired gain level. Power Supply Decoupling, Grounding, and Layout Considerations Between Burst Operation Careful attention to printed circuit board layout details will prevent problems due to associated board parasitics. Proper RF design techniques are mandatory. The 5 V supply power should be delivered to each of the VCC pins via a low impedance power bus to ensure that each pin is at the same potential. The power bus should be decoupled to ground with a 10 µF tantalum capacitor located in close proximity to the AD8325. In addition to the 10 µF capacitor, each VCC pin should be individually decoupled to ground with a 0.1 µF ceramic chip capacitor located as close to the pin as possible. The pin labeled BYP (Pin 21) should also be decoupled with a 0.1 µF capacitor. The PCB should have a lowimpedance ground plane covering all unused portions of the component side of the board, except in the area of the input and output traces (see Figure 10). It is important that all of the AD8325’s ground pins are connected to the ground plane to ensure proper grounding of all internal nodes. The differential The asynchronous TXEN pin is used to place the AD8325 into “Between Burst” mode while maintaining a differential output impedance of 75 Ω. Applying a Logic 0 to the TXEN pin activates the on-chip reverse amplifier, providing a 74% reduction in consumed power. The supply current is reduced from approximately 133 mA to approximately 35 mA. In this mode of operation, between burst noise is minimized and the amplifier can no longer transmit in the upstream direction. In addition to the TXEN pin, the AD8325 also incorporates an asynchronous SLEEP pin, which may be used to place the amplifier in a high output impedance state and further reduce the supply current to approximately 4 mA. Applying a Logic 0 to the SLEEP pin places the amplifier into SLEEP mode. Transitioning into or out of SLEEP mode will result in a transient voltage at the output of the amplifier. Therefore, use only the TXEN pin for DOCSIS compliant “Between Burst” operation. 5V 10F 25V 0.1F AD8325 TSSOP DATEN SDATA CLK 0.1F TXEN DATEN SDATA CLK GND1 VCC TXEN 0.1F SLEEP 0.1F SLEEP GND2 VCC1 ZIN = 150⍀ 165⍀ VIN+ GND10 VCC5 0.1F GND9 BYP VCC4 0.1F VCC2 VCC3 GND3 GND4 GND5 OUT– GND8 GND7 GND6 OUT+ VIN– 0.1F GND11 VCC6 VIN– VIN+ 0.1F 0.1F 0.1F TOKO 617DB-A0070 TO DIPLEXER ZIN = 75⍀ Figure 6. Typical Applications Circuit –8– REV. 0 AD8325 Distortion, Adjacent Channel Power, and DOCSIS Evaluation Board Features and Operation In order to deliver 58 dBmV of high fidelity output power required by DOCSIS, the PA should be able to deliver about 61 dBmV in order to make up for losses associated with the transformer and diplexer. TPC 7 and TPC 8 show the AD8325 second and third harmonic distortion performance versus fundamental frequency for various output power levels. These figures are useful for determining the inband harmonic levels from 5 MHz to 65 MHz. Harmonics higher in frequency will be sharply attenuated by the low-pass filter function of the diplexer. Another measure of signal integrity is adjacent channel power or ACP. DOCSIS section 4.2.9.1.1 states, “Spurious emissions from a transmitted carrier may occur in an adjacent channel that could be occupied by a carrier of the same or different symbol rates.” TPC 12 shows the measured ACP for a 16 QAM, 61 dBmV signal, taken at the output of the AD8325 evaluation board (see Figure 12 for evaluation board schematic). The transmit channel width and adjacent channel width in TPC 12 correspond to symbol rates of 160 KSYM/SEC. Table I shows the ACP results for the AD8325 for all conditions in DOCSIS Table 4-7 “Adjacent Channel Spurious Emissions.” The AD8325 evaluation board (Part # AD8325-EVAL) and control software can be used to control the AD8325 upstream cable driver via the parallel port of a PC. A standard printer cable connected between the parallel port and the evaluation board is used to feed all the necessary data to the AD8325 by means of the Windows-based, Microsoft Visual Basic control software. This package provides a means of evaluating the amplifier by providing a convenient way to program the gain/ attenuation as well as offering easy control of the amplifiers’ asynchronous TXEN and SLEEP pins. With this evaluation kit the AD8325 can be evaluated with either a single-ended or differential input configuration. The amplifier can also be evaluated with or without the PULSE diplexer in the output signal path. To remove the diplexer from the signal path, leave R6 and R8 open and install a 0 Ω chip resistor at R7. A schematic of the evaluation board is provided in Figure 12. Table I. ACP Performance for All DOCSIS Conditions (All Values in dBc) TRANSMIT CHANNEL SYMBOL RATE ADJACENT CHANNEL SYMBOL RATE 160 KSYM/SEC 320 KSYM/SEC 640 KSYM/SEC 1280 KSYM/SEC 2560 KSYM/SEC 160 KSYM/SEC –53.8 –55.6 –61.1 –67.0 –66.7 320 KSYM/SEC –53.1 –53.8 –56.0 –61.5 –67.6 640 KSYM/SEC –54.3 –53.2 –54.0 –56.3 –62.0 1280 KSYM/SEC –56.3 –54.3 –53.4 –54.1 –56.3 2560 KSYM/SEC –58.5 –56.2 –54.4 –53.5 –54.1 Noise and DOCSIS Overshoot on PC Printer Ports At minimum gain, the AD8325’s output noise spectral density is 10 nV/√Hz measured at 10 MHz. DOCSIS Table 4-8, “Spurious Emissions in 5 MHz to 42 MHz,” specifies the output noise for various symbol rates. The calculated noise power in dBmV for 160 KSYM/SECOND is: The data lines on some PC parallel printer ports have excessive overshoot that may cause communications problems when presented to the CLK pin of the AD8325 (TP6 on the evaluation board). The evaluation board was designed to accommodate a series resistor and shunt capacitor (R2 and C5) to filter the CLK signal if required. 2 20 log 10 nV × 160 kHz + 60 = –48 dBmV Hz Comparing the computed noise power of –48 dBmV to the 8 dBmV signal yields –56 dBc, which meets the required level of –53 dBc set forth in DOCSIS Table 4-8. As the AD8325’s gain is increased from this minimum value, the output signal increases at a faster rate than the noise, resulting in a signal to noise ratio that improves with gain. In transmit disable mode, the output noise spectral density computed over 160 KSYM/SECOND is 1.0 nV/√Hz or –68 dBmV. REV. 0 Transformer and Diplexer A 1:1 transformer is needed to couple the differential outputs of the AD8325 to the cable while maintaining a proper impedance match. The specified transformer is available from TOKO (Part # 617DB-A0070); however, MA/COM part # ETC-1-1T-15 can also be used. The evaluation board is equipped with the TOKO transformer, but is also designed to accept the MA/COM transformer. The PULSE diplexer included on the evaluation board provides a high-order low-pass filter function, typically used in the upstream path. The ability of the PULSE diplexer to achieve DOCSIS compliance is neither expressed nor implied by Analog Devices Inc. Data on the diplexer can be obtained from PULSE. –9– AD8325 Differential Inputs Installing the Visual Basic Control Software The AD8325-EVAL evaluation board may be driven with a differential signal in one of two ways. A transformer may be used to convert a single-ended signal to differential, or a differential signal source may be used. Figure 7 and the following paragraphs describe each of these methods. To install the “CABDRIVE_25” evaluation board control software, close all Windows applications and then run “SETUP.EXE” located on Disk 1 of the AD8325 Evaluation Software. Follow the on-screen instructions and insert Disk 2 when prompted to do so. Enter the path of the directory into which the software will be installed and select the button in the upper left corner to complete the installation. Single-Ended-to-Differential Input (Figure 7, Option 1) A TOKO 617DB-A0070 1:1 transformer is preinstalled in the T3 location of the evaluation board. Install 0 Ω chip resistors at R14, R15, and R20, and leave R16 through R19 open. For 50 Ω differential input impedance, install a 51.1 Ω resistor at R13. For 75 Ω differential input impedance, use a 78.7 Ω resistor. In this configuration, the input signal must be applied to the VIN+ port of the evaluation board. For input impedances other than 50 Ω or 75 Ω, the correct value for R13 can be calculated using the following equation. Desired Input Impedance = (R131600) Differential Input (Figure 7, Option 2) If a differential signal source is available, it may be applied directly to both the VIN+ and VIN– input ports of the evaluation board. In this case, 0 Ω chip resistors should be installed at locations R16 through R19, and R14, R15, and R20 should be left open. The equation at the end of the preceding paragraph can be used to compute the correct value for R13 for any desired differential input impedance. For differential input impedances of 75 Ω or 150 Ω, the value of R13 will be 78.7 Ω or 165 Ω respectively. DIFF IN T1 R13 AD8325 To invoke the control software, go to START -> PROGRAMS -> CABDRIVE_25, or select the AD8325.EXE icon from the directory containing the software. Controlling the Gain/Attenuation of the AD8325 The slide bar controls the AD8325’s gain/attenuation, which is displayed in dB and in V/V. The gain scales at 0.7526 dB per LSB with the valid codes being from decimal 0 to 79. The gain code (i.e., position of the slide bar) is displayed in decimal, binary, and hexadecimal (see Figure 8). Transmit Enable, Transmit Disable, and Sleep The “Transmit Enable” and “Transmit Disable” buttons select the mode of operation of the AD8325 by controlling the logic level on the asynchronous TXEN pin. The “Transmit Enable” button applies a Logic 1 to the TXEN pin putting the AD8325 in forward transmit mode. The “Transmit Disable” button applies a Logic 0 to the TXEN pin selecting reverse mode, where the forward signal transmission is disabled while a back termination of 75 Ω is maintained. On early revisions of the software, the “Transmit Enable” and “Transmit Disable” buttons may be called “Power-Up” and “Power-Down” respectively. Checking the “Enable SLEEP Mode” box applies a Logic 0 to the asynchronous SLEEP pin, putting the AD8325 into SLEEP mode. Memory Section DIFFERENTIAL INPUT, OPTION 1 VIN+ R13 Running the Software AD8325 VIN– The “MEMORY” section of the software provides a convenient way to alternate between two gain settings. The “X->M1” button stores the current value of the gain slide bar into memory while the “RM1” button recalls the stored value, returning the gain slide bar to that level. The “X->M2” and “RM2” buttons work in the same manner. DIFFERENTIAL INPUT, OPTION 2 Figure 7. Differential Input Termination Options –10– REV. 0 AD8325 EVALUATION BOARD FEATURES AND OPERATION Figure 8. Screen Display of Windows-Based Control Software REV. 0 –11– AD8325 Figure 9. Evaluation Board—Assembly (Component Side) –12– REV. 0 AD8325 Figure 10. Evaluation Board Layout (Component Side) REV. 0 –13– AD8325 Figure 11. Evaluation Board—Solder Side –14– REV. 0 REV. 0 –15– Figure 12. Evaluation Board Schematic 12 13 14 15 16 17 18 P1 P1 P1 P1 P1 P1 8 P1 P1 7 P1 11 6 P1 P1 5 P1 9 4 P1 10 3 P1 P1 2 P1 P1 1 P1 AGND C3 0.1F C2 0.1F C1 0.1F SLEEP TXEN CLK SDATA DATEN 0⍀ R3 AGND TP7 0⍀ R1 TP5 TP3 TP1 C6 DNI TP8 R2 0⍀ C4 DNI TP4 TP2 C5 1000pF TP6 33 34 35 36 P1 P1 P1 32 31 30 29 28 27 26 25 24 23 22 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 21 20 P1 P1 19 P1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 AGND TSSOP28 28 27 26 25 24 23 22 21 20 19 18 17 16 15 TP14 DNI DATEN GND VCC SDATA VIN– CLK VIN+ GND VCC GND TXEN VCC SLEEP GND BYP GND VCC VCC VCC VCC GND GND GND GND GND GND OUT+ OUT– Z1 R5 DNI TP15 DNI R4 DNI TP17 DNI TP16 DNI TP10 TP11 TP12 SEC 1 2 T2 3 DNI ETC1 PRI 5 4 TP18 DNI 1 AGND TOKO1 PRI SEC 3 2 4 T1 6 TP19 DNI R6 0⍀ AGND R11 DNI R13 51.1⍀ AGND R12 DNI C15 0.1F C16 0.1F DEVICE = 2LUGPWR TB1 C7 0.1F AGND AGND C9 0.1F VCC C11 0.1F PKG_TYPE = R1206 TP13 DNI AGND C8 0.1F C10 0.1F AGND C12 10F TP9 VCC R8 0⍀ R14 0⍀ R16 DNI LPP HPP 9 5 R9 0⍀ TP20 DNI AGND VIN–0 R10 DNI AGND CABLE_0 TP21 DNI HPF_0 VIN+0 R20 0⍀ AGND R21 DNI TP22 DNI CBL R18 DNI COM CX6002 3 10–18 1 AGND R22 DNI TOKO1 DNI ETC1 1 PRI SEC 3 2 2 1 4 T3 6 3 AGND R19 DNI PRI SEC 5 4 T4 R17 DNI DNI = DO NOT INSTALL R7 DNI TP24 R15 0⍀ TP23 AD8325 AD8325 EVALUATION BOARD BILL OF MATERIALS Qty. Description Vendor Ref Desc. 1 1 2 8 11 1 2 8 1 3 1 1 3 2 1 1 1 4 4 2 2 2 2 10 µF 25 V. ‘D’ size tantalum chip capacitor 1,000 pF 50 V. 1206 ceramic chip capacitor 0.1 µF 50 V. 1206 size ceramic chip capacitor 0.1 µF 25 V. 0603 size ceramic chip capacitor 0 Ω 5% 1/8 W. 1206 size chip resistor 51.1 Ω 1% 1/8 W. 1206 size chip resistor Yellow Test Point White Test Point Red Test Point Black Test Point Centronics-type 36-pin Right-Angle Connector Terminal Block 2-Pos Green ED1973-ND SMA End launch Jack (E F JOHNSON # 142-0701-801) 1:1 Transformer TOKO # 617DB – A0070 PULSE Diplexer* AD8325 (TSSOP) UPSTREAM Cable Driver AD8325 REV. B Evaluation PC board #4–40 × 1/4 inch STAINLESS panhead machine screw #4–40 × 3/4 inch long aluminum round stand-off # 2–56 × 3/8 inch STAINLESS panhead machine screw # 2 steel flat washer # 2 steel internal tooth lockwasher # 2 STAINLESS STEEL hex. machine nut ADS # 4-7-2 ADS # 4-5-20 ADS # 4-5-18 ADS # 4-12-8 ADS # 3-18-88 ADS # 3-18-99 ADS# 12-18-32 ADS# 12-18-42 ADS# 12-18-43 ADS# 12-18-44 ADS# 12-3-50 ADS# 12-19-13 ADS# 12-1-31 TOKO PULSE ADI# AD8325XRU NC ADS# 30-1-1 ADS# 30-16-3 ADS# 30-1-17 ADS# 30-6-6 ADS# 30-5-2 ADS# 30-7-6 C12 C5 C15, C16 C1–C3, C7–C11 R1–R3, R6, R8, R9, R14, R15, R20 R13 TP23, TP24 TP1–TP8 TP9 TP10–TP12 (GND) P1 TB1 VIN–, VIN+, CABLE_0 T1–T3 Z2 Z1 Evaluation PC board C02439–2.5–4/01(0) AD8325 Evaluation Board Rev. B, Single-Ended-to-Differential Input – Revised – February 21, 2001 (P1 hardware) (P1 hardware) (P1 hardware) (P1 hardware) NOTES *PULSE Diplexer part numbers B5008 (42 MHz), CX6002 (42 MHz), B5009 (65 MHz). DO NOT INSTALL C4, C6, R4, R5, R7, R10–R12, R16–R19, R21, R22, T2, T4, TP13–TP22. SMA’s TXEN, CLK, SLEEP, DATEN, SDATA, HPF_0 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 28-Lead TSSOP (RU-28) 0.386 (9.80) 0.378 (9.60) 28 15 0.177 (4.50) 0.169 (4.30) 1 PRINTED IN U.S.A. 0.256 (6.50) 0.246 (6.25) 14 PIN 1 0.006 (0.15) 0.002 (0.05) SEATING PLANE 0.0433 (1.10) MAX 0.0256 (0.65) 0.0118 (0.30) BSC 0.0075 (0.19) 0.0079 (0.20) 0.0035 (0.090) –16– 8ⴗ 0ⴗ 0.028 (0.70) 0.020 (0.50) REV. 0