8-BIT SINGLE-CHIP MICROCONTROLLERS HMS77C2000 HMS77C2001 User’s Manual (Ver. 1.1) HMS77C2000/2001 Revision History Ver 1.1 (this manual, NOV. 2002) Add IOL-VOL, IOH-VOH and VPP rising & falling time graphs in the electrical characteristics. Correct mistakes in the paragraph. Version 1.1 Published by MCU Application Team 2002 Hynix Semiconductor All right reserved. Additional information of this manual may be served by Hynix Semiconductor offices in Korea or Distributors and Representatives listed at address directory. Hynix Semiconductor reserves the right to make changes to any information here in at any time without notice. The information, diagrams and other data in this manual are correct and reliable; however, Hynix Semiconductor is in no way responsible for any violations of patents or other rights of the third party generated by the use of this manual. 2 Nov. 2002 Ver 1.1 HMS77C2000/2001 Table of Contents 1. GENERAL DESCRIPTION ...................2 Application .................................................. 2 One-Time-Programmable (OTP) Devices .. 2 2. BLOCK DIAGRAM ................................3 3. PIN ASSIGNMENT ...............................3 4. PACKAGE DIAGRAM ...........................4 5. PIN FUNCTION .....................................5 6. PORT STRUCTURES ...........................6 7. ELECTRICAL CHARACTERISTICS .....8 Absolute Maximum Ratings ........................ 8 Recommended Operating Conditions ......... 8 DC Characteristics (1) ................................ 9 DC Electrical Characteristics (2) ............... 10 AC Electrical Characteristics (1) ............... 11 AC Electrical Characteristics (2) ............... 12 Typical Characteristics .............................. 13 8. ARCHITECTURAL OVERVIEW ..........16 CPU Architecture ...................................... 16 Clocking Scheme/Instruction Cycle .......... 17 Instruction Flow/Pipelining ........................ 17 9. MEMORY ORGANIZATION ................18 Program Memory Organization ................. 18 Data Memory Organization ....................... 18 STATUS Register ..................................... 21 OPTION Register ...................................... 21 OSCCAL Register ..................................... 23 Program Counter ...................................... 23 Stack ......................................................... 24 Indirect Data Addressing; INDF and FSR Registers ................................................... 25 10. I/O PORT ..........................................26 TRIS Register ............................................26 I/O Interfacing ............................................26 I/O Programming Considerations ..............27 11. TIMER0 MODULE AND TMR0 REGISTER ..........................................29 Using Timer0 with an External Clock ........30 Prescaler ...................................................31 12. SPECIAL FEATURES OF THE CPU 33 Configuration Bits ......................................33 Oscillator Configurations ...........................34 Reset .........................................................35 Power-On Reset (POR) .............................37 Internal Reset Timer (IRT) .........................39 Watchdog Timer (WDT) ............................39 Time-Out Sequence, Power Down, and Wake-upfromSLEEPStatusBits(TO/PD/UPWUF) 40 Reset on Brown-Out ..................................41 Power-Down Mode (SLEEP) .....................41 Program Verification/Code Protection .......42 ID Locations ..............................................42 Power Fail Detection Processor ................42 In-Circuit Serial Programming ...................43 13. IN-CIRCUIT SERIAL PROGRAMMING(ICSP) SPECIFICATIONS .........45 Programming The HMS77C200x ..............45 Program Mode Entry .................................45 Configuration Word ...................................49 Code Protection .........................................50 Program/Verify Mode Electrical Characteristics 52 UPIO ......................................................... 26 Oct. 2002 Ver 1.1 1 HMS77C2000/2001 HMS77C2000/2001 8 PIN, 8-BIT CMOS SINGLE-CHIP MICROCONTROLLER Device name EPROM(12bit) RAM HMS77C2000 512 words 25 bytes HMS77C2001 1024 words 41 bytes I/O, I Timer Voltage Range Package 5, 1 1 2.5 ~ 5.5V 8 PDIP, SOP High-Performance RISC CPU: - Noise immunity circuit: Power fail detector - Only 33 single word instructions to learn - Power saving SLEEP mode - All instructions are single cycle (1 us) except for program branches which are two-cycle - Wake-up from SLEEP on pin change - Internal weak pull-ups on I/O pins - Operating speed: DC - 4 MHz clock input DC - 1 us instruction cycle - Internal pull-up on RESET pin - 12-bit wide instructions and 8-bit wide data path - - Seven special function hardware registers - Two-level deep hardware stack - Direct, indirect and relative addressing modes for data and instructions - Internal 4 MHz RC oscillator with programmable calibration Selectable oscillator options: IRC: Internal 4 MHz RC oscillator ERC: External low-cost RC oscillator (200KHz ~ 4MHz) XT: Standard crystal/resonator (455KHz ~ 4MHz) LF: Power saving, low frequency crystal (32KHz ~ 200KHz) - In-circuit serial programming CMOS Technology: - Low power, high speed CMOS EPROM technology - Wide operating voltage range - Wide temperature range: Industrial: -40°C to +85°C - Low power consumption < 2 mA typical @5V, 4 MHz 30 uA typical @3V, 32 kHz 0.25 uA typical standby current @3V, WDT disable Peripheral Features: - 8-bit real time clock/counter (TMR0) with 8-bit programmable prescaler - Power-On Reset (POR) - Internal Reset Timer (IRT) - Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation - Programmable code-protection Nov. 2002 Ver 1.1 1 HMS77C2000/2001 1. GENERAL DESCRIPTION The HMS77C2000 and HMS77C2001 are an advanced CMOS 8-bit microcontrollers with 0.5K/1K words (12bits) of EPROM. They employ a RISC architecture with only 33 single word/single cycle instructions. All instructions are single cycle (1us) except for program branches which take two cycles. The HMS77C2000 and HMS77C2001 deliver performance an order of magnitude higher than their competitors in the same price category. The HMS77C2000 and HMS77C2001 products are equipped with special features that reduce system cost and power requirements. The Power-on reset (POR) and internal reset timer (IRT) remove the need for external reset circuitry. There are four oscillator configurations to choose from IRC (internal RC) oscillator mode to LF (Low Frequency) oscillator mode. Power saving SLEEP mode, watchdog timer and code protection features also improve system cost, power and reliability. The HMS77C2000 and HMS77C2001 are available in the cost-effective one-timeprogrammable (OTP) versions which are suitable for production in any volume. The customer can take full advantage of Hynix Semiconductor’s price leadership in OTP microcontrollers while benefiting from the OTP’s flexibility. Also the HMS77C2000 and HMS77C2001 have an onchip power fail detection circuitry to immunize against power noise. The power fail detection processor may reset MCU to protect the device from malfunction due to power noise. 2 1.1 APPLICATION The HMS77C2000 and HMS77C2001 fit perfectly in applications ranging from personal care appliances and security systems to low-power remote transmitters/receivers. The EPROM technology makes customizing application programs (transmitter codes, appliance settings, receiver frequencies, etc.) extremely fast and convenient. The small footprint packages or surface mounting make these microcontrollers perfect for applications with space limitations. Low-cost, low-power, high performance, ease of use and I/ O flexibility make the HMS77C2000 and HMS77C2001 very versatile even in areas where no microcontroller use has been considered before (e.g., timer functions, coprocessor applications). 1.2 ONE-TIME-PROGRAMMABLE (OTP) DEVICES The availability of OTP devices is especially useful for customers who need the flexibility for frequent code updates or small volume applications. The OTP devices, packaged in plastic packages permit the user to program them once. In addition to the program memory, the configuration bits must also be programmed. Nov. 2002 Ver 1.1 HMS77C2000/2001 2. BLOCK DIAGRAM FSR OSCCAL OPTION 8-bit Timer/ Counter STATUS ALU STACK 1 Data PC STACK 2 Memory Power Fail Detector RESET System controller Xin Clock Generator Timing Control Xout Program Memory W WDT/ TMR0 Prescaler Watch-dog Timer WDT time out Internal Reset Timer Powe-on Reset Instruction Decoder Configuration Word ICSP Internal RC OSC VDD UPIO VSS TRIS Power Supply UP0 UP1 UP2/EC0 UP3/RESET/VPP UP4/XOUT UP5/XIN EC0 FIGURE 2-1 HMS77C2000/20001 BLOCK DIAGRAM 3. PIN ASSIGNMENT 8 PDIP or SOP 1 UP5/XIN 2 UP4/XOUT 3 UP3/RESET/VPP 4 HMS77C2000 HMS77C2001 Nov. 2002 Ver 1.1 VDD 8 VSS 7 UP0 6 UP1 5 UP2/EC0 3 HMS77C2000/2001 4. PACKAGE DIAGRAM 8 PDIP (300MIL) unit: inch MAX MIN 0.260 0.240 TYP 0.300 0.387 0.260 0.240 0.120 0.140 MAX 0.180 MIN 0.020 0.367 4 0.01 8 0 0 0. 0.021 0.015 3° ~ 15° TYP 0.100 0.065 0.050 0.244 0.230 0.1574 0.152 8 SOP (150MIL) 0.195 0.189 0.1574 4 0.0075 TYP 0.050 0.0098 0.020 0.0138 0.152 0.0098 0.004 0.0688 0.060 0.195 0.189 0° ~ 8° 0.035 0.016 Nov. 2002 Ver 1.1 HMS77C2000/2001 5. PIN FUNCTION VDD: Supply voltage. XOUT: Output from the inverting oscillator amplifier. VSS: Circuit ground. UP0~UP5: UP is a 6-bit, CMOS, bidirectional I/O port except for UP3. UP3 port is fixed to input mode UP pins can be used as outputs or inputs according to “0” or “1” written the their port direction register(TRIS). VPP: Programming voltage input RESET: Reset the MCU. XIN: Input to the inverting oscillator amplifier and input to the internal main clock operating circuit. NAME DIP Pin # UP0 7 SOP Pin # 7 I/O/P Type I/O EC0: EC0 is an external clock input to Timer0. It should be tied to VSS or VDD, if not in use, to reduce current consumption. Buffer Type Description TTL/ST Bi-directional I/O port/ serial programming data. Can be software programmed for internal weak pull-up and wake-up from SLEEP on pin change. This buffer is a schmitt trigger input when used in serial programming mode. Bi-directional I/O port/ serial programming clock. Can be software programmed for internal weak pull-up and wake-up from SLEEP on pin change. This buffer is a schmitt trigger input when used in serial programming mode. UP1 6 6 I/O TTL/ST UP2/EC0 5 5 I/O ST Bi-directional I/O port. Can be configured as EC0. UP3/RESET/VPP 4 4 I TTL/ST Input port/master clear (reset) input/programming voltage input. When configured as RESET, this pin is an active low reset to the device. Voltage on RESET/VPP must not exceed VDD during normal device operation or the device will enter programming mode. Can be software programmed for internal weak pull-up and wake-up from SLEEP on pin change. Weak pull-up always on if configured as RESET. ST when in RESET mode. UP4/XOUT 3 3 I/O TTL Bi-directional I/O port/oscillator crystal output. Connections to crystal or resonator in crystal oscillator mode (XT and LF modes only, UPIO in other modes). Bidirectional IO port/oscillator crystal input/external clock source input (UPIO in Internal RC mode only, XIN in all other oscillator modes). TTL input when UPIO, ST input in external RC oscillator mode. UP5/XIN 2 2 I/O TTL/ST VDD 1 1 P - Positive supply for logic and I/O pins VSS 8 8 P - Ground reference for logic and I/O pins TABLE 5-1HMS77C2000/1 PINOUT DESCRIPTION Legend: I = input, O = output, I/O = input/output, P = power, - = not used, TTL = TTL input, ST = schmitt trigger input Nov. 2002 Ver 1.1 5 HMS77C2000/2001 6. PORT STRUCTURES • UP3/RESET RESETE(configuration bit4) Weak Pull-up UPPU(OPTION bit6) To RESET circuit Data Bus VSS Read UPIO • UP0~UP1 UPPU(OPTION bit6) Weak Pull-up VDD Data Reg. Data Bus Tris Reg. Data Bus VSS Data Bus Read UPIO • UP2/EC0 Data Reg. VDD Data Bus Tris Reg. Data Bus VSS Data Bus Read UPIO Timer/Counter 6 Nov. 2002 Ver 1.1 HMS77C2000/2001 • UP5/Xin, UP4/Xout XT, LF Mode (XIN,XOUT) VDD EN ( XT, LF ) Xout To Internal Clock RF VSS Amplifier varies with the oscillation mode Xin ERC Mode (XIN) To Internal Clock Xin Enable (ERC) Internal Capacitance ( appx. 5pF ) Normal I/O(UP4/UP5) Data Reg. VDD Data Bus Tris Reg. Data Bus VSS Data Bus Read UPIO Nov. 2002 Ver 1.1 7 HMS77C2000/2001 7. ELECTRICAL CHARACTERISTICS 7.1 ABSOLUTE MAXIMUM RATINGS Maximum current (ΣIOL) .................................... 100 mA Supply voltage .............................................. -0 to +6.5 V Maximum current (ΣIOH)...................................... 80 mA Storage Temperature ................................-65 to +125 °C Voltage on RESET with respect to VSS .......0.3 to 12.5V Voltage on any pin with respect to VSS. -0.3 to VDD+0.3 Maximum current out of VSS pin ........................100 mA Maximum current into VDD pin ..........................100 mA Maximum output current sunk by (IOL per I/O Pin)25 mA Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum output current sourced by (IOH per I/O Pin) ...............................................................................20 mA 7.2 RECOMMENDED OPERATING CONDITIONS Specifications Parameter Supply Voltage Operating Frequency Operating Temperature 8 Symbol VDD fXIN TOPR Condition Unit Min. Max. fXIN=4MHz 2.5 5.5 ERC Mode 0.2 4 IRC Mode 4 4 XT Mode 0.455 4 LF Mode 32 200 KHz -40 85 °C V MHz Nov. 2002 Ver 1.1 HMS77C2000/2001 7.3 DC CHARACTERISTICS (1) • (TA=-40°C~+85°C) Specification Parameter Symbol Test Condition Min Supply Voltage VDD 2.5 VDD start voltage to ensure Power-On Reset VPOR - VDD rise rate to ensure Power-On Reset SVDD2 RAM Data Retention Voltage Power Fail Detection Typ1 Max Unit 5.5 V VSS - V 0.05 - - V/mS VDR - 0.6 - V VPFD 2.4 2.7 3.2 V XIN = 4MHz, VDD = 5.5V - 1 2.5 mA XIN = 4MHz, VDD = 5.5V - 1 2.5 mA XT osc XIN = 4MHz, VDD = 5.5V - 2 4 mA LF osc XIN = 32KHz, VDD = 3V, WDT Disabled - 30 50 uA VDD = 3V, WDT Enabled - 3 15 VDD = 3V, WDT Disabled - 0.25 14 Supply Current ERC4 osc IRC osc Power Down Current 1. 2. 3. 4. 5. IDD3 IPD5 uA Data in “Typ” column is at 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. This parameter is characterized but not tested. The test conditions for all IDD measurements in NOP execution are: XIN = external square wave; all I/O pins tristated, pulled to VSS, EC0 = VDD, RESET = VDD; WDT disabled/enabled as specified. Does not include current through Rext. The current through the resistor can be estimated by the formula; IR = VDD/2Rext (mA) Power down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS as like measurement conditions of supply current. Nov. 2002 Ver 1.1 9 HMS77C2000/2001 7.4 DC ELECTRICAL CHARACTERISTICS (2) • (TA=-40°C~+85°C) Specification Parameter Symbol Test Condition Min Typ1 Max - VDD Unit Input High Voltage I/O Ports (TTL) 2 0.8VDD I/O Ports (ST) RESET, EC0, (ST) VIH XIN (ST) XIN 0.8VDD RC osc only 0.8VDD XT, LF osc 0.7VDD V Input Low Voltage I/O Ports (TTL) 0.6 I/O Ports (ST) 0.2VDD RESET, EC0, (ST) VIL XIN (ST) XIN Hysteresis of Schmitt Trigger Inputs Input Leakage Current I/O Ports Output High Voltage I/O Ports Output Low Voltage I/O Ports VSS RC osc only 0.1VDD XT, LF 0.3VDD 0.15VDD2 VHYS IL 0.2VDD - VSS ≤ VPIN ≤ VDD V V - - ±5 uA VOH IOH = -3.0mA, VDD = 4.5V VDD - 0.7 - VDD V VOL IOL = 8.5mA, VDD = 4.5V VSS - 0.6 V IPUR VDD = 5.5V, VPIN = VSS 150 250 350 uA 20 40 60 Weak Pull-up current UP0/UP1 RESET 1. 2. 10 Data in “Typ” column is at 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. This parameter are characterized but not tested. Nov. 2002 Ver 1.1 HMS77C2000/2001 7.5 AC ELECTRICAL CHARACTERISTICS (1) • (TA=-40°C~+85°C) Parameter Symbol External Clock Input Frequency Oscillator Frequency External Clock Input Period Oscillator Period 1 FXIN 1 FXIN TXIN TXIN Test Condition Specification Unit Min Typ Max XT osc mode DC - 4.0 MHz LF osc mode DC - 200 KHz ERC osc mode DC - 4.0 MHz XT osc mode 0.2 - 4.0 MHz LF osc mode 32 - 200 KHz XT osc mode 250 - - nS LF osc mode 5 - - uS ERC osc mode 250 - - nS XT osc mode 250 - 5,000 nS LF osc mode 5 - - uS Clock in XIN Pin 1 Low or High Time TXINL TXINH XT osc mode 50 - - nS LF osc mode 2.0 - - uS Clock in XIN Pin 1 Rise or Fall Time TXINR TXINF XT osc mode - - 25 nS LF osc mode - - 50 nS 1. This parameter is characterized but not tested. Nov. 2002 Ver 1.1 11 HMS77C2000/2001 7.6 AC ELECTRICAL CHARACTERISTICS (2) • (TA=-40°C~+85°C) Parameter 1 Specification Symbol Test Condition Min Unit Typ2 Max 4000 - nS RESET Pulse Width (Low) TRESET VDD = 5V Watchdog Timer Time-Out Period ( No-prescaler ) TWDT VDD = 5V 9 18 30 mS TIRT VDD = 5V, ERC/IRC osc 9 18 30 mS Internal Reset Timer Period VDD = 5V, XT/LF osc - 300 - uS 3.6 - 4.4 MHz nS Internal Calibrated RC Frequency FIRC VDD = 5V EC0 High or Low Pulse Width No Prescaler With Prescaler TEC0H TEC0L TCY = 4 X TXIN Instruction cycle time TEC0P N = Prescaler Value ( 1,2,4,......256 ) 10 - - 0.5TCY + 20 - - 20 - - (TCY+40) / N - - EC0 Period No Prescaler With Prescaler 1. 2. nS These parameters are characterized but not tested. Data in “Typ” column is at 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. TXINH TXIN TXINL 0.85VDD XIN 0.15V TXINR TXINF TRESET RESET 0.15VDD TEC0H TEC0H 0.85VDD EC0 0.15VDD TEC0P 12 Nov. 2002 Ver 1.1 HMS77C2000/2001 7.7 TYPICAL CHARACTERISTICS specified range. These graphs and tables are for design guidance only and are not tested or guaranteed. The data is a statistical summary of data collected on units from different lots over a period of time. “Typical” represents the mean of the distribution while “max” or “min” represents (mean + 3σ) and (mean − 3σ) respectively where σ is standard deviation In some graphs or tables the data presented are outside specified operating range (e.g. outside specified VDD range). This is for information only and devices are guaranteed to operate properly only within the Operating Area Normal Operation(Frequency=4MHz) IDD−VDD fXIN (MHz) 10 IDD (mA) Ta= 25°C Ta=25°C 4 8 6 3 4 2 2 1 0 XT ERC 32KHz 0 2 0 2 3 4 5 3 4 5 IRC VDD 6 (V) 6 IOL−VOL, VDD=5.5V IOL−VOL, VDD=2.5V IOL (mA) IOL (mA) Ta=25°C Ta=25°C 40 12 32 24 8 16 4 8 0 0.4 Nov. 2002 Ver 1.1 0.8 1.2 1.6 VOL 2.0 (V) 0 0.4 0.8 1.2 1.6 VOL 2.0 (V) 13 HMS77C2000/2001 IOH−VOH, VDD=5.5V IOH (mA) IOH−VOH, VDD=2.5V IOH (mA) Ta=25°C -20 Ta=25°C -8 -16 -6 -12 -4 -8 -2 -4 0 0.5 1.0 0 VDD-VOH (V) 1.5 0.5 2.0 Typical RC Oscillator Frequency VS. VDD FOSC (MHz) Cext=0pF Ta=25°C 7.5 VDD-VOH (V) 2.0 1.5 Typical RC Oscillator Frequency VS. VDD FOSC (MHz) R=3.3K 1.0 Cext=20pF Ta=25°C 4.5 R=3.3K 4.0 3.5 6.0 R=5K R=5K 3.0 2.5 4.5 2.0 R=10K 3.0 R=10K 1.5 1.0 1.5 0.5 R=100K 0 2.5 FOSC (MHz) 2.00 3 3.5 4 4.5 5 5.5 VDD 6 (V) Typical RC Oscillator Frequency VS. VDD Cext=100pF Ta=25°C FOSC (MHz) 0.8 R=3.3K 3 3.5 4 4.5 5 5.5 VDD 6 (V) Typical RC Oscillator Frequency VS. VDD Cext=300pF Ta=25°C R=3.3K 0.7 1.75 1.50 0.6 R=5K R=5K 0.5 1.25 0.4 1.00 R=10K 0.75 R=10K 0.3 0.2 0.50 0.25 0.1 R=100K 0 2.5 14 R=100K 0 2.5 3 3.5 4 4.5 5 5.5 VDD 6 (V) R=100K 0 2.5 3 3.5 4 4.5 5 5.5 VDD 6 (V) Nov. 2002 Ver 1.1 HMS77C2000/2001 Cext Rext 0pF 20pF 100pF 300pF Average Fosc @ 5V,25°C 3.3K 7.48MHz 5K 6.36MHz 10K 4.04MHz 100K 529KHz 3.3K 4.60MHz 5K 3.62MHz 10K 2.14MHz 100K 249KHz 3.3K 1.75MHz 5K 1.31MHz 10K 734KHz 100K 80KHz 3.3K 702KHz 5K 510KHz 10K 283KHz 100K 30KHz Table 7-1 RC Oscillator Frequencies Nov. 2002 Ver 1.1 15 HMS77C2000/2001 8. ARCHITECTURAL OVERVIEW 8.1 CPU ARCHITECTURE The GMS700 core is a RISC-based CPU and uses a modified Harvard architecture. This architecture uses two separate memories with separate address buses, one for the program memory and the other for the data memory. This architecture adapts 33 single word instructions that are 12bit wide instruction and has an internal 2-stage pipeline (fetch and execute), which results in execution of one instruction per single cycle(1uS@ 4MHz) except for program branches. The HMS77C2000 and HMS77C2001can address 0.5K/ 1K x 12 Bits program memory and 25/41 Bytes data memory. And it can directly or indirectly address data memory. The GMS700 core has three special function registers PC, STATUS and FSR in data memory map and has ATU (Address Translation Unit) to provide address for data memory and has an 8-bit general purpose ALU and working register(W) as an accumulator. The W register consists of 8-bit register and it can not be an addressed register. Program Memory Address Instruction PC with 2-level Stack STATUS Immediate Data Instruction Decode & Control Unit FSR Indirect Address Control Signals Address Translation Unit W ALU Status ALU Data Bus Data Memory Bus FIGURE 8-1 GMS700 CPU BLOCK DIAGRAM 16 Nov. 2002 Ver 1.1 HMS77C2000/2001 8.2 CLOCKING SCHEME/INSTRUCTION CYCLE such that fetch takes one instruction cycle while decode and execute takes another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to change (e.g., GOTO) then two cycles are required to complete the instruction (Figure 8-3). The clock input (XIN pin) is internally divided by four to generate four non-overlapping quadrature clocks namely Q1, Q2, Q3 and Q4. Internally, the program counter is incremented every Q1, and the instruction is fetched from program memory and latched into instruction register in Q4. It is decoded and executed during the following Q1 through Q4. The clocks and instruction execution flow is shown in Figure 8-2 and Figure 8-3. A fetch cycle begins with the program counter (PC) incrementing in Q1. In the execution cycle, the fetched instruction is latched into the Instruction Register (IR) in cycle Q1. This instruction is then decoded and executed during the Q2, Q3, and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write). 8.3 INSTRUCTION FLOW/PIPELINING An Instruction Cycle consists of four Q cycles (Q1, Q2, Q3 and Q4). The instruction fetch and execute are pipelined Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 XIN Q1 Q2 Internal Phase clock Q3 Q4 PC PC PC+2 PC+1 Fetch INST(PC) Execute INST(PC-1) Fetch INST(PC+1) Execute INST(PC) Fetch INST(PC+2) Execute INST(PC+1) FIGURE 8-2 CLOCK/INSTRUCTION CYCLE Fetch 1 1. MOVLW 03H 2. MOVWF UPIO 3. CALL SUB_1 4. BSF UPIO, BIT1 Execute 1 Fetch 2 Execute 2 Fetch 3 Execute 3 Fetch 4 Flush Fetch SUB 1 Execute SUB 1 All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed. FIGURE 8-3 INSTRUCTION PIPELINE FLOW Nov. 2002 Ver 1.1 17 HMS77C2000/2001 9. MEMORY ORGANIZATION The HMS77C2000 and HMS77C2001 memories are organized into program memory and data memory. For devices with more than 512 bytes of program memory, a paging scheme is used. Program memory pages are accessed using one STATUS register bit. For the HMS77C2001 with a data memory register file of more than 32 registers, a banking scheme is used. Data memory banks are accessed using the File Select Register (FSR). PC<9:0> Stack Level 1 Stack Level 2 000H The HMS77C2000 and HMS77C2001 devices have a 12bit program counter (PC) capable of addressing a 0.5K/1K x 12 program memory space. 0FFH 100H Only the first 512 x 12bits(0000 H ~01FF H ) for the HMS77C2000 and 1K x 12bits(0000H-03FFH) for the HMS77C2001 are physically implemented. Refer to Figure 9-1, Figure 9-2. Accessing a location above these boundaries will cause a wraparound within the first 512 x 12 space (HMS77C2000) or 1K x 12 space(HMS77C2001). The effective reset vector is at 000 H , (see Figure 9-1, Figure 9-2). Location 01FF H (HMS77C2000) or location 03FFH (HMS77C2001) contains the internal clock oscillator calibration value. This value should never be overwritten. 1FFH 200H On-chip Program Memory (Page 0) 2FFH 300H On-chip Program Memory (Page 1) 3FFH Reset Vector User Memory Space 9.1 PROGRAM MEMORY ORGANIZATION FIGURE 9-2 HMS77C2001 PROGRAM MEMORY MAP AND STACK PC<8:0> 9.2 DATA MEMORY ORGANIZATION Stack Level 1 Stack Level 2 0FFH 100H On-chip Program Memory 1FFH Reset Vector User Memory Space 000H FIGURE 9-1 HMS77C2000 PROGRAM MEMORY MAP AND STACK Data memory is composed of registers, or bytes of RAM. Therefore, data memory for a device is specified by its register file. The register file is divided into two functional groups: special function registers and general purpose registers. The special function registers include the TMR0 register, the program counter (PC), the status register, the I/O registers (ports), and the file select register (FSR). In addition, special purpose registers are used to control the I/O port configuration and prescaler options. The general purpose registers are used for data and control information under command of the instructions. For the HMS77C2000 the register file is composed of 7 special function registers and 25 general purpose registers (Figure 9-3). For the HMS77C2001 the register file is composed of 7 special function registers, 25 general purpose registers, and 16 general purpose registers that may be addressed using a banking scheme (Figure 9-4). 18 Nov. 2002 Ver 1.1 HMS77C2000/2001 9.2.1 General Purpose Register File The general purpose register file is accessed either directly or indirectly through the file select register FSR. FSR<6:5> File Address 00 00H INDF1 00H INDF1 01H TMR0 01H TMR0 02H PCL 02H PCL 03H STATUS 03H STATUS 04H FSR 05H OSCCAL 06H UPIO 04H FSR 05H OSCCAL 06H UPIO Universal Purpose Register Universal Purpose Register 01 Addressed map back to addresses in Bank 0. Universal Purpose Register 1FH 1FH 1. Not a physical register FIGURE 9-3 HMS77C2000 REGISTER FILE MAP Bank 0 Bank 1 1. Not a physical register FIGURE 9-4 HMS77C2001 REGISTER FILE MAP Nov. 2002 Ver 1.1 19 HMS77C2000/2001 9.2.2 SPECIAL FUNCTION REGISTERS The special registers can be classified into two sets. The special function registers associated with the “core” functions are described in this section. Those related to the operation of the peripheral features are described in the section for each peripheral feature. The Special Function Registers (SFRs) are registers used by the CPU and peripheral functions to control the operation of the device (Table 9-1). Power-On Reset All other resets1 --11 1111 --11 1111 Contains control bits to configure Timer0, Timer0/WDT prescaler, wake-up change, weak pull-up 1111 1111 1111 1111 INDF Uses contents of FSR to address data memory (not a physical register) xxxx xxxx uuuu uuuu 01H TMR0 8-bit real-time clock/counter xxxx xxxx uuuu uuuu 02H2 PCL Low order 8bits of PC 1111 1111 1111 1111 03H STATUS 0001 1xxx q00q quuu3 Indirect data memory address pointer 111x xxxx 111u uuuu Indirect data memory address pointer 110x xxxx 11uu uuuu Address Name Bit7 Bit6 N/A TRIS - - N/A OPTION 00H 04H 04H FSR (HMS77C2000) FSR (HMS77C2001) UPWUF - Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 I/O control registers PA0 TO PD Z DC C 05H OSCCAL CAL4 CAL3 CAL2 CAL1 CAL0 - PFDF PFDEN 1000 0000 1000 0000 06H UPIO - - UP5 UP4 UP3 UP2 UP1 UP0 --xx xxxx --uu uuuu TABLE 9-1 SPECIAL FUNCTION REGISTER SUMMARY 1. Other (non power-up) resets include external reset through RESET, watchdog timer and wake-up on pin change reset. 2. The upper byte of the Program Counter is not directly accessible. See Section 9.6 for an explanation of how to access these bits. 3. If reset was due to wake-up on pin change then bit 7 = 1. All other resets will cause bit 7 = 0. Legend: Shaded boxes = unimplemented or unused, - = unimplemented, read as ‘0’ (if applicable) x = unknown, u = unchanged, q = see the tables in Section 12.7 for possible values. 20 Nov. 2002 Ver 1.1 HMS77C2000/2001 9.3 STATUS REGISTER as destination may be different than intended. This register contains the arithmetic status of the ALU, the RESET status, and the page preselect bit for program memories larger than 512 words. For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register as 000u u1uu (where u = unchanged). The STATUS register can be the destination for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS register It is recommended, therefore, that only BCF, BSF and MOVWF instructions be used to alter the STATUS register because these instructions do not affect the Z, DC or C bits from the STATUS register. For other instructions, which do affect STATUS bits, see Instruction Set Summary. R UPWUF - R/W R R R/W R/W R/W PA0 TO PD Z DC C bit7 UPWUF: UPIO reset bit 1 = Reset due to wake-up from SLEEP on pin change 0 = After power up or other reset - : Unimplemented PA0: Program memory page select bits 0 = page 0 (000h - 1FFh) - GMS77C1000/1001 1 = page 1 (200h - 3FFh) - GMS77C1001 TO: Time-overflow bit 1 = After power-up, watchdog clear instruction, or entering power-down mode 0 = A watchdog timer time-overflow occurred PD: Power-down bit 1 = After power-up or by the watchdog clear instruction 0 = By execution of power-down mode bit0 ADDRESS ; 03H RESET VALUE : 0001_1XXX R = Readable bit W = Writable bit DC: Digit carry/borrow bit (for addition and subtraction) addition 1 = A carry from the 4th low order bit of the result occurred 0 = A carry from the 4th low order bit of the result did not occur subtraction 1 = A borrow from the 4th low order bit of the result did not occur 0 = A borrow from the 4th low order bit of the result occurred C: Carry/borrow bit (for additon,subtraction and rotation) addition 1 = A carry occurred 0 = A carry did not occur subtraction 1 = A borrow did not occur 0 = A borrow occurred rotation Load bit with LSB or MSB, respectively Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero FIGURE 9-5 STATUS REGISTER 9.4 OPTION REGISTER Nov. 2002 Ver 1.1 The OPTION register is a 8-bit wide, write-only register 21 HMS77C2000/2001 which contains various control bits to configure the Timer0/WDT prescaler and Timer0. Note: If TRIS bit is set to ‘0’, the wake-up on change and pull-up functions are disabled for that pin; i.e., note that TRIS overrides OPTION control of UPPU and UPWU. By executing the OPTION instruction, the contents of the W register will be transferred to the OPTION register. A RESET sets the OPTION<7:0> bits. If the T0CS bit is set to ‘1’, UP2 is forced to be an input even if TRIS UP2 = ‘0’. ADDRESS ; N/A RESET VALUE : 1111_1111 W W W W W W W W UPWU UPPU T0CS T0SE PSA PS2 PS1 PS0 6 5 4 3 2 1 bit7 UPWU: UPPU: T0CS: T0SE: PSA: Enable wake-up on pin change (UP0, UP1, UP3) 1 = Disabled 0 = Enabled PS2~PS0: bit0 W = Writable bit -n = Value at POR reset Prescaler rate select bits) Bit Value Timer 0 rate Enable weak pull-ups (UP0, UP1, UP3) 1 = Disabled 0 = Enabled 000 1:2 1:1 001 1:4 1:2 Timer 0 clock source select bit 1 = Transition on EC0 pin 0 = Transition on internal instruction cycle, FOSC/4 010 1:8 1:4 011 1:16 1:8 100 1:32 1:16 101 1:64 1:32 110 1:128 1:64 111 1:256 1:128 Timer 0 source edge select bit 1 = Increment on high to low transition on EC0 pin 0 = Increment on low to high transition on EC0 pin WDT rate Prescaler assignment bit 1 = Prescaler assigned to the WDT 0 = Prescaler assigned to the Timer 0 FIGURE 9-6 OPTION REGISTER 22 Nov. 2002 Ver 1.1 HMS77C2000/2001 9.5 OSCCAL REGISTER quency. The oscillator calibration (OSCCAL) register is used to calibrate the internal 4 MHz oscillator. It contains five bits for calibration. Increasing the cal value increases the fre- Also it controls power fail detection circuit by the lower 2bits. R/W R/W R/W R/W R/W R/W R/W R/W CAL4 CAL3 CAL2 CAL1 CAL0 - PFDF PFDEN 6 5 4 3 2 1 bit7 CAL4~CAL0: Calibration Bits 11111 = High frequency 10000 = Middle frequency ADDRESS ; 05H RESET VALUE : 1000_0000 R = Readable bit W = Writable bit bit0 PFDF: Power-fail detection flag bit. 1 = Reset caused by PFD reset. 0 = PFD reset is not generated. PFDEN: Power-fail detection enable bit 1 = Enable PFD 0 = Disable PFD 00000 = Low frequency FIGURE 9-7 OSCCAL REGISTER 9.6 PROGRAM COUNTER As a program instruction is executed, the program counter (PC) will contain the address of the next program instruction to be executed. The PC value is increased by one every instruction cycle, unless an instruction changes the PC. GOTO Instruction PC Instructions where the PCL is the destination, or Modify PCL instructions, include MOVWF PC, ADDWF PC, and BSF PC,5. 0 PCL Instruction Word For a GOTO instruction, bits 8~0 of the PC are provided by the GOTO instruction word. The PC Latch (PCL) is mapped to PC<7~0>. Bit 5 of the STATUS register provides page information to bit 9 of the PC (Figure 9-8). For a CALL instruction, or any instruction where the PCL is the destination, bits 7~0 of the PC again are provided by the instruction word. However, PC<8> does not come from the instruction word, but is always cleared (Figure 98). 8 7 11 10 9 7 0 PA0 STATUS CALL or Modify PCL Instruction 8 7 11 10 9 PC 0 PCL Instruction Word 7 Reset to ‘0’ 0 PA0 Note: Because PC<8> is cleared in the CALL instruction, or any Modify PCL instruction, all subroutine calls or computed jumps are limited to the first 256 locations of any program memory page (512 words long). Nov. 2002 Ver 1.1 STATUS FIGURE 9-8 LOADING OF PC BRANCH INSTRUCTION 23 HMS77C2000/2001 Device Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on reset Value after reset - PC8 PCL 11 1111 1111 01 1111 1111 HMS77C2001 PC9 PC8 PCL 11 1111 1111 11 1111 1111 HMS77C2000 Bit 9 : Page select bit, provided by PA0 bit of STATS register (HMS77C2001) 1 = Page 1 (200H ~ 3FFH) 0 = Page 0 (000H ~ 1FFH) Bit 8 : Half-page select bit, provided by GOTO instruction (HMS77C2000, HMS77C2001) or cleared when CALL or any modify-PCL instruction are executed. 1 = Half page 1 (200H ~ 2FFH) 0 = Half page 0 (000H ~ 0FFH) Bit 7 ~ 0 : PCL register FIGURE 9-9 PROGRAM COUNTER 9.6.1 EFFECTS OF RESET The program counter is set upon a RESET, which means that the PC addresses the last location in the last page i.e., the oscillator calibration instruction. After executing MOVLW XX, the PC will roll over to location 00H, and begin executing user code. The STATUS register page preselect bits are cleared upon a RESET, which means that page 0 is preselected. Therefore, upon a RESET, a GOTO instruction will automatically cause the program to jump to page 0 until the value of the page bits is altered. 9.7 STACK The HMS77C2000 and HMS77C2001 devices have a 12bit wide L.I.F.O. hardware push/pop stack. A CALL instruction will push the current value of stack into stack 2 and then push the current program counter value, incremented by one, into stack level 1. If more than two 24 sequential ‘CALL’s are executed, only the most recent two return addresses are stored. A RETLW instruction will pop the contents of stack level into the program counter and then copy stack level 2 contents into level 1. If more than two sequential ‘RETLW’s are executed, the stack will be filled with the address previously stored in level 2. Note that the W register will be loaded with the literal value specified in the instruction. This is particularly useful for the implementation of data look-up tables within the program memory. Upon any reset, the contents of the stack remain unchanged, however the program counter (PCL) will also be reset to 0. Note: There are no STATUS bits to indicate stack overflows or stack underflow conditions. There are no instructions mnemonics called PUSH or POP. These are actions that occur from the execution of the CALL and RETLW instructions. Nov. 2002 Ver 1.1 HMS77C2000/2001 9.8 INDIRECT DATA ADDRESSING; INDF AND FSR REGISTERS indirect addressing is shown in Example 4-2. EXAMPLE 4-2: HOW TO CLEAR RAM USING INDIRECT ADDRESSING The INDF register is not a physical register. Addressing INDF actually addresses the register whose address is contained in the FSR register (FSR is a pointer). This is indirect addressing. movlw 0x10 NEXT EXAMPLE 4-1: INDIRECT ADDRESSING incf FSR,F btfsc FSR,4 goto NEXT ;initialize pointer ; to RAM ;clear INDF register ;inc pointer ;all done? ;NO, clear next : ;YES, continue movwf FSR clrf INDF - Register file 07 contains the value 10H - Register file 08 contains the value 0AH - Load the value 07 into the FSR register A read of the INDF register will return the value of 10H The FSR is a 5-bit wide register. It is used in conjunction with the INDF register to indirectly address the data memory area. - Increment the value of the FSR register by one (FSR = 08) The FSR<4:0> bits are used to select data memory addresses 00H to 1FH. - A read of the INDR register now will return the value of 0AH HMS77C2000: Does not use banking. FSR<7:5> are unimplemented and read as '1's. CONTINUE Reading INDF itself indirectly (FSR = 0) will produce 00H. Writing to the INDF register indirectly results in a nooperation (although STATUS bits may be affected). HMS77C2001: Uses FSR<5>. Selects between bank 0 and bank 1. FSR<7:6> is unimplemented, read as ‘1’ . A simple program to clear RAM locations 10H~1FH using (FSR) 6 5 Direct Addressing 4 (opcode) bank select Indirect Addressing (FSR) 6 5 4 0 00 location select 01 00H bank 0 location select Addresses map back to address in Bank 0. 0FH Data Memory1 10H 1FH Bank 0 Bank 12 1. For register map detail see Section 4.2. 2. HMS77C2001 FIGURE 9-10 DIRECT/INDIRECT ADDRESSING Nov. 2002 Ver 1.1 25 HMS77C2000/2001 10. I/O PORT A '0' puts the contents of the output data latch on the selected pins, enabling the output buffer. The exceptions are UP3 which is input only and UP2 which may be controlled by the option register, see Figure 9-6. As with any other register, the I/O register can be written and read under program control. However, read instructions (e.g., MOVF UPIO,W) always read the I/O pins independent of the pin’s input/output modes. On RESET, all I/ O ports are defined as input (inputs are at hi-impedance) since the I/O control registers are all set. Note: A read of the ports reads the pins, not the output data latches. That is, if an output driver on a pin is enabled and driven high, but the external system is holding it low, a read of the port will indicate that the pin is low. 10.1 UPIO UPIO is an 8-bit I/O register. Only the low order 6 bits are used (UP5:UP0). Bits 7 and 6 are unimplemented and read as '0's. Please note that UP3 is an input only pin. The configuration word can set several I/O’s to alternate functions. When acting as alternate functions the pins will read as ‘0’ during port read. Pins UP0, UP1, and UP3 can be configured with weak pull-ups and also with wake-up on change. The wake-up on change and weak pull-up functions are not pin selectable. If pin 4 is configured as RESET, weak pullup is always on and wake-up on change for this pin is not enabled. The TRIS registers are “write-only” and are set (output drivers disabled) upon RESET. 10.3 I/O INTERFACING The equivalent circuit for an I/O port pin is shown in Figure 10-1. All port pins, except UP3 which is input only, may be used for both input and output operations. For input operations these ports are non-latching. Any input must be present until read by an input instruction e.g., MOVF UPIO,W). The outputs are latched and remain unchanged until the output latch is rewritten. To use a port pin as output, the corresponding direction control bit in TRIS must be cleared (=0). For use as an input, the corresponding TRIS bit must be set. Any I/O pin (except UP3) can be programmed individually as input or output. 10.2 TRIS REGISTER The output driver control register is loaded with the contents of the W register by executing the TRIS f instruction. A '1' from a TRIS register bit puts the corresponding output driver in a hi-impedance mode. VDD Data Reg. Data Bus TRIS Reg. Data Bus VSS Data Bus Read FIGURE 10-1 EQUIVALENT CIRCUIT FOR A SINGLE I/O PIN Address N/A Name TRIS Bit7 Bit6 Bit5 Bit4 Bit3 I/O control registers Bit2 Bit1 Bit0 Power-On Reset All other Resets --11 1111 --11 1111 TABLE 10-1 SUMMARY OF PORT REGISTERS Legend: Shaded boxes = unimplemented or unused, - = unimplemented, read as ‘0’, x = unknown, u = unchanged. 26 Nov. 2002 Ver 1.1 HMS77C2000/2001 Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Power-On Reset All other Resets N/A OPTION GPWU GPPU T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 03H STATUS UPWUF PA0 T0 PD Z DC C 0001 1xxx q00q quuu1 06H UPIO UP5 UP4 UP3 UP2 UP1 UP0 11xx xxxx 11uu uuuu Address TABLE 10-1 SUMMARY OF PORT REGISTERS Legend: Shaded boxes = unimplemented or unused, - = unimplemented, read as ‘0’, x = unknown, u = unchanged. 1. If reset was due to wake-up on change, then bit 7 = 1. All other resets will cause bit 7 = 0 10.4 I/O PROGRAMMING CONSIDERATIONS 10.4.1 BI-DIRECTIONAL I/O PORTS Some instructions operate internally as read followed by write operations. The BCF and BSF instructions, for example, read the entire port into the CPU, execute the bit operation and re-write the result. Caution must be used when these instructions are applied to a port where one or more pins are used as input/outputs. For example, a BSF operation on bit5 of UPIO will cause all eight bits of UPIO to be read into the CPU, bit5 to be set and the UPIO value to be written to the output latches. If another bit of UPIO is used as a bidirectional I/O pin (say bit0) and it is defined as an input at this time, the input signal present on the pin itself would be read into the CPU and rewritten to the data latch of this particular pin, overwriting the previous content. As long as the pin stays in the input mode, no problem occurs. However, if bit0 is switched into output mode later on, the content of the data latch may now be unknown. Example 5-1 shows the effect of two sequential read-modify-write instructions (e.g., BCF, BSF, etc.) on an I/O port. pin actively outputting a high or a low should not be driven from external devices at the same time in order to change the level on this pin (“wired-or”, “wired-and”). The resulting high output currents may damage the chip. ;Initial UPIO Settings ;UPIO<5:3> Inputs ;UPIO<2:0> Outputs ; ; UPIO latch UPIO pins ; ---------- ---------BCF UPIO, 5 ;--01 -ppp --11 pppp BCF UPIO, 4 ;--10 -ppp --11 pppp MOVLW 007h ; TRIS UPIO ;--10 -ppp --11 pppp ; ;Note that the user may have expected the ;pin values to be --00 pppp. The 2nd BCF ;caused UP5 to be latched as the pin value (High). 10.4.2 SUCCESSIVE OPERATIONS ON I/O PORTS The actual write to an I/O port happens at the end of an instruction cycle, whereas for reading, the data must be valid at the beginning of the instruction cycle Figure 10-2). Therefore, care must be exercised if a write followed by a read operation is carried out on the same I/O port. The sequence of instructions should allow the pin voltage to stabilize (load dependent) before the next instruction, which causes that file to be read into the CPU, is executed. Otherwise, the previous state of that pin may be read into the CPU rather than the new state. When in doubt, it is better to separate these instructions with a NOP or another instruction not accessing this I/O port. EXAMPLE 5-1: READ-MODIFY-WRITE INSTRUCTIONS ON AN I/O PORT Nov. 2002 Ver 1.1 27 HMS77C2000/2001 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC Instruction fetched MOVWF UPIO PC+1 MOVF UPIO,W PC+2 NOP PC+3 NOP UP5:UP0 Port pin written here Instruction executed MOVWF UPIO (Write to UPIO) This example shows a write to UPIO followed by a read from UPIO. Data setup time = (0.25 TCY-TPD) where: TCY = instruction cycle TPD = propagation delay Therefore, at higher clock frequenies, a write followed by a read may be problematic. Port pin sampled here MOVF UPIO,W (Read UPIO) NOP FIGURE 10-2 SUCCESSIVE I/O OPERATION 28 Nov. 2002 Ver 1.1 HMS77C2000/2001 11. TIMER0 MODULE AND TMR0 REGISTER Counter mode is selected by setting the T0CS bit (OPTION<5>). In this mode, Timer0 will increment either on every rising or falling edge of pin T0CKI. The T0SE bit (OPTION<4>) determines the source edge. Clearing the T0SE bit selects the rising edge. Restrictions on the external clock input are discussed in detail in Section 6.1. The Timer0 module has the following features: - 8-bit timer/counter register, TMR0 - Readable and writable - 8-bit software programmable prescaler - Internal or external clock select - Edge select for external clock Figure 11-1 is a simplified block diagram of the Timer0 module. Timer mode is selected by clearing the T0CS bit (OPTION<5>). In timer mode, the Timer0 module will increment every instruction cycle (without prescaler). If TMR0 register is written, the increment is inhibited for the following two instruction cycles (Figure 11-2 and Figure 11-3). The user can work around this by writing an adjusted value to the TMR0 register. The prescaler may be used by either the Timer0 module or the Watchdog Timer, but not both. The prescaler assignment is controlled in software by the control bit PSA (OPTION<3>). Clearing the PSA bit will assign the prescaler to Timer0. The prescaler is not readable or writable. When the prescaler is assigned to the Timer0 module, prescale values of 1:2, 1:4,..., 1:256 are selectable. Section 6.2 details the operation of the prescaler. A summary of registers associated with the Timer0 module is found in Table 6-1. Data bus FOSC/4 Noise Filter 0 PSOUT 1 MUX 1 Programmable Prescaler UP2/EC0 pin MUX 0 8 Sync with Internal Clocks (2 TCY delay) T0SE T0CS1 3 PS2, PS1, PS01 TMR0 reg PSOUT Sync PSA1 Note 1 : Bits T0CS, T0SE, PSA, PS2, PS1 and PS0 are located in the OPTION register. 2 : The prescaler is shared with the watchdog timer. FIGURE 11-1 TIMER0 BLOCK DIAGRAM Nov. 2002 Ver 1.1 29 HMS77C2000/2001 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC (Program Counter) PC-1 Instruction Fetch PC PC+1 [ W ’ TMR0 ] [ TMR0 ’ W ] Instruction Executed TMR0 PC+2 PC+3 [ TMR0 ’ W ] [ TMR0 ’ W ] Write TMR0 Read TMR0 executed reads NT0 T0 T0+1 T0+2 Read TMR0 reads NT0 PC+4 PC+5 PC+6 [ TMR0 ’ W ] [ TMR0 ’ W ] Read TMR0 reads NT0 Read TMR0 Read TMR0 reads NT0+1 reads NT0+2 NT0 NT0+1 NT0+2 FIGURE 11-2 TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALER Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC (Program Counter) PC-1 Instruction Fetch Instruction Executed TMR0 PC PC+1 [ W ’ TMR0 ] [ TMR0 ’ W ] PC+2 PC+3 [ TMR0 ’ W ] Write TMR0 Read TMR0 executed reads NT0 T0 PC+4 PC+5 PC+6 [ TMR0 ’ W ] [ TMR0 ’ W ] Read TMR0 reads NT0 Read TMR0 Read TMR0 Read TMR0 reads NT0 reads NT0+1 reads NT0+2 T0+1 NT0 [ TMR0 ’ W ] NT0+1 FIGURE 11-3 TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALER 1:2 Address Name 01H TMR0 N/A OPTION N/A TRIS Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Timer0 - 8-bit real-time clock/counter Power-On Reset RESET and WDT Reset xxxx xxxx uuuu uuuu UPWU UPPU T0CS T0SE PSA PS2 PS1 PS0 1111 1111 0011 1111 - - UP5 UP4 UP3 UP2 UP1 UP0 --11 1111 --11 1111 TABLE 11-1 REGISTERS ASSOCIATED WITH TIMER0 Legend: Shaded cells not used by Timer0, - = unimplemented, x = unknown, u = unchanged. 11.1 USING TIMER0 WITH AN EXTERNAL CLOCK When an external clock input is used for Timer0, it must meet certain requirements. The external clock requirement is due to internal phase clock (TOSC) synchronization. Also, there is a delay in the actual incrementing of Timer0 after synchronization. 30 11.1.1 EXTERNAL CLOCK SYNCHRONIZATION When no prescaler is used, the external clock input is the same as the prescaler output. The synchronization of T0CKI with the internal phase clocks is accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks (Figure 11-4). Therefore, it is necessary for T0CKI to be high for at least 2TOSC (and a small RC delay of 20 ns) and low for at least 2TOSC (and Nov. 2002 Ver 1.1 HMS77C2000/2001 11.1.2 TIMER0 INCREMENT DELAY a small RC delay of 20 ns). Refer to the electrical specification of the desired device. Since the prescaler output is synchronized with the internal clocks, there is a small delay from the time the external clock edge occurs to the time the Timer0 module is actually incremented. Figure 11-4 shows the delay from the external clock edge to the timer incrementing. When a prescaler is used, the external clock input is divided by the asynchronous ripple counter-type prescaler so that the prescaler output is symmetrical. For the external clock to meet the sampling requirement, the ripple counter must be taken into account. Therefore, it is necessary for T0CKI to have a period of at least 4TOSC (and a small RC delay of 40 ns) divided by the prescaler value. The only requirement on T0CKI high and low time is that they do not violate the minimum pulse width requirement of 10 ns. Refer to parameters 40, 41 and 42 in the electrical specification of the desired device. 11.1.3 OPTION REGISTER EFFECT ON UP2 TRIS If the option register is set to read TIMER0 from the pin, the port is forced to an input regardless of the TRIS register setting. Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 External Clock Input or Prescaler Output(2) Small Pulse misses sampling (1) External Clock/Prescaler Output After Sampling (3) Increment TMR0 (Q4) TMR0 T0 T0+1 T0+2 Note 1: Delay from clock input change to TMR0 increment is 3TOSC to 7TOSC . (Duration of Q = TOSC). Therefore, the error in measuring the interval between two edges on TMR0 input = ±4TOSC max. 2: External clock if no prescaler selected, prescaler output otherwise. 3: The arrows indicate the points in time where sampling occurs. FIGURE 11-4 TIMER0 TIMING WITH EXTERNAL CLOCK 11.2 PRESCALER 11.2.1 SWITCHING PRESCALER ASSIGNMENT An 8-bit counter is available as a prescaler for the Timer0 module, or as a postscaler for the Watchdog Timer (WDT), respectively. For simplicity, this counter is being referred to as “prescaler” throughout this data sheet. Note that the prescaler may be used by either the Timer0 module or the WDT, but not both. Thus, a prescaler assignment for the Timer0 module means that there is no prescaler for the WDT, and vice-versa. The prescaler assignment is fully under software control (i.e., it can be changed “on the fly” during program execution). To avoid an unintended device RESET, the following instruction sequence (Example 6-1) must be executed when changing the prescaler assignment from Timer0 to the WDT. The PSA and PS2:PS0 bits (OPTION<3:0>) determine prescaler assignment and prescale ratio. When assigned to the Timer0 module, all instructions writing to the TMR0 register (e.g., CLRF 1, MOVWF 1, BSF 1,x, etc.) will clear the prescaler. When assigned to WDT, a CLRWDT instruction will clear the prescaler along with the WDT. The prescaler is neither readable nor writable. On a RESET, the prescaler contains all '0's. Nov. 2002 Ver 1.1 EXAMPLE 6-1: CHANGING PRESCALER (TIMER0 → WDT) 1.CLRWDT ;Clear WDT 2.CLRF TMR0 ;Clear TMR0 & Prescaler 3.MOVLW ‘00xx1111’b ;These 3 lines (5,6,7) 4.OPTION ; are required only if ; desired 5.CLRWDT ;PS<2:0> are 000 or 001 6.MOVLW ‘00xx1xxx’b ;Set Postscaler to 7.OPTION ; desired WDT rate To change prescaler from the WDT to the Timer0 module, use the sequence shown in Example 6-2. This sequence must be used even if the WDT is disabled. A CLRWDT in- 31 HMS77C2000/2001 struction should be executed before switching the prescaler. ;prescaler MOVLW ‘xxxx0xxx’ ;Select TMR0, new ;prescale value and ;clock source OPTION EXAMPLE 6-2: CHANGING PRESCALER (WDT → TIMER0) CLRWDT ;Clear WDT and TCY ( = FOSC/4) Data bus 0 8 1 Noise Filter MUX 1 0 UP2/EC0 pin MUX Sync with Internal Clocks TMR0 reg (2cycle delay) T0SE T0CS PSA 0 Watchdog Timer 1 8-bit Prescaler MUX clear 8 8 - to - 1 MUX WDT Enable bit PS2:PS0 PSA 0 1 MUX PSA WDT Time-Out FIGURE 11-5 BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER 32 Nov. 2002 Ver 1.1 HMS77C2000/2001 12. SPECIAL FEATURES OF THE CPU ability. If using XT or LF selectable oscillator options, there is always an 18 ms (nominal) delay provided by the Internal Reset Timer (IRT), intended to keep the chip in reset until the crystal oscillator is stable. If using IRC or ERC there is an 18 ms delay only on VDD power-up. What sets a microcontroller apart from other processors are special circuits to deal with the needs of real-time applications. The HMS77C2000 and HMS77C2001 have a host of such features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving operating modes and offer code protection. With this timer on-chip, most applications need no external reset circuitry. These features are: - Oscillator selection - Reset - Power-On Reset (POR) - Internal Reset Timer (IRT) - Wake-up from SLEEP on pin change - Watchdog Timer (WDT) - SLEEP - Code protection - ID locations - In-circuit Serial Programming The SLEEP mode is designed to offer a very low current power-down mode. The user can wake-up from SLEEP through a change on input pins or through a Watchdog Timer time-out. Several oscillator options are also made available to allow the part to fit the application, including an internal 4 MHz oscillator. The ERC oscillator option saves system cost while the LF crystal option saves power. A set of configuration bits are used to select various options. 12.1 CONFIGURATION BITS The HMS77C2000 and HMS77C2001 configuration word consists of 12 bits. Configuration bits can be programmed to select various device configurations. Two bits are for the selection of the oscillator type, one bit is the Watchdog Timer enable bit, and one bit is the RESET enable bit. The HMS77C2000 and HMS77C2001 have a Watchdog Timer which can be shut off only through configuration bit WDTE. It runs off of its own RC oscillator for added relibit11 Configuration Word PORLS: RESETE: 5 - 4 PORLS RESETE 3 CP 2 1 bit0 WDTE FOSC1 FOSC0 Address : FFFH Unimplemented, read as ‘0’ Power on reset level selection bit 1 = 1.7v(Typ.) 0 = Data retention voltage 0.6v(Typ.) RESET pin enable bit. 1 = RESET pin enabled 0 = RESET tied to VDD(internally). CP: Code protection bit. 1 = Code protection off 0 = Code protection on WDTE: Watchdog timer enable bit 1 = WDT enabled 0 = WDT disabled FOSC1~FOSC0: Oscillator selection bits 11 = ERC - external RC oscillator 10 = IRC - internal RC oscillator 01 = XT oscillator 00 = LF oscillator FIGURE 12-1 CONFIGURATION WORD FOR HMS77C2000/1 Nov. 2002 Ver 1.1 33 HMS77C2000/2001 12.2 OSCILLATOR CONFIGURATIONS 12.2.1 OSCILLATOR TYPES Clock from ext. system The HMS77C2000 and HMS77C2001 can be operated in four different oscillator modes. The user can program two configuration bits (FOSC1:FOSC0) to select one of these four modes: - LF: Low Frequency - XT: Crystal/resonator - IRC: Internal 4 MHz Oscillator - ERC: External Resistor/Capacitor In XT or LF modes, a crystal or ceramic resonator is connected to the UP5/XIN and UP4/XOUT pins to establish oscil lati on (Fi gure 12-2). The HMS77 C200 0 and HMS77C2001 oscillator design requires the use of a parallel cut crystal. Use of a series cut crystal may give a frequency out of the crystal manufacturers specifications. When in XT or LF modes, the device can have an external clock source drive the UP5/XIN pin (Figure 12-3). XIN SLEEP RF(2) XTAL OPEN XOUT FIGURE 12-3 EXTERNAL CLOCK INPUT OPERATION (XT OR LF OSC CONFIGURATION) 12.2.2 CRYSTAL OSCILLATOR / CERAMIC RESONATORS C11 XIN XOUT To internal logic C21 Note 1: See Capacitor Selection tables for recommended values of C1 and C2. 2: RF varies with the crystal chosen (approx. value = 10 MΩ). FIGURE 12-2 CRYSTAL OPERATION OR CERAMIC RESONATOR (XT OR LF OSC CONFIGURATION) Osc Type Resonator Freq Cap.Range C1 Cap. Range C2 XT 4.0 MHz 30 pF 30 pF TABLE 12-1 CAPACITOR SELECTION FOR CERAMIC RESONATORS Note: These values are for design guidance only. Since each resonator has its own characteristics, the user should consult the resonator manufacturer for appropriate values of external components. Osc Type Crystal Freq Cap.Range C1 Cap. Range C2 LF 32 kHz1 15 pF 15 pF XT 200 kHz 1 MHz 4 MHz 47~68 pF 15 pF 15 pF 47-68 pF 15 pF 15 pF TABLE 12-2 CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR 1. For VDD > 4.5V, C1 = C2 ≈ 30 pF is recommended. Note: These values are for design guidance only. Rs may be required to avoid overdriving crystals with low drive level specification. Since each crystal has its own characteristics, the user should consult the crystal manufacturer for appropriate values of external components. 12.2.3 EXTERNAL RC OSCILLATOR For timing insensitive applications, the RC device option offers additional cost savings. The RC oscillator frequency is a function of the supply voltage, the resistor (Rext) and capacitor (Cext) values, and the operating temperature. In addition to this, the oscillator frequency will vary from unit to unit due to normal process parameter variation. Furthermore, the difference in lead frame capacitance between 34 Nov. 2002 Ver 1.1 HMS77C2000/2001 package types will also affect the oscillation frequency, especially for low Cext values. The user also needs to take into account variation due to tolerance of external R and C components used. Figure 12-4 shows how the R/C combination is connected to the HMS77C2000 and HMS77C2001. For Rext values below 2.2 kΩ, the oscillator operation may become unstable, or stop completely. For very high Rext values e.g., 1 MΩ) the oscillator becomes sensitive to noise, humidity and leakage. Thus, we recommend keeping Rext between 3 kΩ and 100 kΩ. Although the oscillator will operate with no external capacitor (Cext = 0 pF), we recommend using values above 20 pF for noise and stability reasons. With no or small external capacitance, the oscillation frequency can vary dramatically due to changes in external capacitances, such as PCB trace capacitance or package lead frame capacitance. The Electrical Specifications sections show RC frequency variation from part to part due to normal process variation. The variation is larger for larger R (since leakage current variation will affect RC frequency more for large R) and for smaller C (since variation of input capacitance will affect RC frequency more). Also, see the Electrical Specifications sections for variation of oscillator frequency due to VDD for given Rext/ Cext values as well as frequency variation due to operating temperature for given R, C, and VDD values. VDD Rext XIN Internal Clock N Cext VSS FIGURE 12-4 EXTERNAL RC OSCILLATOR MODE 12.2.4 INTERNAL 4 MHz RC OSCILLATOR The internal RC oscillator provides a fixed 4 MHz (nominal) system clock at VDD = 5V and 25°C, see “Electrical Characteristics” section for information on variation over voltage and temperature. Nov. 2002 Ver 1.1 In addition, a calibration instruction is programmed into the top of memory which contains the calibration value for the internal RC oscillator. This location is never code protected regardless of the code protect settings. This value is programmed as a MOVLW XX instruction where xx is the calibration value, and is placed at the reset vector. This will load the W and OSCCAL registers with the calibration value upon reset and the PC will then roll over to the users program at address 000H. And the user has to consider the bits related to power fail detection circuit. If the user then want to update the calibration value, has to rewrite the OSCCAL register with the user’s settig value. OSCCAL, when written to with the calibration value, will “trim” the internal oscillator to remove process variation from the oscillator frequency. Note: Please note that erasing the device will also erase the pre-programmed internal calibration value for the internal oscillator. The calibration value must be read prior to erasing the part. so it can be reprogrammed correctly later. Bits <7:3>, CAL4-CAL0 are used for calibration. Adjusting CAL4~0 from 00000 to 11111 yields a higher clock speed. 12.3 RESET The device differentiates between various kinds of reset: - Power on reset (POR) - RESET reset during normal operation - RESET reset during SLEEP - WDT time-out reset during normal operation - WDT time-out reset during SLEEP - Wake-up from SLEEP on pin change Some registers are not reset in any way; they are unknown on POR and unchanged in any other reset. Most other registers are reset to “reset state” on power-on reset (POR), RESET, WDT or wake-up on pin change reset during normal operation. They are not affected by a WDT reset during SLEEP or RESET reset during SLEEP, since these resets are viewed as resumption of normal operation. The exceptions to this are TO, PD, and UPWUF bits. They are set or cleared differently in different reset situations. These bits are used in software to determine the nature of reset. See Table 8-3 for a full description of reset states of all reg- 35 HMS77C2000/2001 isters. Address Power-On Reset RESET Reset WDT time-out Wake-up on Pin Change W N/A qqqq xxxx1 qqqq uuuu INDF 00H xxxx xxxx uuuu uuuu TMR0 01H xxxx xxxx uuuu uuuu PC 02H 1111 1111 1111 1111 STATUS 03H 0001 1xxx q00q quuu2 FSR(HMS77C2000) 04H 111x xxxx 111u uuuu FSR(HMS77C2001) 04H 110x xxxx 11uu uuuu OSCCAL 05H 1000 0000 uuuu uuu0 UPIO 06H --xx xxxx --uu uuuu OPTION N/A 1111 1111 1111 1111 TRIS N/A --11 1111 --11 1111 Register TABLE 12-3 RESET CONDITIONS FOR ALL REGISTERS 1. Bits <7;2> of W register contain oscillator calibration values due to MOVLW XX instruction at top of memory. 2. See Table 12-7 for reset value for specific conditions. If reset was due to wake-up on pin change, then bit7 = 1. All other resets will cause bit 7 = 0. Legend: - = unimplemented, read as ‘0’, x = unknown, u = unchanged. q = value depends on condition. STATUS (Addr:03H) PCL (Addr:02H) Power On reset 0001 1xxx 1111 1111 RESET reset during normal operation 000u uuuu 1111 1111 RESET reset during SLEEP 0001 0uuu 1111 1111 WDT reset during SLEEP 0000 0uuu 1111 1111 WDT reset normal operation 0000 uuuu 1111 1111 Wake-up from SLEEP on pin change 1001 0uuu 1111 1111 TABLE 12-4 RESET CONDITIONS FOR SPECIAL REGISTER Legend : - = unimplemented, read as ‘0’, x = unknown, u = unchanged. 12.3.1 RESET ENABLE This configuration bit when unprogrammed (left in the ‘1’ state) enables the external RESET function. When pro- 36 grammed, the RESET function is tied to the internal VDD, and the pin is assigned to be a UPIO. See Figure 12-5. When pin UP3/RESET/VPP is configured as RESET, the Nov. 2002 Ver 1.1 HMS77C2000/2001 these conditions are not met, the device must be held in reset until the operating parameters are met. internal pull-up is always on. WEAK PULL-UP A simplified block diagram of the on-chip power-on reset circuit is shown in Figure 12-6. RESETE INTERNAL RESET UP3/RESET/VPP FIGURE 12-5 RESET SELECT 12.4 POWER-ON RESET (POR) The HMS77C2000 and HMS77C2001 incorporate on-chip Power-On Reset (POR) circuitry which provides an internal chip reset for most power-up situations. The on-chip POR circuit holds the chip in reset until VDD has reached a high enough level for proper operation. To take advantage of the internal POR, program the UP3/RESET/VPP pin as RESET and tie through a resistor to VDD or program the pin as UP3. An internal weak pull-up resistor is implemented using a transistor. This will eliminate external RC components usually needed to create a Poweron Reset. A maximum rise time for VDD is specified. See ‘Electrical Characteristics’ for details. When the device starts normal operation (exits the reset condition), device operating parameters (voltage, frequency, temperature, ...) must be met to ensure operation. If The power-on reset circuit and the internal reset timer circuit are closely related. On power-up, the reset latch is set and the IRT is reset. The IRT timer begins counting once it detects RESET to be high. After the time-out period, which is typically 18 ms, it will reset the reset latch and thus end the onchip reset signal. A power-up example where RESET is held low is shown in Figure 12-7. VDD is allowed to rise and stabilize before bringing RESET high. The chip will actually come out of reset TIRT msec after RESET goes high. In Figure 12-8 and Figure 12-9, the on-chip power-on reset feature is being used (RESET and VDD are tied together or the pin is programmed to be UP3.). The VDD is stable before the start-up timer times out and there is no problem in getting a proper reset. And the user can select the level of power-on reset (0.6V, 1.7V). Note: When the device starts normal operation (exits the reset condition), device operating parameters (voltage, frequency, temperature, etc.) must be meet to ensure operation. If these conditions are not met, the device must be held in reset until the operating conditions are met. Power-Up Detect VDD pin change wake-up on pin change SLEEP UP3/RESET/VPP pin RESETE WDT time out reset On-Chip IRT OSC 8-bit asynch ripple counter (start-up timer) S Q R Q Internal RESET FIGURE 12-6 SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT Nov. 2002 Ver 1.1 37 HMS77C2000/2001 VDD RESET TIRT INTERNAL POR IRT TIMER-OUT INTERNAL RESET FIGURE 12-7 TIME-OUT SEQUENCE ON POWER-UP(RESET PULLED LOW) VDD RESET TIRT INTERNAL POR IRT TIMER-OUT INTERNAL RESET FIGURE 12-8 TIME-OUT SEQUENCE ON POWER-UP(RESET TIED TO VDD): FAST VDD RISE TIME 38 Nov. 2002 Ver 1.1 HMS77C2000/2001 VDD RESET TIRT INTERNAL POR IRT TIMER-OUT INTERNAL RESET FIGURE 12-9 TIME-OUT SEQUENCE ON POWER-UP(RESET TIED TO VDD): SLOW VDD RISE TIME 12.5 INTERNAL RESET TIMER (IRT) In the HMS77C2000 and HMS77C2001, IRT runs from RESET and varies based on oscillator selection (see Table 8-5.) The IRT operates on an internal RC oscillator. The processor is kept in RESET as long as the IRT is active. The IRT delay allows VDD to rise above VDD min., and for the oscillator to stabilize. Oscillator circuits based on crystals or ceramic resonators require a certain time after power-up to establish a stable oscillation. The on-chip IRT keeps the device in a RESET condition for approximately 18ms after RESET has reached a logic high (VIHRESET) level. Thus, programming UP3/RESET/VPP as RESET and using an external RC network connected to the RESET input is not required in most cases, allowing for savings in cost-sensitive and/or space restricted applications, as well as allowing the use of the UP3/RESET/VPP pin as a general purpose input. The Device Reset time delay will vary from chip to chip due to VDD, temperature, and process variation. See AC parameters for details. The IRT will also be triggered upon a Watchdog Timer time-out. This is particularly important for applications using the WDT to wake from SLEEP mode automatically. 12.6 WATCHDOG TIMER (WDT) The Watchdog Timer (WDT) is a free running on-chip RC oscillator which does not require any external components. This RC oscillator is separate from the external RC oscil- Nov. 2002 Ver 1.1 lator of the UP5/XIN pin and the internal 4 MHz oscillator. That means that the WDT will run even if the main processor clock has been stopped, for example, by execution of a SLEEP instruction. During normal operation or SLEEP, a WDT reset or wake-up reset generates a device RESET. The TO bit (STATUS<4>) will be cleared upon a Watchdog Timer reset. The WDT can be permanently disabled by programming the configuration bit WDTE as a ‘0’ (Section 8.1). Refer to the HMS77C2000 and HMS77C2001 Programming Specifications to determine how to access the configuration word. Oscillator Configuration POR Reset Subsequent Resets IRC & ERC 18 ms(typ.) 300us(typ.) XT & LF 18 ms(typ.) 18ms(typ.) TABLE 12-5 IRT(INTERNAL RESET TIMER PERIOD) 12.6.1 WDT PERIOD The WDT has a nominal time-out period of 18 ms, (with no prescaler). If a longer time-out period is desired, a prescaler with a division ratio of up to 1:128 can be assigned to the WDT (under software control) by writing to the OPTION register. Thus, a time-out period of a nominal 2.3 seconds can be realized. These periods vary with temperature, V DD and part-to-part process variations (see DC specs). Under worst case conditions (VDD = Min., Temperature = Max., max. WDT prescaler), it may take several seconds 39 HMS77C2000/2001 before a WDT time-out occurs. and generating a device RESET. The SLEEP instruction resets the WDT and the postscaler, if assigned to the WDT. This gives the maximum SLEEP time before a WDT wake-up reset. 12.6.2 WDT PROGRAMMING CONSIDERATIONS The CLRWDT instruction clears the WDT and the postscaler, if assigned to the WDT, and prevents it from timing out SLEEP From TMR0 Clock Source Watchdog Timer 8-bit asynchronous ripple counter on-chip RC-OSC PSA clearing WDT 0 1 MUX Postscaler 8 clear 8 - to - 1 MUX enable PS2:PS0 PSA 0 To TMR0 1 MUX PSA WDTE SLEEP WDT Time-Out clearing WDT FIGURE 12-10 WATCHDOG TIMER BLOCK DIAGRAM Address N/A Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Power-On Reset All other resets OPTION GPWU GPPU T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 TABLE 12-6 SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER Legend: Shaded boxes = Not used by WDT, - = unimplemented, read as ‘0’, u = unchanged. 12.7 TIME-OUT SEQUENCE, POWER DOWN, AND WAKE-UP FROM SLEEP STATUS BITS (TO/PD/UPWUF) The TO, PD, and UPWUF bits in the STATUS register can be tested to determine if a RESET condition has been caused by a power-up , powe fail condition, a RESET, Watchdog Timer (WDT) reset or SLEEP mode wake-up reset. UPWUF TO PD RESET was caused by 0 1 1 Power-up (POR) 0 u u RESET or PFD reset from normal operation TABLE 12-7 TO/PD/UPWUF STATUS AFTER RESET Legend: u = unchanged 40 Nov. 2002 Ver 1.1 HMS77C2000/2001 UPWUF TO PD RESET was caused by 0 1 0 RESET Wake-up from SLEEP 0 0 u WDT time-out from normal operation 0 0 0 WDT wake-up from SLEEP 1 1 0 Wake-up from SLEEP on pin change VDD VDD VDD 33k Q1 10k RESET 40k1 TABLE 12-7 TO/PD/UPWUF STATUS AFTER RESET Legend: u = unchanged UPWUF TO PD Power-up 0 1 1 WDT Timeout 0 0 u SLEEP inst. 0 1 0 CLRWDT inst. u 1 1 Event Remarks No effect on PD VSS This circuit will activate reset when VDD goes below VZ + 0.7V (wher VZ=Zener voltage). FIGURE 12-11 BROWN-OUT PROTECTION CIRCUIT 1 No effect on UPUWF VDD VDD TABLE 12-8 EFFECTS AFFECTION TO/PD/UPWUF STATUS Legend: u = unchanged Note: The TO, PD, and UPWUF bits maintain their status (u) until a reset occurs. A lowpulse on the RESET input does not change the TO, PD, and UPWUF status bits. 12.8 RESET ON BROWN-OUT A brown-out is a condition where device power (VDD) dips below its minimum value, but not to zero, and then recovers. The device should be reset in the event of a brown-out. To reset HMS77C2000 and HMS77C2001 when a brownout occurs, external brown-out protection circuits may be built, as shown in Figure 12-11, Figure 12-12. VDD R1 Q1 R2 10k RESET 40k1 VSS This brown-out circuit is less expensive, although less accurate. Transistor Q1 turns off when VDD is below a certain level such that: VDD = R1/(R1+R2) = 0.7V FIGURE 12-12 BROWN-OUT PROTECTION CIRCUIT 2 12.9 POWER-DOWN MODE (SLEEP) A device may be powered down (SLEEP) and later powered up (Wake-up from SLEEP). 12.9.1 SLEEP The Power-Down mode is entered by executing a SLEEP instruction. If enabled, the Watchdog Timer will be cleared but keeps running, the TO bit (STATUS<4>) is set, the PD bit (STATUS<3>) is cleared and the oscillator driver is turned off. The I/O ports maintain the status they had before the SLEEP instruction was executed (driving high, driving Nov. 2002 Ver 1.1 41 HMS77C2000/2001 low, or hi-impedance). It should be noted that a RESET generated by a WDT timeout does not drive the RESET pin low. while in SLEEP mode. The WDT is cleared when the device wakes from sleep, regardless of the wake-up source. For lowest current consumption while powered down, the T0CKI input should be at VDD or VSS and the UP3/RESET/VPP pin must be at a logic high level (VIHMC) if RESET is enabled. 12.10 PROGRAM VERIFICATION/CODE PROTECTION 12.9.2 WAKE-UP FROM SLEEP If the code protection bit has not been programmed, the onchip program memory can be read out for verification purposes. The device can wake-up from SLEEP through one of the following events: - An external reset input on UP3/RESET/VPP pin, when configured as RESET. - A Watchdog Timer time-out reset (if WDT was enabled). - A change on input pin UP0, UP1, or UP3/RESET/VPP when wake-up on change is enabled. These events cause a device reset. The TO, PD, and UPWUF bits can be used to determine the cause of device reset. The TO bit is cleared if a WDT time-out occurred (and caused wake-up). The PD bit, which is set on power-up, is cleared when SLEEP is invoked. The UPWUF bit indicates a change in state while in SLEEP at pins UP0, UP1, or UP3 (since the last time there was a file or bit operation on UP port). Note: Right before entering SLEEP, read the input pins. When in SLEEP, wake up occurs when the values at the pins change from the state they were in at the last reading. If a wake-up on change occurs and the pins are not read before reentering SLEEP, a wake up will occur immediately even if no pins change 42 The first 64 locations can be read by the HMS77C2000 and HMS77C2001 regardless of the code protection bit setting. The last memory location cannot be read if code protection is enabled on the HMS77C2000 and HMS77C2001. 12.11 ID LOCATIONS Four memory locations are designated as ID locations where the user can store checksum or other code identification numbers. These locations are not accessible during normal execution but are readable and writable during program/verify. Use only the lower 4 bits of the ID locations and always program the upper 8 bits as ‘0’s. 12.12 POWER FAIL DETECTION PROCESSOR The HMS77C2000 and HMS77C2001 have an on-chip power fail detection circuitry to immunize against power noise. If VDD falls below a level for longer 100ns, the power fail detection processor may reset MCU to protect the Nov. 2002 Ver 1.1 HMS77C2000/2001 device from the malfunction due to Power Noise. R/W R/W R/W R/W R/W R/W R/W R/W CAL4 CAL3 CAL2 CAL1 CAL0 - PFDF PFDEN 6 5 4 3 2 1 bit7 CAL4~CAL0: Calibration Bits 11111 = High frequency 10000 = Middle frequency 00000 = Low frequency bit0 ADDRESS ; 05H RESET VALUE : 1000_0000 R = Readable bit W = Writable bit PFDF: Power-fail detection flag bit. 1 = Reset caused by PFD reset. 0 = PFD reset is not generated. PFDEN: Power-fail detection enable bit 1 = Enable PFD 0 = Disable PFD FIGURE 12-13 OSCCAL REGISTER The bit0(PFDEN) of OSCCAL register activates the PFD Circuit, and bit1(PFDF) indicates ‘power fail detection situation”. The normal detection level is typically 2.7V. Figure 12-14 shows a “power fail detection situations”. VDD Note: The PFD circuit is not implemented on the in circuit emulator, user can not experiment with it. There fore, after final development user program, this function may be experimented on OTP. TNVDD ≥ 100nS VDD=2.7V VDR TIRT PFDEN = 1 PFDR Internal RESET VDD VDD=2.7V VDR TIRT VDD ≤ VDR PFDR PFDEN = 1 Internal RESET POR When VDD falls below approximately 0.6V or 1.7V level, Power-On Reset may occur. FIGURE 12-14 POWER FAIL DETECTION SITUATIONS 12.13 IN-CIRCUIT SERIAL PROGRAMMING The HMS77C2000 and HMS77C2001 microcontrollers with EPROM program memory can be serially programmed while in the end application circuit. This is sim- Nov. 2002 Ver 1.1 ply done with two lines for clock and data, and three other lines for power, ground, and the programming voltage. This allows customers to manufacture boards with unprogrammed devices, and then program the microcontroller just before shipping the product. This also allows the most 43 HMS77C2000/2001 recent firmware or a custom firmware to be programmed. The device is placed into a program/verify mode by holding the UP0, UP1 and the other pins(UP2, UP4, UP5) low while raising the RESET (VPP) pin from VIL to VIH. UP1 becomes the programming clock and UP0 becomes the programming data. Both UP1 and UP0 are schmitt trigger inputs in this mode. After reset, a 6-bit command is then supplied to the device. Depending on the command, 14-bits of program data are then supplied to or from the device, depending if the command was a load or a read. For complete details of serial programming, please refer to the HMS77C2000 and HMS77C2001 programming specifications. A typical in-circuit serial programming connection is shown in Figure 12-15. External connector signals To Normal Connections +5V VDD 0V VSS VPP RESET/VPP CLK UP1 Data I/O UP0 To Normal Connections FIGURE 12-15 TYPICAL IN-CIRCUIT SERIAL PROGRAMMING CONNECTION 44 Nov. 2002 Ver 1.1 HMS77C2000/2001 13. IN-CIRCUIT SERIAL PROGRAMMING(ICSP) SPECIFICATIONS 13.1 PROGRAMMING THE HMS77C200X The HMS77C2000 and HMS77C2001 can be programmed using a serial method. Due to this serial programming, the HMS77C2000 and HMS77C2001 can be programmed while in the user’s system increasing design flexibility. T h i s p r o g r a m m i n g s p e c i f ic a t i o n a p p l i e s t o t h e HMS77C2000 and HMS77C2001 devices in all packages. - Perform blank check at VDD = VDDMIN. Report failure. The device may not be properly erased. - Program location with pulses and verify after each pulse at VDD = VDDP : where VDDP = VDD range required during programming (4.5V ~ 5.5V). Programming / Verify Condition 13.1.1 Hardware Requirement The HMS77C2000 and HMS77C2001 require two programmable power supplies, one for VDD(4.5V to 5.5V recommended) and one for VPP(11.25V to 11.75V). Both supplies should have a minimum resolution of 0.25V. 13.1.2 Programming Mode The programming mode for the HMS77C2000 and HMS77C2001 allows programming of user program memory, special locations used for ID, and the configuration word for the HMS77C2000 and HMS77C2001. VPP = 11.25V to 11.75V VDD = VDDP = 4.5V to 5.5V If location fails to program after “N” pulses, then report error as a programming failure. Note: Device must be verified at minimum and maximum specified operating voltages as specified in the data sheet. - Once location passes “Step 2”, apply 3x overprogramming, i.e., apply 3 times the number of pulses that were required to program the location. This will guarantee a solid programming margin. The over programming should be made “software programmable” for easy updates. - Program all locations. - Verify all locations (using speed verify mode) at VDD = VDDMIN. - Verify all locations at VDD = VDDMAX. 13.2 PROGRAM MODE ENTRY The program/verify mode is entered by holding UP0, UP1 and the other pins(UP2, UP4, UP5) low while raising VPP pin from VIL to VIHH. Once in this mode the user program memory and the test program memory can be accessed and programmed in a serial fashion. The first selected memory location is the configuration word. Incrementing the PC once (using the increment address command) selects location 0x000 of the regular program memory. Afterwards all other memory locations from 001H~1FFH(HMS77C2000), 001H~3FFH(HMS77C2001) can be addressed by incrementing the PC. If the program counter has reached the last user program location and is incremented again, the on-chip special EPROM area will be addressed. System Requirement Clearly, to implement this technique, the most stringent requirements will be that of the power supplies: - VPP: VPP can be a fixed 11.25V to 11.75V It must not exceed 13V to avoid damage to the pin and should be current limited to approximately 100mA. - VDD: 4.5V to 5.5V with 0.25V granularity. Since this method calls for verification at different VDD values, a programmable VDD power supply is needed. - Current Requirement: 200mA maximum (See Figure 13-2 to determine where the special EPROM area is located) 13.2.1 Programming Method The programming technique is described in the following section. It is designed to guarantee good programming margins. It does, however, require a variable power supply for VDD. Programming Method Details Nov. 2002 Ver 1.1 Software Requirement Certain parameters should be programmable (and therefore easily modified) for easy upgrade. - Pulse Width 45 HMS77C2000/2001 - Maximum number of pulses, present limit 3. is a MOVLW XX instruction. - Number of over-programming pulses: should be (A x N) + B, where N = number of pulses required in regular programming. In our current algorithm A=3, B=0. The ID locations area is only enabled if the device is in programming/verify mode. Thus, in normal operation mode only the memory location 000H to NNNH will be accessed and the program counter will just roll over from address NNNH to 000H when incremented. 13.2.2 Programming Pulse Width Program Memory Cells: The configuration word can only be accessed immediately after RESET/VPP going from VIL to VIHH. When programming one word of EPROM, a programming pulse width(TPW) of 100us is recommended. The Maximum number of programming attempts should be limited to 3 per word. After the first successful verify, the same location should be over-programmed with 3 additional programming. The program counter will be set to all ‘1’s upon RESET = VIL. Thus, it has the value “FFFH” when accessing the configuration EPROM. Incrementing the program counter once causes the program counter to roll over to all ‘0’s. Incrementing the program counter 4K times after reset does not allow access to the configuration EPROM. Configuration Word: Customer ID Code Locations The configuration word for oscillator selection, WDT (watchdog timer) disable and code protection, and RESET enable, POR (power-on reset) generation level selection, requires the same as program memory cells. Per definition, the first four words (address TTT to TTT + 3) are reserved for customer use. It is recommended that the customer use only the four lower order bits (bits 0 through 3) of each word and filling the eight higher order bits with ‘0’s. 13.2.3 Special Memory Locations The highest address of program memory space is reserved for the internal RC oscillator calibration value. This location should not be overwritten except when this location is blank, and it should be verified, when programmed, that it 46 A user may want to store an identification code (ID) in the ID locations and still be able to read this code after the code protection bit was programmed. Nov. 2002 Ver 1.1 HMS77C2000/2001 START Blank check @VDD=VDDMIN NO Pass ? YES Report programming failure Programm 1 Location @VPP=11.5V VDD=VDDP Pass ? Report possible Erase Failure Continue programming at user’s option NO N>3? NO N=N+1 (N = # of program pulses) YES Increment PC to point to next location, N=0 Apply N additional Program pulse NO All location done YES Verify all locations @VDD = VDDMIN Pass ? NO Report verify failure @VDDMIN NO Report verify failure @VDDMAX YES Verify all locations @VDD = VDDMAX Pass ? YES Now porgram configuration word Verify configuration word @VDDMAX & VDDMIN END FIGURE 13-1 PROGRAMMING METHOD FLOWCHART Nov. 2002 Ver 1.1 47 HMS77C2000/2001 Address 0 Bit Number 11 000H Use porgram Memory (NNNH+1)x12 bit NNNH TTTH 0 0 ID0 TTTH + 1 0 0 ID1 TTTH + 2 0 0 ID2 TTTH + 3 0 0 ID3 For Customer Use (4x4 bit usable) For Factory Use TTTH + 3FH FFFH Cofiguration word 6 bits NNNH : Highest normal EPROM memory address. NNNH = 1FFH for HMS77C2000, NNNH = 3FFH for HMS77C2001 Note that some versions will have an oscillator calibration value programmed at NNNH. TTTH : Start address of special EPROM area and ID locations. TTTH = 200H for HMS77C2000 TTTH = 400H for HMS77C2001 FIGURE 13-2 SERIES PROGRAM MEMORY MAP IN PROGRAM/VERIFY MODE Example: Customer Code D1D2H The Customer ID code “D1D2H” should be stored in the ID locations 200H ~ 203H like this (HMS77C2000): 2000 2001 2002 2003 : : : : 0000 0000 0000 0000 0000 0000 0000 0000 1101 0001 1101 0010 to VIHH. Once in this mode the user program memory and the configuration memory can be accessed and programmed in a serial fashion. The mode of operation is serial. UP0 and UP1 are Schmitt Trigger inputs in this mode. The sequence that enters the device into the programming/ verify mode places all other logic into the reset state (the RESET pin was initially at VIL). The means that all I/O are in the reset state (high impedance inputs). Reading these four memory locations, even with the code protection bit programmed would still output on UP0 the bit sequence “1101”, “0001”, “1101”, “0010” which is “D1D2H”. Note: All other pins except UP0 and UP1 must be low. Note: All other locations in HMS77C2000/2001 configuration memory are reserved and should not be programmed. The UP1 pin is used as a clock input pin. and the UP0 pin is used for entering command bits and data input/output during serial operation. 13.2.4 Program / Verify Mode The program/verify mode is entered by holding pins UP0, UP1 and the other pins low while raising VPP pin from VIL 48 Program/Verify Operation To input a command, the clock pin (UP1) is cycled six times. Each command bit is latched on the falling edge of the clock with the LSB of the command being input first. The data on pin UP0 is required to have a minimum setup and hold time (See AC/DC spec.) with respect to the fall- Nov. 2002 Ver 1.1 HMS77C2000/2001 ing edge of the clock. - Commands that have data associated with them (read and load) are specified to have a minimum delay of 1us between the command and the data. After this delay the clock pin is cycled 16 times with the first cycle being a start bit and the last cycle being a stop bit. Data is also input and output LSB first. Therefore, during a read operation the LSB will be transmitted onto pin UP0 on the rising edge of the second cycle, and during a load operation the LSB will be latched on the falling edge of the second cycle. A minimum 1us delay is also specified between consecutive commands. Read Data After receiving this command, the chip will transmit data bits out of the memory currently accessed starting with the second rising edge of the clock input. The UP0 pin will go into output mode on the second rising clock edge, and it will revert back to input mode (hi-impedance) after the 16th rising edge. Because this is a 12 bit core, the two MSB’s of the data are unused and read as ‘0’. A timing diagram of this command is shown in Figure 13-5. - Increment Address The PC is incremented when this command is received. A timing diagram of this command is shown in Figure 13-6. - Begin Programming A load data command must be given before every begin programming command. Programming of the appropriate memory (test program memory or user program memory) will begin after this command is received and decoded. Programming should be performed with a series of 100us programming pulses. A programming pulse is defined as the time between the begin programming command and the End programming command. - End Programming As soon as receiving end programming command, the chip stops programming the memory (configuration program memory or user program memory) that it was programming at the time. All commands are transmitted LSB first. Data words are also transmitted LSB first. The data is transmitted on the rising edge and latched on the falling edge of the clock. To allow for decoding of commands and reversal of data pin configuration, a time separation of at least 1us is required between a command and a data word (or another command). Mapping (MSB ... LSB) Data Load data 0 0 0 0 1 0 0, data(14),0 Read data 0 0 0 1 0 0 0, data(14),0 Increment address 0 0 0 1 1 0 Begin programming 0 0 1 0 0 0 End programming 0 0 1 1 1 0 Command TABLE 13-1 COMMAND MAPPING - Load Data After receiving this command, the chip will load in a 14-bit “data word” when 16 cycles are applied, as described previously. Because this is a 12bit core, the two MSB’s of the data are ignored. A timing diagram for the load data command is shown in Figure 13-4. Nov. 2002 Ver 1.1 13.3 CONFIGURATION WORD The HMS77C2000 and HMS77C2001 devices have several configuration bits. These bits can be programmed (reads ‘0’) or left unprogrammed (reads ‘1’) to select various device configurations. 49 HMS77C2000/2001 bit11 - Configuration Word PORLS: 4 5 PORLS RESETE 3 CP 2 1 bit0 WDTE FOSC1 FOSC0 Address : FFFH Unimplemented, read as ‘0’ Power on reset level selection bit 1 = 1.7v(Typ.) 0 = Data retention voltage 0.6v(Typ.) RESETE: RESET pin enable bit. 1 = RESET pin enabled 0 = RESET tied to VDD(internally). CP: Code protection bit. 1 = Code protection off 0 = Code protection on WDTE: Watchdog timer enable bit 1 = WDT enabled 0 = WDT disabled FOSC1~FOSC0: Oscillator selection bits 11 = ERC - external RC oscillator 10 = IRC - internal RC oscillator 01 = XT oscillator 00 = LF oscillator FIGURE 13-3 CONFIGURATION WORD FOR HMS77C2000/1 13.4 CODE PROTECTION The program code written into the EPROM can be protected by writing to the CP bit of the configuration word. In the HMS77C2000 and HMS77C2001, it is still possible to program and read locations 000H through 03FH, after code protection. Once code protection is enabled, all code protected locations read 555H and prevented from further programming. All unprotected segments, including the internal oscillator calibration value, ID, and configuration word read as normal. These locations can be programmed. 13.4.1 Embedding Configuration Word and ID information in the Hex File To allow portability of code, the programmer is required to read the configuration word and ID locations from the hex file when loading the hex file. If configuration word information was not present in the hex file then a simple warning message may be issued. Similarly, while saving a hex file, configuration word and ID information must be included. An option to not include this information may be provided. Program Memory Segment R/W in Protected Mode R/W in Unprotected Mode Configuration Word (FFFH) R/W Enable R/W Enable 00H ~ 3FH R/W Enable R/W Enable 40H ~ 1FEH Read Disable (555H), Write Disable R/W Enable 1FFH Oscillator Calibration Value R/W Enable R/W Enable ID Location (200H ~ 203H) R/W Enable R/W Enable TABLE 13-2 CODE PROTECTION(HMS77C2000) 50 Nov. 2002 Ver 1.1 HMS77C2000/2001 Program Memory Segment R/W in Protected Mode R/W in Unprotected Mode Configuration Word (FFFH) R/W Enable R/W Enable 00H ~ 3FH R/W Enable R/W Enable 40H ~ 3FEH Read Disable(555H), Write Disable R/W Enable 3FFH Oscillator Calibration Value R/W Enable R/W Enable ID Location (400H ~ 403H) R/W Enable R/W Enable TABLE 13-3 CODE PROTECTION(HMS77C2001) - 13.4.2 Checksum Calculations Checksum is calculated by reading the contents of the HMS77C2000 and HMS77C2001 memory locations and adding up the opcodes up to the maximum user addressable location, (not including the last location which is reserved for the oscillator calibration value). Any carry bits exceeding 16-bits are neglected. Finally, the configuration word (appropriately masked) is added to the checksum. Checksum computation for the HMS77C2000 and HMS77C2001 are shown in Table 13-4 . The checksum is calculated by summing the following: - The contents of all program memory locations - The configuration word, appropriately masked Device Masked ID locations (when applicable) The least significant 16 bits of this sum is the checksum The following table describes how to calculate the checksum for each device. Note that the checksum calculation differs depending on the code protect setting. Since the program memory locations read out differently depending on the code protect setting, the table describes how to manipulate the actual program memory values to simulate the values that would be read from a protected device. When calculating a checksum by reading a device, the entire program memory can simply be read and summed. The configuration word and ID locations can always be read. The oscillator calibration value location is not used in the above checksums. Code Protect Checksum HMS77C2000 OFF ON SUM [000H ~ 1FEH] + CFGW & 03FH SUM [000H ~ 03FH] + CFGW & 03FH + SUM(IDS) HMS77C2000 OFF ON SUM [000H ~ 3FEH] + CFGW & 03FH SUM [000H ~ 03FH] + CFGW & 03FH + SUM(IDS) TABLE 13-4 CHECKSUM COMPUTATION Legend: CFGW = Configuration Word SUM[a~b] = [ Sum of locations a through b inclusive] SUM_ID = ID locations masked by FH then made into a 16 bit value with ID0 as the most significant nibble. For example, ID0 = 12H, ID1 = 37H, ID2 = 4H, ID0 = 26H, then SUM_ID = 2746H. Checksum = [Sum of all the individual expressions] MODULO [FFFFH] + = addition, & = Bitwise AND Nov. 2002 Ver 1.1 51 HMS77C2000/2001 13.5 PROGRAM/VERIFY MODE ELECTRICAL CHARACTERISTICS Parameter Sym. Characteristic Min. Typ. Max. Unit PD1 VDDP Supply voltage 4.75 5.0 5.25 V PD2 IDDP Supply current during programming 20 mA from VDD PD3 VDDV Supply voltage during verify VDDMIN VDDMAX V Note1 PD4 VIHH Induced Voltage for program mode entry 11.25 11.75 V PD5 IPP Programming supply current 50 mA from VPP PD6 VIH1 UP0, UP1 input high level 0.8 VDD VDD V Schmit Trigger Input PD7 VIL1 UP0, UP1 input low level 0 0.2VDD V Schmitt Trigger Input P1 TR VPP pin rising time - - 1 ms P2 TF VPP pin falling time - - 1 ms P3 TSET1 Data in setup time before clock ↓ 100 ns P4 THLD1 Data in hold time before clock ↓ 100 ns P5 TDLY1 Data input not driven to next clock input (delay required between command/data or command/command) 1.0 us P6 TDLY2 Delay between clock ↓ to clock ↑ of next command or data 1.0 us P7 TDLY2 Clock ↑ to data out valid (during read data) 200 ns P8 THLD0 Hold time after VPP ↑ 2 us 11.5 Condition TABLE 13-5 AC/DC CHARACTERISTICS TIMING REQUIREMENTS FOR PROGRAM/VERIFY MODE 1. Program must be verified at the minimum and maximum VDD limits for the part. 52 Nov. 2002 Ver 1.1 HMS77C2000/2001 VIHH 11V RESET/VPP 10V 100ns P8 2 1 3 4 6 5 P6 1usMIN 1 2 3 4 5 15 UP1(Clock) 0 0 1 0 ~ ~ ~ ~ 0 UP0(Data) 0 P5 1usMIN P3 P3 P4 P4 100nsMIN Reset 0 Program/Verify Mode 100nsMIN FIGURE 13-4 LOAD DATA COMMAND (PROGRAM/VERIFY) VIHH 11V RESET/VPP 10V 100ns P8 2 1 3 4 6 5 P6 1usMIN 1 2 3 4 0 1 0 0 0 B0 0 ~ ~ ~ ~ UP0(Data) 14 15 16 ~ ~ UP1(Clock) B1... B10 B11 0 0 0 P5 1usMIN P3 P4 100nsMIN Reset UP0=Input UP0=Output UP0=Input Program/Verify Mode FIGURE 13-5 READ DATA COMMAND(PROGRAM/VERIFY) Nov. 2002 Ver 1.1 53 HMS77C2000/2001 VIHH 11V RESET/VPP 10V 100ns P8 1 2 3 4 6 5 P6 1usMIN Next Command 2 1 UP1(Clock) 0 UP0(Data) 1 0 1 0 0 0 0 P5 1usMIN P3 P4 100nsMIN Reset Program/Verify Mode FIGURE 13-6 INCREMENT ADDRESS (PROGRAM/VERIFY VIHH 11V RESET/VPP 10V “End Programming” “Begin Programming” P8 1 2 3 0 0 0 4 6 5 1 2 3 4 0 1 1 1 6 5 UP1(Clock) UP0(Data) 1 0 0 0 0 Programming Pulse (internal Signal) 100us FIGURE 13-7 BEGIN & END PROGRAMMING(PROGRAM/VERIFY) 54 Nov. 2002 Ver 1.1 HMS77C2000/2001 VIHH 11V 10V RESET/VPP P1(TR) P2(TF) FIGURE 13-8 VPP RISING & FALLING Nov. 2002 Ver 1.1 55 HMS77C2000/2001 SALES NETWORKS KOREA SINGAPORE HYNIX Semiconductor Inc. Seoul Office. HYNIX Semiconductor Asia Pte. Ltd. Young Dong Bldg, 891 Daechi-dong, Kangnam-gu Seoul Korea 7 Temasek Boulevard Suntec Tower One #42-02 Singapore 038987 Tel : 02-3459-3837 Tel : 65-432-4553 Fax : 02-3459-3945 Fax : 65-336-5933 U.S.A TAIWAN HYNIX Semiconductor America Inc. HYNIX Semiconductor Taiwan Inc. 3101 North First Street San Jose, CA 95134 8FI., No.161, Section 2, Minsheng East Road., Taipei, Taiwan, R.O.C Tel : 1-408-232-8152 Tel : 886-2-2500-8357 Fax : 1-408-232-8135 Fax : 886-2-2509-8977 HONGKONG DEUTSCHLAND HYNIX Semiconductor Hongkong Ltd. HYNIX Semiconductor Deutschland GmbH. Rm 1602, 16F., Bank of America Tower 12 Harcourt Road, HongKong Frankfurter Str., 107 D-65479 Raunheim, Germany Tel : 852-2971-1614 Tel : 49-6142-921-343 Fax : 852-2971-1622 Fax : 49-6142-921-214 BEIJING OFFICE UNITED KINGDOM HYNIX Semiconductor Inc. Beijing Office. HYNIX Semiconductor U.K. Ltd. Rm. 1902 Landmark Tower, 8 North Dongsanhuam Road, Chaoyang District Beijing 100004 P.R. China 241 Brooklands Road, Weybridge, Surrey, KT13 ORH, U.K. Tel : 86-10-6590-6934 Tel : 44-1932-827-733 Fax : 86-10-6590-0908 Fax : 44-1932-827-7746 SHANGHAI OFFICE JAPAN HYNIX Semiconductor Inc. Shanghai Office. HYNIX Semiconductor Japan Inc. 3F., Tianhong Bldg. 80 Xianxia R/d, Shanghai, China Yurakucho-Denki Bld. North 9F 1-7-1, Yurakucho, Chiyoda-Ku, Tokyo, Japan Tel : 86-21-6257-5522 Tel : 81-3-3211-1911 Fax : 86-21-6209-2686 Fax : 81-3-3211-5447~8 56 Nov. 2002 Ver 1.1