ETC HV4630DJ

HV4522/HV4530
HV4622/HV4630
32-Channel Serial To Parallel Converter
with P-Channel Open Drain Outputs
Ordering Information
*
Package Options
Device
Recommended
Operating
VPP Max
44 J-Lead Quad
Ceramic Chip Carrier
44 J-Lead Quad
Plastic Chip Carrier
44 Quad Plastic
Gullwing
Die
HV4522
-220
HV4522DJ*
HV4522PJ*
HV4522PG*
HV4522X
HV4530
-300
HV4530DJ*
HV4530PJ
HV4530PG
HV4530X
HV4622
-220
HV4622DJ*
HV4622PJ*
HV4622PG*
HV4622X
HV4630
-300
HV4630DJ*
HV4630PJ
HV4630PG
HV4630X
Not Recommended for New Design
Features
General Description
❏ Processed with HVCMOS Technology
The HV45 and HV46 are low-voltage serial to high-voltage
parallel converters with P-Channel open drain outputs. These
devices have been designed for use as drivers for AC-electroluminescent displays. They can also be used in any application
requiring multiple output high-voltage current source capabilities
such as driving inkjet and electrostatic print heads, plasma
panels, or vacuum fluorescent displays.
❏ Output voltages to -300V
❏ Source current minimum 60 mA
❏ Shift register speed 8 MHz
❏ Polarity and blanking inputs
❏ CMOS compatible inputs
These devices consist of a 32-bit shift register, 32 data latches,
and control logic to perform polarity and blanking functions. Data
is shifted through the shift register on the logic high-to-low
transition of the clock. The HV45 shifts in the counterclockwise
direction when viewed from the top of the package and the HV46
shifts in the clockwise direction. A data output buffer is provided
for cascading devices. This output reflects the current status of
the last bit of the shift register. The data in the shift register is
latched when the latch enable pin is brought to logic high and then
returned to ground. If the latch enable pin is held high, the latch
becomes transparent and the shift register data is directly reflected in the outputs.
❏ Forward and reverse shifting options
❏ 44-lead plastic and ceramic surface mount packages
❏ Hi-Rel processing available
❏ Can be used with the HV55 and HV56 to provide 300V
push pull operation
Absolute Maximum Ratings1
Supply voltage, VDD
+0.5V to -16V
Off state output voltage
HV4530/HV4630
+0.5V to -315V
HV4522/ HV4622
+0.5V to -240V
Logic input levels
Ground
+0.5V to VDD - 0.3V
current2
Continuous total power
For applications requiring active pull down as well as pull up, the
HV45 and HV46 can be paired with the HV55 and HV56 devices,
respectively.
1.5A
dissipation 3
Operating temperature range
Storage temperature range
Lead temperature 1.6mm (1/16 inch)
from case for 10 seconds
Plastic
Ceramic
1200mW
1500mW
Ceramic -55°C to +125°C
Plastic -40°C to +85°C
-65°C to +150°C
260°C
Notes:
1. All voltages are referenced to VSS.
2. Duty cycle is limited by the total power dissipated in the package.
3. For operation above 25°C ambient derate linearly to maximum operating
temperature at 20mW/°C for plastic and at 15mW/°C for ceramic.
12-23
12
HV4522/HV4530//HV4622/HV4630
Electrical Characteristics1 (over recommended operating conditions unless noted)
DC Characteristics
Symbol
Parameter
IDD
VDD supply current
IDDQ
Min
Max
Units
-15
mA
fCLK = 8 MHz
FDATA = 4 MHz
Quiescent VDD supply current
-100
µA
VIN = VSS or VDD
IO(OFF)
Off state output current
-100
µA
All SWS parallel
IIH
High-level logic input current
-1
µA
VIH = VDD
IIL
Low-level logic input current
+1
µA
VIL = VSS
VOH
High-level output data out
V
IDout = -100µA
VOL
Low-level output voltage
-30.0
V
IHVout = -60mA
-1.0
V
IDout = -100µA
+1.5
V
IOL = +60mA
VDD + 1.0V
HVOUT
Data out
VOC
HVOUT clamp voltage
Conditions
AC Characteristics (VDD = -12V, TC = 25°C)
Symbol
Parameter
Min
Max
Units
8
MHz
Conditions
fCLK
Clock frequency
tWH/tWL
Clock width high or low
62
ns
tSU
Data set-up time before clock rises
50
ns
tH
Data hold time after clock rises
20
ns
tON
Turn ON time, HVOUT from enable
400
ns
RL = 10K to VOO MAX
tDHL
Delay time clock to data high to low
100
ns
CL = 15pF
tDLH
Delay time clock to data low to high
100
ns
CL = 15pF
tDLE
Delay time clock to LE low to high
50
ns
tWLE
Width of LE pulse
50
ns
tSLE
LE set-up time before clock falls
50
ns
Recommended Operating Conditions
Symbol
Parameter
VDD
Logic supply voltage
HVOUT
Output off voltage
VIH
High-level input voltage (LOGIC “1”)
VIL
Low-level input voltage (LOGIC “0”)
fCLK
Clock frequency
TA
Operating free-air temperature
Min
Max
Units
-10.8
-13.2
V
HV4530 and HV4630
+0.3
-300
V
HV4522 and HV4622
+0.3
-220
V
VDD + 2V
VDD
V
-2.0
V
0
8
MHz
Plastic
-40
+85
°C
Ceramic
-55
+125
°C
Note: All voltages are referenced to VSS.
12-24
HV4522/HV4530//HV4622/HV4630
Input and Output Equivalent Circuits
VSS
VSS
VSS
Data Out
Input
HVOUT
VDD
VDD
Logic Data Output
Logic Inputs
High Voltage Output
Switching Waveforms
VSS
Data Input
50%
Data Valid
50%
VSS-12
tSU
tH
VSS
Clock
50%
50%
50%
tWH
50%
VSS-12
tWL
VSS
50%
VSS-12
tDHL
Data Out
VSS
50%
VSS-12
tDLH
Latch Enable
VSS
50%
50%
VSS-12
tWLE
tDLE
tSLE
VSS
HV OUT
w/ S/R HIGH
10%
tON
12-25
VOO
12
HV4522/HV4530//HV4622/HV4630
Functional Block Diagram
VSS
Polarity
Blanking
Latch Enable
Data Input
Latch
HVOUT1
Clock
Latch
HVOUT2
32-Bit
Shift
Register
(Outputs 3 to 30
not shown)
Latch
Data Out
HVOUT31
Latch
HVOUT32
Function Table
Inputs
Function
Outputs
Shift Reg
1 2…32
HV Outputs
1
2…32
Data Out
*
Data
CLK
LE
BL
POL
All on
X
X
X
L
L
*
*…*
H
H…H
*
All off
X
X
X
L
H
*
*…*
L
L…L
*
Invert mode
X
X
L
H
L
*
*…*
*
*…*
*
H or L
↓
L
H
H
H or L *…*
*
*…*
*
Load
latches
X
H or L
↑
H
H
*
*…*
*
*…*
*
X
H or L
↑
H
L
*
*…*
*
*…*
*
Transparent
latch mode
L
↓
H
H
H
L
*…*
L
*…*
*
H
↓
H
H
H
H
*…*
H
*…*
*
Load S/R
Notes:
H = high level = -12V, L = low level = 0V, X = irrelevant, ↓ = high-to-low transition, ↑ = low-to-high transition.
* = dependent on previous stage’s state before the last CLK high-to-low transition or last LE high.
12-26
HV4522/HV4530//HV4622/HV4630
Pin Configurations
Package Outline
HV45
44 Pin J-Lead Package
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Function
HVOUT 17
HVOUT 18
HVOUT 19
HVOUT 20
HVOUT 21
HVOUT 22
HVOUT 23
HVOUT 24
HVOUT 25
HVOUT 26
HVOUT 27
HVOUT 28
HVOUT 29
HVOUT 30
HVOUT 31
HVOUT 32
N/C
Data Out
N/C
N/C
N/C
Polarity
39 38 37 36 35 34 33 32 31 30 29
Pin
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Function
Clock
VSS
VDD
Latch Enable
Data In
Blanking
HVOUT 1
HVOUT 2
HVOUT 3
HVOUT 4
HVOUT 5
HVOUT 6
HVOUT 7
HVOUT 8
HVOUT 9
HVOUT 10
HVOUT 11
HVOUT 12
HVOUT 13
HVOUT 14
HVOUT 15
HVOUT 16
Pin
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Function
Clock
VSS
VDD
Latch Enable
Data In
Blanking
HVout 32
HVOUT 31
HVOUT 30
HVOUT 29
HVOUT 28
HVOUT 27
HVOUT 26
HVOUT 25
HVOUT 24
HVOUT 23
HVOUT 22
HVOUT 21
HVOUT 20
HVOUT 19
HVOUT 18
HVOUT 17
40
28
41
27
42
26
43
25
44
24
1
23
2
22
3
21
4
20
5
19
6
18
7
8
9 10 11 12 13 14 15 16 17
top view
44-pin J-Lead Package
HV46
44 Pin J-Lead Package
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Function
HVOUT 16
HVOUT 15
HVOUT 14
HVOUT 13
HVOUT 12
HVOUT 11
HVOUT 10
HVOUT 9
HVOUT 8
HVOUT 7
HVOUT 6
HVOUT 5
HVOUT 4
HVOUT 3
HVOUT 2
HVOUT 1
N/C
Data Out
N/C
N/C
N/C
Polarity
12
12-27
HV4522/HV4530/HV4622/HV4630
Pin Configurations
Package Outline
HV45
44-Pin Plastic Gullwing (QFP) Package
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Function
HVOUT 12
HVOUT 13
HVOUT 14
HVOUT 15
HVOUT 16
HVOUT 17
HVOUT 18
HVOUT 19
HVOUT 20
HVOUT 21
HVOUT 22
HVOUT 23
HVOUT 24
HVOUT 25
HVOUT 26
HVOUT 27
HVOUT 28
HVOUT 29
HVOUT 30
HVOUT 31
HVOUT 32
N/C
Pin
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Function
Data Out
N/C
N/C
N/C
Polarity
Clock
VSS
VDD
Latch Enable
Data In
Blanking
HVOUT 1
HVOUT 2
HVOUT 3
HVOUT 4
HVOUT 5
HVOUT 6
HVOUT 7
HVOUT 8
HVOUT 9
HVOUT 10
HVOUT 11
44 43 42 41 40 39 38 37 36 35 34
Function
HVOUT 21
HVOUT 20
HVOUT 19
HVOUT 18
HVOUT 17
HVOUT 16
HVOUT 15
HVOUT 14
HVOUT 13
HVOUT 12
HVOUT 11
HVOUT 10
HVOUT 9
HVOUT 8
HVOUT 7
HVOUT 6
HVOUT 5
HVOUT 4
HVOUT 3
HVOUT 2
HVOUT 1
N/C
Pin
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
33
2
32
3
31
4
30
5
29
6
28
7
27
8
26
9
25
10
24
11
23
12 13 14 15 16 17 18 19 20 21 22
top view
44-pin PQFP Package
HV46
44-Pin Plastic Gullwing (QFP) Package
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
1
Function
Data Out
N/C
N/C
N/C
Polarity
Clock
VSS
VDD
Latch Enable
Data In
Blanking
HVOUT 32
HVOUT 31
HVOUT 30
HVOUT 29
HVOUT 28
HVOUT 27
HVOUT 26
HVOUT 25
HVOUT 24
HVOUT 23
HVOUT 22
12-28