L6239 12V DISK DRIVE SPINDLE DRIVER PRODUCT PREVIEW General MULTIPOWER BCD TECHNOLOGY 12V OPERATION REGISTER BASED ARCHITECTURE SLEEP AND IDLE MODES FOR LOW POWER CONSUMPTION SERIAL INTERFACE Spindle Driver March 1995 GND Out C 2 Out C Out B 3 Rsense2 Rsense1 4 Rsense3 Out A 5 Out B Out A 6 1 44 43 42 41 40 GND 7 39 GND Vpower 8 38 AGND Vpower 9 37 N.C. Cpump1 10 36 Ctr Tap Vpump 11 35 CSA Input Cpump2 12 34 PWM/Slew Vanalog 13 33 gm Comp bemf_det 14 32 Gate Drive Vreg_Base 15 31 PWM Timer Vreg_Vsense 16 30 N.C. GND 17 29 GND N.C. SLoad Sclk R/W POR Brake SDIO 18 19 20 21 22 23 24 25 26 27 28 Vdgtl The L6239 is a single chip sensorless (DC) spindle motor controller including power stages suitable for use in disk drives. The device has a serial interface for a microprocessor running up to 10 mega bits per second. There are registers on chip to allow the setting of the desired operating modes No external components are required in the sensor-less operation as the control functions are integrated on chip (e.g. PIN CONNECTION SYS CLOCK DESCRIPTION B.E.M.F. processing & digital masking). When a power On Reset (P.O.R.) is accepted, the internal registers are reset, the spindle power circuitry is tri-stated, and dynamic braking of the spindle is applied. This device is built in BCD II technology allowing dense digital/analog circuitry to be combined with high power DMOS output stage. GND POWER UP SEQUENCING POWER DOWN SEQUENCING PWM OPERATION LOW VOLTAGE SENSE DYNAMIC BRAKE THERMAL WARNING THERMAL SHUTDOWN NEGATIVE VOLTAGE REGULATOR SUPPORT ORDERING NUMBER: L6239 Vreg_Isense Other Functions PLCC44 Seq. Increment BEMF PROCESSING FOR SENSOR-LESS MOTOR COMMUTATION INTERNAL POWER DEVICES PROGRAMMABLE SLEW-RATE FOR REDUCED E.M.I. 20 FOR ANY HALF BRIDGE WORST CASE (1Ω PER DEVICE) B.E.M.F. DETECTION READABLE FROM REGISTER OR PIN NO SNUBBERS REQUIRED FOR LOOP COMPENSATION OR E.M.I. CONTROL D95IN222 1/13 This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice. L6239 - MICROPROCESSOR SPIN-UP & SPEED CONTROL - MICROPROCESSOR INITIATED STARTUP - SPEED COMPENSATION BY EXTERNAL RC NETWORK - NO SNUBBERS REQUIRED FOR CURRENT LOOP COMPENSATION OR EMI CONTROL - MICROPROCESSOR ACCELERATION CONTROL VIA DAC (FOR SMOOTH TRANSITION TO AT SPEED CONTROL) - GRAY CODE COUNTER FOR COMMUTATION CONTROL (INCREMENTED BY SPIN_CLOCK PIN). - BEMF DETECTION READABLE FROM REGISTERS (A,B OR C PHASES) OR PIN (BEMF_DET). AUTOMATIC CLAMPING OF OUTPUT TO PREVENT SUBSTRATE CURRENT PROGRAMMABLE SLEW RATE CONTROL (LINEAR MODE ONLY) 8 BIT RESOLUTION SPINDLE DAC FOR MICROPROCESSOR ACCELERATION CONTROL DYNAMIC BRAKING BY COMMAND FEATURES General POWER UP MICROPROCESSOR RESET SEQUENCING - POWER UP RESET AND DELAY - INTERNAL REGISTER INITIALIZATION OVER TEMPERATURE PROTECTION MASKING ON CHIP COMMUTATION EXTERNALLY CONTROLLED NEGATIVE VOLTAGE SUPPORT CIRCUITRY Interface SERIAL SYNCHRONOUS - SCLK, SLOAD, SDIO, R/W - UP TO 10 MEGABIT DATA RATE Spindle Driver INTERNAL POWER DEVICES THREE PHASE BRIDGE PLUS BIPOLAR DRIVER BLOCK DIAGRAM Vdgtl Vanalog 13 34 PWM/Linear VRef & Bias spin_range POR R/W SDIO SLoad Sclk Sequence Increment PWM Timer PWM/Slew 21 31 10 CHARGE PUMP LINEAR SLEW RATE CONTROL & PWM MONOSTABLE 12 11 9 25 22 SERIAL INTERFACE THERMAL SHUTDOWM CONTROL REGISTER 23 27 4 26 xout, yout, zout 5 xin, yin, zin 19 enable_clk 3 2 + SYS CLOCK BEMF + SENSE 42 + ZERO CROSSING DETECTOR 36 - 3 43 14 20 44 SYSTEM CLOCK 8 Ds7 ..Ds0 Spin DAC Vreg_Base Vreg_Isense Vreg_Vsense 18 16 NEGATIVE VOLTAGE REGULATOR To PWM Monostable 6,7,17,29,39,40 DRV CNTL + PWM COMP. 38 AV=4V/V 35 CSA 33 gm Comp 2/13 Brake Out A Out B Out C Ctr Tap Rsense1 Rsense2 Rsense3 + - 15 Vpower 41 bemf_A,B,C bemf_det Vpump 1 single/multi_ 6-STATE GRAY CODE COUNTER Cpump2 8 POWER STAGE 24 Cpump1 32 Gate Drive D95IN218A GND AGND CSA Input L6239 ABSOLUTE MAXIMUM RATINGS Symbol Parameter VS Maximum Supply Voltage (Vanalog, power max) VS Maximum Supply Voltage (Vdigital max) Value Unit 15 V 7 V VImax Maximum Input Voltage Vdigital ± 0.3 V VI min Minimum Input Voltage GND - 0.5 V 2.2 A Ipeak/Idc Ptot Tstg , Tj Peak Sink/Source Output Current/DC Sink Source Output Current Maximum Total Power Dissipation Maximum Storage and Junction Temperature Range 3 W -40 to 150 °C THERMAL DATA Symbol Rth j-amb Parameter Thermal Resistance Junction-ambient (standard PCB mounted) Value Unit 27 °C/W Note: This standard board construction includes: A 4 layer board, for 1cm2 hest copper area best sinks located at the chips vertices each with 4 rows of 4 columns of plated vias (od = 0.104cm, diameter = 0.0584cm) through to the ground plane. 3/13 L6239 PIN DESCRIPTION Pin Types: I = Input, O = Output, P = Power, A = Analog (passive) N. Name Function Pin Type POWER 6, 7, 17, 29, 40 Ground 38 Analog Ground 8, 9,37 VPower 13 VAnalog 21 Vdgtl Power Ground AI Analog Signal Return AI Driver Power Supply (12V) AI Analog Supply (12V) AI Logic Supply (5V) AI SERIAL INTERFACE, DIGITAL & TEST PINS 22 SDIO Serial Port Data I/O 25 R/W Serial Port Read/Write Input DI/O 27 SLoad Serial Port Chip Select. Port is selected when low DI 26 SCLK Serial Port Clock DI 19 Sequence Increment Increments the spindle commutation on low to high transition DI 23 Brake Applies braking (all low side drivers energized) after the timedefined by Brake_time. Active low DI 24 POR Resets the controller on receipt of POR low DI 14 BEMF det Post masching BEMF zero crossing signal DO 20 SYS CLK Sistem clock DI 28 TP out1 Test pin 1 TO 30 TP out2 Test pin 2 TO DI ANALOG PINS 4, 5 Coil A Motor Coil Driver for phase A. This pin is also used for sensing the BEMF AI/O 1, 2 Coil B As above for phase B AI/O 41, 42 Coil C As above for phase C AI/O 36 Center Tap 3, 43, 44 Rsense 35 Center tap motor connection AI/O Sense Resistor Pins AI/O CSA Input Current Sense Amplifier Input for sensing of voltage across the external sense resistor. AI/O 33 GM Comp A series RC network to ground that defines the compensation for the Transconductance Loop AO 32 Gate Drive (NOTE 1) For external PMOS applications AI/O 10 Cpump 1 Positive terminal of the pump capacitor A/O 12 Cpump 2 Negative terminal of the pump capacitor A/O 11 Vpump Charge pump output A/O 34 PWM/ Slew An RC network to GND defines the slew ate from this pin AO 31 PWM Timer 15 Vreg Base Masking for PWM (max) AO Negative voltage regulator - Base A/O 18 Vreg Isense Negative voltage regulator - Current input AI 16 Vreg Vsense Negative voltage regulator - Regulator AI NOTE 1: for internal mode, this pin must be grounded. For external mode, connect this pin to the external PMOS. 4/13 L6239 ELECTRICAL CHARACTERISTICS (Tamb = 0 to 70°C; VA = Vpower = 12V; Vdigital = 5V, unless otherwise specified. Parameters market with an * are guaranteed by design, but not 100% tested in production) Symbol Parameter Test Condition Min. Typ. Max. Unit V GENERAL Vanalog, Power Supply Voltage Range 10 12 13.6 Vdigital Supply Voltage Range 4.5 5 5.5 V Iready12 Quiescent Current Spindle Enabled 15 mA Isleep12 Quiescent Current Spindle Disabled 1000 µA Iready5 Quiescent Current Spindle Enabled 5 mA Isleep5 Quiescent Current Spindle Disabled 1000 µA THERMAL SHUTDOWN *ThWarn *ThSh Dwn Thermal Warning 130 150 170 °C Thermal Shutdown 155 175 195 °C 2.0 V/µs SPINDLE DRIVER SECTION Io dv/dt on Maximum Output Current 2.2 A Voltage Sew Rate Turn on 0.2 Turn off 0.1* 1.0* V/µs R DS(on) Total Total Output On Resistance (Sink + Source) Tj = 25°C, Tj = 125°C, Iload = 2.0A 1.0 2.0 Ω RDS(on) Device Sink Output On Resistance Tj = 25°C, Tj = 125°C, Iload = 2.0A 0.5 1.0 Ω Io (LEAK) Output Leakage Current 1 mA 1.5 V VF Body Diode Forward Drop Im = 2.0A Output Slew Rate R slew = 100KΩ Im = 100mA dVo/dt 0.30 0.9 V 0.35 V/µs * Yet to be confirmed DAC ACCELERATION CONTROL / SENSE AMPLIFIER RES NL Resolution Full scale Differential Non-linearity 0-1 bit excluded INL Integral Non- linearity FS Full Scale Accuracy CT Conversion Time FSCT Full Scale Temp Coefficient 0 to 125°C Gain Curr. Sense Gain Ratio 4:1 or 20:1 1% resistence tolerance (0.5Ω) DAC out OFFSET DAC Output 0 Input Offset of Sense Amp 0 7 8 bits 0.5 LSB 1.5 LSB 5 % 10 µs 250 ppm/°C TBD % 2 V 15 mV LOGIC SECTION (All digital inputs are CMOS compatible) Vih High Level Input Voltage 3.5 Vil Low Level Input Voltage Voh High Level Output Voltage Iout = 1.0mA Vol Low Level Output Voltage Iout = 1.0mA Iin Input Leakage Current Tj = 125°C, 1 Iwsi Minimum Sequence Increment High Time Fsys System Clock Frequency V 1.5 V 0.4 V 1 mA 10.0 MHz 4.5 -1 V Note 1 5/13 L6239 ELECTRICAL CHARACTERISTICS (continued) Symbol Parameter Test Condition Min. Typ. Max. Unit C in Logic Input Capacitance (except Serial Port Clock) All inputs except SCLK 5 pF C in Serial Port Clock Input Capacitance (Logic Level Low) SCLK 10 pF PORIN POR Pulse Width µs 1 4 Note1: The minimum time that the Sequence Increment pin must be held high during eternal sequence incrementing is equal to SysCk BEMF AMPLIFIER IAmpin Input Bias Current VBEMF Minimum Bemf (Pk-Pk) 60 Voltage Offset Hysteresis 11 VOFF_HYST 10.0 µA mV 18 25 mV 500 ms 10 µA BRAKE Tbrake Time from POR signal receipt to expected receipt of Brake signal Ibrlk Brake Leakage Current Ibrin Brake Low Input Current 0.01 µA 100 NEGATIVE VOLTAGE REGULATOR - CURRENT SENSE COMPARATOR Ibias Input Bias Current 0.3V input 2 µA Tresp Response Time 20mV overdrive 1 µs HighTh High hysteresis threshold 0.336 0.464 V LowTh Low Hysteresis Threshold 0.033 0.046 V NEGATIVE VOLTAGE REGULATOR - VOLTAGE SENSE COMPARATOR Ibias Input Bias Current 0.3V input 2 µA Tresp Response Time 20mV overdrive 1 µs VTh Comparator Threshold 1.20 VHys Comparator Hysteresis 5 1.27 1.333 V 20 mV NEGATIVE VOLTAGE REGULATOR - DRIVER OUTPUT Ilow Low Output Current VO < 3.5V 4 mA Vhigh Output High Voltage I = 0.1mA; (VDig = 5V) 4.8 V Vlow Output Low Voltage I = -4mA 3.5 V LOOP BACK COMPARATOR Vth 6/13 Switching Threshold 0.45 0.50 0.55 V L6239 INTERNAL REGISTER DEFINITION Spin Control Register (Reg 0) The first (bits 0-8) is to program the current to the Reg: 0 Type: Write only. BIT 0 LABEL SPIN DAC BIT 0 spindle motor to allow motor control and to present the ”at speed” voltage for the charge pump. Often this will be used to limit the start-up current. DESCRIPTION Spindle current limit LSB @POR_ LOW 0 1 SPIN DAC BIT 1 0 2 SPIN DAC BIT 2 0 3 SPIN DAC BIT 3 0 4 SPIN DAC BIT 4 0 5 SPIN DAC BIT 5 0 6 SPIN DAC BIT 6 7 SPIN DAC BIT 7 Spindle current limit MSB 0 8 SPIN RANGE Spindle transconductance loop gain range select, 0 = 4:1, 1= 20:1 0 0 System Input Register (Reg 1) Reg: 1 Type: Write only. BIT LABEL DESCRIPTION @POR_ LOW 0 SLEEP A0 puts the spindle into a high impedance state 0 1 BRAKE A1 turns on all lower spindle drivers to brake the spindle 0 2 PWM/LINEAR Selects either PWM (1) or Linear (0) modes of operation 0 3 SINGLE/MULTI 1 selects phase. A for zero crossings, 0 selects all three phases 0 4 ENABLE CLK Enables (1) the SPIN CLK pulses to increment the spindle counter 0 5 RESPHASE Logic low to reset spindle counter 0 6 TRIST di Logic low to tristate BEMF DET output. 0 7 CLKDIV2 Logic low - sys clk; logic high - half system clock 0 8 ENABLE NEG Enables Negative Voltage circuitry (when set to 1). 0 9 TIME2X Logic low - masking time equal to 512 cycles of sys clk. Logic high masking time equal to 1024 cycles of sys clk. 0 10 TEST PIN1 Test pin 0 11 TEST PIN2 Test pin 0 System Input Register (Reg 2) Reg: 2 Type: Read only. BIT LABEL DESCRIPTION @POR 0 BEMF A Phase A zero crossing detected 0 1 BEMF B Phase B zero crossing detected 0 2 BEMF C Phase C zero crossing detected 0 3 IN X Grey code counter bit X 0 4 IN Y Grey code counter bit Y 0 5 IN Z Grey code counter bit Z 0 6 THERM_WARN Thermal shutdown warning. This occurs approximately 25°C before the device goes into thermal shutdown. 0 7 LOOP_BACK If PWM bit is set to 0, this bit represent the status of the loopback comparator 0 7/13 L6239 Register Select Table INPUT: A3 - A0 REGISTER SELECTED TYPE 0000 0 WRITE 0001 1 WRITE 0010 2 READ CIRCUIT OPERATION General This device includes a sensorless spin driver, power sequencing with dynamic braking and serial interface for a microprocessor. The device is register based to eliminate single point interconnects where ever possible. It is designed to operate with a 12V power supply. POR When POR goes low, the L6239 resets itself and Symbol all registers to the ”@POR” state (see register description). The L6239 assumes that a separate brake command must be issues to brake the spindle. Serial Interface The serial interface is designed to be compatible with the Intel 80196 (and other similar micros) serial interface but is capable of faster data rates, up to 10MHz. All read and write operations must consists of 16 bits, with the 80196 this would be two 8 bit accesses. The first four bits are address and the next 12 are data. If the address is a read register, then the L6239 will use the SCLK from the system to shift out 12 bits of data from the addressed register. The system must provide 16 SCLK pulses to insure that the read operation completes. The SDIO line is capable of driving a 60pf load. Description Min. Typ. Max. Unit tRWS R/W setup time to SCLK going high 100 ns tSLS SLOAD setup time to SCLK going high 100 ns tRWH R/W hold time after SCLK going high 100 ns tSLH SLOAD hold time after SCLK going high 100 ns tSCKD SCLK high to Data Valid 10 30 50 ns tRWD R/W High to Data Valid Data bit D [0] valid from HiZ 10 30 50 ns tAS Address setup time to SCLK going high 30 ns tDS Data setup time to SCLK going high 30 ns tAH Address hold after SCLK going high 10 ns tDH Data hold time after SCLK going high 10 ns tSDZ SDIO tri-state after SLOAD going high 30 ns tRWZ SDIO tri-state afterR/W going low 30 ns tPER tREC (*) Minimum SCLK period 100 ns Recycle - Time between successive accesses 100 ns tDUT Clock duty cycle 40 50 tSCLK SCLK Clock timing 100 0.1 60 % µs (*) For 10MHz system clock operation (in other words, 1 or more clock cycles of SCLK). Serial Interface Truth Table 8/13 R/W SLOAD SDIO DIRECTION 1 1 Tri-state (Port un-selected) Tri-state 0 1 Tri-state (Port un-selected) Tri-state 0 0 Address/Data input Input 1 0 Data output Output L6239 Figure 1: Serial Write Timing Diagram R/W SLOAD tRWS tRWH tSLS tSLH tPER SCLK 4 bit address (FIXED) SDIO A0 A1 A2 12 bit address (FIXED) A3 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D94IN121 tAS tAH tDS tDH Figure 2: Serial Read Timing Diagram tSLS R/W tRWH tRWS tRWS SLOAD tPER SCLK tRWD tSCKD INPUT SDIO A0 A1 OUTPUT A2 A3 HiZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D94IN122 tAS tAH The write cycle has a fixed address and data length. Four bits of address and 12 bits of data must be clocked in to allow the data to be loaded into the desired register. The write cycle is initiated by setting SLOAD and R/W low. Setting R/W low causes the SDIO line to be tristated for data input. SLOAD low enables the internal counter to increment on the rising edge of SCLK. The address and data are clocked into the chip serially on each rising edge of SCLK as shown above. when both the 4 bits of address and the 12 bits of the data have been clocked in, then the address register will be written to with the provided data. Setting SLOAD high will clear theinternal logic and tri-state the SDIO line. This also provides a way of safely aborting a write by simply forcing SLOAD high. NOTE: SLOAD must be kept low during the entire duration of the 16 write clocks. The read cycle is initiated by setting SLOAD low and clocking in a valid read address. Only four bits of address are necessary, if more than four bits are clocked in, the four MSBs will be ignored (i.e. only the first four bits will be used). If a valid address is detected, the rising edge of R/W will liad the desired register into the internal serial/parallel register is then serially clocked out on every rising edge of SCLK (LSB is clocked out first). Additional padded bits clocked out will be zero. NOTE: If SLOAD is set low with R?W high, the current contents of the internal shift register can be clocked out. This is useful for a ”read back” of the data last written into the required register. Figure 3, illustrates the case where the serial port is deselected while reading data. During a read mode, the mP is in tri-state and the L6239 is writing data on to the SDIO pin. If the 9/13 L6239 Figure 4: System Level Interface Figure 3 CLK SCLK DATA SDIO R/W MICRO SLOAD CS1 SLOAD R/W R/W L6239 CS2 SCLK R/W SDIO CLK OTHER DEVICE DATA D95IN221 tSDZ tRWD tSCKD tRWZ CS D94IN123 L6239 is deselected by bring SLOAD high, the serial port stops writing and assumes a tri-state condition after time tSTZ. When R/W goes low, the Serial Port stops writing to SDIO. This is actually a transparent operation, since SDIO is already tri-stated. Next, SLOAD goes low, selecting the L6239, but SDIO remains low since R/W is still low. When R/W goes high, the L6239 starts to write to SDIO with the data valid after time, tRWD. At the end of the read operation, R/W goes low and SDIO goes into tristate condition after time tRWZ. drive is in bipolar mode (Unipolar is not supported). S_A_L, S_B_L and S_C_L are the lower spindle drive transistors. They are active in bipolar drive. In linear mode the active transistor’s gate drive is controlled so as to bring the current in the motor to the level set by the speed control compensation circuit or the current limit DAC. Activating the BRAKE mode turns on all the lower drivers. RESET places the state machine into a known state (see @POR column of register definitions). To increment the commutation state either Spin_Clock signal is clocked. Power Devices/Spindl State Machine S_AU, S_B_U and S_C_U are the upper spindle drive transistors. They are active whenever the Thermal Warning & Shutdown The Thermal (Shutdown) Warning is designed to allow the system to take any actions required Figure 5 +5V ENABLE_NEG Good decoupling must be used. e.g. minimum 22µF Vreg_Base Vreg_Cur + 20KΩ 1.6KΩ 2KΩ 100pF 2Ω 43KΩ 1.2V 5Ω +5V 10KΩ + - Vreg_Reg 20KΩ 20KΩ L6239 D94IN124 10/13 22µF 75Ω Load L6239 prior to the L6239 shut down at the Thermal Shutdown level. Once the Thermal SHutdown is triggered the spindle is tristated and the chip is reset (although the serial interface can still be used). No braking function taken place. The chip remains in this state with the serial interface available for access Once the device falls below the Thermal Warning temperature, the L6239 output stage is no longer tristated. If there is still sufficient motion in the motor, the µP has the opportunuty to resynchronize the output Negative Voltage Regulator Support This device includes support for a negative voltage supply. The regulator uses a regulation technique, that generates an external negative voltage, but does not require an negative power supply. the diagram below shows the circuitry included in the L6239 to support the Regulator. The more lightly colored circuitry is the recommended external circuitry that actually creates the negative voltage. The circuit has been designed so that all external componentsa can be inexpensive. For example, the transistor needs only to be a 2N@()&A and the diode a 1N4148. 11/13 L6239 PLCC44 PACKAGE MECHANICAL DATA mm DIM. MIN. TYP. MAX. MIN. TYP. MAX. A 17.4 17.65 0.685 0.695 B 16.51 16.65 0.650 0.656 C 3.65 3.7 0.144 0.146 D 4.2 4.57 0.165 0.180 d1 2.59 2.74 0.102 0.108 d2 E 0.68 14.99 0.027 16 0.590 0.630 e 1.27 0.050 e3 12.7 0.500 e4 1.98 0.078 F 0.46 0.018 F1 0.71 0.028 G M 12/13 inch 0.101 1.16 0.004 0.046 L6239 Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. 1995 SGS-THOMSON Microelectronics - All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands - Singapore Spain - Sweden - Switzerland - Taiwan - Thaliand - United Kingdom - U.S.A. 13/13