Pin Information for the Cyclone® IV EP4CE6 Device Version 1.2 Notes (1), (2), (3) Bank Number B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B3 B3 VREFB Group Pin Name / Function VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB3N0 VREFB3N0 PT-EP4CE6-1.2 Copyright © 2011 Altera Corp. IO IO IO IO IO IO IO IO IO nSTATUS IO IO IO IO IO DCLK IO nCONFIG TDI TCK TMS TDO nCE CLK1 CLK2 CLK3 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO Optional Function(s) Configuration Function F256/ U256 DIFFIO_L6p DIFFIO_L6n DIFFIO_L7p DIFFIO_L7n DIFFIO_L8p DIFFIO_L8n VREFB2N0 DIFFIO_L9p DIFFIO_L9n RUP1 RDN1 D4 E5 F5 B1 C2 C1 F3 D2 D1 F4 G5 F2 F1 G2 G1 H1 H2 H5 H4 H3 J5 J4 J3 E1 M2 M1 J2 J1 J6 K6 L6 K2 K1 L2 L1 L3 N2 N1 K5 L4 DIFFIO_L10p DIFFIO_L10n DIFFIO_B1p DIFFIO_B1n R1 P2 P1 N3 P3 DIFFIO_L1p DIFFIO_L1n VREFB1N0 DIFFIO_L2p DIFFIO_L2n DATA1,ASDO FLASH_nCE,nCSO nSTATUS DIFFIO_L3p DIFFIO_L3n DIFFIO_L4p DIFFIO_L4n DCLK DATA0 nCONFIG TDI TCK TMS TDO nCE DIFFCLK_0n DIFFCLK_1p DIFFCLK_1n DIFFIO_L5p DIFFIO_L5n E144 (4) DQS for X8/X9 in F256/U256 DQS for X16/X18 in F256/U256 DQS for X8/X9 in E144 1 2 3 DQS2L/CQ3L DQS2L/CQ3L DQS2L/CQ3L DQS0L/CQ1L,DPCLK0 DQS0L/CQ1L,DPCLK0 DQS1L/CQ1L#,DPCLK1 DQS1L/CQ1L#,DPCLK1 DQS3L/CQ3L# DQS3L/CQ3L# 6 7 8 9 10 DQS0L/CQ1L,DPCLK0 11 12 13 14 15 16 18 20 21 23 24 25 DQ1L DQ1L 28 DQ1L 30 DQS1L/CQ1L#,DPCLK1 DQ1L 31 DQ1L DQ1L 32 DQ1L 33 DQ1L 34 DQS3L/CQ3L# DQ1L DM1L/BWS#1L 38 39 DM3B/BWS#3B Pin List DM5B/BWS#5B Page 1 of 8 Pin Information for the Cyclone® IV EP4CE6 Device Version 1.2 Notes (1), (2), (3) Bank Number B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 VREFB Group Pin Name / Function VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 PT-EP4CE6-1.2 Copyright © 2011 Altera Corp. IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO Optional Function(s) DIFFIO_B2p DIFFIO_B2n PLL1_CLKOUTp PLL1_CLKOUTn DIFFIO_B4p DIFFIO_B4n VREFB3N0 DIFFIO_B5p DIFFIO_B5n DIFFIO_B6p DIFFIO_B6n DIFFIO_B7p DIFFIO_B7n DIFFIO_B8p DIFFIO_B8n DIFFIO_B9p DIFFIO_B9n DIFFIO_B10p DIFFIO_B10n DIFFIO_B11p DIFFIO_B11n DIFFIO_B12p DIFFIO_B12n DIFFIO_B13p DIFFIO_B13n DIFFIO_B14p DIFFIO_B14n DIFFIO_B15p DIFFIO_B15n DIFFIO_B16p DIFFIO_B16n DIFFIO_B17p DIFFIO_B17n DIFFIO_B18p DIFFIO_B18n VREFB4N0 DIFFIO_B19p DIFFIO_B19n RUP2 RDN2 DIFFIO_B20p DIFFIO_B20n Configuration Function F256/ U256 R3 T3 T2 R4 T4 N5 N6 M6 P6 M7 K8 R5 T5 R6 T6 L7 R7 T7 L8 M8 N8 P8 R8 T8 R9 T9 K9 L9 M9 N9 R10 T10 R11 T11 R12 T12 K10 L10 P9 P11 R13 T13 M10 N11 T14 T15 E144 (4) DQS for X8/X9 in F256/U256 DQ3B 42 DQS1B/CQ1B#,DPCLK2 43 44 DQ3B DQ3B DQ3B 46 DQS3B/CQ3B# DQS for X16/X18 in F256/U256 DQ5B DQS1B/CQ1B#,DPCLK2 DQS3B/CQ3B# DQ5B DQ3B DQ5B DQ3B DQ3B DQS5B/CQ5B# 49 DQ3B 50 DM5B/BWS#5B 51 DQ5B DQ5B 52 53 54 55 DQ5B DQ5B DQS5B/CQ5B# DQ5B DM5B/BWS#5B DQ5B DQ5B DQ5B 58 DQ5B DQS4B/CQ5B 59 DQ5B 60 DQ5B DQ5B DQ5B DQ5B DQS4B/CQ5B DQ5B 64 DQS2B/CQ3B 65 DQS2B/CQ3B Pin List DQS3B/CQ3B# DQS5B/CQ5B# DQ1B DQ1B DQ1B DQ1B DQS4B/CQ5B DQ1B DQ1B DQ5B DQ5B DQ5B DQ1B DQ1B 66 67 DQ5B 68 DQS0B/CQ1B,DPCLK3 DQS1B/CQ1B#,DPCLK2 DQ5B DQ5B DQ5B DQ3B DQ5B DQS for X8/X9 in E144 DQ5B DQS0B/CQ1B,DPCLK3 DQS0B/CQ1B,DPCLK3 Page 2 of 8 Pin Information for the Cyclone® IV EP4CE6 Device Version 1.2 Notes (1), (2), (3) Bank Number B4 B4 B4 B4 B4 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 VREFB Group Pin Name / Function VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB5N0 VREFB5N0 VREFB5N0 VREFB5N0 VREFB5N0 VREFB5N0 VREFB5N0 VREFB5N0 VREFB5N0 VREFB5N0 VREFB5N0 VREFB5N0 VREFB5N0 VREFB5N0 VREFB5N0 VREFB5N0 VREFB5N0 VREFB5N0 VREFB5N0 VREFB5N0 VREFB5N0 VREFB5N0 VREFB5N0 VREFB5N0 VREFB5N0 VREFB6N0 VREFB6N0 VREFB6N0 VREFB6N0 VREFB6N0 VREFB6N0 VREFB6N0 VREFB6N0 VREFB6N0 VREFB6N0 VREFB6N0 VREFB6N0 VREFB6N0 VREFB6N0 VREFB6N0 VREFB6N0 PT-EP4CE6-1.2 Copyright © 2011 Altera Corp. IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO CLK7 CLK6 CLK5 CLK4 CONF_DONE MSEL0 MSEL1 MSEL2 IO IO IO IO IO IO IO IO IO IO Optional Function(s) Configuration Function DIFFIO_B21p DIFFIO_B21n DIFFIO_B22p DIFFIO_B22n RUP3 RDN3 DIFFIO_R11n DIFFIO_R11p DIFFIO_R10n DIFFIO_R10p VREFB5N0 DIFFIO_R9n DIFFIO_R9p DIFFIO_R8n DIFFIO_R8p DIFFIO_R7n DIFFIO_R7p DIFFIO_R6n DIFFIO_R6p DEV_OE DEV_CLRn DIFFCLK_3n DIFFCLK_3p DIFFCLK_2n DIFFCLK_2p DIFFIO_R4n DIFFIO_R4p CONF_DONE MSEL0 MSEL1 MSEL2 INIT_DONE CRC_ERROR DIFFIO_R3n DIFFIO_R3p nCEO CLKUSR VREFB6N0 DIFFIO_R2n DIFFIO_R2p F256/ U256 R14 P14 L11 M11 N12 N13 M12 L12 K12 N14 P15 P16 R16 K11 N16 N15 L14 L13 L16 L15 J11 K16 K15 J16 J15 J14 J12 J13 M16 M15 E16 E15 H14 H13 H12 G12 G16 G15 F13 F16 F15 B16 F14 D16 D15 G11 E144 (4) DQS for X8/X9 in F256/U256 DQS for X16/X18 in F256/U256 DQS for X8/X9 in E144 69 70 71 72 73 74 75 76 DM1R/BWS#1R 77 DQ1R DQS3R/CQ3R# DQ1R DQS3R/CQ3R# DQS3R/CQ3R# DQS1R/CQ1R#,DPCLK4 DQS1R/CQ1R#,DPCLK4 DQS0R/CQ1R,DPCLK5 DQS0R/CQ1R,DPCLK5 DQ1R DQ1R 80 DQ1R DQ1R 83 84 DQ1R 85 DQS1R/CQ1R#,DPCLK4 86 87 DQ1R DQ1R 88 89 90 91 92 94 96 97 98 99 100 101 103 104 DQS0R/CQ1R,DPCLK5 105 Pin List Page 3 of 8 Pin Information for the Cyclone® IV EP4CE6 Device Version 1.2 Notes (1), (2), (3) Bank Number B6 B6 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 VREFB Group Pin Name / Function VREFB6N0 VREFB6N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 PT-EP4CE6-1.2 Copyright © 2011 Altera Corp. IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO Optional Function(s) Configuration Function DIFFIO_R1n DIFFIO_R1p DIFFIO_T21n DIFFIO_T21p DIFFIO_T20n DIFFIO_T20p DIFFIO_T19n DIFFIO_T19p PLL2_CLKOUTn PLL2_CLKOUTp RUP4 RDN4 DIFFIO_T18n DIFFIO_T18p DIFFIO_T17n DIFFIO_T17p VREFB7N0 DIFFIO_T16n DIFFIO_T16p DIFFIO_T15n DIFFIO_T15p DIFFIO_T14n DIFFIO_T14p DIFFIO_T13n DIFFIO_T13p DIFFIO_T12n DIFFIO_T12p DIFFIO_T11n DIFFIO_T11p DIFFIO_T10n DIFFIO_T10p DIFFIO_T9n DIFFIO_T9p DIFFIO_T8n DIFFIO_T8p VREFB8N0 DIFFIO_T7n DIFFIO_T7p DIFFIO_T6n DIFFIO_T5n DIFFIO_T5p DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 F256/ U256 C16 C15 C14 D14 D11 D12 A13 B13 A14 B14 E11 E10 A12 B12 A11 B11 C11 F10 F9 F11 A15 A10 B10 C9 D9 E9 A9 B9 A8 B8 C8 D8 E8 F8 A7 B7 F6 F7 C6 A6 B6 E7 E6 A5 A2 B5 E144 (4) DQS for X8/X9 in F256/U256 106 DQS2R/CQ3R DQ5T DQS for X16/X18 in F256/U256 DQS for X8/X9 in E144 DQS2R/CQ3R DQ5T 110 DQS0T/CQ1T,DPCLK6 DQS0T/CQ1T,DPCLK6 111 DQ5T 112 113 114 115 DQ5T DQ5T DQ5T DQ5T 119 120 121 DQS2T/CQ3T DQ5T DQ5T DQ5T DQ5T 124 DM5T/BWS#5T 125 DQS4T/CQ5T 126 127 128 129 DQS5T/CQ5T# DQ3T 132 DQ3T 133 DQ3T DQ3T 135 DQ5T DQ5T DQ5T DM5T/BWS#5T DQS4T/CQ5T DQS0T/CQ1T,DPCLK6 DQ1T DQ1T DQ5T DQ5T DQ5T DQ5T DQ1T DQS2T/CQ3T DQS5T/CQ5T# DQ5T DQ5T DQS5T/CQ5T# DQ1T DQ1T DQ5T DQ5T DQ1T 136 DQS3T/CQ3T# DQ3T 137 DQ3T 138 DQ3T DQ3T DQS3T/CQ3T# DQ5T DQ5T DQ5T DQ5T 141 DQ3T DQ5T Pin List DQS3T/CQ3T# DQ1T Page 4 of 8 Pin Information for the Cyclone® IV EP4CE6 Device Version 1.2 Notes (1), (2), (3) Bank Number B8 B8 B8 B8 B8 B8 B8 B8 VREFB Group Pin Name / Function VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 PT-EP4CE6-1.2 Copyright © 2011 Altera Corp. IO IO IO IO IO IO IO IO GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GNDA1 GNDA2 VCCINT VCCINT VCCINT VCCINT VCCINT Optional Function(s) DIFFIO_T4n DIFFIO_T4p DIFFIO_T3n DIFFIO_T3p DIFFIO_T2n DIFFIO_T2p DIFFIO_T1n DIFFIO_T1p Configuration Function F256/ U256 A4 B4 D5 D6 A3 B3 C3 D3 H7 H8 H9 H10 J7 J8 J9 J10 B2 B15 C5 C12 D7 D10 E4 E13 G4 G13 K4 K13 M4 M13 N7 N10 P5 P12 R2 R15 E2 H16 H15 M5 E12 G6 G7 G8 G9 G10 E144 (4) DQS for X8/X9 in F256/U256 DM3T/BWS#3T 142 DQS1T/CQ1T#,DPCLK7 143 144 19 27 41 48 57 63 82 95 118 123 131 140 4 22 79 DQS for X16/X18 in F256/U256 DQS for X8/X9 in E144 DM5T/BWS#5T DQS1T/CQ1T#,DPCLK7 DQS1T/CQ1T#,DPCLK7 DQ1T DM1T 36 108 5 29 45 61 78 Pin List Page 5 of 8 Pin Information for the Cyclone® IV EP4CE6 Device Version 1.2 Notes (1), (2), (3) Bank Number VREFB Group Pin Name / Function VCCINT VCCINT VCCINT VCCIO1 VCCIO1 VCCIO2 VCCIO2 VCCIO3 VCCIO3 VCCIO3 VCCIO4 VCCIO4 VCCIO4 VCCIO5 VCCIO5 VCCIO6 VCCIO6 VCCIO7 VCCIO7 VCCIO7 VCCIO8 VCCIO8 VCCIO8 VCCA1 VCCA2 VCCD_PLL1 VCCD_PLL2 Optional Function(s) Configuration Function F256/ U256 H6 H11 K7 E3 G3 K3 M3 P4 P7 T1 P10 P13 T16 K14 M14 E14 G14 A16 C10 C13 A1 C4 C7 L5 F12 N4 D13 E144 (4) DQS for X8/X9 in F256/U256 DQS for X16/X18 in F256/U256 DQS for X8/X9 in E144 102 116 134 17 26 40 47 56 62 81 93 117 122 130 139 35 107 37 109 Notes: (1) If the p pin or n pin is not available for the package, the particular differential pair is not supported. (2) For DQS pins that do not have the associated DQ pins, the particular DQS is not supported. (3) For more information about pin definition and pin connection guidelines, refer to the Cyclone IV Device Family Pin Connection Guidelines. (4) The E144 package has an exposed pad at the bottom of the package. This exposed pad is a ground pad that must be connected to the ground plane on your PCB. This exposed pad is used for electrical connectivity, and not for thermal purposes. PT-EP4CE6-1.2 Copyright © 2011 Altera Corp. Pin List Page 6 of 8 B7 B3 B4 VREFB3N0 VREFB4N0 PLL2 VREFB6N0 B8 VREFB5N0 VREFB7N0 B6 B1 B2 PLL1 VREFB8N0 B5 VREFB1N0 VREFB2N0 Pin Information for the Cyclone® IV EP4CE6 Device Version 1.2 Notes: 1. This is a top view of the silicon die. 2. This is only a pictorial representation to provide an idea of placement on the device. For exact locations, refer to the pin list and the Quartus® II software. PT-EP4CE6-1.2 Copyright © 2011 Altera Corp. Bank & PLL Diagram Page 7 of 8 Pin Information for the Cyclone® IV EP4CE6 Device Version 1.2 Version Number 1.0 1.1 1.2 PT-EP4CE6-1.2 Copyright © 2011 Altera Corp. Date 1/25/2010 12/6/2010 6/10/2011 Changes made Initial Release. Added UBGA package support. Removed Pin Definitions sheet. Revision History Page 8 of 8