AD AD9387NKBBCZ-80

FEATURES
General
Low power HDMI/DVI transmitter ideal for portable
applications
Compatible with HDMI v. 1.3, DVI v. 1.0, and HDCP v. 1.2
Single 1.8 V power supply
Video/audio inputs accept logic levels from 1.8 V to 3.3 V
64-lead LFCSP, Pb-free package
76-ball CSP_BGA, Pb-free package
Digital video
80 MHz operation supports all resolutions from 480i to
1080i and XGA at 75 Hz
Programmable 2-way color space converter
Supports RGB, YCbCr, and DDR
Supports ITU656-based embedded syncs
Automatic input video format timing detection (CEA-861D)
Digital audio
Supports standard S/PDIF for stereo LPCM or compressed
audio up to 192 kHz
8-channel, uncompressed LPCM I2S audio up to 192 kHz
Special features for easy system design
On-chip MPU with I2C® master to perform HDCP
operations and EDID reading operations
5 V tolerant I2C and HPD I/Os, no extra device needed
No audio master clock needed for supporting S/PDIF
and I2S
On-chip MPU reports HDMI events through interrupts and
registers
FUNCTIONAL BLOCK DIAGRAM
SCL SDA
INT
MCL MDA
INTERRUPT
HANDLER
I2C
SLAVE
HPD
HDCP
CORE
HDCP-EDID
MICROCONTROLLER
REGISTER
CONFIGURATION
LOGIC
I2C
MASTER
CLK
DDCSDA
DDCSCL
VSYNC
HSYNC
VIDEO
DATA
CAPTURE
DE
D[23:0]
Tx0[1:0]
COLOR
SPACE
CONVERSION
4:2:2 TO
4:4:4
CONVERSION
HDMI
Tx
CORE
XOR
MASK
Tx1[1:0]
Tx2[1:0]
TxC[1:0]
S/PDIF
MCLK
I2S[3:0]
AUDIO
DATA
CAPTURE
LRCLK
AD9387NK
SCLK
06507-001
Preliminary Technical Data
High Performance, Low Power
HDMI™/DVI Transmitter
AD9387NK
Figure 1.
APPLICATIONS
Digital video cameras
Digital still cameras
Personal media players
Cellular handsets
DVD players and recorders
Digital set-top boxes
A/V receivers
HDMI repeater/splitter
GENERAL DESCRIPTION
The AD9387NK is an 80 MHz, high definition multimedia
interface (HDMI) v.1.3 transmitter. It supports HDTV formats
up to 720p and 1080i and computer graphic resolutions up to
XGA (1024 × 768 @ 75Hz). With the inclusion of HDCP, the
AD9387NK allows the secure transmission of protected content,
as specified by the HDCP v.1.1 protocol.
The AD9387NK supports both S/PDIF and 8-channel I2S audio.
Its high fidelity, 8-channel I2S can transmit either stereo or 7.1
surround audio at 192 kHz. The S/PDIF can carry stereo LPCM
audio or compressed audio, including Dolby® Digital, DTS®,
and THX®.
The AD9387NK helps reduce system design complexity and cost
by incorporating such features as an internal MPU for HDCP
operations, an I2C master for EDID reading, a single 1.8 V power
supply, and 5 V tolerance on the I2C and hot plug detect pins.
Fabricated in an advanced CMOS process, the AD9387NK
is available in a space saving, 76-ball CSP_BGA or 64-lead LFCSP
surface-mount package. Both packages are available as Pb-free
parts and are specified from −25°C to +85°C.
Rev. PrA
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
AD9387NK
Preliminary Technical Data
TABLE OF CONTENTS
Features .............................................................................................. 1
Design Resources ..........................................................................7
Applications....................................................................................... 1
Document Conventions ...............................................................7
General Description ......................................................................... 1
PCB Layout Recommendations.......................................................8
Functional Block Diagram .............................................................. 1
Power Supply Bypassing ...............................................................8
Specifications..................................................................................... 3
Digital Inputs .................................................................................8
Absolute Maximum Ratings............................................................ 4
External Swing Resistor................................................................8
Explanation of Test Levels ........................................................... 4
Output Signals ...............................................................................8
ESD Caution.................................................................................. 4
Outline Dimensions ..........................................................................9
Pin Configuration and Function Descriptions............................. 5
Ordering Guide .............................................................................9
Applications Information ................................................................ 7
Rev. PrA | Page 2 of 12
Preliminary Technical Data
AD9387NK
SPECIFICATIONS
Table 1.
Parameter
DIGITAL INPUTS
Input Voltage, High (VIH)
Input Voltage, Low (VIL)
Input Capacitance
DIGITAL OUTPUTS
Output Voltage, High (VOH)
Output Voltage, Low (VOL)
THERMAL CHARACTERISTICS
Thermal Resistance
θJC Junction-to-Case
θJA Junction-to-Ambient
Ambient Temperature
DC SPECIFICATIONS
Input Leakage Current (IIL)
Input Clamp Voltage
Differential High Level Output Voltage
Differential Output Short-Circuit Current
POWER SUPPLY
VDD (All) Supply Voltage
VDD Supply Voltage Noise
Power-Down Current
Transmitter Supply Current 2
Transmitter Total Power
AC SPECIFICATIONS
CLK Frequency
TMDS Output CLK Duty Cycle
Worst Case CLK Input Jitter
Input Data Setup Time
Input Data Hold Time
TMDS Differential Swing
VSYNC and HSYNC Delay from DE Falling Edge
VSYNC and HSYNC Delay to DE Rising Edge
DE High Time
DE Low Time
Differential Output Swing
Low-to-High Transition Time
High-to-Low Transition Time
AUDIO AC TIMING
Sample Rate
I2S Cycle Time
I2S Setup Time
I2S Hold Time
Audio Pipeline Delay
1
2
3
Conditions
Temp
Full
Full
25°C
VI
VI
V
1.4
Full
Full
VI
VI
VDD − 0.1
Full
V
V
V
25°C
25°C
25°C
−16 mA
+16 mA
I2S and S/PDIF
AD9387NK-BCPZ-80/AD9387NK-BBCZ-80
Test Level 1
Min
Typ
Max Unit
3.5
0.7
3
−25
15.2
59
+25
V
V
pF
0.4
V
V
+85
°C/W
°C/W
°C
VI
V
V
V
IV
−10
Full
Full
25°C
25°C
Full
IV
V
IV
IV
VI
1.71
25°C
25°C
Full
Full
Full
13.5
48
25°C
25°C
IV
IV
IV
IV
IV
VI
VI
VI
VI
VI
25°C
25°C
VII
VII
75
75
490
490
Ps
Ps
Full
25°C
25°C
25°C
25°C
IV
IV
IV
IV
IV
32
192
1
kHz
UI3
ns
ns
μs
See the Explanation of Test Levels section.
Using low output drive strength.
UI = unit interval.
Rev. PrA | Page 3 of 12
+10
−0.8
+0.8
AVCC
10
1.8
1.89
50
V
mV p-p
μA
mA
mW
80
52
2
MHz
%
ns
ns
ns
mV
UI 3
UI3
UI3
UI3
10
55
100
1
1
800
1000
1
1
1200
8191
138
15
0
75
μA
V
V
V
μA
AD9387NK
Preliminary Technical Data
ABSOLUTE MAXIMUM RATINGS
EXPLANATION OF TEST LEVELS
Table 2.
Parameter
Digital Inputs
Digital Output Current
Operating Temperature Range
Storage Temperature Range
Maximum Junction Temperature
Maximum Case Temperature
Rating
5 V to 0.0 V
20 mA
−40°C to +85°C
−65°C to +150°C
150°C
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
I.
100% production tested.
II.
100% production tested at 25°C and sample tested at
specified temperatures.
III.
Sample tested only.
IV.
Parameter is guaranteed by design and characterization
testing.
V.
Parameter is a typical value only.
VI.
100% production tested at 25°C; guaranteed by design
and characterization testing.
VII.
Limits defined by HDMI specification; guaranteed by
design and characterization testing.
ESD CAUTION
Rev. PrA | Page 4 of 12
Preliminary Technical Data
AD9387NK
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
DGND
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
DVDD
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PIN 1
INDICATOR
+
AD9387NK
TOP VIEW
(Not to Scale)
DVDD
D15
D16
D17
D18
D19
D20
D21
D22
D23
MCL
MDA
SDA
SCL
DDCSDA
DDCSCL
10 9 8 7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
K
06507-002
PVDD
EXT_SWG
AVDD
HPD
TxC–
TxC+
AVDD
Tx0–
Tx0+
PD/A0
Tx1–
Tx1+
AVDD
Tx2–
Tx2+
INT
NOTES
1. GND PADDLE ON BOTTOM OF PACKAGE.
BOTTOM VIEW
(Not to Scale)
06507-003
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
DVDD
D0
DE
HSYNC
VSYNC
CLK
S/PDIF
MCLK
I2S0
I2S1
I2S2
I2S3
SCLK
LRCLK
PVDD
PVDD
Figure 3. 76-Ball BGA Configuration (Top View)
Figure 2. 64-Lead LFCSP Pin Configuration (Top View)
Table 3. Pin Function Descriptions
Pin No.
BGA
LFCSP
A1 to A10,
39 to 47,
B1 to B10, C9,
50 to 63, 2
C10, D9, D10
D1
6
C2
3
C1
4
D2
5
J3
18
Mnemonic
D[23:0]
Type 1
I
Description
Video Data Input. Digital input in RGB or YCbCr format. Supports CMOS logic levels
from 1.8 V to 3.3 V.
CLK
DE
HSYNC
VSYNC
EXT_SWG
I
I
I
I
I
K3
20
HPD
I
E2
7
S/PDIF
I
E1
8
MCLK
I
F2, F1, G2, G1
9 to 12
I2S[3:0]
I
H2
H1
J7
13
14
26
SCLK
LRCLK
PD/A0
I
I
I
K1, K2
21, 22
TxC−/TxC+
O
K10, J10
30, 31
Tx2−/Tx2+
O
Video Clock Input. Supports CMOS logic levels from 1.8 V to 3.3 V.
Data Enable Bit for Digital Video. Supports CMOS logic levels from 1.8 V to 3.3 V.
Horizontal Sync Input. Supports CMOS logic levels from 1.8 V to 3.3 V.
Vertical Sync Input. Supports CMOS logic levels from 1.8 V to 3.3 V.
Sets internal reference currents. Place 887 Ω resistor (1% tolerance) between this
pin and ground.
Hot Plug Detect Signal. This indicates to the interface if the receiver is
connected. Supports CMOS logic levels from 1.8 V to 5.0 V.
S/PDIF (Sony/Philips Digital Interface) Audio Input. This is the audio input from a
Sony/Philips digital interface. Supports CMOS logic levels from 1.8 V to 3.3 V.
Audio Reference Clock. 128 × N × fS with N = 1, 2, 3, or 4. Set to 128 × sampling
frequency (fS), 256 × fS, 384 × fS, or 512 × fS. Supports CMOS logic levels from 1.8
V to 3.3 V.
I2S Audio Data Inputs. These represent the eight channels of audio (two per
input) available through I2S. Supports CMOS logic levels from 1.8 V to 3.3 V.
I2S Audio Clock. Supports CMOS logic levels from 1.8 V to 3.3 V.
Left/Right Channel Selection. Supports CMOS logic levels from 1.8 V to 3.3 V.
Power-Down Control and I2C Address Selection. The I2C address and the PD
polarity are set by the PD/A0 pin state when the supplies are applied to the
AD9387NK. Supports CMOS logic levels from 1.8 V to 3.3 V.
Differential Clock Output. Differential clock output at pixel clock rate; TMDS
logic level.
Differential Output Channel 2. Differential output of the red data at 10× the pixel
clock rate; TMDS logic level.
Rev. PrA | Page 5 of 12
AD9387NK
Preliminary Technical Data
BGA
K7, K8
Pin No.
LFCSP
27, 28
K4, K5
Mnemonic
Tx1−/Tx1+
Type 1
O
24, 25
Tx0−/Tx0+
O
H10
32
INT
O
J2, J5, J8, K9
D5, D6, D7, E7
19, 23, 29
1,48,49
AVDD
DVDD
P
P
G4, G5, J1
15, 16, 17
PVDD
P
D4, E4, F4, J4,
G6, J6, K6, F7,
G7, H9, J9
F9
64, Paddle
on bottom
side
36
GND
P
SDA
C2
F10
35
SCL
C2
E10
37
MDA
C2
E9
38
MCL
C2
G9
34
DDCSDA
C2
G10
33
DDCSCL
C2
1
2
Description
Differential Output Channel 1. Differential output of the green data at 10× the
pixel clock rate; TMDS logic level.
Differential Output Channel 0. Differential output of the blue data at 10× the
pixel clock rate; TMDS logic level.
Interrupt. Open drain. A 2 kΩ pull-up resistor to the microcontroller I/O supply is
recommended.
1.8 V Power Supply for TMDS Outputs.
1.8 V Power Supply for Digital and I/O Power Supply. These pins supply power to
the digital logic and I/Os. They should be filtered and as quiet as possible.
1.8 V PLL Power Supply. The most sensitive portion of the AD9387NK is the clock
generation circuitry. These pins provide power to the clock PLL. The designer
should provide quiet, noise-free power to these pins.
Ground. The ground return for all circuitry on-chip. It is recommended that the
AD9387NK be assembled on a single, solid ground plane with careful attention
given to ground current paths.
Serial Port Data I/O. This pin serves as the serial port data I/O slave for register
access. Supports CMOS logic levels from 1.8V to 3.3V.
Serial Port Data Clock. This pin serves as the serial port data clock slave for
register access. Supports CMOS logic levels from 1.8V to 3.3V.
Serial Port Data I/O Master to HDCP Key EEPROM. Supports CMOS logic levels
from 1.8 V to 3.3 V.
Serial Port Data Clock Master to HDCP Key EEPROM. Supports CMOS logic levels
from 1.8 V to 3.3 V.
Serial Port Data I/O to Receiver. This pin serves as the master to the DDC bus.
Supports 5 V CMOS logic level.
Serial Port Data Clock to Receiver. This pin serves as the master clock for the DDC
bus. Supports 5 V CMOS logic level.
I = input, O = output, P = power supply, C = control.
For a full description of the 2-wire serial interface and its functionality, obtain documentation by contacting NDA from [email protected]
Rev. PrA | Page 6 of 12
Preliminary Technical Data
AD9387NK
APPLICATIONS INFORMATION
DESIGN RESOURCES
DOCUMENT CONVENTIONS
Analog Devices, Inc. evaluation kits, reference design schematics,
and other support documentation are available under NDA
from [email protected]
In this data sheet, data is represented using the conventions
described in Table 4.
Table 4. Document Conventions
Other resources include the following:
•
•
•
EIA/CEA-861D, a technical specifications document that
describes audio and video infoframes, as well as the E-EDID
structure for HDMI. It is available from the Consumer
Electronics Association (CEA).
HDMI v. 1.3, a defining document for HDMI 1.3, and
HDMI Compliance Test Specification v. 1.3. They are
available from HDMI Licensing, LLC.
HDCP Specification v1.1, the defining technical specifications
document for the HDCP v. 1.1. It is available from Digital
Content Protection, LLC.
Data
Type
0xNN
0bNN
NN
Bit
Rev. PrA | Page 7 of 12
Format
Hexadecimal (Base 16) numbers are represented using
the C language notation, preceded by 0x.
Binary (Base 2) numbers are represented using the C
language notation, preceded by 0b.
Decimal (Base 10) numbers are represented using no
additional prefixes or suffixes.
Bits are numbered in little endian format; that is, the
least significant bit of a byte or word is referred to as Bit 0.
AD9387NK
PCB LAYOUT RECOMMENDATIONS
The AD9387NK is a high precision, high speed analog device.
For maximum performance, it is important that board layout
be optimized.
Other Input Signals
POWER SUPPLY BYPASSING
The PD/A0 input pin can be connected to GND or supply
(through a resistor or a control signal). The device address and
power-down polarity are set by the state of the PD/A0 pin when
the AD9387NK supplies are applied/enabled. For example, if
the PD/A0 pin is low (when the supplies are turned on), then
the device address is 0x72 and the power-down is active high.
If the PD/A0 pin is high (when the supplies are turned on),
the device address is 0x7A and the power down is active low.
It is recommended that each power supply pin be bypassed
with a 0.1 μF capacitor. The exception is when two or more
supply pins are adjacent to each other. For these groupings of
powers and grounds, it is necessary to have only one bypass
capacitor. The fundamental idea is to have a bypass capacitor
within about 0.5 cm of each power pin. Avoid placing the
capacitor on the opposite side of the PC board from the
AD9387NK, as doing so interposes resistive vias in the path.
The bypass capacitors should be located between the power plane
and the power pin. Current should flow from the power plane
to the capacitor to the power pin. Do not make a power connection
between the capacitor and the power pin. Placing a via underneath
the capacitor pads, down to the power plane, is generally the
best approach.
It is particularly important to maintain low noise and good
stability of PVDD (the PLL supply). Abrupt changes in PVDD
can result in similarly abrupt changes in sampling clock phase
and frequency. Such changes can be avoided by careful attention
to regulation, filtering, and bypassing. It is best practice to provide
separate regulated supplies for each of the analog circuitry
groups (AVDD and PVDD).
It is also recommended that a single ground plane be used
for the entire board. Experience has repeatedly shown that
the noise performance is the same or better with a single
ground plane. Using multiple ground planes can be detrimental because each separate ground plane is smaller, and
long ground loops can result.
DIGITAL INPUTS
Video and Audio Data Input Signals
The digital inputs on the AD9387NK are designed to work with
signals ranging from 1.8 V to 3.3 V logic level. Therefore, no extra
components need to be added when using 3.3 V logic. Any
noise that gets onto the clock input (labeled CLK) trace adds
jitter to the system. Therefore, minimize the video clock input
(Pin 6, CLK) trace length, and do not run any digital or other
high frequency traces near it. Make sure to match the length of
the input data signals to optimize data capture, especially for
high frequency modes, such as 720p or XGA at 75 Hz and
double data rate input formats.
The HPD must be connected to the HDMI connector. A 10 kΩ
pull-down resistor to ground is also recommended.
The SCL and SDA pins should be connected to the I2C master.
A pull-up resistor of 2 kΩ to 1.8 V or 3.3 V is recommended.
EXTERNAL SWING RESISTOR
The external swing resistor must be connected directly to the
EXT_SWG pin and ground. The external swing resistor must
have a value of 887 Ω (±1% tolerance). Avoid running any high
speed ac or noisy signals next to, or close to, the EXT_SWG pin.
OUTPUT SIGNALS
TMDS Output Signals
The AD9387NK has three TMDS data channels (0, 1, and 2)
that output signals up to 800 MHz, as well as the TMDS output
data clock. To minimize the channel-to-channel skew, make the
trace length of these signals the same. Also, these traces need
a 50 Ω characteristic impedance and should be routed as 100 Ω
differential pairs. Best practice recommends routing these lines on
the top PCB layer, avoiding the use of vias.
Other Output Signals (non TMDS)
DDCSCL and DDCSDA
The DDCSCL and DDCSDA outputs need a minimum amount
of capacitance loading to ensure the best signal integrity. The
DDCSCL and DDCSDA capacitance loading must be less than
50 pF to meet the HDMI compliance specification. The DDCSCL
and DDCSDA must be connected to the HDMI connector, and
a pull-up resistor to 5 V is required. The pull-up resistor must
have a value between 1.5 kΩ and 2 kΩ.
INT Pin
The INT pin is an output that should be connected to the system
microcontroller. A pull-up resistor to 1.8 V or 3.3 V is required
for proper operation; the recommended value is 2 kΩ.
MCL and MDA
The MCL and MDA outputs should be connected to the EEPROM
containing the HDCP key (if HDCP is implemented). Pull-up
resistors of 2 kΩ are recommended.
Rev. PrA | Page 8 of 12
Preliminary Technical Data
AD9387NK
OUTLINE DIMENSIONS
9.00
BSC SQ
0.30
0.25
0.18
0.60 MAX
0.60 MAX
49
48
PIN 1
INDICATOR
64
1
PIN 1
INDICATOR
+
8.75
BSC SQ
TOP
VIEW
(BOTTO M VIEW)
0.45
0.40
0.35
1.00
0.85
0.80
12° MAX
4.85
4.70 SQ*
4.55
EXPOSED PAD**
33
32
17
16
7.50
REF
0.80 MAX
0.65 TYP
0.05 MAX
0.02 NOM
0.50 BSC
SEATING
PLANE
0.20 REF
64 LFCSP (LEAD FRAME CHIP SCALE PACKAGE)
* COMPLIANT TO JEDEC STANDARDS MO-220-VMMD
EXCEPT FOR EXPOSED PAD DIMENSION
**Note: PAD is CONNECTED to GND
DIMENSIONS in Millimeters
Figure 4. 64-Lead Lead Frame Chip Scale Package [LFCSP]
(CP-64)
Dimensions shown in millimeters
A1 CORNER
INDEX AREA
6.10
6.00 SQ
5.90
10 9
8
7 6
5
4
3 2 1
A
B
BALL A1
PAD CORNER
TOP VIEW
C
4.50
BSC SQ
D
E
0.50
BSC
F
G
H
J
K
DETAIL A
BOTTOM VIEW
0.75
REF
*1.40 MAX
DETAILA
0.65 MIN
0.15 MIN
COPLANARITY
0.08 MAX
*COMPLIANT TO JEDEC STANDARDS MO-225
WITH THE EXCEPTION TO PACKAGE HEIGHT.
012006-0
0.35 SEATING
0.30 PLANE
0.25
BALL DIAMETER
Figure 5. 76-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
6 mm × 6 mm × 1.4 mm
(BC-76)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD9387NKBCPZ-80 1
AD9387NKBBCZ-801
AD9387NKBBCZRL-801
AD9387NK/PCB
1
Temperature Range
−25°C to +85°C
−25°C to +85°C
−25°C to +85°C
Package Description
64-Lead Formed Chip Scale Package
76-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
76-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
Evaluation Board
Z = Pb-free part.
Rev. PrA | Page 9 of 12
Package Option
CP-64
BC-76
BC-76
AD9387NK
NOTES
Rev. PrA | Page 10 of 12
Preliminary Technical Data
AD9387NK
NOTES
Rev. PrA | Page 11 of 12
AD9387NK
NOTES
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent
Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
PR06507-0-12/06(PrA)
Rev. PrA | Page 12 of 12