a FEATURES Throughput: 570 kSPS (Warp Mode) 500 kSPS (Normal Mode) INL: ⴞ2.5 LSB Max (ⴞ0.0038% of Full-Scale) 16 Bits Resolution with No Missing Codes S/(N+D): 90 dB Typ @ 10 kHz THD: –100 dB Typ @ 10 kHz Analog Input Voltage Range: 0 V to 2.5 V Both AC and DC Specifications No Pipeline Delay Parallel and Serial 5 V/3 V Interface Single 5 V Supply Operation Power Dissipation 97 mW Typical, 21 W @ 100 SPS Power-Down Mode: 7 W Max Package: 48-Lead Quad Flat Pack (LQFP) Pin-to-Pin Compatible Upgrade of the AD7660 16-Bit, 570 kSPS CMOS ADC AD7664* FUNCTIONAL BLOCK DIAGRAM AVDD AGND REF REFGND DVDD DGND OVDD AD7664 OGND SERIAL PORT IN SWITCHED CAP DAC INGND 16 DATA[15:0] BUSY PARALLEL INTERFACE CLOCK PD RESET CONTROL LOGIC AND CALIBRATION CIRCUITRY RD CS SER/PAR OB/2C WARP IMPULSE CNVST APPLICATIONS Data Acquisition Instrumentation Digital Signal Processing Spectrum Analysis Medical Instruments Battery-Powered Systems Process Control GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The AD7664 is a 16-bit, 570 kSPS, charge redistribution SAR, analog-to-digital converter that operates from a single 5 V power supply. The part contains a high-speed 16-bit sampling ADC, an internal conversion clock, error correction circuits, and both serial and parallel system interface ports. 1. Fast Throughput The AD7664 is a 570 kSPS, charge redistribution, 16-bit SAR ADC with internal error correction circuitry. The AD7664 is hardware factory calibrated and is comprehensively tested to ensure such ac parameters as signal-to-noise ratio (SNR) and total harmonic distortion (THD), in addition to the more traditional dc parameters of gain, offset, and linearity. It features a very high sampling rate mode (Warp) and, for asynchronous conversion rate applications, a fast mode (Normal) and, for low power applications, a reduced power mode (Impulse) where the power is scaled with the throughput. It is fabricated using Analog Devices’ high-performance, 0.6 micron CMOS process, with correspondingly low cost and is available in a 48-lead LQFP with operation specified from –40°C to +85°C. 2. Superior INL The AD7664 has a maximum integral nonlinearity of 2.5 LSBs with no missing 16-bit code. 3. Single-Supply Operation The AD7664 operates from a single 5 V supply and typically dissipates only 97 mW. In impulse mode, its power dissipation decreases with the throughput to, for instance, only 21 µW at a 100 SPS throughput. It consumes 7 µW maximum when in power-down. 4. Serial or Parallel Interface Versatile parallel or 2-wire serial interface arrangement compatible with both 3 V or 5 V logic. *Patent pending. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2000 AD7664–SPECIFICATIONS (–40ⴗC to +85ⴗC, AVDD = DVDD= 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.) Parameter Conditions Min RESOLUTION ANALOG INPUT Voltage Range Operating Input Voltage Analog Input CMRR Input Current Input Impedance THROUGHPUT SPEED Complete Cycle Throughput Rate Time Between Conversions Complete Cycle Throughput Rate Complete Cycle Throughput Rate DC ACCURACY Integral Linearity Error Differential Linearity Error No Missing Codes Transition Noise Full-Scale Error2 Unipolar Zero Error2 Power Supply Sensitivity AC ACCURACY Signal-to-Noise Spurious Free Dynamic Range Total Harmonic Distortion Signal-to-(Noise+Distortion) VIN – VINGND VIN VINGND fIN = 10 kHz 570 kSPS Throughput In Warp Mode In Warp Mode In Warp Mode In Normal Mode In Normal Mode In Impulse Mode In Impulse Mode 1 0 0 –2.5 –1 16 0.7 ±5 ±3 AVDD = 5 V ± 5% fIN = 10 kHz fIN = 100 kHz fIN = 10 kHz fIN = 100 kHz fIN = 10 kHz fIN = 100 kHz fIN = 10 kHz fIN = 100 kHz –60 dB Input Full-Scale Step REFERENCE External Reference Voltage Range External Reference Current Drain 570 kSPS Throughput VREF +3 +0.5 V V V dB µA 1.75 570 1 2 500 2.25 444 µs kSPS ms µs kSPS µs kSPS +2.5 +1.5 LSB1 LSB Bits LSB % of FSR LSB LSB 62 7 See Analog Input Section REF = 2.5 V ± 0.08 ± 15 90 88 100 90 –100 –90 90 85 30 18 dB3 dB dB dB dB dB dB dB dB MHz 2 5 ns ps rms ns 250 2.3 DIGITAL INPUTS Logic Levels VIL VIH IIL IIH 2.5 115 –0.3 +2.0 –1 –1 DIGITAL OUTPUTS Data Format Pipeline Delay ISINK = 1.6 mA ISOURCE = –500 µA Unit Bits 0 –0.1 –0.1 –3 dB Input Bandwidth POWER SUPPLIES Specified Performance AVDD DVDD OVDD Operating Current4 AVDD DVDD5 OVDD5 Max 16 SAMPLING DYNAMICS Aperture Delay Aperture Jitter Transient Response VOL VOH Typ 2.7 V µA +0.8 OVDD + 0.3 +1 +1 V V µA µA Parallel or Serial 16-Bits Conversion Results Available Immediately After Completed Conversion 0.4 OVDD – 0.6 V V 4.75 4.75 2.7 V V V 5 5 5.25 5.25 5.25 570 kSPS Throughput 15.5 3.8 100 –2– mA mA µA REV. 0 AD7664 Parameter Conditions POWER SUPPLIES (Continued) Power Dissipation7 Min 570 kSPS Throughput4 100 SPS Througput6 In Power-Down Mode7 Typ Max Unit 97 21 115 7 mW µW µW +85 °C 8 TEMPERATURE RANGE Specified Performance TMIN to TMAX –40 NOTES 1 LSB means Least Significant Bit. With the 0 V to 2.5 V input range, one LSB is 38.15 µV. 2 See Definition of Specifications section. These specifications do not include the error contribution from the external reference. 3 All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full-scale unless otherwise specified. 4 In normal mode. 5 Tested in parallel reading mode. 6 In impulse mode. 7 With all digital inputs forced to OVDD or OGND respect ively. 8 Contact factory for extended temperature range. Specifications subject to change without notice. TIMING SPECIFICATIONS (–40ⴗC to +85ⴗC, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.) Refer to Figures 11 and 12 Convert Pulsewidth Time Between Conversions (Wrap Mode/Normal Mode/Impulse Mode) CNVST LOW to BUSY HIGH Delay BUSY HIGH All Modes Except in Master Serial Read After Convert Mode (Warp Mode/Normal Mode/Impulse Mode) Aperture Delay End of Conversion to BUSY LOW Delay Conversion Time (Warp Mode/Normal Mode/Impulse Mode) Acquisition Time RESET Pulsewidth Symbol Min t1 t2 5 1.75/2/2.25 Typ t3 t4 Refer to Figures 13, 14, and 15 (Parallel Interface Modes) CNVST LOW to DATA Valid Delay (Warp Mode/Normal Mode/Impulse Mode) DATA Valid to BUSY LOW Delay Bus Access Request to DATA Valid Bus Relinquish Time Max Unit Note 1 ns µs 25 1.5/1.75/2 ns µs 1.5/1.75/2 ns ns µs 2 t5 t6 t7 10 t8 t9 250 10 ns ns t10 1.5/1.75/2 µs 40 50 ns ns ns 45 t11 t12 t13 5 2 Refer to Figures 16 and 17 (Master Serial Interface Modes) CS LOW to SYNC Valid Delay CS LOW to Internal SCLK Valid Delay2 CS LOW to SDOUT Delay CNVST LOW to SYNC Delay (Warp Mode/Normal Mode/Impulse Mode) SYNC Asserted to SCLK First Edge Delay Internal SCLK Period Internal SCLK HIGH (INVSCLK Low)3 Internal SCLK LOW (INVSCLK Low)3 SDOUT Valid Setup Time SDOUT Valid Hold Time SCLK Last Edge to SYNC Delay CS HIGH to SYNC HI-Z CS HIGH to Internal SCLK HI-Z CS HIGH to SDOUT HI-Z BUSY HIGH in Master Serial Read After Convert (Warp Mode/Normal Mode/Impulse Mode) CNVST LOW to SYNC Asserted Delay (Warp Mode/Normal Mode/Impulse Mode) SYNC Deasserted to BUSY LOW Delay REV. 0 t14 t15 t16 t17 10 10 10 25/275/525 t18 t19 t20 t21 t22 t23 t24 t25 t26 t27 t28 4 40 30 9.5 4.5 3 3 75 10 10 10 2.75/3/3.25 ns ns ns ns ns ns ns ns ns ns ns ns ns µs t29 1/1.25/1.5 µs t30 50 ns –3– AD7664 TIMING SPECIFICATIONS (Continued) Symbol Min t31 t32 t33 t34 t35 t36 t37 5 3 5 5 25 10 10 Typ Max Unit 2 Refer to Figures 18 and 20 (Slave Serial Interface Modes) External SCLK Setup Time External SCLK Active Edge to SDOUT Delay SDIN Setup Time SDIN Hold Time External SCLK Period External SCLK HIGH External SCLK LOW ns ns ns ns ns ns ns 16 NOTES 1 In warp mode only, the maximum time between conversions is 1 ms, otherwise, there is no required maximum time. 2 In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load C L of 10 pF; otherwise, the load is 60 pF maximum. 3 If the polarity of SCLK is inverted, the timing references of SCLK are also inverted. Specifications subject to change without notice. Internal Power Dissipation3 . . . . . . . . . . . . . . . . . . . 700 mW Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Lead Temperature Range (Soldering 10 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C ABSOLUTE MAXIMUM RATINGS 1 Analog Inputs IN2, REF . . . . . . . . . . . . AVDD + 0.3 V to AGND – 0.3 V INGND, REFGND . . . . . . . . . . . . . . . . . . AGND ± 0.3 V Ground Voltage Differences AGND, DGND, OGND . . . . . . . . . . . . . . . . . . . . . ± 0.3 V Supply Voltages AVDD, DVDD, OVDD . . . . . . . . . . . . . . . . . . . . . . . . 7 V AVDD to DVDD, AVDD to OVDD . . . . . . . . . . . . . . ± 7 V DVDD to OVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 7 V Digital Inputs Except the Data Bus D(7:4) . . . –0.3 V to DVDD + 0.3 V Data Bus Inputs D(7:4) . . . . . . –0.3 V to OVDD + 0.3 V NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 See Analog Input section. 3 Specification is for device in free air: 48-Lead LQFP: θJA = 91°C/W, θJC = 30°C/W. ORDERING GUIDE Model Temperature Range Package Description Package Option AD7664AST AD7664ASTRL EVAL-AD7664CB1 EVAL-CONTROL BOARD2 –40°C to +85°C –40°C to +85°C Quad Flatpack (LQFP) Quad Flatpack (LQFP) Evaluation Board Controller Board ST-48 ST-48 NOTES 1 This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BOARD for evaluation/demonstration purposes. 2 This board allows a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7664 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. –4– WARNING! ESD SENSITIVE DEVICE REV. 0 AD7664 TO OUTPUT PIN PIN CONFIGURATION 48-Lead LQFP (ST-48) IOL NC NC NC NC NC NC NC NC NC 60pF1 INGND ⴙ1.4V CL REFGND REF 1.6mA 48 47 46 45 44 43 42 41 40 39 38 37 IOH AGND 1 AVDD 2 Figure 1. Load Circuit for Digital Interface Timing, SDOUT, SYNC, SCLK Outputs, CL = 10 pF NC 3 DGND 4 OB/2C 5 WARP 6 RESET CS RD DGND 29 BUSY 30 D0 9 D1 10 28 2V 0.8V D2 11 D3 12 26 25 D15 D14 D13 D12 D11/RDERROR D9/SCLK D10/SYNC D8/SDOUT 13 14 15 16 17 18 19 20 21 22 23 24 DVDD DGND NC = NO CONNECT Figure 2. Voltage Reference Levels for Timing 27 OVDD 0.8V PD 33 t DELAY D4/EXT/INT D5/INVSYNC D6/INVSCLK 2V 34 31 TOP VIEW (Not to Scale) SER/PAR 8 0.8V t DELAY AGND CNVST 32 AD7664 IMPULSE 7 2V 35 36 PIN 1 IDENTIFIER D7/RDC/SDIN OGND 500A PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Type Description 1 2 3, 40–48 4, 30 5 AGND AVDD NC DGND OB/2C P P 6 WARP DI 7 IMPULSE DI 8 SER/PAR DI 9–12 DATA[0:3] DO 13 DATA[4] or EXT/INT DI/O 14 DATA[5] or INVSYNC DI/O 15 DATA[6] or INVSCLK DI/O Analog Power Ground Pin. Input Analog Power Pins. Nominally 5 V. No Connect. Must Be Tied to Analog Ground. Straight Binary/Binary Two’s Complement. When OB/2C is HIGH, the digital output is straight binary; when LOW, the MSB is inverted resulting in a two’s complement output from its internal shift register. Mode Selection. When HIGH and IMPULSE LOW, this input selects the fastest mode, the maximum throughput is achievable, and a minimum conversion rate must be applied in order to guarantee full specified accuracy. When LOW, full accuracy is maintained independent of the minimum conversion rate. Mode Selection. When HIGH and WARP LOW, this input selects a reduced power mode. In this mode, the power dissipation is approximately proportional to the sampling rate. Serial/Parallel Selection Input. When LOW, the parallel port is selected; when HIGH, the serial interface mode is selected and some bits of the DATA bus are used as a serial port. Bit 0 to Bit 3 of the Parallel Port Data Output Bus. These pins are always outputs, regardless of the state of SER/PAR. When SER/PAR is LOW, this output is used as Bit 4 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, this input, part of the serial port, is used as a digital select input for choosing the internal or an external data clock. With EXT/INT tied LOW, the internal clock is selected on SCLK output. With EXT/INT set to a logic HIGH, output data is synchronized to an external clock signal connected to the SCLK input. When SER/PAR is LOW, this output is used as Bit 5 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, this input, part of the serial port, is used to select the active state of the SYNC signal. It is active in both master and slave mode. When LOW, SYNC is active HIGH. When HIGH, SYNC is active LOW. When SER/PAR is LOW, this output is used as Bit 6 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, this input, part of the serial port, is used to invert the SCLK signal. It is active in both master and slave mode. REV. 0 DI DI –5– AD7664 Pin No. 16 Mnemonic Type Description DATA[7] or RDC/SDIN DI/O When SER/PAR is LOW, this output is used as Bit 7 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, this input, part of the serial port, is used as either an external data input or a read mode selection input depending on the state of EXT/INT. 17 18 OGND OVDD P P 19 20 21 DVDD DGND DATA[8] or SDOUT P P DO 22 DATA[9] or SCLK DI/O 23 DATA[10] or SYNC DO 24 DATA[11] or RDERROR DO 25–28 DATA[12:15] DO 29 BUSY DO 30 31 DGND RD P DI 32 CS DI 33 34 RESET PD DI DI When EXT/INT is HIGH, RDC/SDIN could be used as a data input to daisy chain the conversion results from two or more ADCs onto a single SDOUT line. The digital data level on SDIN is output on DATA with a delay of 16 SCLK periods after the initiation of the read sequence. When EXT/INT is LOW, RDC/SDIN is used to select the read mode. When RDC/SDIN is HIGH, the data is output on SDOUT during conversion. When RDC/SDIN is LOW, the data can be output on SDOUT only when the conversion is complete. Input/Output interface Digital Power Ground. Input/Output interface Digital Power. Nominally at the same supply than the supply of the host interface (5 V or 3 V). Digital Power. Nominally at 5 V. Digital Power Ground. When SER/PAR is LOW, this output is used as Bit 8 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, this output, part of the serial port, is used as a serial data output synchronized to SCLK. Conversion results are stored in an on-chip register. The AD7664 provides the conversion result, MSB first, from its internal shift register. The DATA format is determined by the logic level of OB/2C. In serial mode, when EXT/INT is LOW, SDOUT is valid on both edges of SCLK. In serial mode, when EXT/INT is HIGH: If INVSCLK is LOW, SDOUT is updated on SCLK rising edge and valid on the next falling edge. If INVSCLK is HIGH, SDOUT is updated on SCLK falling edge and valid on the next rising edge. When SER/PAR is LOW, this output is used as the Bit 9 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, this pin, part of the serial port, is used as a serial data clock input or output, dependent upon the logic state of the EXT/INT pin. The active edge where the data SDOUT is updated depends upon the logic state of the INVSCLK pin. When SER/PAR is LOW, this output is used as the Bit 10 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, this output, part of the serial port, is used as a digital output frame synchronization for use with the internal data clock (EXT/INT = Logic LOW). When a read sequence is initiated and INVSYNC is LOW, SYNC is driven HIGH and remains HIGH while SDOUT output is valid. When a read sequence is initiated and INVSYNC is High, SYNC is driven LOW and remains LOW while SDOUT output is valid. When SER/PAR is LOW, this output is used as the Bit 11 of the Parallel Port Data Output Bus. When SER/PAR is HIGH and EXT/INT is HIGH, this output, part of the serial port, is used as a incomplete read error flag. In slave mode, when a data read is started and not complete when the following conversion is complete, the current data is lost and RDERROR is pulsed high. Bit 12 to Bit 15 of the Parallel Port Data output bus. These pins are always outputs regardless of the state of SER/PAR. Busy Output. Transitions HIGH when a conversion is started, and remains HIGH until the conversion is complete and the data is latched into the on-chip shift register. The falling edge of BUSY could be used as a data ready clock signal. Must Be Tied to Digital Ground. Read Data. When CS and RD are both LOW, the interface parallel or serial output bus is enabled. RD and CS are OR’d together internally. Chip Select. When CS and RD are both LOW, the interface parallel or serial output bus is enabled. RD and CS are OR’d together internally. Reset Input. When set to a logic HIGH, reset the AD7664. Current conversion if any is aborted. Power-Down Input. When set to a logic HIGH, power consumption is reduced and conversions are inhibited after the current one is completed. –6– REV. 0 AD7664 Pin No. Mnemonic Type Description 35 CNVST DI 36 37 38 39 43 AGND REF REFGND INGND IN P AI AI AI AI Start Conversion. A falling edge on CNVST puts the internal sample/hold into the hold state and initiates a conversion. In impulse mode (IMPULSE HIGH and WARP LOW), if CNVST is held low when the acquisition phase (t8) is complete, the internal sample/hold is put into the hold state and a conversion is immediately started. Must Be Tied to Analog Ground. Reference Input Voltage. Reference Input Analog Ground. Analog Input Ground. Primary Analog Input with a Range of 0 V to VREF. NOTES AI = Analog Input DI = Digital Input DI/O = Bidirectional Digital DO = Digital Output P = Power DEFINITION OF SPECIFICATIONS TOTAL HARMONIC DISTORTION (THD) INTEGRAL NONLINEARITY ERROR (INL) THD is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in decibels. Linearity error refers to the deviation of each individual code from a line drawn from “negative full scale” through “positive full scale.” The point used as “negative full scale” occurs 1/2 LSB before the first code transition. “Positive full scale” is defined as a level 1 1/2 LSB beyond the last code transition. The deviation is measured from the middle of each code to the true straight line. DIFFERENTIAL NONLINEARITY ERROR (DNL) In an ideal ADC, code transitions are 1 LSB apart. Differential nonlinearity is the maximum deviation from this ideal value. It is often specified in terms of resolution for which no missing codes are guaranteed. FULL-SCALE ERROR The last transition (from 011 . . . 10 to 011 . . . 11 in two’s complement coding) should occur for an analog voltage 1 1/2 LSB below the nominal full scale (2.49994278 V for the 0 V–2.5 V range). The full-scale error is the deviation of the actual level of the last transition from the ideal level. UNIPOLAR ZERO ERROR SIGNAL-TO-NOISE RATIO (SNR) SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in decibels. SIGNAL TO (NOISE + DISTORTION) RATIO (S/[N+D]) S/(N+D) is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for S/(N+D) is expressed in decibels. APERTURE DELAY Aperture delay is a measure of the acquisition performance and is measured from the falling edge of the CNVST input to when the input signal is held for a conversion. The first transition should occur at a level 1/2 LSB above analog ground (19.073 µV for the 0 V–2.5 V range). Unipolar zero error is the deviation of the actual transition from that point. TRANSIENT RESPONSE SPURIOUS FREE DYNAMIC RANGE (SFDR) OVERVOLTAGE RECOVERY The difference, in decibels (dB), between the rms amplitude of the input signal and the peak spurious signal. The time required for the AD7664 to achieve its rated accuracy after a full-scale step function is applied to its input. The time required for the ADC to recover to full accuracy after an analog input signal 150% of full-scale is reduced to 50% of the full-scale value. EFFECTIVE NUMBER OF BITS (ENOB) ENOB is a measurement of the resolution with a sine wave input. It is related to S/(N+D) by the following formula: ENOB = (S/[N+D]dB – 1.76)/6.02) and is expressed in bits. REV. 0 –7– 2.5 1.50 2.0 1.25 1.5 1.00 1.0 0.75 0.5 0.50 DNL – LSB INL – LSB AD7664–Typical Performance Characteristics 0 –0.5 0.25 0 –1.0 –0.25 –1.5 –0.50 –2.0 –0.75 –2.5 0 16384 32768 CODE –1.00 65536 49152 TPC 1. Integral Nonlinearity vs. Code 0 16384 32768 CODE 49152 65536 TPC 4. Differential Nonlinearity vs. Code 8000 10000 7288 7148 9008 9000 7000 8000 6000 7000 COUNTS COUNTS 5000 4000 6000 5000 4000 3000 3340 3643 3000 2000 753 1000 2000 1173 1000 0 12 10 0 0 0 0 0 7F86 7F87 7F88 7F89 7F8A 7F8B 7F8C 7F8D 7F8E 7F8F CODE – Hexa TPC 2. Histogram of 16,384 Conversions of a DC Input at the Code Transition 257 136 0 0 TPC 5. Histogram of 16,384 Conversions of a DC Input at the Code Center 0 –96 96 4096 POINT FFT f S = 570kHz f IN = 10.39kHz, –0.5dB SNR = 90.1dB SINAD = 89.6dB THD = –98.7dB SFDR = 100.3dB –40 –60 –98 93 SNR AND S/(N+D) – dB –20 AMPLITUDE – dB of Full Scale 0 7FB3 7FB4 7FB5 7FB6 7FB7 7FB8 7FB9 7FBA 7FBB CODE – Hexa –80 –100 –120 THD –100 90 SNR –102 87 –140 THD – dB 0 –160 84 –55 –180 0 50 100 150 200 FREQUENCY – kHz 250 300 TPC 3. FFT Plot –35 –15 5 25 45 65 TEMPERATURE – ⴗC 85 105 –104 125 TPC 6. SNR, THD vs. Temperature –8– REV. 0 AD7664 100 15.0 110 –60 105 –65 14.5 95 SFDR –70 100 S/(N+D) 13.0 85 12.5 80 –75 95 –80 90 –85 85 –90 80 –95 2ND HARMONICS 11.5 1 10 100 FREQUENCY – kHz 65 –105 11.0 1000 3RD HARMONICS 10 100 FREQUENCY – kHz –110 1 TPC 7. SNR, S/(N+D), and ENOB vs. Frequency 60 1k TPC 10. THD, Harmonics, and SFDR vs. Frequency 92 50 OVDD = 2.7V, 85ⴗC 40 SNR 90 t12 DELAY – ns SNR (REFERRED TO FULL SCALE) – d 70 –100 75 70 75 THD 12.0 SFDR – dB 13.5 THD, HARMINICS – dB 90 ENOB – Bits SNR AND S/(N+D) – dB 14.0 ENOB SNR S/(N+D) 88 30 OVDD = 2.7V, 25ⴗC 20 OVDD = 5V, 85ⴗC 10 OVDD = 5V, 25ⴗC 86 –60 –50 –40 –20 –30 INPUT LEVEL – dB 0 0 –10 TPC 8. SNR and S/(N+D) vs. Input Level POWER-DOWN OPERATING CURRENTS – nA OPERATING CURRENTS – A 10k DVDD, WARP/NORMAL AVDD, IMPULSE 100 DVDD, IMPULSE 10 1 OVDD, ALL MODES 0.1 0.01 1 10 100 1k 10k SAMPLING RATE – SPS 100k 200 150 90 AVDD 80 70 60 50 OVDD 40 30 20 DVDD 10 0 –50 1000k TPC 9. Operating Currents vs. Sample Rate REV. 0 100 CL – pF 100 AVDD, WARP/NORMAL 0.001 0.1 50 TPC 11. Typical Delay vs. Load Capacitance CL 100k 1k 0 –25 0 25 50 TEMPERATURE – ⴗC 75 100 TPC 12. Power-Down Operating Currents vs. Temperature –9– AD7664 CIRCUIT INFORMATION Modes of Operation The AD7664 is a very fast, low power, single supply, precise 16-bit analog-to-digital converter (ADC). The AD7664 features different modes to optimize performances according to the applications. The AD7664 features three modes of operations, Warp, Normal, and Impulse. Each of these modes is more suitable for specific applications. The Warp mode allows the fastest conversion rate up to 570 kSPS. However, in this mode, and this mode only, the full specified accuracy is guaranteed only when the time between conversion does not exceed 1 ms. If the time between two consecutive conversions is longer than 1 ms, for instance, after power-up, the first conversion result should be ignored. This mode makes the AD7664 ideal for applications where both high accuracy and fast sample rate are required. In warp mode, the AD7664 is capable of converting 570,000 samples per second (570 kSPS). The AD7664 provides the user with an on-chip track/hold, successive approximation ADC that does not exhibit any pipeline or latency, making it ideal for multiple multiplexed channel applications. The AD7664 can be operated from a single 5 V supply and be interfaced to either 5 V or 3 V digital logic. It is housed in a 48-lead LQFP package that saves space and allows flexible configurations as either serial or parallel interface. The AD7664 is a pin-to-pin compatible upgrade of the AD7660. The normal mode is the fastest mode (500 kSPS ) without any limitation about the time between conversions. This mode makes the AD7664 ideal for asynchronous applications such as data acquisition systems, where both high accuracy and fast sample rate are required. The impulse mode, the lowest power dissipation mode, allows power saving between conversions. When operating at 100 SPS, for example, it typically consumes only 21 µW. This feature makes the AD7664 ideal for battery-powered applications. CONVERTER OPERATION The AD7664 is a successive-approximation analog-to-digital converter based on a charge redistribution DAC. Figure 3 shows the simplified schematic of the ADC. The capacitive DAC consists of an array of 16 binary weighted capacitors and an additional “LSB” capacitor. The comparator’s negative input is connected to a “dummy” capacitor of the same value as the capacitive DAC array. Transfer Functions Using the OB/2C digital input, the AD7664 offers two output codings: straight binary and two’s complement. The LSB size is VREF/65536, which is about 38.15 µV. The ideal transfer characteristic for the AD7664 is shown in Figure 4 and Table I. During the acquisition phase, the common terminal of the array tied to the comparator's positive input is connected to AGND via SWA. All independent switches are connected to the analog input IN. Thus, the capacitor array is used as a sampling capacitor and acquires the analog signal on IN input. Similarly, the “dummy” capacitor acquires the analog signal on INGND input. ADC CODE – Straight Binary 1 LSB = VREF/65536 When the CNVST input goes low, a conversion phase is initiated. When the conversion phase begins, SWA and SWB are opened first. The capacitor array and the “dummy” capacitor are then disconnected from the inputs and connected to the REFGND input. Therefore, the differential voltage between IN and INGND captured at the end of the acquisition phase is applied to the comparator inputs, causing the comparator to become unbalanced. By switching each element of the capacitor array between REFGND or REF, the comparator input varies by binary-weighted voltage steps (VREF/2, VREF/4, . . . VREF/65536). The control logic toggles these switches, starting with the MSB first, to bring the comparator back into a balanced condition. After the completion of this process, the control logic generates the ADC output code and brings BUSY output low. 111...111 111...110 111...101 000...010 000...001 000...000 0V 1 LSB 0.5 LSB ANALOG INPUT Figure 4. ADC Ideal Transfer Function IN REF REFGND LSB MSB 32,768C 16,384C 4C 2C VREF –1 LSB VREF –1.5 LSB C SWA SWITCHES CONTROL C BUSY COMP CONTROL LOGIC INGND OUTPUT CODE 65,536C SWB CNVST Figure 3. ADC Simplified Schematic –10– REV. 0 AD7664 Table I. Output Codes and Ideal Input Voltages TYPICAL CONNECTION DIAGRAM Description Analog Input Digital Output Code Hexa Straight Two’s Binary Complement FSR –1 LSB FSR – 2 LSB Midscale + 1 LSB Midscale Midscale – 1 LSB –FSR + 1 LSB –FSR 2.499962 V 2.499923 V 1.250038 V 1.25 V 1.249962 V 38 µV 0V FFFF1 FFFE 8001 8000 7FFF 0001 00002 Figure 5 shows a typical connection diagram for the AD7664. Analog Input Figure 6 shows an equivalent circuit of the input structure of the AD7664. 7FFF1 7FFE 0001 0000 FFFF 8001 80002 AVDD D1 IN OR INGND R1 D2 Figure 6. Equivalent Analog Input Circuit The two diodes D1 and D2 provide ESD protection for the analog inputs IN and INGND. Care must be taken to ensure that the analog input signal never exceeds the supply rails by more than 0.3 V. This will cause these diodes to become forwardbiased and start conducting current. These diodes can handle a forward-biased current of 100 mA maximum. For instance, these conditions could eventually occur when the input buffer’s (U1) supplies are different from AVDD. In such case, an input buffer with a short circuit current limitation can be used to protect the part. 100⍀ 10F 100nF DIGITAL SUPPLY (3.3V OR 5V) 10F AVDD C2 AGND NOTES 1 This is also the code for overrange analog input (V IN – VINGND above VREF – VREFGND). 2 This is also the code for underrange analog input (V IN below VINGND) ANALOG SUPPLY (5V) C1 AGND 100nF DGND DVDD 100nF OVDD OGND 10F SERIAL PORT SCLK 2.5V REF1 REF CREF1 SDOUT 100nF REFGND BUSY C/P/DSP AD7664 CNVST ANALOG INPUT (0V TO 2.5V) D3 15⍀ U12 IN CC OB/2C SER/PAR 2.7nF DVDD WARP INGND PD IMPULSE CS RESET RD CLOCK NOTES: 1 THE AD780 IS RECOMMENDED WITH CREF = 47F. 2 THE AD829 IS RECOMMENDED WITH A COMPENSATION CAPACITOR CC = 82 pF, TYPE CERAMIC NPO. 3 OPTIONAL LOW JITTER CNVST. Figure 5. Typical Connection Diagram REV. 0 –11– AD7664 Driver Amplifier Choice This analog input structure allows the sampling of the differential signal between IN and INGND. Unlike other converters, the INGND input is sampled at the same time as the IN input. By using this differential input, small signals common to both inputs are rejected, as shown in Figure 7, which represents the typical CMR over frequency. For instance, by using INGND to sense a remote signal ground, difference of ground potentials between the sensor and the local ADC ground are eliminated. Although the AD7664 is easy to drive, the driver amplifier needs to meet at least the following requirements: • The driver amplifier and the AD7664 analog input circuit have to be able together to settle for a full-scale step the capacitor array at a 16-bit level (0.0015%). For instance, operation at the maximum throughput of 570 kSPS requires a minimum gain bandwidth product of 39 MHz. • The noise generated by the driver amplifier needs to be kept as low as possible in order to preserve the SNR and transition noise performance of the AD7664. The noise coming from the driver is filtered by the AD7664 analog input circuit one-pole low-pass filter made by R1 and C2. For instance, a driver such as the AD829, with an equivalent input noise of 2 nV/√Hz and configured as a buffer, thus, with a noise gain of 1, degrades the SNR by only 0.45 dB. A driver amplifier with an equivalent input noise of 5 nV/√Hz in the same configuration will add 1.9 dB degradation. 70 60 CMRR – dB 50 40 30 20 • To even further reduce the noise filtering done by the AD7664 analog input circuit, an external simple one-pole RC filter between the amplifier output and the ADC analog input will slightly improve the ac performances, specially, the SNR and the transition noise. For example, as shown in Figure 5, a 15 Ω source resistor with a 2.7 nF good linearity capacitor (NPO or mica type) limit the bandwidth to 4 MHz. 10 0 1 100 10 FREQUENCY – kHz 1k Figure 7. Analog Input CMR vs. Frequency During the acquisition phase, the impedance of the analog input IN can be modeled as a parallel combination of capacitor C1 and the network formed by the series connection of R1 and C2. Capacitor C1 is primarily the pin capacitance. The resistor R1 is typically 140 Ω and is a lumped component made up of some serial resistors and the on resistance of the switches. The capacitor C2 is typically 60 pF and is mainly the ADC sampling capacitor. During the conversion phase, where the switches are opened, the input impedance is limited to C1. The R1, C2 makes a one-pole low-pass filter that reduces undesirable aliasing effect and limits the noise. When the source impedance of the driving circuit is low, the AD7664 can be driven directly. Large source impedances will significantly affect the ac performances, especially the total harmonic distortion. The maximum source impedance depends on the amount of total harmonic distortion (THD) that can be tolerated. The THD degrades in function of the source impedance and the maximum input frequency as shown in Figure 8. –70 RS = 100⍀ RS = 50⍀ –75 THD – dB RS = 20⍀ –85 RS = 11⍀ The AD7664 uses an external 2.5 V voltage reference. The voltage reference input REF of the AD7664 has a dynamic input impedance. Therefore, it should be driven by a low impedance source with an efficient decoupling between REF and REFGND inputs. This decoupling depends on the choice of the voltage reference, but usually consists of a low ESR tantalum capacitor and a 100 nF ceramic capacitor. Appropriate value for the tantalum capacitor is 47 µF with the low-cost, low-power ADR291 voltage reference, or with the low-noise, low-drift AD780 voltage reference. For applications using multiple AD7664s, it is more effective to buffer the reference voltage with a low-noise, very stable op amp like the AD8031. Power Supply –90 –95 100 FREQUENCY – kHz Voltage Reference Input Care should also be taken with the reference temperature coefficient of the voltage reference which directly affects the full-scale accuracy if this parameter matters. For instance, a ± 15 ppm/°C tempco of the reference changes the full scale by ± 1 LSB/°C. –80 –100 10 • The driver needs to have a THD performance suitable to that of the AD7664. TPC 10 gives the THD versus frequency that the driver should preferably exceed. The AD829 meets these requirements. The AD829 requires an external compensation capacitor of 82 pF. This capacitor should have good linearity as an NPO ceramic or mica or prolypropylene type. Moreover, the use of a noninverting 1 gain arrangement is recommended and helps to obtain the best signal-to-noise ratio. 1k The AD7664 uses three sets of power supply pins: an analog 5 V supply AVDD, a digital 5 V core supply DVDD, and a digital input/output interface supply OVDD. The OVDD supply allows direct interface with any logic working between 2.7 V and 5.25 V. To reduce the number of supplies needed, the digital core (DVDD) can be supplied through a simple RC filter from the analog supply as shown in Figure 5. The AD7664 is independent Figure 8. THD vs. Analog Input Frequency and Source Resistance –12– REV. 0 AD7664 of power supply sequencing and thus free from supply voltage induced latchup. Additionally, it is very insensitive to power supply variations over a wide frequency range as shown in Figure 9. t2 t1 CNVST –50 BUSY –55 t4 t3 PSRR – dB –60 t6 t5 MODE ACQUIRE CONVERT ACQUIRE t7 t8 CONVERT –65 –70 Figure 11. Basic Conversion Timing –75 –80 1 100 10 1000 INPUT FREQUENCY – kHz Figure 9. PSRR vs. Frequency POWER DISSIPATION VS. THROUGHPUT Operating currents are very low during the acquisition phase, which allows a significant power saving when the conversion rate is reduced as shown in Figure 10. This power saving depends on the mode used. In impulse mode, the AD7664 automatically reduces its power consumption at the end of each conversion phase. This feature makes the AD7664 ideal for very low power battery applications. It should be noted that the digital interface remains active even during the acquisition phase. To reduce the operating digital supply currents even further, the digital inputs need to be driven close to the power supply rails (i.e., DVDD or DGND for all inputs except EXT/INT, INVSYNC, INVSCLK, RDC/SDIN, and OVDD or OGND for these last four inputs). In impulse mode, conversions can be automatically initiated. If CNVST is held low when BUSY is low, the AD7664 controls the acquisition phase and then automatically initiates a new conversion. By keeping CNVST low, the AD7664 keeps the conversion process running by itself. It should be noted that the analog input has to be settled when BUSY goes low. Also, at power-up, CNVST should be brought low once to initiate the conversion process. In this mode, the AD7664 could sometimes run slightly faster then the guaranteed limits in the impulse mode of 444 kSPS. This feature does not exist in warp or normal modes. t9 RESET BUSY DATA t8 100k WARP/NORMAL CNVST OPERATING CURRENTS – A 10k Figure 12. RESET Timing 1k Although CNVST is a digital signal, it should be designed with special care with fast, clean edges, and levels with minimum overshoot and undershoot or ringing. 100 IMPULSE For applications where the SNR is critical, CNVST signal should have a very low jitter. Some solutions to achieve that is to use a dedicated oscillator for CNVST generation or, at least, to clock it with a high-frequency low-jitter clock as shown in Figure 5. 10 1 0.1 0.1 1 10 100 1k 10k SAMPLING RATE – SPS 100k 1M Figure 10. Power Dissipation vs. Sample Rate CONVERSION CONTROL Figure 11 shows the detailed timing diagrams of the conversion process. The AD7664 is controlled by the signal CNVST which initiates conversion. Once initiated, it cannot be restarted or aborted, even by the power-down input PD, until the conversion is complete. The CNVST signal operates independently of CS and RD signals. REV. 0 –13– AD7664 CS = 0 DIGITAL INTERFACE The AD7664 has a versatile digital interface; it can be interfaced with the host system by using either a serial or parallel interface. The serial interface is multiplexed on the parallel data bus. The AD7664 digital interface also accommodates both 3 V or 5 V logic by simply connecting the OVDD supply pin of the AD7664 to the host system interface digital supply. Finally, by using the OB/2C input pin, both two’s complement or straight binary coding can be used. PREVIOUS CONVERSION t 13 SERIAL INTERFACE The AD7664 is configured to use the serial interface when the SER/PAR is held high. The AD7664 outputs 16 bits of data, MSB first, on the SDOUT pin. This data is synchronized with the 16 clock pulses provided on SCLK pin. The output data is valid on both the rising and falling edge of the data clock. t1 t 10 MASTER SERIAL INTERFACE Internal Clock t4 The AD7664 is configured to generate and provide the serial data clock SCLK when the EXT/INT pin is held low. The AD7664 also generates a SYNC signal to indicate to the host when the serial data is valid. The serial clock SCLK and the SYNC signal can be inverted if desired. Depending on RDC/SDIN input, the data can be read after each conversion or during the following conversion. Figure 16 and Figure 17 show the detailed timing diagrams of these two modes. t 11 PREVIOUS CONVERSION DATA t3 Figure 15. Slave Parallel Data Timing for Reading (Read During Convert) CNVST DATA BUS t4 t 12 CS = RD = 0 t3 BUSY DATA BUS The two signals CS and RD control the interface. CS and RD have a similar effect because they are OR’d together internally. When at least one of these signals is high, the interface outputs are in high impedance. Usually, CS allows the selection of each AD7664 in multicircuits applications and is held low in a single AD7664 design. RD is generally used to enable the conversion result on the data bus. BUSY t1 CNVST, RD NEW DATA Figure 13. Master Parallel Data Timing for Reading (Continuous Read) PARALLEL INTERFACE The AD7664 is configured to use the parallel interface when the SER/PAR is held low. The data can be read either after each conversion, which is during the next acquisition phase, or during the following conversion as shown, respectively, in Figure 14 and Figure 15. When the data is read during the conversion, however, it is recommended that it is read only during the first half of the conversion phase. That avoids any potential feedthrough between voltage transients on the digital interface and the most critical analog conversion circuitry. Usually, because the AD7664 is used with a fast throughput, the mode master, read during conversion is the most recommended serial mode when it can be used. In read-during-conversion mode, the serial clock and data toggle at appropriate instants which minimize potential feedthrough between digital activity and the critical conversion decisions. In read-after-conversion mode, it should be noted that, unlike in other modes, the signal BUSY returns low after the 16 data bits are pulsed out and not at the end of the conversion phase which results in a longer BUSY width. CS SLAVE SERIAL INTERFACE External Clock RD BUSY DATA BUS CURRENT CONVERSION t 12 The AD7664 is configured to accept an externally supplied serial data clock on the SCLK pin when the EXT/INT pin is held high. In this mode, several methods can be used to read the data. When CS and RD are both low, the data can be read after each conversion or during the following conversion. The external clock can be either a continuous or discontinuous clock. A discontinuous clock can be either normally high or normally low when inactive. Figure 18 and Figure 20 show the detailed timing diagrams of these methods. t 13 Figure 14. Slave Parallel Data Timing for Reading (Read After Convert) –14– REV. 0 AD7664 EXT/INT = 0 CS, RD RDC/SDIN = 0 INVSCLK = INVSYNC = 0 t3 CNVST t 28 BUSY t 30 t 29 t 25 SYNC t 14 t 18 t 19 t 20 SCLK t 24 t 21 1 2 3 D15 D14 14 15 t 26 16 t 15 t 27 SDOUT X t 16 D2 D1 D0 t 23 t 22 Figure 16. Master Serial Data Timing for Reading (Read After Convert) EXT/INT = 0 RDC/SDIN = 1 INVSCLK = INVSYNC = 0 CS, RD t1 CNVST t3 BUSY t 17 t 25 SYNC t 14 t 19 t 20 t 21 t 15 SCLK 1 t 24 2 3 14 15 t 26 16 t 18 t 27 SDOUT X t 16 t 22 D15 D14 D2 D1 D0 t 23 Figure 17. Master Serial Data Timing for Reading (Read Previous Conversion During Convert) REV. 0 –15– AD7664 EXT/INT = 1 INVSCLK = 0 CS, RD BUSY t 35 t 36 t 37 SCLK 1 2 t 31 3 14 15 16 17 18 t 32 X SDOUT t 16 D15 D14 D13 D1 D0 X15 X14 X14 X13 X1 X0 Y15 Y14 t 34 SDIN X15 t 33 Figure 18. Slave Serial Data Timing for Reading (Read After Convert) While the AD7664 is performing a bit decision, it is important that voltage transients not occur on digital input/output pins or degradation of the conversion result could occur. This is particularly important during the second half of the conversion phase because the AD7664 provides error correction circuitry that can correct for an improper bit decision made during the first half of the conversion phase. For this reason, it is recommended that when an external clock is being provided, it is a discontinuous clock that is toggling only when BUSY is low or, more importantly, that is does not transition during the latter half of BUSY high. BUSY OUT BUSY BUSY AD7664 AD7664 #2 (UPSTREAM) #1 (DOWNSTREAM) RDC/SDIN SDOUT RDC/SDIN SDOUT CNVST CNVST CS CS SCLK SCLK DATA OUT External Discontinuous Clock Data Read After Conversion Though the maximum throughput cannot be achieved using this mode, it is the most recommended of the serial slave modes. Figure 18 shows the detailed timing diagrams of this method. After a conversion is complete, indicated by BUSY returning low, the result of this conversion can be read while both CS and RD are low. The data is shifted out, MSB first, with 16 clock pulses and is valid on both rising and falling edge of the clock. Among the advantages of this method, the conversion performance is not degraded because there are no voltage transients on the digital interface during the conversion process. Another advantage is to be able to read the data at any speed up to 40 MHz which accommodates both slow digital host interface and the fastest serial reading. Finally, in this mode only, the AD7664 provides a “daisy chain” feature using the RDC/SDIN input pin for cascading multiple converters together. This feature is useful for reducing component count and wiring connections when desired as, for instance, in isolated multiconverter applications. An example of the concatenation of two devices is shown in Figure 19. Simultaneous sampling is possible by using a common CNVST signal. It should be noted that the RDC/SDIN input is latched on the opposite edge of SCLK of the one used to shift out the data on SDOUT. Hence, the MSB of the “upstream” converter just follows the LSB of the “downstream” converter on the next SCLK cycle. SCLK IN CS IN CNVST IN Figure 19. Two AD7664s in a “Daisy Chain” Configuration External Clock Data Read During Conversion Figure 20 shows the detailed timing diagrams of this method. During a conversion, while both CS and RD are both low, the result of the previous conversion can be read. The data is shifted out, MSB first, with 16 clock pulses and is valid on both rising and falling edge of the clock. The 16 bits have to be read before the current conversion is complete. If that is not done, RDERROR is pulsed high and can be used to interrupt the host interface to prevent incomplete data reading. There is no “daisy chain” feature in this mode and RDC/SDIN input should always be tied either high or low. To reduce performance degradation due to digital activity, a fast discontinuous clock of, at least 18 MHz, when impulse mode is used, 25 MHz when normal mode is used or 40 MHz when warp mode is used, is recommended to ensure that all the bits are read during the first half of the conversion phase. It is also possible to begin to read the data after conversion and continue to read the last bits even after a new conversion has been initiated. That allows the use of a slower clock speed like 14 MHz in impulse mode, 18 MHz in normal mode and 25 MHz in warp mode. –16– REV. 0 AD7664 EXT/INT = 1 INVSCLK = 0 CS, RD CNVST BUSY t3 t 35 t 36 t 37 SCLK 1 2 t 31 14 15 16 t 32 X SDOUT 3 D15 D14 D1 D13 D0 t 16 Figure 20. Slave Serial Data Timing for Reading (Read Previous Conversion During Convert) MICROPROCESSOR INTERFACING ADSP-21065L in Master Serial Interface The AD7664 is ideally suited for traditional dc measurement applications supporting a microprocessor, and ac signal processing applications interfacing to a digital signal processor. The AD7664 is designed to interface either with a parallel 16-bit-wide interface or with a general-purpose serial port or I/O ports on a microcontroller. A variety of external buffers can be used with the AD7664 to prevent digital noise from coupling into the ADC. The following sections illustrate the use of the AD7664 with an SPI-equipped microcontroller, the ADSP-21065L and ADSP-218x signal processors. As shown in Figure 22, the AD7664 can be interfaced to the ADSP-21065L using the serial interface in master mode without any glue logic required. This mode combines the advantages of reducing the number of wire connections and being able to read the data during or after conversion at user convenience. SPI Interface (MC68HC11) Figure 21 shows an interface diagram between the AD7664 and an SPI-equipped microcontroller like the MC68HC11. To accommodate the slower speed of the microcontroller, the AD7664 acts as a slave device and data must be read after conversion. This mode allows also the “daisy chain” feature. The convert command could be initiated in response to an internal timer interrupt. The reading of output data, one byte at a time, if necessary, could be initiated in response to the end-of-conversion signal (BUSY going low) using to an interrupt line of the microcontroller. The Serial Peripheral Interface (SPI) on the MC68HC11 is configured for master mode (MSTR = 1), Clock Polarity Bit (CPOL) = 0, Clock Phase Bit (CPHA) = 1 and SPI Interrupt Enable (SPIE = 1) by writing to the SPI Control Register (SPCR). The IRQ is configured for edge-sensitive-only operation (IRQE = 1 in OPTION register). The AD7664 is configured for the internal clock mode (EXT/INT low) and acts, therefore, as the master device. The convert command can be generated by either an external low jitter oscillator or, as shown, by a FLAG output of the ADSP-21065L or by a frame output TFS of one serial port of the ADSP-21065L which can be used as a timer. The serial port on the ADSP-21065L is configured for external clock (IRFS = 0), rising edge active (CKRE = 1), external late framed sync signals (IRFS = 0, LAFS = 1, RFSR = 1) and active high (LRFS = 0). The serial port of the ADSP-21065L is configured by writing to its receive control register (SRCTL)—see ADSP-2106x SHARC User’s Manual. Because the serial port within the ADSP-21065L will be seeing a discontinuous clock, an initial word reading has to be done after the ADSP-21065L has been reset to ensure that the serial port is properly synchronized to this clock during each following data read operation. DVDD OVDD OR OGND AD7664* ADSP-21065L* SHARC SER/PAR RDC/SDIN RD EXT/INT DVDD AD7664* MC68HC11* CS OVDD SER/PAR SYNC SDOUT INVSYNC SCLK INVSCLK CNVST RFS DR RCLK FLAG OR TFS EXT/INT BUSY CS SDOUT RD SCLK INVSCLK CNVST *ADDITIONAL PINS OMITTED FOR CLARITY IRQ Figure 22. Interfacing to the ADSP-21065L Using the Serial Master Mode MISO/SDI SCK I/O PORT *ADDITIONAL PINS OMITTED FOR CLARITY Figure 21. Interfacing the AD7664 to SPI Interface REV. 0 –17– AD7664 APPLICATION HINTS Bipolar and Wider Input Ranges In some applications, it is desired to use a bipolar or wider analog input range like, for instance, ± 10 V, ± 5 V or 0 V to 5 V. Although the AD7664 has only one unipolar range, by simple modifications of the input driver circuitry, bipolar and wider input ranges can be used without any performance degradation. Figure 23 shows a connection diagram which allows that. Components values required and resulting full-scale ranges are shown in Table II. The DVDD supply of the AD7664 can be either a separate supply or come from the analog supply AVDD or the digital interface supply OVDD. When the system digital supply is noisy, or fast switching digital signals are present, it is recommended that if no separate supply available, connect the DVDD digital supply to the analog supply, AVDD, through an RC filter as shown in Figure 5, and connect the system supply to the interface digital supply, OVDD, and the remaining digital circuitry. When DVDD is powered from the system supply, it is useful to insert a bead to further reduce high-frequency spikes. For applications where accurate gain and offset are desired, they can be calibrated by acquiring a ground and a voltage reference using an analog multiplexer, U2, as shown in Figure 23. Also, CF can be used as a one-pole antialiasing filter. CF R1 R2 ANALOG INPUT Layout The AD7664 has very good immunity to noise on the power supplies as can be seen in Figure 9. However, care should still be taken with regard to grounding layout. IN U1 AD7664 U2 The printed circuit board that houses the AD7664 should be designed so the analog and digital sections are separated and confined to certain areas of the board. This facilitates the use of ground planes that can be easily separated. Digital and analog ground planes should be joined in only one place, preferably underneath the AD7664, or, at least, as close as possible to the AD7664. If the AD7664 is in a system where multiple devices require analog-to-digital ground connections, the connection should still be made at one point only, a star ground point, which should be established as close as possible to the AD7664. It is recommended to avoid running digital lines under the device as these will couple noise onto the die. The analog ground plane should be allowed to run under the AD7664 to avoid noise coupling. Fast switching signals like CNVST or clocks should be shielded with digital ground to avoid radiating noise to other sections of the board, and should never run near analog signal paths. Crossover of digital and analog signals should be avoided. Traces on different but close layers of the board should run at right angles to each other. This will reduce the effect of feedthrough through the board. The power supplies lines to the AD7664 should use as large trace as possible to provide low impedance paths and reduce the effect of glitches on the power supplies lines. Good decoupling is also important to lower the supplies impedance presented to the AD7664 and reduce the magnitude of the supply spikes. Decoupling ceramic capacitors, typically 100 nF, should be placed on each power supplies pins AVDD, DVDD, and OVDD close to, and ideally right up against, these pins and their corresponding ground pins. Additionally, low ESR 10 µF capacitors should be located in the vicinity of the ADC to further reduce low frequency ripple. R3 R4 100nF INGND REF 2.5V REF CREF 100nF REFGND Figure 23. Using the AD7664 in 16-Bit Bipolar and/or Wider Input Ranges Table II. Component Values and Input Ranges Input Range R1 R2 R3 R4 ± 10 V ±5 V 0 V to –5 V 250 Ω 500 Ω 1 kΩ 2 kΩ 2 kΩ 1 kΩ 10 kΩ 10 kΩ None 8 kΩ 6.67 kΩ 0Ω The AD7664 has five different ground pins: INGND, REFGND, AGND, DGND, and OGND. INGND is used to sense the analog input signal. REFGND senses the reference voltage and should be a low impedance return to the reference because it carries pulsed currents. AGND is the ground to which most internal ADC analog signals are referenced. This ground must be connected with the least resistance to the analog ground plane. DGND must be tied to the analog or digital ground plane depending on the configuration. OGND is connected to the digital system ground. Evaluating the AD7664 Performance A recommended layout for the AD7664 is outlined in the evaluation board for the AD7664. The evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from a PC via the Eval-Control Board. –18– REV. 0 AD7664 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 0.067 (1.70) 0.059 (1.50) 0.055 (1.40) 0.028 (0.7) 0.020 (0.5) 0.012 (0.3) 0.362 (9.19) 0.354 (9.00) SQ 0.346 (8.79) 36 0.039 (1.00) REF 25 37 24 SEATING PLANE 0.280 (7.1) 0.276 (7.0) SQ 0.272 (6.9) TOP VIEW (PINS DOWN) 0.006 (0.15) 0.004 (0.10) 0.002 (0.05) 0ⴗ MIN 48 13 12 1 0.023 (0.58) 0.010 (0.26) 0.020 (0.50) 0.007 (0.18) 0.017 (0.42) 0.006 (0.15) 0.007 (0.177) 0.005 (0.127) 0.004 (0.107) C02046–7.5–7/00 (rev. 0) 48-Lead Quad Flatpack (LQFP) (ST-48) 0.057 (1.45) 0.055 (1.40) 0.053 (1.35) PRINTED IN U.S.A. 7ⴗ 3.5ⴗ 0ⴗ REV. 0 –19–