CM2021-02TR
HDMI Receiver Port Protection and Interface Device
Features
Product Description
•
•
The CM2021-02TR HDMI Receiver Port Protection
and Interface Device is specifically designed for next
generation HDMI Host interface protection.
•
•
•
•
•
•
HDMI 1.3 compliant
0.05pF matching capacitance between the TMDS
intra-pair
Level shifting/isolation circuitry
Provides ESD protection to IEC61000-4-2 Level 4
- 8kV contact discharge
- 15kV air discharge
Matched 0.5mm trace spacing (TSSOP)
Simplified layout for HDMI connectors
Backdrive protection
RoHS-compliant, lead-free packaging
An integrated package provides all ESD, level shift and
backdrive protection for an HDMI port in a single 38Pin TSSOP package.
The CM2021-02TR part is specifically designed to
complement the CM2020 protection part in HDMI
transmitters (DVD, STB/OPVR, etc.).
Applications
•
•
•
PC
Consumer electronics
Displays and digital television
Electrical Schematic
ESD_BYP
5V_SUPPLY
TMDS_D2+
TMDS_D1+
TMDS_D0+
TMDS_CK+
TMDS_GND
TMDS_GND
TMDS_GND
TMDS_GND
TMDS_D2–
TMDS_D1–
TMDS_D0–
TMDS_CK–
LV SUPPLY
CE_REMOTE_IN
LV SUPPLY
CE_REMOTE_OUT
DDC_DAT_OUT
LV SUPPLY
LV SUPPLY
DDC_CLK_IN
DDC_DAT_IN
DDC_CLK_OUT
HOTPLUG_DET_IN
HOTPLUG_DET_OUT
© 2008 California Micro Devices Corp. All rights reserved.
490 N. McCarthy Blvd., Milpitas, CA 95035-5112
● Tel: 408.263.3214
Issue B – 07/14/08
●
Fax: 408.263.7846
●
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1
CM2021-02TR
PACKAGE / PINOUT DIAGRAM
TOP VIEW
5V_SUPPLY
1
38
NC
LV_SUPPLY
2
37
ESD_BYP
GND
3
36
GND
TMDS_D2+
4
35
TMDS_D2+
TMDS_GND
5
34
TMDS_GND
TMDS_D2–
6
33
TMDS_D2–
TMDS_D1+
7
32
TMDS_D1+
TMDS_GND
8
31
TMDS_GND
TMDS_D1–
9
30
TMDS_D1–
TMDS_D0+
10
29
TMDS_D0+
TMDS_GND
11
28
TMDS_GND
TMDS_D0–
12
27
TMDS_D0–
TMDS_CK+
13
26
TMDS_CK+
TMDS_GND
14
15
25
TMDS_GND
TMDS_CK–
24
TMDS_CK–
CE_REMOTE_IN
16
23
CE_REMOTE_OUT
DDC_CLK_IN
17
22
DDC_CLK_OUT
DDC_DAT_IN
18
21
DDC_DAT_OUT
HOTPLUG_DET_IN
19
20
HOTPLUG_DET_OUT
38-PIN TSSOP PACKAGE
Note: This drawing is not to scale.
PIN DESCRIPTIONS
PINS
4, 35
NAME
TMDS_D2+
ESD Level
8kV2
TMDS 0.9pF ESD protection.1
6, 33
TMDS_D2–
8kV2
TMDS 0.9pF ESD protection.1
7, 32
TMDS_D1+
8kV2
TMDS 0.9pF ESD protection.1
9, 30
TMDS_D1–
8kV2
TMDS 0.9pF ESD protection.1
10, 29
TMDS_D0+
2
8kV
TMDS 0.9pF ESD protection.1
12, 27
TMDS_D0–
8kV2
TMDS 0.9pF ESD protection.1
13, 26
TMDS_CK+
8kV2
TMDS 0.9pF ESD protection.1
15, 24
TMDS_CK–
2
8kV
16
CE_REMOTE_IN
2kV3
TMDS 0.9pF ESD protection.1
LV_SUPPLY referenced logic level into ASIC.
23
CE_REMOTE_OUT
8kV2
5V_SUPPLY referenced logic level out plus 3.5pF ESD to connector.
17
DDC_CLK_IN
2kV3
LV_SUPPLY referenced logic level into ASIC.
22
DDC_CLK_OUT
8kV2
5V_SUPPLY referenced logic level out plus 3.5pF ESD to connector.
18
DDC_DAT_IN
2kV
LV_SUPPLY referenced logic level into ASIC.
21
DDC_DAT_OUT
8kV2
5V_SUPPLY referenced logic level out plus 3.5pF ESD to connector.
19
HOTPLUG_DET_IN
2kV3
LV_SUPPLY referenced logic level into ASIC.
20
HOTPLUG_DET_OUT
2
LV_SUPPLY
1
5V_SUPPLY
37
ESD_BYP
3
DESCRIPTION
2
5V_SUPPLY referenced logic level out plus 3.5pF ESD to connector.
3
2kV
Bias for CE / DDC / HOTPLUG level shifters.
2kV3
Current source for 5V_OUT.
8kV
3
2kV
This pin may be connected to a 0.1μF ceramic capacitor, but it is not
necessary.
© 2008 California Micro Devices Corp. All rights reserved.
2
490 N. McCarthy Blvd., Milpitas, CA 95035-5112
● Tel: 408.263.3214
Issue B – 07/14/08
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CM2021-02TR
PIN DESCRIPTIONS (CONT’D)
PINS
5, 34, 8, 31,
11, 28, 14,
25
3, 36
38
NAME
TMDS_GND
ESD Level
N/A
GND
NC
N/A
N/A
DESCRIPTION
TMDS ESD and Parasitic GND return.4
Supply GND reference.
No connect.
Note 1: These 2 pins need to be connected together in-line on the PCB.
Note 2: Standard IEC 61000-4-2, CDISCHARGE=150pF, RDISCHARGE=330Ω, 5V_SUPPLY and LV_SUPPLY within recommended
operating conditions, GND=0V, each bypassed with a 0.1μF ceramic capacitor connected to GND.
Note 3: Human Body Model per MIL-STD-883, Method 3015, CDISCHARGE=100pF, RDISCHARGE=1.5kΩ, 5V_SUPPLY and
LV_SUPPLY within recommended operating conditions, GND=0V, and each bypassed with a 0.1μF ceramic capacitor connected to GND.
Note 4: These pins should be routed directly to the associated GND pins on the HDMI connector with single point ground vias at the
connector
Backdrive Protection
Two scenarios below describe what can happen when
a powered device is connected to an unpowered
device via an HDMI interface, substantiating the need
for backdrive protection for this type of interface.
In a classic scenario, a DVD player is connected to a
TV via an HDMI interface. If the DVD player is switched
off and the TV is left on, there is a possibility of reverse
current flow back into the main power supply rail of the
DVD player. Typically, the DVD’s power supply has
some form of bulk supply capacitance associated with
it. Because all CMOS logic exhibits a very high
impedance on the power rail node when “off,” if there is
very little parasitic shunt resistance and as little as a
few milliamps of “backdrive” current flowing back into
the power rail, it is possible over time to charge that
bulk supply capacitance to some intermediate level. If
this level rises above the power-on-reset (POR)
voltage level of some of the integrated circuits in the
DVD player, these devices may not reset properly
when the DVD player is turned back on.
LV_SUPPLY
=OFF
To avoid either of these situations, the CM2021-02TR
is designed to block backdrive current, guaranteeing no
more than 5μA on any I/O pin when the I/O pin voltage
is greater than the CM2021-02TR supply voltage.
+5V
+5V
LV_SUPPLY
=OFF
LOW VOLTAGE
HDMI ASIC
HDMI SOURCE
In a more serious scenario, if any SOC devices are
incorporated in the design which have built-in level
shifter and DRC diodes for ESD protection, there is
even a higher risk for damage. In this case, if there is a
pullup resistor (such as with DDC) on the other end of
the cable, that resistance will pull the SOC chips
“output” up to a high level. This will forward bias the
upper ESD diode in the DRC and charge the bulk
capacitance in a similar fashion like above. If the
current flow is high enough, even as little as a few
milliamps, it could destroy one of the SOC chip’s
internal DRC diodes, as they are not designed for
passing DC.
ASIC
HDMI SINK
LOW VOLTAGE
HDMI ASIC
ASIC
HDMI SINK
HDMI SOURCE
Figure 1. Backdrive Protection Diagram
© 2008 California Micro Devices Corp. All rights reserved.
490 N. McCarthy Blvd., Milpitas, CA 95035-5112
● Tel: 408.263.3214
Issue B – 07/14/08
●
Fax: 408.263.7846
●
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3
CM2021-02TR
Ordering Information
PART NUMBERING INFORMATION
Lead-free Finish
Pins
Package
Ordering Part Number1
Part Marking
38
TSSOP-38
CM2021-02TR
CM2021-02TR
Note 1: Parts are shipped in Tape and Reel form unless otherwise specified.
Specifications
ABSOLUTE MAXIMUM RATINGS
PARAMETER
RATING
UNITS
VCC5V, VCCLV
6.0
V
DC Voltage at any Channel Input
6.0
V
–65 to +150
°C
Storage Temperature Range
STANDARD (RECOMMENDED) OPERATING CONDITIONS
SYMBOL
PARAMETER
MIN
TYP
MAX
UNITS
5V_SUPPLY
Operating Supply Voltage
GND
5
5.5
V
LV_SUPPLY
Bias Supply Voltage
1
3.3
5.5
V
85
°C
Operating Temperature Range
–40
ELECTRICAL OPERATING CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
ICC5V
Operating Supply Current
ICCLV
IOFF
(SEE NOTE 1)
TYP
MAX
UNITS
5V_SUPPLY = 5.0V
110
130
μA
Bias Supply Current
LV_SUPPLY = 3.3V
1
5
μA
OFF state leakage current,
level shifting NFET
LV_SUPPLY = 0V
0.1
5
μA
IBACKDRIVE
Current conducted from output
pins to V_SUPPLY rails when
powered down
5V_SUPPLY < VCH_OUT;
Signal pins: TMDS_[2:0]+/–,
TMDS_CK+/–, CE_REMOTE_OUT,
DDC_DAT_OUT, DDC_CLK_OUT,
HOTPLUG_DET_OUT Only
0.1
5
μA
IBACKDRIVE,
CEC
Current through
CE-REMOTE_OUT when
powered down
CE-REMOTE_IN = CE_SUPPLY <
CE_REMOTE_OUT
0.1
1
μA
75
95
140
mV
0.6
0.6
0.85
0.85
0.95
0.95
V
V
VON
VF
MIN
VOLTAGE drop across level
shifting NFET when ON
LV_SUPPLY = 2.5V, VS = GND,
IDS = 3mA
Diode Forward Voltage
Top Diode
Bottom Diode
IF = 8mA, TA = 25°C;
Note 2
© 2008 California Micro Devices Corp. All rights reserved.
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CM2021-02TR
ELECTRICAL OPERATING CHARACTERISTICS (CONT’D) (SEE NOTE 1)
VESD
±8
kV
ESD Withstand Voltage (IEC)
Pins 4, 7,10,13, 20, 21, 22, 23, 24,
27, 30, 33;
Notes 2 and 3
Channel Clamp Voltage
Positive Transients
Negative Transients
TA = 25°C, IPP = 1A, tP = 8/20μs;
Notes 2 and 4
Dynamic Resistance
Positive Transients
Negative Transients
TA = 25°C, IPP = 1A, tP = 8/20μs;
Notes 2 and 4
TMDS Channel Leakage
Current
TA = 25°C;
Note 2
0.01
1
μA
CIN, TMDS
TMDS Channel Input
Capacitance
5V_SUPPLY = 5.0V,
Measured at 1MHz,
VBIAS=2.5V;
Note 2
0.9
1.2
pF
ΔCIN, TMDS
TMDS Channel Input
Capacitance Matching
5V_SUPPLY = 5.0V,
Measured at 1MHz,
VBIAS=2.5V;
Notes 2 and 5
0.05
CIN, DDC
Level Shifting Input
Capacitance, Capacitance to
GND
5V_SUPPLY = 5V,
Measured at 100KHz,
VBIAS=2.5V;
Note 2
3.5
4
pF
CIN, CEC
Level Shifting Input
Capacitance, Capacitance to
GND
5V_SUPPLY = 5V,
Measured at 100KHz,
VBIAS=2.5V;
Note 2
3.5
4
pF
CIN, HP
Level Shifting Input
Capacitance, Capacitance to
GND
5V_SUPPLY = 5V,
Measured at 100KHz,
VBIAS=2.5V;
Note 2
3.5
4
pF
VCL
RDYN
ILEAK
11.0
–2.0
V
V
1.2
0.9
Ω
Ω
pF
Note 1: Operating characteristics are over standard operating conditions unless otherwise specified.
Note 2: This parameter is guaranteed by design and verified by device characterization.
Note 3: Standard IEC 61000-4-2, CDISCHARGE=150pF, RDISCHARGE=330Ω, 5V_SUPPLY and LV_SUPPLY within recommended
operating conditions, GND=0V, each bypassed with a 0.1μF ceramic capacitor connected to GND.
Note 4: These measurements performed with no external capacitor on ESD_BYP.
Note 5: Intra-pair matching, each TMDS pair (i.e. D+, D–)
© 2008 California Micro Devices Corp. All rights reserved.
490 N. McCarthy Blvd., Milpitas, CA 95035-5112
● Tel: 408.263.3214
Issue B – 07/14/08
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5
CM2021-02TR
Performance Information
Typical Filter Performance (TA=25°C, DC Bias=0V, 50 Ohm Environment)
Figure 2. Insertion Loss vs. Frequency (TMDS_D1– to GND)
© 2008 California Micro Devices Corp. All rights reserved.
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CM2021-02TR
Application Information
5V_SUPPLY
CM2021-02TR
LV_SUPPLY
NOTE 2
{
38
2
37
3
36
CBYP
OPTIONAL
100nF
4
35
TMDS_D2+
5
34
TMDS_GND
6
33
TMDS_D2–
7
32
TMDS_D1+
8
31
TMDS_GND
9
30
TMDS_D1–
10
29
TMDS_D0+
11
28
TMDS_GND
12
27
TMDS_D0–
13
26
TMDS_CK+
14
15
25
TMDS_GND
24
TMDS_CK–
ASIC_CEC
16
23
CE_REMOTE
ASIC_SCL
17
22
ASIC_SDA
18
21
N/C
DDC_CLK
19
20
TMDS_D2+
TMDS_D2–
{
NOTE 1
1
N.C.
TMDS_D1+
TMDS_D1–
TMDS_D0+
TMDS_D0–
TMDS_CK+
TMDS_CK–
HOTPLUG_DET
DDC_DAT
NOTE 3
GND
+5V OUT
+3.3V
HOTPLUG_DET
HDMI
Connector
RCEC
RDAT
LAYOUT NOTES
NOTE 1) Differential TMDS Pairs should be
designed as normal 100Ω HDMI microstrip.
Single Ended TMDS traces underneath CM2021
and between CM2021 and Connector should be
tuned to match chip/connector parasitics. (See
MediaGuardTM Application Notes.)
2kΩ
RSCL
2kΩ
EEPROM_CLK
27K
EEPROM_DAT
DCEC
+5V OUT
RPD
1kΩ
NOTE 2) Level Shifter signals should be biased
with a weak pullup to the desired local
LV_SUPPLY. If the local ASIC includes sufficient
pullups to register a logic high when the CM2021
NFET is "off", then external pullups are not needed.
NOTE 3) Place CM2021 as close to conector as possible,
and as with any controlled impedance line avoid ANY
silkscreening over TMDS lines.
Figure 3. Typical Application for CM2021-02TR
© 2008 California Micro Devices Corp. All rights reserved.
490 N. McCarthy Blvd., Milpitas, CA 95035-5112
● Tel: 408.263.3214
Issue B – 07/14/08
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7
CM2021-02TR
measurements, for example. The MediaGuard™
backdrive isolation circuitry limits this current to less
than 10μA, and will help ensure HDMI compliance.
Application Information
Design Considerations
1. DUT On vs. DUT Off
2. EEPROM Configurations
Many HDMI CTS tests require a power off condition on
the System Under Test. Many Dual Rail Clamp (DRC)
ESD diode configurations will be forward biased when
their VDD rail is lower than the I/O pin bias, thereby
exhibiting extremely high apparent capacitance
The EDID EEPROM may be connected to either the
ASIC LV domain or Connector 5V domain of the
CM2021. See the MediaGuard EEPROM Application
Note for further circuit connection and layout examples.
Figure 4. Design Example
© 2008 California Micro Devices Corp. All rights reserved.
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490 N. McCarthy Blvd., Milpitas, CA 95035-5112
● Tel: 408.263.3214
Issue B – 07/14/08
●
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CM2021-02TR
Mechanical Details
TSSOP-38 Mechanical Specifications
Mechanical Package Diagrams
CM2021-02TR devices are supplied in 38-pin TSSOP
packages. Dimensions are presented below.
For complete information on the TSSOP-38, see the
California Micro Devices TSSOP Package Information
document.
TOP VIEW
D
38
37
36
35 34
33 32 31 30
29
28 27 26
25 24
23 22 21
20
PACKAGE DIMENSIONS
E
Package
TSSOP
JEDEC No.
MO-153 (Variation BD-1)
Pins
38
Dimensions
1
Millimeters
Min
Max
Min
—
1.20
—
0.047
0.05
0.15
0.002
0.006
b
0.17
0.27
0.007
0.011
c
0.09
0.20
0.004
0.008
D
9.60
9.80
0.378
0.386
E1
4.30
e
0.45
# per tape
and reel
4
5
6
7
8
9
10
11 12 13
14 15
16 17 18
19
SIDE VIEW
A
SEATING
PLANE
A1
b
e
0.252 BSC
4.50
0.50 BSC
L
3
Max
A
6.40 BSC
2
Inches
A1
E
E1
Pin 1 Marking
0.169
0.177
0.020 BSC
0.75
0.018
END VIEW
c
0.030
2500 pieces
L
Controlling dimension: millimeters
Package Dimensions for TSSOP-38
© 2008 California Micro Devices Corp. All rights reserved.
490 N. McCarthy Blvd., Milpitas, CA 95035-5112
● Tel: 408.263.3214
Issue B – 07/14/08
●
Fax: 408.263.7846
●
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9
CM2021-02TR
Tape and Reel Specifications
PART NUMBER
PACKAGE SIZE
(mm)
POCKET SIZE (mm)
B0 X A0 X K0
TAPE WIDTH
W
REEL
DIAMETER
QTY PER
REEL
P0
P1
CM2021-02TR
9.70 X 6.40 X 1.20
10.20 X 6.90 X 1.80
16mm
330mm (13")
2500
4mm
12mm
10 Pitches Cumulative
Tolerance On Tape
±0.2 mm
Po
Top
Cover
Tape
Ao
W
Bo
Ko
For tape feeder reference
only including draft.
Concentric around B.
Embossment
Center Lines
of Cavity
P1
User Direction of Feed
© 2008 California Micro Devices Corp. All rights reserved.
10
490 N. McCarthy Blvd., Milpitas, CA 95035-5112
● Tel: 408.263.3214
Issue B – 07/14/08
●
Fax: 408.263.7846
●
www.cmd.com