EMC PH86P168A

PH86P168AxS/xJ
8-Bit Microcontroller
with OTP ROM
Green Product
Specification
Doc. Version 1.0
ELAN MICROELECTRONICS CORP.
January 2006
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are trademarks of ELAN Microelectronics Corporation
Copyright © 2005 by ELAN Microelectronics Corporation
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Printed in Taiwan
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Contents
Contents
1
2
3
General Description ...................................................................................... 1
Features ......................................................................................................... 1
Pin Assignments and Descriptions.............................................................. 2
3.1
Pin Assignments ................................................................................................. 2
3.2
Pin Descriptions ................................................................................................. 3
3.2.1
3.2.2
3.2.3
3.2.4
4
PH86P168ABPS/NBPJ and PH86P168ABMS/NBMJ Pin Descriptions .............3
PH86P168AAPS/NAPJ and PH86P168AAMS/NAMJ Pin Descriptions .............3
PH86P168AAASS/NAASJ Pin Descriptions .......................................................4
PH86P168AAKMS/NAKMJ Pin Descriptions......................................................4
Function Description..................................................................................... 5
4.1
Operational Registers......................................................................................... 5
4.1.1
4.1.2
4.1.3
4.1.4
4.1.5
4.1.6
4.1.7
4.1.8
4.2
Special Purpose Registers ................................................................................. 8
4.2.1
4.2.2
4.2.3
4.2.4
4.2.5
4.2.6
4.2.7
4.2.8
4.2.9
4.3
4.4
Port 6 Input Change Wake-up/Interrupt Function Usage..................................16
RESET and Wake-up ....................................................................................... 17
4.5.1
4.5.2
4.6
Accumulator (A) Register ....................................................................................8
Control (CONT ) Register....................................................................................9
I/O Port Control (IOC5 ~ IOC6) Registers...........................................................9
Prescaler Counter (IOCA ) Register....................................................................9
Pull-Down Control (IOCB) Register...................................................................10
Open-Drain Control (IOCC ) Register ...............................................................10
Pull-High Control (IOCD) Register ....................................................................11
WDT Control (IOCE) Register ...........................................................................11
IOCF (Interrupt Mask Register).........................................................................12
TCC/WDT & Prescaler ..................................................................................... 12
I/O Ports ........................................................................................................... 13
4.4.1
4.5
Indirect Addressing (R0) Register .......................................................................6
Time Clock / Counter (R1) Register ....................................................................6
Program Counter and Stack (R2) Register .........................................................6
Status (R3) Register ............................................................................................7
RAM Select (R4) Register...................................................................................7
Port 5 ~ Port 6 (R5 ~ R6) Registers ....................................................................8
Interrupt Status (RF) Register .............................................................................8
General Purpose (R10 ~ R3F) Registers............................................................8
Summary of Initialized Values for Registers......................................................19
The Status of RST, T, and P of STATUS Register .............................................21
4.5.2.1 RST, T and P after RESET Values .....................................................21
4.5.2.2 Event Affecting T and P Status ...........................................................21
Interrupt ............................................................................................................ 22
Green Product Specification (V1.0) 01.06.2006
• iii
Contents
4.7
Oscillator .......................................................................................................... 23
4.7.1
4.7.2
4.7.3
4.8
CODE Option Register ..................................................................................... 26
4.8.1
4.8.2
4.9
Oscillator Modes................................................................................................23
4.7.1.1 Oscillator Modes Defined by OSC, HLF, and HLP.............................23
4.7.1.2 The Summary of Maximum Operating Speeds ..................................23
Crystal Oscillator/Ceramic Resonators (XTAL) .................................................23
4.7.2.1 Capacitor Selection Guide for Crystal Oscillator or
Ceramic Resonator ............................................................................24
External RC Oscillator Mode.............................................................................25
4.7.3.1 RC Oscillator Frequencies .................................................................26
Code Option Register (Word 0).........................................................................26
Customer ID Register (Word 1).........................................................................28
Power-On Considerations ................................................................................ 29
4.10 External Power-On Reset Circuit .................................................................... 29
4.11 Residual-Voltage Protection ............................................................................. 30
4.12 Instruction Set .................................................................................................. 31
4.13 Timing Diagrams .............................................................................................. 33
4.13.1 AC Test Input/Output Waveform........................................................................33
4.13.2 RESET Timing (CLK = ”0”)................................................................................33
4.13.3 TCC Input Timing (CLKS = ”0”) .........................................................................33
5
6
Absolute Maximum Ratings........................................................................ 34
Electrical Characteristics............................................................................ 34
6.1
DC Electrical Characteristic.............................................................................. 34
6.2
AC Electrical Characteristics ............................................................................ 35
6.3
Device Characteristics...................................................................................... 36
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.3.6
Port 6 Vih/Vil vs. VDD (Input Pin with Schmitt Inverter) ....................................36
Port 5 Input Threshold Voltage (Vth) vs. VDD...................................................36
Ports 5 & Port 6 Voh vs. Ioh, VDD=5V and 3V .................................................37
Ports 5 & Port 6 Vol vs. Iol, VDD=5V and 3V....................................................37
WDT Time Out Period vs. VDD (Prescaler Set to 1:1)......................................38
Typical RC OSC Frequency vs. VDD (Cext = 100pF, Temp. = 25℃) ..............39
6.3.7
Typical RC OSC Frequency vs. VDD
(with R and C under Ideal Conditions) ..............................................................39
Typical and Maximum Operating Current
(ICC1/2/3/4) vs. Temperature ............................................................................40
Typical and Maximum Standby Current
(ISB1 and ISB2) vs. Temperature .....................................................................42
6.3.8
6.3.9
6.3.10 Operating Voltage under Temperature Range of 0°C to 70°C
and –40°C to 85°C ............................................................................................43
6.3.11 Operating Current Range (Based on High and Low Freq. @ =25℃)
vs. Voltage.........................................................................................................44
iv •
Green Product Specification (V1.0) 01.06.2006
Contents
APPENDIX
A
Package Types............................................................................................. 45
A..1 Package Detailed Information .......................................................................... 46
A.1.1
A.1.2
A.1.3
A.1.4
A.1.5
B
C
14-Lead Plastic Dual in line (PDIP) — 300 Mil .................................................46
14-Lead Plastic Small Outline (SOP) — 150 Mil...............................................47
18-Lead Plastic Dual in Line (PDIP) — 300 Mil ................................................48
18-Lead Plastic Small Outline (SOP) — 300 Mil...............................................49
20-Lead Plastic Small Outline (SSOP) — 209 Mil ............................................50
Quality Assurance and Reliability .............................................................. 51
Address Trap Detect.................................................................................... 52
Green Product Specification (V1.0) 01.06.2006
•v
Contents
Specification Revision History
Doc. Version
1.0
vi •
Revision Description
Initial version
Date
01/06/2006
Green Product Specification (V1.0) 01.06.2006
PH86P168AxS/xJ
8-Bit Microcontroller with OTP ROM
1
General Description
PH86P168AxS/xJ is an 8-bit microprocessor designed and developed with low-power,
high-speed CMOS technology. It is equipped with 1K*13-bits Electrical One Time
Programmable Read Only Memory (OTP-ROM). It provides three PROTECTION bits
to prevent user’s code in the OTP memory from being intruded. Eight OPTION bits are
also provided to meet user’s additional requirements.
With its OTP-ROM feature, the PH86P168AxS/xJ is able to offer a convenient way of
developing and verifying user’s programs. Moreover, user can take advantage of
ELAN DWriter to easily program his development code.
2
Features
„
Operating voltage range: 2.5V~5.5V
„
Operating temperature range: -40°C~85°C
„
Operating frequency range (base on 2 clocks ):
• Crystal mode: DC~20MHz at 5V, DC~8MHz at 3V, DC~4MHz at 2.5V.
• ERC mode: DC~4MHz at 5V, DC~4MHz at 3V, DC~4MHz at 2.5V.
„
Low power consumption:
• Less then 2 mA at 5V/4MHz
• Typically 20 µA at 3V/32KHz
• Typically 1 µA during sleep mode
„
1K × 13 bits on chip ROM
„
One security register to prevent intrusion of OTP memory codes
„
One configuration register to accommodate user’s requirements
„
48× 8 bits on chip registers (SRAM, general purpose register)
„
2 bi-directional I/O ports
„
5 level stacks for subroutine nesting
„
8-bit real time clock/counter (TCC) with selective signal sources, trigger edges, and
overflow interrupt
„
Two clocks per instruction cycle
„
Power down (SLEEP) mode
„
Three available interruptions
• TCC overflow interrupt
• Input-port status changed interrupt (wake up from sleep mode)
• External interrupt
Green Product Specification (V1.0) 01.06.2006
(This specification is subject to change without further notice)
•1
PH86P168AxS/xJ
8-Bit Microcontroller with OTP ROM
„
Programmable free running watchdog timer
„
8 programmable pull-high pins
„
7 programmable pull-down pins
„
8 programmable open-drain pins
„
2 programmable R-option pins
„
Package types:
•
•
•
•
•
•
3
14 pin DIP
300mil
14 pin SOP
150mil
18 pin DIP
300mil
18 pin SOP
300mil
20 pin SSOP 209mil
20 pin SSOP 209mil
„
99.9% single instruction cycle commands
„
The transient point of system frequency between HXT and LXT is around 400KHz
Pin Assignments and Descriptions
3.1 Pin Assignments
P53
2
TCC
3
/RESET
4
Vss
5
P60/INT
6
P61
7
14
13
1
18
P51
P53
2
17
P50
P51
TCC
3
P50
/RESET
4
Vss
5
P60/INT
6
VDD
P61
7
P67
P62
8
8
P66
P63
9
12
OSCI
11
OSCO
10
9
PH86P168AAPS/NAPJ
PH86P168AAMS/NAMJ
1
PH86P168ABPS/NBPJ
PH86P168ANBMS/NBPJ
P52
P52
20
NC
P52
1
2
19
P51
P53
2
P53
3
18
P50
TCC
3
TCC
4
17
OSCI
/RESET
4
/RESET
5
16
OSCO
Vss
5
15
VDD
Vss
6
14
P67
P60/INT
7
13
P66
P61
8
12
P65
P62
11
P64
P63
Vss
6
P60/INT
7
P61
8
P62
9
P63
10
PH86P168AAKMS/NAKMJ
1
PH86P168AAASS/NAASJ
NC
P52
16
OSCI
15
OSCO
14
VDD
13
P67
12
P66
11
P65
10
P64
20
P51
19
P50
18
OSCI
17
OSCO
16
VDD
15
VDD
14
P67
13
P66
9
12
P65
10
11
P64
Fig. 1-1 Pin Assignments
2•
Green Product Specification (V1.0) 01.06.2006
(This specification is subject to change without further notice)
PH86P168AxS/xJ
8-Bit Microcontroller with OTP ROM
3.2 Pin Descriptions
3.2.1 PH86P168ABPS/NBPJ and PH86P168ABMS/NBMJ Pin Descriptions
Symbol Pin No.
Type
VDD
10
–
OSCI
12
I
OSCO
11
I/O
TCC
3
I
/RESET
4
I
P50~P53
13, 14,
1, 2
I/O
P60~P61
6~7
I/O
P66~P67
8~9
I/O
/INT
VSS
6
5
I
–
Function
y Power supply
y XTAL type: Crystal input terminal or external clock input pin
y ERC type: RC oscillator input pin
y XTAL type: Output terminal for crystal oscillator or external clock input pin
y RC type: Instruction clock output
y External clock signal input
y The real time clock/counter (with Schmitt trigger input pin), must be tied
to VDD or VSS if not in use
y Input pin with Schmitt trigger. If this pin remains at logic low, the controller
will also remain at reset condition.
y P50~P53 are bi-directional I/O pins
y P50 and P51 can also be defined as the R-option pins
y P50~P52 can be set as pull-down by software
y P60~P61 are bi-directional I/O pins
y These pins can be set as pull-high, pull-down, or open-drain through
software programming
y P66~P67 are bi-directional I/O pins
y These pins can be set as pull-high or open-drain through software
programming
y External interrupt pin triggered by falling edge
y Ground
3.2.2 PH86P168AAPS/NAPJ and PH86P168AAMS/NAMJ Pin Descriptions
Symbol Pin No.
Type
VDD
14
–
OSCI
16
I
OSCO
15
I/O
TCC
3
I
/RESET
4
I
P50~P53
17,18,
1, 2
I/O
P60~P67
6~13
I/O
/INT
VSS
6
5
I
–
Function
y Power supply
y XTAL type: Crystal input terminal or external clock input pin
y ERC type: RC oscillator input pin
y XTAL type: Output terminal for crystal oscillator or external clock input pin
y RC type: Instruction clock output
y External clock signal input
y The real time clock/counter (with Schmitt trigger input pin), must be tied to
VDD or VSS if not in use
y Input pin with Schmitt trigger. If this pin remains at logic low, the controller
will also remain at reset condition.
y P50~P53 are bi-directional I/O pins
y P50 and P51 can also be defined as the R-option pins
y P50~P52 can be set as pull-down by software
y P60~P67 are bi-directional I/O pins
y These pins can be set as pull-high or open-drain through software
programming
y P60~P63 can also be set as pull-down by software
y External interrupt pin triggered by falling edge
y Ground
Green Product Specification (V1.0) 01.06.2006
(This specification is subject to change without further notice)
•3
PH86P168AxS/xJ
8-Bit Microcontroller with OTP ROM
3.2.3 PH86P168AAASS/NAASJ Pin Descriptions
Symbol Pin No.
Type
VDD
15
–
OSCI
17
I
OSCO
16
I/O
TCC
4
I
/RESET
5
I
P50~P53
18, 19,
2, 3
I/O
P60~P67
7~14
I/O
/INT
VSS
7
6
I
–
Function
y Power supply
y XTAL type: Crystal input terminal or external clock input pin
y ERC type: RC oscillator input pin
y XTAL type: Output terminal for crystal oscillator or external clock input pin
y RC type: Instruction clock output
y External clock signal input
y The real time clock/counter (with Schmitt trigger input pin), must be tied to
VDD or VSS if not in use
y Input pin with Schmitt trigger. If this pin remains at logic low, the controller
will also remain at reset condition.
y P50~P53 are bi-directional I/O pins
y P50 and P51 can also be defined as the R-option pins
y P50~P52 can be set as pull-down by software
y P60~P67 are bi-directional I/O pins
y These pins can be set as pull-high or open-drain through software
programming
y P60~P63 can also be set as pull-down by software
y External interrupt pin triggered by falling edge
y Ground
3.2.4 PH86P168AAKMS/NAKMJ Pin Descriptions
4•
Symbol
Pin No.
Type
VDD
15,16
–
OSCI
18
I
OSCO
17
I/O
TCC
3
I
/RESET
4
I
Function
y
y
y
y
y
y
y
y
P50~P53 19, 20, 1, 2
I/O
P60~P67
7~14
I/O
y
y
y
y
y
/INT
VSS
7
5, 6
I
–
y
y
y
Power supply
XTAL type: Crystal input terminal or external clock input pin
ERC type: RC oscillator input pin
XTAL type: Output terminal for crystal oscillator or external clock input pin
RC type: Instruction clock output
External clock signal input
The real time clock/counter (with Schmitt trigger input pin), must be tied to
VDD or VSS if not in use
Input pin with Schmitt trigger. If this pin remains at logic low, the controller
will also remain at reset condition.
P50~P53 are bi-directional I/O pins
P50 and P51 can also be defined as the R-option pins
P50~P52 can be set as pull-down by software
P60~P67 are bi-directional I/O pins
These pins can be set as pull-high or open-drain through software
programming
P60~P63 can also be set as pull-down by software
External interrupt pin triggered by falling edge
Ground
Green Product Specification (V1.0) 01.06.2006
(This specification is subject to change without further notice)
PH86P168AxS/xJ
8-Bit Microcontroller with OTP ROM
4
Function Description
OSCO
/RESET
OSCI
WDT timer
TCC
/INT
Oscillator/Timing
Control
ROM
Prescaler
R2
Stack
IOCA
Interrupt
Controller
RAM
R4
ALU
Instruction
Register
R3
R1(TCC)
Instruction
Decoder
ACC
DATA & CONTROL BUS
IOC6
R6
P60//INT
P61
P62
P63
P64
P65
P66
P67
I/O
PORT 6
IOC5
R5
I/O
PORT 5
P50
P51
P52
P53
Fig. 4-1 Function Block Diagram
4.1 Operational Registers
The following is the operational registers’ data memory configuration.
Address
R PAGE Registers
IOC PAGE Registers
00
01
02
03
R0
R1
R2
R3
(IAR)
(TCC)
(PC)
(Status)
Reserve
CONT
Reserve
Reserve
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
︰
3F
R4
R5
R6
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
RF
(RSR)
(Port5)
(Port6)
Reserve
IOC5
IOC6
Reserve
Reserve
Reserve
IOCA
IOCB
IOCC
IOCD
IOCE
IOCF
(Interrupt Status)
(Control Register)
(I/O Port Control Register)
(I/O Port Control Register)
(Prescaler Control Register)
(Pull-down Register)
(Open-drain Control)
(Pull-high Control Register)
(WDT Control Register)
(Interrupt Mask Register)
General Registers
Green Product Specification (V1.0) 01.06.2006
(This specification is subject to change without further notice)
•5
PH86P168AxS/xJ
8-Bit Microcontroller with OTP ROM
4.1.1 Indirect Addressing (R0) Register
R0 is not a physically implemented register. Its major function is to perform as an
indirect addressing pointer. Any instruction using R0 as a pointer actually accesses
data pointed by the RAM Select Register (R4).
4.1.2 Time Clock / Counter (R1) Register
„
Increased by an external signal edge, which is defined by TE bit (CONT-4) through
the TCC pin, or by the instruction cycle clock.
„
Writable and readable as any other registers.
„
Defined by resetting PAB (CONT-3).
„
The prescaler is assigned to TCC, if the PAB bit (CONT-3) is reset.
„
The contents of the prescaler counter will be cleared only when TCC register is
written with a value.
4.1.3 Program Counter and Stack (R2) Register
„
Depending on the device type, R2 and hardware stack are 10-bits wide. The R2
structure is depicted in Fig. 4-2 below.
„
Generates 1024×13 bits on-chip OTP ROM addresses to the relative programming
instruction codes. One program page is 1024 words long.
„
R2 is set as all “0” when under RESET condition.
„
"JMP" instruction allows direct loading of the lower 10 program counter bits. Thus,
"JMP" allows PC to go to any location within a page.
„
"CALL" instruction loads the lower 10 bits of the PC, and then PC+1 is pushed into
the stack. Thus, the subroutine entry address can be located anywhere within a
page.
„
"RET" ("RETL k," "RETI") instruction loads the program counter with the contents
of the top-level stack.
„
"ADD R2, A" allows the contents of ‘A’ to be added to the current PC, and the ninth
and tenth bits of the PC are cleared.
„
"MOV R2, A" allows to load an address from the "A" register to the lower 8 bits of
the PC, and the ninth and tenth bits of the PC are cleared.
„
Any instruction that writes to R2 (e.g., "ADD R2,A," "MOV R2,A," "BC R2,6",⋅etc.)
will cause the ninth and tenth bits (A8~A9) of the PC to be cleared. Thus, the
computed jump is limited to the first 256 locations of a page.
„
All instructions are single instruction cycle (fclk/2 or fclk/4) except for the instruction
that would change the contents of R2. Such instruction will need one more
instruction cycle.
6•
Green Product Specification (V1.0) 01.06.2006
(This specification is subject to change without further notice)
PH86P168AxS/xJ
8-Bit Microcontroller with OTP ROM
Reset Vector
Interrupt Vector
PC (A9 ~ A0)
000H
008H
User Memory
Space
On-chip Program
Memory
Stack Level 1
Stack Level 2
Stack Level 3
Stack Level 4
Stack Level 5
3FFH
Fig. 4-2 R2 (Program Counter) & Stack Organization
4.1.4 Status (R3) Register
Bit 7
GP2
Bit 0 (C):
Bit 6
GP1
Bit 5
GP0
Bit 4
T
Bit 3
P
Bit 2
Z
Bit 1
DC
Bit 0
C
Carry flag
Bit 1 (DC): Auxiliary carry flag
Bit 2 (Z):
Zero flag
Set to "1" if the result of an arithmetic or logic operation is zero
Bit 3 (P):
Power down bit
Set to “1” during power on or by a "WDTC" command
Reset to “0” by a "SLEP" command
Bit 4 (T):
Time-out bit
Set to “1” with the "SLEP" and "WDTC" commands, or during power up
Reset to “0” by WDT time-out
Bit 5~7 (GP0 ~ 2): General-purpose read/write bits
4.1.5 RAM Select (R4) Register
Bit 7
Bit 6
Bit 5
Bit 4
Not used (read only)
Bit 3
Bit 2
Bit 1
Bit 0
Select Registers
Z flag of R3 will set to “1” when R4 content is equal to “3F.” When R4=R4+1, R4
content will function as R0. See the data memory configuration shown in Section 4.1.
Bits 0~5:
are used to select registers (Address: 00~06, 0F~3F) in indirect address
mode
Bits 6~7:
are not used (read only)
Bits 6~7 are set to “1” all the time
Green Product Specification (V1.0) 01.06.2006
(This specification is subject to change without further notice)
•7
PH86P168AxS/xJ
8-Bit Microcontroller with OTP ROM
4.1.6 Port 5 ~ Port 6 (R5 ~ R6) Registers
R5 and R6 are I/O registers. Only the lower 4 bits of R5 are available.
4.1.7 Interrupt Status (RF) Register
Bit 7
-
Bit 6
Bit 5
-
Bit 4
-
Bit 3
-
-
Bit 2
EXIF
Bit 1
ICIF
Bit 0
TCIF
RF can be cleared by instruction but cannot be set
IOCF is the interrupt mask register (see Section 4.2.9)
NOTE
The result of reading RF is the "logic AND" of RF and IOCF.
0: disable interrupt request
1: enable interrupt request
Bit 0 (TCIF): TCC overflow interrupt flag
Set when TCC overflows. Reset by software.
Bit 1 (ICIF): Port 6 input status change interrupt flag
Set when Port 6 input changes. Reset by software.
Bit 2 (EXIF): External interrupt flag
Set by falling edge on /INT pin. Reset by software.
Bits 3 ~ 7:
Not used
4.1.8 General Purpose (R10 ~ R3F) Registers
R10 ~ R3F are all 8-bit general-purpose registers
4.2 Special Purpose Registers
4.2.1 Accumulator (A) Register
8•
„
Internal data transfer, or instruction operand holding
„
It cannot be addressed
Green Product Specification (V1.0) 01.06.2006
(This specification is subject to change without further notice)
PH86P168AxS/xJ
8-Bit Microcontroller with OTP ROM
4.2.2 Control (CONT ) Register
Bit 7
-
Bit 6
Bit 5
Bit 4
/INT
TS
TE
Bit 3
PAB
Bit 2
Bit 1
Bit 0
PSR2
PSR1
PSR0
CONT register is both readable and writable
Bit 0 ~ Bit 2 (PSR0 ~ PSR2): TCC/WDT prescaler bits
PSR2
PSR1
PSR0
TCC Rate
WDT Rate
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1:2
1:4
1:8
1:16
1:32
1:64
1:128
1:256
1:1
1:2
1:4
1:8
1:16
1:32
1:64
1:128
Bit 3 (PAB): Prescaler assignment bit
0: TCC
1: WDT
Bit 4 (TE):
TCC signal edge
0: increment if the transition from low to high takes place on TCC pin
1: increment if the transition from high to low takes place on TCC pin
Bit 5 (TS):
TCC signal source
0: internal instruction cycle clock
1: transition on TCC pin
Bit 6 (/INT): Interrupt enable flag
0: masked by DISI or hardware interrupt
1: enabled by ENI/RETI instructions
Bit 7:
Not used
4.2.3 I/O Port Control (IOC5 ~ IOC6) Registers
„
0: defines the relative I/O pin as output
1: put the relative I/O pin into high impedance
„
Only the lower 4 bits of IOC5 can be defined.
„
IOC5 and IOC6 registers are both readable and writable
4.2.4 Prescaler Counter (IOCA ) Register
„
IOCA register is readable
„
The value of IOCA is equal to the contents of Prescaler counter
„
Down counter
Green Product Specification (V1.0) 01.06.2006
(This specification is subject to change without further notice)
•9
PH86P168AxS/xJ
8-Bit Microcontroller with OTP ROM
4.2.5 Pull-Down Control (IOCB) Register
Bit 7
/PD7
Bit 6
/PD6
Bit 5
/PD5
Bit 4
Bit 3
/PD4
-
Bit 2
/PD2
Bit 1
/PD1
Bit 0
/PD0
IOCB Register is both readable and writable.
Bit 0 (/PD0): Control bit is used to enable the P50 pin pull-down
0: Enable internal pull-down
1: Disable internal pull-down
Bit 1 (/PD1): Control bit is used to enable the P51 pin pull-down
Bit 2 (/PD2): Control bit is used to enable the P52 pin pull-down
Bit 3:
Not used
Bit 4 (/PD4): Control bit is used to enable the P60 pin pull-down
Bit 5 (/PD5): Control bit is used to enable the P61 pin pull-down
Bit 6 (/PD6): Control bit is used to enable the P62 pin pull-down
Bit 7 (/PD7): Control bit is used to enable the P63 pin pull-down
4.2.6 Open-Drain Control (IOCC ) Register
Bit 7
OD7
Bit 6
OD6
Bit 5
OD5
Bit 4
Bit 3
OD4
OD3
Bit 2
OD2
Bit 1
OD1
Bit 0
OD0
IOCC Register is both readable and writable.
Bit 0 (OD0): Control bit is used to enable the P60 pin open-drain
0: Disable open-drain output
1: Enable open-drain output
Bit 1 (OD1): Control bit is used to enable the P61 pin open-drain
Bit 2 (OD2): Control bit is used to enable the P62 pin open-drain
Bit 3 (OD3): Control bit is used to enable the P63 pin open-drain
Bit 4 (OD4): Control bit is used to enable the P64 pin open-drain
Bit 5 (OD5): Control bit is used to enable the P65 pin open-drain
Bit 6 (OD6): Control bit is used to enable the P66 pin open-drain
Bit 7 (OD7): Control bit is used to enable the P67 pin open-drain
10 •
Green Product Specification (V1.0) 01.06.2006
(This specification is subject to change without further notice)
PH86P168AxS/xJ
8-Bit Microcontroller with OTP ROM
4.2.7 Pull-High Control (IOCD) Register
Bit 7
/PH7
Bit 6
/PH6
Bit 5
/PH5
Bit 4
/PH4
Bit 3
/PH3
Bit 2
/PH2
Bit 1
/PH1
Bit 0
/PH0
IOCD Register is both readable and writable
Bit 0 (/PH0): Control bit is used to enable the P60 pin pull-high
0: Enable internal pull-high
1: Disable internal pull-high
Bit 1 (/PH1): Control bit is used to enable the P61 pin pull-high
Bit 2 (/PH2): Control bit is used to enable the P62 pin pull-high
Bit 3 (/PH3): Control bit is used to enable the P63 pin pull-high
Bit 4 (/PH4): Control bit is used to enable the P64 pin pull-high
Bit 5 (/PH5): Control bit is used to enable the P65 pin pull-high
Bit 6 (/PH6): Control bit is used to enable the P66 pin pull-high
Bit 7 (/PH7): Control bit is used to enable the P67 pin pull-high
4.2.8 WDT Control (IOCE) Register
Bit 7
WDTE
Bits 0~3, 5:
Bit 6
EIS
Bit 5
-
Bit 4
Bit 3
ROC
Bit 2
-
Bit 1
-
-
Bit 0
-
Not used
Bit 4 (ROC): ROC is used for the R-option
Setting the ROC to "1" will enable the status of R-option pins (P50∼P51)
that are read by the controller. Clearing the ROC will disable the
R-option function. If the R-option function is selected, you must connect
the P51 pin or/and P50 pin to VSS with a 430KΩ external resistor (Rex).
If the Rex is connected or disconnected, the status of P50 (P51) is read
as "0" or "1" respectively Refer to Fig. 4-6 under Section 4.4.
Bit 6 (EIS):
Control bit is used to define the P60 (/INT) pin function
0: P60, bi-directional I/O pin
1: /INT, external interrupt pin. In this case, the I/O control bit of P60
(bit 0 of IOC6) must be set to "1"
EIS is both readable and writable.
When EIS is "0," the path of /INT is masked. When EIS is "1,” the status
of /INT pin can also be read by way of reading Port 6 (R6). Refer to Fig.
4-5(a) under Section 4.4.
Bit 7 (WDTE): Control bit is used to enable Watchdog timer
0: Disable WDT
1: Enable WDT
WDTE is both readable and writable
Green Product Specification (V1.0) 01.06.2006
(This specification is subject to change without further notice)
• 11
PH86P168AxS/xJ
8-Bit Microcontroller with OTP ROM
4.2.9 IOCF (Interrupt Mask Register)
Bit 7
-
Bit 6
-
Bit 5
Bit 4
-
Bit 3
-
-
Bit 2
EXIE
Bit 1
ICIE
Bit 0
TCIE
Individual interrupt is enabled by setting its associated control bit in the IOCF to "1."
Global interrupt is enabled by the ENI instruction and is disabled by the DISI instruction.
Refer to Fig. 4-8 under Section 4.6.
IOCF register is both readable and writable.
Bit 0 (TCIE): TCIF interrupt enable bit
0: disable TCIF interrupt
1: enable TCIF interrupt
Bit 1 (ICIE): ICIF interrupt enable bit
0: disable ICIF interrupt
1: enable ICIF interrupt
Bit 2 (EXIE): EXIF interrupt enable bit
0: disable EXIF interrupt
1: enable EXIF interrupt
Bits 3~7:
Not used.
4.3 TCC/WDT & Prescaler
An 8-bit counter available as prescaler for the TCC or WDT. The prescaler is available
for either the TCC or WDT only at any given time, and the PAB bit of the CONT register
is used to determine the prescaler assignment. The PSR0~PSR2 bits determine the
ratio. The prescaler is cleared each time the instruction is written to TCC under TCC
mode. The WDT and prescaler, when assigned to WDT mode, are cleared by the
“WDTC” or “SLEP” instructions. Fig. 4-3 below, depicts the circuit diagram of
TCC/WDT.
„
12 •
R1 (TCC) is an 8-bit timer/counter. The clock source of TCC can be internal or
external clock input (edge selectable from TCC pin). If TCC signal source is from
internal clock, TCC will increase by 1 at every instruction cycle (without prescaler).
Referring to Fig. 4-3 below, CLK=Fosc/2 or CLK=Fosc/4 application is determined
by the CODE Option bit CLK status. CLK=Fosc/2 is used when CLK bit is "0," and
CLK=Fosc/4 is used when CLK bit is "1." If TCC signal source comes from external
clock input, TCC is increased by 1 at every falling edge or rising edge of TCC pin.
Green Product Specification (V1.0) 01.06.2006
(This specification is subject to change without further notice)
PH86P168AxS/xJ
8-Bit Microcontroller with OTP ROM
The watchdog timer is a free running on-chip RC oscillator. The WDT will keep on
running even when the oscillator driver has been turned off (i.e., in sleep mode).
During normal operation or sleep mode, a WDT time-out (if enabled) will cause the
device to reset. The WDT can be enabled or disabled any time during normal
mode by software programming. Refer to WDTE bit of IOCE register. Without
prescaler, the WDT time-out period is approximately 18 ms1 (default).
„
Data Bus
CLK(=Fosc/2 or Fosc/4)
0
TCC
Pin
1
1
M
U
X
0
TE
TS
0
WDT
1
WTE
(in IOCE)
M
U
X
SYNC
2 cycles
TCC (R1)
TCC overflow interrupt
PAB
M
U
X
8-bit Counter
PAB
8-to-1 MUX
M
U
X
IOCA
PAB
PSR0~PSR2
0
Initial
value
1
MUX
PAB
WDT time-out
Fig. 4-3 TCC and WDT Block Diagram
4.4 I/O Ports
The I/O registers, both Port 5 and Port 6, are bi-directional tri-state I/O ports. Port 6 can
be set as pull-high internally by software. Furthermore, Port 6 can also be set as
open-drain output by software and supports input status change interrupt (or wake-up)
function. P50 ~ P52 and P60 ~ P63 pins can be pulled down by software. Each I/O pin
can be defined as "input" or "output" pin by the I/O control register (IOC5 ~ IOC6). P50
~ P51 are the R-option pins which are enabled by setting the ROC bit in the IOCE
register to “1.” When the R-option function is used, it is recommended that P50 ~ P51
are used as output pins. When R-option is in enabled state, P50 ~ P51 must be
programmed as input pins. Under R-option mode, the current/power consumption by
Rex should be taken into the consideration to promote energy conservation.
The I/O registers and I/O control registers are both readable and writable. The I/O
interface circuits for Port 5 and Port 6 are depicted in Figures 4-4, 4-5(a), 4-5(b), and
4-6 shown below.
1
Vdd = 5V, set up time period = 16.8ms ± 30%
Vdd = 3V, set up time period = 18ms ± 30%
Green Product Specification (V1.0) 01.06.2006
(This specification is subject to change without further notice)
• 13
PH86P168AxS/xJ
8-Bit Microcontroller with OTP ROM
PCRD
P
R
Q
_
Q
PORT
C
L
D
P
R
Q
_
Q
C
L
PCW R
CLK
IO D
D
PDW R
CLK
PDRD
0
1
M
U
X
NOTE: Pull-down is not shown in the figure
Fig. 4-4(a) I/O Port and I/O Control Register Port 5 Circuit Diagram
PC R D
Q
_
Q
P
R D
C L K
C
L
Q
_
Q
P
R D
C L K
C
L
P 6 0 /I N T
PO R T
B it 6 o f I O C E
P
R
C L K
C
L
D
0
Q
1
_
Q
PC W R
IO D
PD W R
M
U
X
PD R D
P
R
C L K
C
L
D
T 10
Q
_
Q
IN T
NOTE: Pull-high/down and open-drain are not shown in the figure
Fig. 4-5(b) I/O Port and I/O Control Register P60 (/INT) Circuit Diagram
14 •
Green Product Specification (V1.0) 01.06.2006
(This specification is subject to change without further notice)
PH86P168AxS/xJ
8-Bit Microcontroller with OTP ROM
PCRD
P61~P67
PORT
0
1
Q
_
Q
P
R D
CLK
C
L
Q
_
Q
P
R D
CLK
C
L
PCWR
IOD
PDWR
M
U
X
TIN
PDRD
P
R
CLK
C
L
D
Q
_
Q
NOTE: Pull-high/down and open-drain are not shown in the figure
Fig. 4-5(c) I/O Port and I/O Control Register for P61~P67 Circuit Diagram
IOCE.1
D
P
R
Q
Interrupt
CLK
_
C Q
L
RE.1
ENI Instruction
P
D R Q
T10
T11
CLK
_
C
L Q
P
Q R
D
CLK
_
Q C
L
T17
DISI Instruction
/SLEP
Interrupt
(Wake-up from SLEEP)
Next Instruction
(Wake-up from SLEEP)
Fig. 4-5(d) Block Diagram on I/O Port 6 with Input Change Interrupt/Wake-up
Green Product Specification (V1.0) 01.06.2006
(This specification is subject to change without further notice)
• 15
PH86P168AxS/xJ
8-Bit Microcontroller with OTP ROM
4.4.1 Port 6 Input Change Wake-up/Interrupt Function Usage
(I) Wake-up from Port 6 Input Status Change
(II) Port 6 Input Status Change Interrupt
(a) Before SLEEP
1. Read I/O Port 6 (MOV R6,R6)
1. Disable WDT* (using very carefully)
2. Execute "ENI"
2. Read I/O Port 6 (MOV R6,R6)
3. Enable interrupt (Set IOCF.1)
3. Execute "ENI" or "DISI"
4. IF Port 6 change (interrupt)
→ Interrupt vector (008H)
4. Enable interrupt (Set IOCF.1)
5. Execute "SLEP" instruction
(b) After Wake-up
1. IF "ENI" → Interrupt vector (008H)
2. IF "DISI" → Next instruction
* Software disables WDT (watchdog timer) but hardware must be enabled before applying the Port 6 Change
Wake-Up function (CODE Option Register and Bit 11 (ENWDTB-) set to “1”).
PCRD
VCC
ROC
Q
P
R
Q
C
L
Q
P
R
Q
C
L
Weakly
Pull-up
PORT
D
CLK
PCWR
IOD
D
PDWR
PDRD
0
Rex*
1
M
U
X
*The Rex is a 430K ohm external
resistor
Fig. 4-6 I/O Port with R-option (P50,P51) Circuit Diagram
16 •
Green Product Specification (V1.0) 01.06.2006
(This specification is subject to change without further notice)
PH86P168AxS/xJ
8-Bit Microcontroller with OTP ROM
4.5 RESET and Wake-up
A RESET is initiated by one of the following events:
1. Power on reset
2. /RESET pin input "low," or
3. WDT time-out (if enabled)
The device is kept in a RESET condition for a period of approximately 18ms2 (one
oscillator start-up timer period) after the reset is detected. Once the RESET occurs, the
following functions are performed (see Fig. 4-7 under Section 4.5.2.1)
„
The oscillator is running, or will be started.
„
The Program Counter (R2) is set to all "0."
„
All I/O port pins are configured as input mode (high-impedance state).
„
The Watchdog timer and prescaler are cleared.
„
When power is switched on, the upper 3 bits of R3 are cleared.
„
All the CONT register bits are set to "1" except for the Bit 6 (INT flag).
„
All the IOCA register bits are set to "1."
„
All the IOCB register bits are set to "1."
„
The IOCC register is cleared.
„
All the IOCD register bits are set to "1."
„
Bit 7 of the IOCE register is set to "1," and Bits 4 and 6 are cleared.
„
Bits 0 ~2 of RF and bits 0 ~2 of IOCF registers are cleared.
The sleep (power down) mode is asserted by executing the “SLEP” instruction. While
entering sleep mode, WDT (if enabled) is cleared but keeps on running. The controller
can be awakened by:
1. External reset input on /RESET pin,
2. WDT time-out (if enabled), or
3. Port 6 input status changes (if enabled).
The first two cases will cause the PH86P168AxS/xJ to reset. The T and P flags of R3
can be used to determine the source of the reset (wake-up). The last case is
considered the continuation of the program execution. The global interrupt ("ENI" or
"DISI" being executed) decides whether or not the controller branches to the interrupt
vector following wake-up. If ENI is executed before SLEP, the instruction will begin to
execute from the address 008H after wake-up. If DISI is executed before SLEP, the
operation will restart from the succeeding instruction right next to SLEP after wake-up.
2
Vdd = 5V, set up time period = 16.8ms ± 30%
Vdd = 3V, set up time period = 18ms ± 30%
Green Product Specification (V1.0) 01.06.2006
(This specification is subject to change without further notice)
• 17
PH86P168AxS/xJ
8-Bit Microcontroller with OTP ROM
Only one of Cases 2 and 3 can be enabled before entering into sleep mode, i.e.,
[a] if Port 6 Input Status Change Interrupt is enabled before SLEP, WDT must be
disabled by software. However, the WDT bit in the option register remains enabled.
Hence, the PH86P168AxS/xJ can be awakened only by either Case 1 or 3.
[b] if WDT is enabled before SLEP, Port 6 Input Status Change Interrupt must be
disabled. Hence, the PH86P168AxS/xJ can only be awakened by either Case 1 or
2. Refer to the section (Section 4.6) on Interrupt.
If Port 6 Input Status Change Interrupt is used to wake-up the PH86P168AxS/xJ (Case
[a] above), the following instructions must be executed before SLEP:
MOV A, @xx000110b
CONTW
CLR R1
MOV A, @xxxx1110b
CONTW
WDTC
MOV A, @0xxxxxxxb
IOW RE
MOV R6, R6
MOV A, @00000x1xb
IOW RF
ENI (or DISI)
SLEP
; Select internal TCC clock
; Clear TCC and prescaler
; Select WDT prescaler
; Clear WDT and prescaler
; Disable WDT
; Read Port 6
; Enable Port 6 input change interrupt
; Enable (or disable) global interrupt
; Sleep
NOP
One problem you should be aware of is that after waking up from the sleep mode, WDT
is enabled automatically. The WDT operation (being enabled or disabled) should be
handled appropriately by software after waking up from the sleep mode.
18 •
Green Product Specification (V1.0) 01.06.2006
(This specification is subject to change without further notice)
PH86P168AxS/xJ
8-Bit Microcontroller with OTP ROM
4.5.1 Summary of Initialized Values for Registers
Legend:
U = Unknown or don’t care
Address
Name
P = Previous value before reset
Reset Type
Bit 7
Bit 6
Bit 5
X
X
X
Bit Name
N/A
N/A
N/A
0x00
0x01
0x02
0x03
0x04
0x05
IOC5
IOC6
CONT
R0(IAR)
R1(TCC)
R2(PC)
R3(SR)
R4(RSR)
P5
t = Check with Section 4.5.2.1
Bit 4 Bit 3
X
Bit 2
Bit 1
Bit 0
C53
C52
C51
C50
Power-On
U
U
U
U
1
1
1
1
/RESET and WDT
Wake-Up from Pin
Change
Bit Name
U
U
U
U
1
1
1
1
U
U
U
U
P
P
P
P
C67
C66
C65
C64
C63
C62
C61
C60
Power-On
1
1
1
1
1
1
1
1
/RESET and WDT
Wake-Up from Pin
Change
Bit Name
1
1
1
1
1
1
1
1
P
P
P
P
P
P
P
P
X
/INT
TS
TE
PAB
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
P
P
P
P
P
P
P
P
Power-On
/RESET and WDT
Wake-Up from Pin
Change
Bit Name
PSR2 PSR1 PSR0
-
-
-
-
-
-
-
-
Power-On
/RESET and WDT
Wake-Up from Pin
Change
Bit Name
U
P
U
P
U
P
U
P
U
P
U
P
U
P
U
P
P
P
P
P
P
P
P
P
-
-
-
-
-
-
-
-
Power-On
/RESET and WDT
Wake-Up from Pin
Change
Bit Name
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
P
P
P
P
P
P
P
P
Power-On
/RESET and WDT
Wake-Up from Pin
Change
Bit Name
-
-
-
-
-
-
-
-
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
*0/P
*0/P
*0/P
*0/P
*1/P
*0/P
*0/P
*0/P
GP2
GP1
GP0
T
P
Z
DC
C
0
0
0
0
0
0
1
t
1
t
U
P
U
P
U
P
P
P
P
t
t
P
P
P
Power-On
/RESET and WDT
Wake-Up from Pin
Change
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin
Change
Bit Name
-
-
-
-
-
-
-
-
1
1
1
1
U
P
U
P
U
P
U
P
U
P
U
P
1
1
P
P
P
P
P
P
X
X
X
X
P53
P52
P51
P50
Power-On
0
0
0
0
U
U
U
U
/RESET and WDT
0
0
0
0
P
P
P
P
Wake-Up from Pin
0
0
0
0
P
P
P
P
Change
* Jump to address 0x08, or execute the instruction following the “SLEP” instruction.
Green Product Specification (V1.0) 01.06.2006
(This specification is subject to change without further notice)
• 19
PH86P168AxS/xJ
8-Bit Microcontroller with OTP ROM
Address
0x06
0x0F
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
Name
P6
RF(ISR)
IOCA
IOCB
IOCC
IOCD
IOCE
IOCF
0x10~0x2F R10~R2F
20 •
Reset Type
Bit 7
Bit 6
Bit 5
Bit 4 Bit 3
Bit 2
Bit 1
Bit 0
Bit Name
P67
P66
P65
P64
P63
P62
P61
P60
Power-On
U
U
U
U
U
U
U
U
/RESET and WDT
Wake-Up from Pin
Change
Bit Name
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
X
X
X
X
X
EXIF
ICIF
TCIF
Power-On
U
U
U
U
U
0
0
0
/RESET and WDT
Wake-Up from Pin
Change
Bit Name
U
U
U
U
U
0
0
0
U
U
U
U
U
P
P
P
-
-
-
-
-
-
-
-
Power-On
1
1
1
1
1
1
1
1
/RESET and WDT
Wake-Up from Pin
Change
Bit Name
1
1
1
1
1
1
1
1
P
P
P
P
P
P
P
P
/PD7
/PD6
/PD5
/PD4
X
/PD2
/PD1
/PD0
Power-On
1
1
1
1
U
1
1
1
/RESET and WDT
Wake-Up from Pin
Change
Bit Name
1
1
1
1
U
1
1
1
P
P
P
P
U
P
P
P
OD7
OD6
OD5
OD4
OD3
OD2
OD1
OD0
Power-On
0
0
0
0
0
0
0
0
/RESET and WDT
Wake-Up from Pin
Change
Bit Name
0
0
0
0
0
0
0
0
P
P
P
P
P
P
P
P
/PH7
/PH6
/PH5
/PH4
/PH3
/PH2
/PH1
/PH0
Power-On
1
1
1
1
1
1
1
1
/RESET and WDT
Wake-Up from Pin
Change
Bit Name
1
1
1
1
1
1
1
1
P
P
P
P
P
P
P
P
WDTE
EIS
X
ROC
X
X
X
X
Power-On
1
0
U
0
U
U
U
U
/RESET and WDT
Wake-Up from Pin
Change
Bit Name
1
0
U
0
U
U
U
U
1
P
U
P
U
U
U
U
X
X
X
X
X
EXIE
ICIE
TCIE
Power-On
U
U
U
U
U
0
0
0
/RESET and WDT
Wake-Up from Pin
Change
Bit Name
U
U
U
U
U
0
0
0
U
U
U
U
U
P
P
P
-
-
-
-
-
-
-
-
Power-On
U
U
U
U
U
U
U
U
/RESET and WDT
Wake-Up from Pin
Change
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
Green Product Specification (V1.0) 01.06.2006
(This specification is subject to change without further notice)
PH86P168AxS/xJ
8-Bit Microcontroller with OTP ROM
4.5.2 The Status of RST, T, and P of STATUS Register
A RESET condition is initiated by the following events:
1. A power-on condition
2. A high-low-high pulse on /RESET pin
3. Watchdog timer time-out
4.5.2.1 RST, T and P after RESET Values
The values of T (Time-out) and P (Power-down) as listed below are used to verify how
the processor wakes up.
Reset Type
T
Power on
/RESET during Operating mode
/RESET wake-up during SLEEP mode
WDT during Operating mode
WDT wake-up during SLEEP mode
Wake-Up on pin change during SLEEP mode
P
1
1
*P
*P
1
0
0
1
0
*P
0
0
*P = Previous status before reset
4.5.2.2 Event Affecting T and P Status
The table below shows the events that may affect the status of T (Time-out) and
P (Power-down).
Event
T
P
Power on
1
1
WDTC instruction
1
1
WDT time-out
0
*P
SLEP instruction
1
0
Wake-Up on pin change during SLEEP mode
1
0
*P = Previous status before reset
VDD
D
CLK
Oscillator
Q
CLK
CLR
Power-on
Reset
Voltage
Detector
WDTE
WDT
WDT Timeout
Setup Time
RESET
/RESET
Fig. 4-7 Controller Reset Block Diagram
Green Product Specification (V1.0) 01.06.2006
(This specification is subject to change without further notice)
• 21
PH86P168AxS/xJ
8-Bit Microcontroller with OTP ROM
4.6 Interrupt
The PH86P168AxS/xJ has three falling-edge interrupts as listed below:
1. TCC overflow interrupt
2. Port 6 Input Status Change Interrupt
3. External interrupt [(P60, /INT) pin].
Before the Port 6 Input Status Change Interrupt is enabled, reading Port 6 (e.g.,
"MOV R6,R6") is necessary. Each Port 6 pin of will have this feature when its status
changes. Any pin configured as output or P60 pin configured as “/INT,” is excluded
from this function. The Port 6 Input Status Change Interrupt can wake up the
PH86P168AxS/xJ from the sleep mode if Port 6 is enabled prior to going into the sleep
mode by executing SLEP instruction. When the chip wakes-up, the controller will
continue to execute the succeeding address if the global interrupt is disabled or
branches to the interrupt vector 008H if the global interrupt is enabled.
RF is the interrupt status register that records the interrupt requests in the relative
flags/bits. IOCF is an interrupt mask register. The global interrupt is enabled by the
ENI instruction and is disabled by the DISI instruction. When one of the enabled
interrupts occurs, the next instruction will be fetched from address 008H. Once in the
interrupt service routine, the source of an interrupt can be determined by polling the flag
bits in RF. The interrupt flag bit must be cleared by instructions before leaving the
interrupt service routine and before interrupts are enabled to avoid recursive interrupts.
The flag (except ICIF bit) in the Interrupt Status Register (RF) is set regardless of the
status of its mask bit or ENI execution. Note that the outcome of RF will be the logic
AND of RF and IOCF (refer to Fig. 4-7 above). The RETI instruction ends the interrupt
routine and enables the global interrupt (execution of ENI).
When an interrupt is generated by the INT instruction (enabled), the next instruction will
be fetched from address 001H.
VCC
D
/IRQn
P
R
CLK
RF
C
L
Q
IRQn
INT
_
Q
RFRD
IRQm
ENI/DISI
Q
IOCF
_
Q
P
R
C
L
IOD
D
CLK
IOCFWR
/RESET
IOCFRD
RFWR
Fig. 4-8 Interrupt Input Circuit
22 •
Green Product Specification (V1.0) 01.06.2006
(This specification is subject to change without further notice)
PH86P168AxS/xJ
8-Bit Microcontroller with OTP ROM
4.7 Oscillator
4.7.1 Oscillator Modes
The PH86P168AxS/xJ can be operated in three different oscillator modes, namely,
External RC oscillator mode (ERC), High XTAL oscillator mode (HXT), and Low XTAL
oscillator mode (LXT). User can select one of them by programming OSC, HLF, and
HLP in the CODE option register. The following table depicts how these three modes
are defined.
4.7.1.1 Oscillator Modes Defined by OSC, HLF, and HLP
Mode
OSC
HLF
ERC (External RC oscillator mode)
0
1
1
X
1
1
0
HXT (High XTAL oscillator mode)
1
LXT (Low XTAL oscillator mode)
HLP
2
2
X
2
X
0
1
The transient point of system frequency between HXT and LXY is around 400 kHz
2
X = Don’t care
4.7.1.2 The Summary of Maximum Operating Speeds
The maximum operational frequency of crystal/resonator under different VDDs is as
listed below.
Condition
Two cycles with two clocks
VDD
Fxt Max Freq.
3.0
8.0 MHz
5.0
20.0 MHz
4.7.2 Crystal Oscillator/Ceramic Resonators (XTAL)
PH86P168AxS/xJ can be driven by an external clock signal through the OSCI pin as
illustrated in the following figure.
OSCI
Ext. Clock
OSCO
PH86P168AxS/xJ
Fig. 4-9 External Clock Input Circuit
Green Product Specification (V1.0) 01.06.2006
(This specification is subject to change without further notice)
• 23
PH86P168AxS/xJ
8-Bit Microcontroller with OTP ROM
In most applications, Pin OSCI and Pin OSCO can connected with a crystal or ceramic
resonator to generate oscillation. The figure below depicts such circuit. The same
thing is applicable whether it is in the HXT mode or LXT mode. Table below provides
the recommended values of C1 and C2. Since each resonator has its own attribute,
you should refer to its specification for the appropriate values of C1 and C2. RS, a
serial resistor, may be necessary for AT strip cut crystal or low frequency mode.
C1
OSCI
PH86P168AxS/xJ
XTAL
OSCO
RS
C2
Fig. 4-10 Crystal/Resonator Circuit
4.7.2.1 Capacitor Selection Guide for Crystal Oscillator or Ceramic
Resonator
The table below provides the recommended values of C1 and C2. Since each
resonator has its own attribute, you should refer to its specification for the appropriate
values of C1 and C2. RS, a serial resistor, may be necessary for AT strip cut crystal or
low frequency mode.
Oscillator Type
Frequency Mode
Frequency
C1(pF)*
C2(pF)*
Ceramic Resonators
HXT
455 kHz
2.0 MHz
4.0 MHz
100~150
20~40
10~30
100~150
20~40
10~30
LXT
32.768kHz
100KHz
200KHz
25
25
25
15
25
25
HXT
455KHz
1.0MHz
2.0MHz
4.0MHz
20~40
15~30
15
15
20~150
15~30
15
15
Crystal Oscillator
* The values shown for capacitors C1 & C2 are for reference only.
24 •
Green Product Specification (V1.0) 01.06.2006
(This specification is subject to change without further notice)
PH86P168AxS/xJ
8-Bit Microcontroller with OTP ROM
4.7.3 External RC Oscillator Mode
For some applications that do not need a very precise timing calculation, the RC
oscillator (Fig. 4-11 below) offers a lot of cost savings. Nevertheless, it should be noted
that the frequency of the RC oscillator is influenced by the supply voltage, the values of
the resistor (Rext), the capacitor (Cext), and even by the operation temperature.
Moreover, the frequency also changes slightly from one chip to another due to the
manufacturing process variation.
In order to maintain a stable system frequency, the values of the Cext should not be
less than 20pF, and that the value of Rext should not be greater than 1 MΩ. If they
cannot be kept in this range, the frequency is easily affected by noise, humidity, and
leakage.
The smaller the Rext in the RC oscillator, the faster its frequency will be. On the
contrary, for very low Rext values, for instance, 1 KΩ, the oscillator will become
unstable because the NMOS cannot accurately discharge the current of the
capacitance.
Based on the above factors, it must be kept in mind that all of the supply voltage, the
operation temperature, the components of the RC oscillator, the package types, the
way the PCB is laid out, will affect the system frequency.
Vcc
Rext
OSCI
Cext
PH86P168AxS/xJ
Fig. 4-11 External RC Oscillator Mode Circuit
Green Product Specification (V1.0) 01.06.2006
(This specification is subject to change without further notice)
• 25
PH86P168AxS/xJ
8-Bit Microcontroller with OTP ROM
4.7.3.1 RC Oscillator Frequencies
Cext
Rext
Average Fosc
5V, 25°C
Average Fosc
3V, 25°C
3.3k
3.92 MHz
3.65 MHz
5.1k
2.67 MHz
2.60 MHz
10k
1.39MHz
1.40 MHz
20 pF
100k
149 KHz
156 KHz
3.3k
1.39 MHz
1.33 MHz
5.1k
10k
940 KHz
480 KHz
920 KHz
475 KHz
100k
52 KHz
50 KHz
3.3k
595 KHz
560 KHz
5.1k
400 KHz
390 KHz
10k
200 KHz
200 KHz
100k
21 KHz
20 KHz
100 pF
300 pF
NOTE: 1. Values derived and measured from DIP packages
2. Values are for design references only
3. The frequency drift is about ±30%
4.8 CODE Option Register
The PH86P168AxS/xJ has a CODE option word that is not a part of the normal
program memory. The option bits cannot be accessed during normal program
execution.
The following is the Code Option Register and Customer ID Register arrangement
distribution:
Word 0
Word 1
Bit12~Bit0
Bit12~Bit0
4.8.1 Code Option Register (Word 0)
WORD 0
Bit12 Bit11 Bit10
-
-
-
Bit9
Bit8
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
-
CLKS
ENWDTB
-
HLF
OSC
HLP
PR2
PR1
PR0
Bit 9~Bit 12: Not used (reserved)
This bit is set to “1” all the time
Bit 8 (CLKS): Instruction period option bit
0: two oscillator periods
1: four oscillator periods
(Refer to Section 4-12, Instruction Set)
Bit 7 (ENWDTB): Watchdog timer enable bit
0: Enable
1: Disable
26 •
Green Product Specification (V1.0) 01.06.2006
(This specification is subject to change without further notice)
PH86P168AxS/xJ
8-Bit Microcontroller with OTP ROM
Bit 6:
Not used (reserved)
This bit is set to “1” all the time
Green Product Specification (V1.0) 01.06.2006
(This specification is subject to change without further notice)
• 27
PH86P168AxS/xJ
8-Bit Microcontroller with OTP ROM
Bit 5 (HLF):
XTAL frequency selection
0: XTAL2 type (low frequency, 32.768KHz)
1: XTAL1 type (high frequency)
This bit will affect system oscillation only when Bit 4 (OSC) is “1.” When
OSC is”0,” HLF must be “0”.
NOTE
The transient point of system frequency between HXT and LXY is around 400 KHz.
Bit 4 (OSC): Oscillator type selection
0: RC type
1: XTAL type (XTAL1 and XTAL2)
Bit 3 (HLP):
Power selection
0: Low power
1: High power
Bit 2 ~ Bit 0 (PR2 ~ PR0): Protect bits
PR2 ~ PR0 are protect bits that can be set as follows:
PR2
PR1
PR0
Protect
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Disable
4.8.2 Customer ID Register (Word 1)
Bit 12 ~ Bit 0
XXXXXXXXXXXXX
Bit 12 ~ Bit 0: Customer’s ID code
28 •
Green Product Specification (V1.0) 01.06.2006
(This specification is subject to change without further notice)
PH86P168AxS/xJ
8-Bit Microcontroller with OTP ROM
4.9 Power-On Considerations
Any microcontroller is not guaranteed to start to operate properly before the power
supply stays at its steady state.
PH86P168AxS/xJ POR voltage range is 1.2V~1.8V. Under customer application,
when power is OFF, Vdd must drop to below 1.2V and remains OFF for 10µs before
power can be switched ON again. This way, the PH86P168AxS/xJ will reset and works
normally. The extra external reset circuit will work well if Vdd can rise at very fast speed
(50 ms or less). However, under most cases where critical applications are involved,
extra devices are required to assist in solving the power-up problems.
4.10 External Power-On Reset Circuit
The circuit shown below implements an external RC to produce the reset pulse. The
pulse width (time constant) should be kept long enough for Vdd to reach the minimum
operation voltage. This circuit is used when the power supply has a slow rise time.
Because the current leakage from the /RESET pin is about ±5µA, it is recommended
that R should not be greater than 40K. In this way, the /RESET pin voltage is held
below 0.2V. The diode (D) acts as a short circuit at the moment of power down. The
capacitor C will discharge rapidly and fully. Rin, the current-limited resistor, will prevent
high current or ESD (electrostatic discharge) from flowing into /RESET pin.
Vdd
R
/RESET
D
PH86P168AxS/xJ
Rin
C
Fig. 4-12 External Power-Up Reset Circuit
Green Product Specification (V1.0) 01.06.2006
(This specification is subject to change without further notice)
• 29
PH86P168AxS/xJ
8-Bit Microcontroller with OTP ROM
4.11 Residual-Voltage Protection
When battery is replaced, device power (Vdd) is taken off but residual-voltage remains.
The residual-voltage may trips below Vdd minimum, but not to zero. This condition
may cause a poor power-on reset. Figures 4-13 and 4-14 illustrate how to build a
residual-voltage protection circuit.
Vdd
Vdd
33K
PH86P168AxS/xJ
Q1
10K
/RESET
40K
1N4684
Fig. 4-13 Circuit 1 for the Residue Voltage Protection
Vdd
Vdd
R1
PH86P168AxS/xJ
Q1
/RESET
40K
R2
Fig. 4-14 Circuit 2 for the Residue Voltage Protection
30 •
Green Product Specification (V1.0) 01.06.2006
(This specification is subject to change without further notice)
PH86P168AxS/xJ
8-Bit Microcontroller with OTP ROM
4.12
Instruction Set
Each instruction in the instruction set is a 13-bit word divided into an OP code and one
or more operands. Normally, all instructions are executed within one single instruction
cycle (one instruction consists of 2 oscillator periods), unless the program counter is
changed by instruction "MOV R2,A," "ADD R2,A," or by instructions of arithmetic or
logic operation on R2 (e.g., "SUB R2,A," "BS(C) R2,6," "CLR R2," etc.). In this case,
the execution takes two instruction cycles.
If for some reasons, the specification of the instruction cycle is not suitable for certain
applications, try modifying the instruction as follows:
1. Change one instruction cycle to consist of 4 oscillator periods.
2. "JMP,” "CALL," "RET," "RETL," and "RETI," or the conditional skip ("JBS," "JBC,"
"JZ," "JZA," "DJZ," and "DJZA") commands which were tested to be true, are
executed within two instruction cycles. The instructions that are written to the
program counter also take two instruction cycles.
Case (1) is selected by the CODE Option bit, called CLK. One instruction cycle
consists of two oscillator clocks if CLK is low, and four oscillator clocks if CLK is high.
Note that once the 4 oscillator periods within one instruction cycle is selected as in
Case (A), the internal clock source to TCC should be CLK=Fosc/4, instead of Fosc/2 as
indicated in Fig. 4-3 (TCC and WDT Block Diagram) in Section 4.3.
Furthermore, the instruction set has the following features:
1. Every bit of any register can be set, cleared, or tested directly.
2. The I/O register can be regarded as general register. That is, the same instruction
can operate on I/O register.
LEGEND: "R" represents a register designator that specifies which one of the registers (including operational registers
and general purpose registers) is to be utilized by the instruction.
"b" represents a bit field designator that selects the value for the bit which is located in the register "R" and
affects operation.
"k" represents an 8 or 10-bit constant or literal value.
Instruction Binary
0
0
0
0
0
0
0
0
0
0000
0000
0000
0000
0000
0000
0000
0000
0000
Mnemonic
0000
0001
0010
0011
0100
rrrr
0000
0001
0010
0000
0001
0002
0003
0004
000r
0010
0011
0012
NOP
DAA
CONTW
SLEP
WDTC
IOW R
ENI
DISI
RET
0 0000 0001 0011
0013
RETI
0
0
0
0
0014
001r
00rr
0080
CONTR
IOR R
MOV R,A
CLRA
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0001
0001
0001
Hex
0001
0001
01rr
1000
0100
rrrr
rrrr
0000
Green Product Specification (V1.0) 01.06.2006
(This specification is subject to change without further notice)
Operation
No Operation
Decimal Adjust A
A → CONT
0 → WDT, Stop oscillator
0 → WDT
A → IOCR
Enable Interrupt
Disable Interrupt
[Top of Stack] → PC
[Top of Stack] → PC, Enable
Interrupt
CONT → A
IOCR → A
A→R
0→A
Status Affected
None
C
None
T,P
T,P
1
None
None
None
None
None
None
1
None
None
Z
• 31
PH86P168AxS/xJ
8-Bit Microcontroller with OTP ROM
Instruction Binary
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0000
0001
0001
0001
0001
0010
0010
0010
0010
0011
0011
0011
0011
0100
0100
0100
0100
0101
0101
0101
0101
Mnemonic
Status Affected
Z
Z,C,DC
Z,C,DC
Z
Z
Z
Z
Z
Z
Z
Z
Z,C,DC
Z,C,DC
Z
Z
Z
Z
Z
Z
None
None
SUB A,k
INT
PC+1 → [SP], 001H → PC
None
ADD A,k
k+A → A
Z,C,DC
00rr
01rr
01rr
01rr
01rr
02rr
02rr
02rr
02rr
03rr
03rr
03rr
03rr
04rr
04rr
04rr
04rr
05rr
05rr
05rr
05rr
CLR R
SUB A,R
SUB R,A
DECA R
DEC R
OR A,R
OR R,A
AND A,R
AND R,A
XOR A,R
XOR R,A
ADD A,R
ADD R,A
MOV A,R
MOV R,R
COMA R
COM R
INCA R
INC R
DJZA R
DJZ R
0 0110 00rr rrrr
06rr
RRCA R
0 0110 01rr rrrr
06rr
RRC R
0 0110 10rr rrrr
06rr
RLCA R
0 0110 11rr rrrr
06rr
RLC R
0 0111 00rr rrrr
07rr
SWAPA R
0
0
0
0
0
0
0
1
1
1
1
1
1
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
07rr
07rr
07rr
0xxx
0xxx
0xxx
0xxx
1kkk
1kkk
18kk
19kk
1Akk
1Bkk
SWAP R
JZA R
JZ R
BC R,b
BS R,b
JBC R,b
JBS R,b
CALL k
JMP k
MOV A,k
OR A,k
AND A,k
XOR A,k
1 1100 kkkk kkkk
1Ckk
RETL k
1 1101 kkkk kkkk
1Dkk
1 1110 0000 0001
1E01
1 1111 kkkk kkkk
1Fkk
01rr
10rr
11rr
bbrr
bbrr
bbrr
bbrr
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
Operation
0→R
R-A → A
R-A → R
R-1 → A
R-1 → R
A∨R→A
A∨R→R
A&R→A
A&R→R
A⊕R→A
A⊕R→R
A+R→A
A+R→R
R→A
R→R
/R → A
/R → R
R+1 → A
R+1 → R
R-1 → A, skip if zero
R-1 → R, skip if zero
R(n) → A(n-1),
R(0) → C, C → A(7)
R(n) → R(n-1),
R(0) → C, C → R(7)
R(n) → A(n+1),
R(7) → C, C → A(0)
R(n) → R(n+1),
R(7) → C, C → R(0)
R(0-3) → A(4-7),
R(4-7) → A(0-3)
R(0-3) ↔ R(4-7)
R+1 → A, skip if zero
R+1 → R, skip if zero
0 → R(b)
1 → R(b)
if R(b)=0, skip
if R(b)=1, skip
PC+1 → [SP], (Page, k) → PC
(Page, k) → PC
k→A
A∨k→A
A&k→A
A⊕k→A
k → A,
[Top of Stack] → PC
k-A → A
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
0111
0111
0111
100b
101b
110b
111b
00kk
01kk
1000
1001
1010
1011
11rr
00rr
01rr
10rr
11rr
00rr
01rr
10rr
11rr
00rr
01rr
10rr
11rr
00rr
01rr
10rr
11rr
00rr
01rr
10rr
11rr
Hex
C
C
C
C
None
None
None
None
2
None
3
None
None
None
None
None
None
Z
Z
Z
None
Z,C,DC
1
This instruction is applicable to IOC5 ~ IOC6 and IOCB ~ IOCF only
This instruction is not recommended for RF operation
3
This instruction cannot operate under RF
2
32 •
Green Product Specification (V1.0) 01.06.2006
(This specification is subject to change without further notice)
PH86P168AxS/xJ
8-Bit Microcontroller with OTP ROM
4.13 Timing Diagrams
4.13.1
AC Test Input/Output Waveform
2.4
2.0
0.8
TEST POINTS
2.0
0.8
0.4
AC Testing : Input is driven at 2.4V for logic "1",and 0.4V for logic "0".Timing measurements are
made at 2.0V for logic "1",and 0.8V for logic "0".
Fig. 4-15 AC Test Input/Output Waveform Timing Diagram
4.13.2
RESET Timing (CLK = ”0”)
NOP
Instruction 1
Executed
CLK
/RESET
Tdrh
Fig. 4-16 RESET Timing (CLK = ”0”)Timing Diagram
4.13.3
TCC Input Timing (CLKS = ”0”)
Tins
CLK
TCC
Ttcc
Fig. 4-17 TCC Input Timing (CLKS = ”0”) Timing Diagram
Green Product Specification (V1.0) 01.06.2006
(This specification is subject to change without further notice)
• 33
PH86P168AxS/xJ
8-Bit Microcontroller with OTP ROM
5
Absolute Maximum Ratings
„
PH86P168AXS/XJ
Items
6
Rating
Temperature under bias
–40°C to 85°C
Storage temperature
–65°C to 150°C
Working voltage
2.5 to 5.5V
Working frequency
DC to 20MHz
Input voltage
Vss-0.3V to Vdd+0.5V
Output voltage
Vss-0.3V to Vdd+0.5V
Electrical Characteristics
6.1 DC Electrical Characteristic
(Ta=25 °C, VDD=5V±5%, VSS=0V)
Symbol
FXT
ERC
IIL
VIH1
VIL1
VIHT1
VILT1
VIHX1
VILX1
VIH2
VIL2
VIHT2
VILT2
VIHX2
VILX2
Parameter
XTAL: VDD to 3V
XTAL: VDD to 5V
ERC: VDD to 5V
Input Leakage Current for input
pins
Input High Voltage (VDD=5V)
Input Low Voltage (VDD=5V)
Input High Threshold Voltage
(VDD=5V)
Input Low Threshold Voltage
(VDD=5V)
Clock Input High Voltage
(VDD=5V)
Clock Input Low Voltage
(VDD=5V)
Input High Voltage (VDD=3V)
Input Low Voltage (VDD=3V)
Input High Threshold Voltage
(VDD=3V)
Input Low Threshold Voltage
(VDD=3V)
Clock Input High Voltage
(VDD=3V)
Clock Input Low Voltage
(VDD=3V)
Condition
Two cycle with two clocks
Two cycle with two clocks
R: 5.1KΩ, C: 100 pF
Min
DC
DC
F±30%
VIN = VDD, VSS
Ports 5, 6
Ports 5, 6
2.0
/RESET, TCC(Schmitt trigger)
2.0
/RESET, TCC(Schmitt trigger)
OSCI
Typ
Max
Unit
940
8.0
20.0
F±30%
MHz
MHz
kHz
±1
µA
0.8
V
V
V
0.8
3.5
OSCI
Ports 5, 6
Ports 5, 6
1.5
/RESET, TCC(Schmitt trigger)
1.5
/RESET, TCC(Schmitt trigger)
OSCI
V
1.5
V
0.4
V
V
V
0.4
2.1
OSCI
V
V
V
0.9
V
VOH1
Output High Voltage (Ports 5)
IOH = -12.0 mA
2.4
V
VOH1
Output High Voltage (Ports 6)
(Schmitt trigger)
IOH = -12.0 mA
2.4
V
VOL1
Output Low Voltage(Port5)
IOL = 12.0 mA
34 •
0.4
V
Green Product Specification (V1.0) 01.06.2006
(This specification is subject to change without further notice)
PH86P168AxS/xJ
8-Bit Microcontroller with OTP ROM
Symbol
Parameter
VOL1
Output Low Voltage (Ports 6)
(Schmitt trigger)
IPH
Pull-high current
IPD
Pull-down current
ISB1
Power down current
ISB2
Power down current
ICC1
Operating supply current
(VDD=3V)
at two cycles/four clocks
ICC2
Operating supply current
(VDD=3V)
at two cycles/four clocks
ICC3
Operating supply current
(VDD=5.0V)
at two cycles/two clocks
ICC4
Operating supply current
(VDD=5.0V)
at two cycles/four clocks
Condition
Min
Typ
IOL = 12.0 mA
Pull-high active, input pin at
VSS
Pull-down active, input pin at
VDD
All input and I/O pins at VDD,
output pin floating, WDT
disabled
All input and I/O pins at VDD,
output pin floating, WDT
enabled
/RESET= 'High', Fosc=32KHz
(Crystal type,CLKS="0"),
output pin floating, WDT
disabled
/RESET= 'High', Fosc=32KHz
(Crystal type,CLKS="0"),
output pin floating, WDT
enabled
/RESET= 'High', Fosc=4MHz
(Crystal type, CLKS="0"),
output pin floating, WDT
enabled
/RESET= 'High', Fosc=10MHz
(Crystal type, CLKS="0"),
output pin floating, WDT
enabled
Max
Unit
0.4
V
–50
–70
–240
µA
25
50
120
µA
1
2
µA
15
µA
20
30
µA
25
35
µA
2.0
mA
4.0
mA
Typ
Max
Unit
50
55
%
15
6.2 AC Electrical Characteristics
(Ta=25 °C, VDD=5V±5%, VSS=0V)
Symbol
Parameter
Conditions
Min
Dclk
Input CLK duty cycle
45
Tins
Instruction cycle time
(CLKS="0")
Ttcc
TCC input period
(Tins+20)/N*
Tdrh
Device reset hold time
11.8
Trst
/RESET pulse width
Ta = 25°C
2000
Twdt
Watchdog timer period
Ta = 25°C
11.8
Tset
Input pin setup time
0
ns
Thold
Input pin hold time
20
ns
Tdelay
Output pin delay time
50
ns
Crystal type
100
DC
ns
RC type
500
DC
ns
Cload=20pF
ns
16.8
21.8
ms
ns
16.8
21.8
ms
*N = selected prescaler ratio
Green Product Specification (V1.0) 01.06.2006
(This specification is subject to change without further notice)
• 35
PH86P168AxS/xJ
8-Bit Microcontroller with OTP ROM
6.3 Device Characteristics
The graphs provided in the following pages were derived based on a limited number of
samples and are shown herein for reference purposes only and are not guaranteed for
its accuracy. In some graphs, the data may be out of the specified warranted operating
range.
6.3.1 Port 6 Vih/Vil vs. VDD (Input Pin with Schmitt Inverter)
Vih/Vil (Input Pins with Schmitt Inverter)
2.5
Vih/Vil (Volt)
2
Vih max (-40℃ to 85℃)
Vih typ 25℃
Vih min (-40℃ to 85℃)
1.5
1
Vil max (-40℃ to 85℃)
0.5
Vil typ 25℃
Vil min (-40℃ to 85℃)
0
2.5
3
3.5
4
4.5
5
5.5
VDD (Volt)
Fig. 6-1 Graph on Port 6 Vih/Vil vs. VDD
6.3.2 Port 5 Input Threshold Voltage (Vth) vs. VDD
Vth (Input Threshold Voltage) of I/O pins
2
Max(-40℃ to 85℃)
Vth (Volt)
1.5
Typ 25℃
1
Min(-40℃ to 85℃)
0.5
0
2.5
3
3.5
4
4.5
5
5.5
VDD (Volt)
Fig. 6-2 Graph on Port 5 Input Threshold Voltage (Vth) vs. VDD
36 •
Green Product Specification (V1.0) 01.06.2006
(This specification is subject to change without further notice)
PH86P168AxS/xJ
8-Bit Microcontroller with OTP ROM
6.3.3 Ports 5 & Port 6 Voh vs. Ioh, VDD=5V and 3V
Voh/Ioh (3V)
0
0
-5
-2
-10
-4
Ioh (mA)
Ioh (mA)
Voh/Ioh (5V)
Min 85℃
Min 85℃
-15
-6
-20
-8
Typ 25℃
Typ 25℃
Max –40
Max –40
-10
-25
1.5
2
2.5
3
3.5
4
4.5
0
5
0.5
1
1.5
2
2.5
3
Voh (Volt)
Voh (Volt)
Fig. 6-3 Graph on Ports 5 & 6 Voh vs. Ioh, VDD=5V
Fig. 6-4 Graph on Ports 5 & 6 Voh vs. Ioh, VDD=3V
6.3.4 Ports 5 & Port 6 Vol vs. Iol, VDD=5V and 3V
Vol/Iol (5V)
Vol/Iol (3V)
45
100
Max -40
90
Max -40
40
80
35
70
30
Typ 25℃
Typ 25℃
50
Min 85℃
Iol (mA)
Iol (mA)
60
25
Min 85℃
20
40
15
30
10
20
5
10
0
0
0
0.5
1
1.5
2
2.5
3
Vol (Volt)
Fig. 6-5 Graph on Ports 5 & 6 Vol vs. Ioh, VDD=5V
Green Product Specification (V1.0) 01.06.2006
(This specification is subject to change without further notice)
0
0.5
1
1.5
2
2.5
3
Vol (Volt)
Fig. 6-6 Graph on Ports 5 & 6 Voh vs. Iol, VDD=3V
• 37
PH86P168AxS/xJ
8-Bit Microcontroller with OTP ROM
6.3.5 WDT Time Out Period vs. VDD (Prescaler Set to 1:1)
WDT Time out
45
40
35
Max 85℃
WDT period (mS)
30
Max 70℃
25
Typ 25℃
20
Min 0℃
15
Min -40℃
10
5
0
2
3
4
5
6
VDD (Volt)
Fig. 6-7 Graph on WDT Time Out Period vs. VDD (Perscaler Set to 1:1)
38 •
Green Product Specification (V1.0) 01.06.2006
(This specification is subject to change without further notice)
PH86P168AxS/xJ
8-Bit Microcontroller with OTP ROM
6.3.6 Typical RC OSC Frequency vs. VDD
(Cext = 100pF, Temp. = 25℃)
Cext = 100pF, Typical RC Frequency vs. VDD
1.6
R = 3.3K
1.4
Frequency (M Hz)
1.2
R = 5.1K
1
0.8
R = 10K
0.6
0.4
0.2
R = 100K
0
3
3.5
4
4.5
5
5.5
VDD (Volt)
Fig. 6-8 Graph on Typical RC OSC Frequency vs. VDD (Cext = 100pF, Temperature at 25℃)
6.3.7 Typical RC OSC Frequency vs. VDD
(with R and C under Ideal Conditions)
VDD = 5V
VDD = 3V
Fig. 6-9 Graph on Typical RC OSC Frequency vs. VDD (with R & C under Ideal Conditions)
Green Product Specification (V1.0) 01.06.2006
(This specification is subject to change without further notice)
• 39
PH86P168AxS/xJ
8-Bit Microcontroller with OTP ROM
6.3.8 Typical and Maximum Operating Current (ICC1/2/3/4) vs.
Temperature
The following four conditions exist with the Operating Current ICC1 to ICC4:
„
ICC1: VDD=3V, Fosc=32K Hz, 2 clocks, WDT disabled
„
ICC2: VDD=3V, Fosc=32K Hz, 2 clocks, WDT enabled
„
ICC3: VDD=5V, Fosc=4M Hz, 2 clocks, WDT enabled
„
ICC4: VDD=5V, Fosc=10M Hz, 2 clocks, WDT enabled
Typical ICC1 and ICC2 vs. Temperature
15
Current (uA)
12
9
6
3
0
-40
-20
0
20
40
60
80
Temperature (℃)
Fig. 6-10 Graph on Typical Operating Current (ICC1 and ICC2) vs. Temperature
Maximum ICC1 and ICC2 vs. Temperature
21
Current (uA)
18
15
12
9
6
-40
-20
0
20
40
60
80
Temperature (℃)
Fig. 6-11 Graph on Maximum Operating Current (ICC1 and ICC2) vs. Temperature
40 •
Green Product Specification (V1.0) 01.06.2006
(This specification is subject to change without further notice)
PH86P168AxS/xJ
8-Bit Microcontroller with OTP ROM
Current (mA)
Typical ICC3 and ICC4 vs. Temperature
4
3.5
3
2.5
2
1.5
1
0.5
0
Typ ICC4
Typ ICC3
-40
-20
0
20
40
60
80
Temperature (℃)
Fig. 6-12 Graph on Typical Operating Current (ICC3 and ICC4) vs. Temperature
Maximum ICC3 and ICC4 vs. Temperature
4.5
Max ICC4
Current (mA)
4
3.5
3
2.5
Max ICC3
2
1.5
1
-40
-20
0
20
40
60
80
Temperature (℃)
Fig. 6-13 Graph on Maximum Operating Current (ICC3 and ICC4) vs. Temperature
Green Product Specification (V1.0) 01.06.2006
(This specification is subject to change without further notice)
• 41
PH86P168AxS/xJ
8-Bit Microcontroller with OTP ROM
6.3.9 Typical and Maximum Standby Current (ISB1 and ISB2) vs.
Temperature
The following two conditions exist with the Standby Current ISB1 and ISB2:
„
ISB1: VDD=5V, WDT disabled
„
ISB2: VDD=5V, WDT enabled
Typical ISB1 and ISB2 vs. Temperature
12
Current (uA)
10
Typ ISB2
8
6
4
Typ ISB1
2
0
-40
-20
0
20
40
60
80
Temperature (℃)
Fig. 6-14 Graph on Typical Standby Current (ISB1 and ISB2) vs. Temperature
Maximum ISB1 and ISB2 vs. Temperature
12
Current (uA)
10
8
6
4
2
0
-40
-20
0
20
40
60
80
Temperature (℃)
Fig. 6-15 Graph on Maximum Standby Current (ISB1 and ISB2) vs. Temperature
42 •
Green Product Specification (V1.0) 01.06.2006
(This specification is subject to change without further notice)
PH86P168AxS/xJ
8-Bit Microcontroller with OTP ROM
6.3.10 Operating Voltage under Temperature Range of
0°C to 70°C and –40°C to 85°C
Fig. 6-16 Graph on Operating Voltage under Temperature Range of 0°C to 70°C
Fig. 6-17 Graph on Operating Voltage under Temperature Range of –40°C to 85°C
Green Product Specification (V1.0) 01.06.2006
(This specification is subject to change without further notice)
• 43
PH86P168AxS/xJ
8-Bit Microcontroller with OTP ROM
6.3.11 Operating Current Range (Based on High and
Low Freq. @ =25℃) vs. Voltage
PH86P168AxS/xJ HXT V-I
2.5
2.25
2
I(mA)
1.75
1.5
1.25
1
0.75
0.5
0.25
0
2.3
2.8
3.3
3.8
4.3
4.8
5.3
Voltage(V)
Fig. 34 Operating Current Range (Based on High Freq. @ =25℃) vs. Voltage
PH86P168AxS/xJ LXT V-I
40
35
30
I(uA)
25
20
15
10
5
0
2.3
2.8
3.3
3.8
4.3
4.8
5.3
Voltage(V)
Fig. 35 Operating Current Range (Based on Low Freq. @ =25℃) vs. Voltage
44 •
Green Product Specification (V1.0) 01.06.2006
(This specification is subject to change without further notice)
PH86P168AxS/xJ
8-Bit Microcontroller with OTP ROM
APPENDIX
A Package Types
OTP MCU
Mark
Package Type
Pin Count
Package Size
PH86P168ABPS
PH86P168ABPS
DIP
14
300 mil
PH86P168ABMS
PH86P168ABMS
SOP
14
150 mil
PH86P168AAPS
PH86P168AAPS
DIP
18
300 mil
PH86P168AAMS
PH86P168AAMS
SOP
18
300 mil
PH86P168AAASS
PH86P168AAASS
SSOP
20
209 mil
PH86P168AAKMS
PH86P168AAKMS
SSOP
20
209 mil
PH86P168ABPJ
PH86P168ABPJ
DIP
14
300 mil
PH86P168ABMJ
PH86P168ABMJ
SOP
14
150 mil
PH86P168AAPJ
PH86P168AAPJ
DIP
18
300 mil
PH86P168AAMJ
PH86P168AAMJ
SOP
18
300 mil
PH86P168AAASJ
PH86P168AAASJ
SSOP
20
209 mil
PH86P168AAKMJ
PH86P168AAKMJ
SSOP
20
209 mil
• S/J:Green product is not contain hazardous substances.
The third edition of Sony SS-00259 standard.
Pb content should be less than 100ppm.
Pb content to fit in with Sony spec.
Part no.
Electroplate type
Ingredient (%)
Melting point(℃)
Electrical resistivity
(μuohm-cm)
Hardness (hv)
Elongation (%)
EM78P156NxS/xJ
Pure Tin
Sn :100%
232℃
11.4
8~10
>50%
Green Product Specification (V1.0) 01.06.2006
(This specification is subject to change without further notice)
• 45
PH86P168AxS/xJ
8-Bit Microcontroller with OTP ROM
A.1 Package Detailed Information
A.1.1
46 •
14-Lead Plastic Dual in line (PDIP) — 300 Mil
Green Product Specification (V1.0) 01.06.2006
(This specification is subject to change without further notice)
PH86P168AxS/xJ
8-Bit Microcontroller with OTP ROM
A.1.2
14-Lead Plastic Small Outline (SOP) — 150 Mil
Green Product Specification (V1.0) 01.06.2006
(This specification is subject to change without further notice)
• 47
PH86P168AxS/xJ
8-Bit Microcontroller with OTP ROM
A.1.3
48 •
18-Lead Plastic Dual in Line (PDIP) — 300 Mil
Green Product Specification (V1.0) 01.06.2006
(This specification is subject to change without further notice)
PH86P168AxS/xJ
8-Bit Microcontroller with OTP ROM
A.1.4
18-Lead Plastic Small Outline (SOP) — 300 Mil
Green Product Specification (V1.0) 01.06.2006
(This specification is subject to change without further notice)
• 49
PH86P168AxS/xJ
8-Bit Microcontroller with OTP ROM
A.1.5
50 •
20-Lead Plastic Small Outline (SSOP) — 209 Mil
Green Product Specification (V1.0) 01.06.2006
(This specification is subject to change without further notice)
PH86P168AxS/xJ
8-Bit Microcontroller with OTP ROM
B Quality Assurance and Reliability
Test Category
Solderability
Test Conditions
Remarks
Solder temperature=245±5℃,for 5 seconds up to the stopper
using a rosin-type flux
Step1: TCT ,65℃(15mins)~150℃(15mins),10 cycles
Step2: bake 125℃,TD(durance)=24 hrs
For SMD IC(such as
SOP, QFP, SOJ, etc.)
Step3:soak 30°C /60%,TD(durance)=192hrs
Pre-condition
Step4:IR flow 3cycles
(Pkg thickness≧2.5mm or Pkg volume≧350mm3 ----225±5
℃)
(Pkg thickness≦2.5mm or Pkg volume≦350mm3 ----240±5
℃)
Temperature cycle
test
–65℃(15mins)~150℃(15mins) , 200 cycles
Pressure cooker test
TA =121℃,RH=100%,pressure=2atm, TD(durance)= 96 Hrs
High temperature
/high humidity test
TA=85℃ , RH=85%,TD(durance)=168 ,500 Hrs
High-temperature
storage life
TA=150℃, TD(durance)=500,1000Hrs
High-temperature
operating life
TA=125 ℃ , VCC=Max. operating voltage, TD(durance)
=168,500,1000Hrs
Latch-up
TA=25℃, VCC=Max. operating voltage, 150mA/20V
ESD(HBM)
TA=25℃, ≧∣±3KV∣
ESD(MM)
TA=25℃, ≧∣±300V∣
Green Product Specification (V1.0) 01.06.2006
(This specification is subject to change without further notice)
IP_ND,OP_ND,IO_ND
IP_NS,OP_NS,IO_NS
IP_PD,OP_PD,IO_PD,
IP_PS,OP_PS,IO_PS,
VDD-VSS(+),VDD_V
SS(-)mode
• 51
PH86P168AxS/xJ
8-Bit Microcontroller with OTP ROM
C Address Trap Detect
An address trap detect is one of the fail-safe function that detects CPU malfunction
caused by noise or the like. If the CPU attempts to fetch an instruction from a part of
RAM, an internal recovery circuit will auto started. Until CPU got the correct function, it
will execute the next program that follows.
Vdd
/Reset
Tvr
Tvd
Internal POR
Tpor
Power on
Reset
Symbol
Parameter
Condition
Min.
Typ.
Max.
Unit
Tpor
Power on reset time
Vdd = 5V, -40℃ to 85℃
10.5
16.8
22
ms
Tvd
Vdd Voltage drop time
Vdd = 5V, -40℃ to 85℃
-
-
1*
us
Tvr
Vdd Voltage rise time
Vdd = 5V, -40℃ to 85℃
-
-
1**
us
* Tvd is the period of Vdd voltage less than POR voltage 1.9 volts.
** Tvr is the period of Vdd voltage higher than 5.5 volts.
52 •
Green Product Specification (V1.0) 01.06.2006
(This specification is subject to change without further notice)