LOGIC PRODUCTS
LATCHE5/F Ll P-FLOP5
815807.5808
8ns
ORDERING CODE
PACKAGES
Vcc. sv 立 S%;TA=O.C 阳 +70.C
国
啕
i
叶
一c
l
mr
一四
-1·
c-
D
M
趴-3
MM-创
p-c
•
COMMERCIAL RANGES
N8TS807N
•
MI Ll TARY RANGES
I Vcc"SV 主 10%; TA= - SS.C 10 + 12S.C
N8TS808N
Dr
S8TS807F
•
DESCRIPTION
PINS
DESCRIPTION
The data on the D inputs are transferred to
the latch outputs when the Latch Enable
(E) input is HIGH. The latch remains trans.
parent to the data inputs while E is HIGH ,
and stores the data present one setup
time before the HIGH.to.LOW enable tran.
sition. The enable gate has about 400mV
of hysteresis built in to help minimize
problems that signal and ground noise
can cause on the latching operation.
A11
Inputs
AII
Outputs
NOTE
An 8T5 unit load (5ul) 惜
50.抖A IIH
and - 2.0mA
IIL
all eight 3- State buffers independent of
the latch operation. When OE is LOW , the
latched or transparent data appears at the
outputs. When OE is HIGH , the outputs
are in the HIGH impedance "off" state ,
which means they will neither drive nor
load the bus.
The 3.State output buffers are designed to
drive heavily loaded 3.State buses , MOS
memories , or MOS microprocessors. The
active LOW Output Enable (OE) controls
The 8TS808 is an 8.bit , edge.triggered reg.
ister coupled to eight 3.State output buf.
fers. The two sections of the device are
controlled independently by the Clock
(CP) and Output Enable (δE) control gates.
PIN CONFIGURATION
LOGIC SYMBOL
8TSI07
民U4
，帽
'··sa--8··
口口』门』内』内工M』阿」何
ZE
-mwRMDBAD-mDD
02
02 [!
E丐
03 [l
õ4
04 IT
~
3J
E丐
05 [ï
õ8
~ ð7
08 [!
07 [!
ill
:J
E
19 18
v,.,,., = Pin 20
GN币)=Pin 10
[I
QNO~
16 15 14 13 12
8TSI08
23456
7 8 9
iiJ CP
币9
18 17 16 15 14 13 12
:能:2:21:
5-76
17
a
The 3.State output buffers are designed to
drive heavily loaded 3.State buses , MOS
memories , or MOS microprocessors. The
8TS807
8T饵"
国 δ0 1
The register is fuliy edge triggered. The
state of each 0 input , one setup time be.
fore the LOW.to.HIGH clock transition , is
transferred to the corresponding flip.
outpu t. The cloc l< buffer has
flop's
about 400mV of hysteresis buiit in to help
minimize probiems that signai and ground
noise can cause on the ciocking opera.
tion.
LOGIC SYMBOL (IEE ElIEC)
23458789
8TSI07
S8 TS808F
m一w仙
INPUT AND OUTPUT LOADING AND FAN.OUT TABLE
The 8TS807 is an octal transparent latch
coupled to eight 3.State output buffers.
The two sections of the device are con.
trolled independently by Latch Enable (E)
and Output Enable (δE) control gates.
FLW Bn
宁'
nU 』 nu
10ns
v，民 "-A 【 -AH
飞"一 m-m
U
吓。
-e-6
DELAY
c--CJV
ao-oo
''-eo
TE-T'
山 σ-mω-HH
··』
TYPE
。口 -o口
• 8.bit transparent latch 8TS807
• 8.blt posltlve, edge.
triggered register 8TS808
. • 3.State Invertlng output
buffers
• Common 3.State Output
Enable
• Independent register and
3.State buffer operatlon
'807 Octal Transparent betch With 3.State Outputs
'808 Octal 0 Flip.Flop With 3.State Outputs
wBr FMA e-HV anEE-N
TYPICAL PROPAGATION
8TSI08
LOGIC PRODUCTS
8T5807. 5808
LATCHE5/FLl p.FLOP5
唱t
active LOW Output Enable (OE) controls
all eight 3.State buffers independent of
the register operation. When δ~ is LOW ,
the data in the register appears at the out.
puts. When OE is HIGH , the outputs are in
the HIGH impedance "off" state , which
means they will neither drive nor load the
bus.
LOGIC DIAGRAM , 8TS807
a
(1)
Vcc .Pln 20
OND-Pln 10
LOGIC DIAGRAM , 8TS808
二一百二一
Vcc .Pln 20
OND. Pln 10
MODE SELECT-FUNCTION TABLE, 8TS807
。 PERATINO MODES
INPUTS
INTERNAL REOISTER
。UTPUTS
。E
E
Dn
Enable and read reglster
L
L
H
H
L
H
L
H
H
L
Latch and read register
L
L
L
L
h
L
H
"
α翩翩， α邱执』饱
H
x
x
x
(Z)
。0- 0 7
L
MODE SELECT-FUNCTION TABLE, 8TSωe
。 PERATINO MODES
INPUTS
ÕI
Load and read register
L
L
Load register and disable outputs
H
H
…
H. HIGH .011'0"'."
h • HIGH .0ItI0' ,..., on
L • LOW .oltloe I..el
CP
x
x
tup tlme prlor to the LOW.to.HIGH clock tran.ltlon
INTERNAL REOISTER
Dn
。 UTPUTS
。0- 0 7
h
L
H
H
L
x
x
x
x
(Z)
(Z)
1 • LOW .011'0' 1刷酬。"…tup 11m. prlor to th. LOW.to.HIGH clock tr.n.ltlon
HIGH Im pe<l.nca "0"" It.t.
1 • LOW.to.HIGH clock tran副 tlon
X- Don 't __
(Z).
5-77
LOGIC PRODUCTS
8T5807. Sà08
LATCHES/F Ll p.FLOPS
唱F
ABSOLUTE MAXIMUM RATINGS
(Over operating free.air temperature range unless otherwise noted.)
V cc
V 1N
Input voltage
IIN
Input current
V OUT
Voltage applied to output in HIGH output state
TA
UNIT '
58T5
N8T5
7.0
7.0
V
-0.5 to + 5.5
- 0.5 to + 5.5
V
mA
PARAMETER
Supply voltage
- 30 to + 5
-30 to + 5
- 0.5 to + V cc
- 0.5 to + V cc
V
-55 to + 125
o to 70
.C
Operating free.air temperature range
」
RECOMMENDED OPERATING CONDITIONS
8T5
PARAMETER
Vcc
Supply voltage
V 1H
HIGH.level input voltage
UNIT
Mln
Nom
M8X
Mil
4.5
5.0
5.5
v
Com'l
4.75
5.0
5.25
V
Mil
+0.8
v
Com'l
+0.8
V
"'18
mA
V
2.0
V 1L
LOW.level input voltage
IIK
Input clamp current
10H
HIGH.level output current
10L
LOW.level outpJt current
TA
。 perating free.air temperature
2.0
mA
Com'l
Mil
-6.5
mA
M iI
20
mA
Com'l
20
mA
+ 125
.C
70
.C
Mil
55
Com'l
NOTE
VIL = + O.7V MAX for 58T5 at TA= + 125'C only
DC ELECTRICAL CHARACTERISTICS
o
咀-
一一，一一一一一一一
"
(Over recommended operating fre e- air temperature range unless otherwise noted.)
PARAMETER
TE5T CONDITION5
8T5807 , 808
'
Mln
Typ 2
Mil
2.4
3.0
Com'l
2.4
3.1
M8X
UNIT
V 1K
Input clamp voltage
V cc = MIN , 11= I'K
-1.2
v
v
v
v
v
I ,.,.. u
OZH
Off.state ~utput current ,
HIGH.level voltage applied
Vcc=MAX , V1H=MIN , V o =2.4V
50
μA
1"",
OZL
Off.state ootput current ,
LOW.level voltage applied
Vcc=MAX , V1H=MIN , V o =0.5V
-50
μA
Input current at maximum
input voltage
V cc = MAX , V 1= 5.5V
1.0
mA
IIH
HIGH.level input current
V cc = MAX , V 1= 2:7V
50
μA
IIL
LOW.level input current
Vcc=MAX , V 1=0.5V
-0.25
mA
105
Short.circuit output
current 3
-100
mA
V OH
HIGH.level output voltage
V OL
LOW.level output voltage
Icc
5upply current (total)
Vcc=MIN , V1H=MIN , V1L=MAX , 10H=MAX
V cc = MIN , V 1H = MIN ,
V 1L = MAX
Mil
0.5 4
Com'l
0.5
V cc = MAX
V cc = MAX
-40
ICCL
8T5807
105
160
mA
ICCL
AII inputs grounded , 8T5808
102
140
mA
IccZ
CP , OE= 4.5V
D inputs=GND
131
180
mA
NOTE5
t. For conditions shown as MIN or MAX. use the appropriate value specif帽d under recommended operating conditlons for the applicable type.
2. AII typical values are at VCC = 5V. TA= 25 'c
3. 10S is tested with VOUT = + O.5V and VCC =VCC MAX + O.5V. Not more than one output should be shorted at a lime and duratlon of the short circull should not exceed one
second
4. VOL = + O.45V MAX for 58TS at TA = + 125'C only.
5.78
LOGIC PRODUCTS
8T5807. 5808
LATCHE5/FLl P-FLOPS
'
AC CHARACTERISTICS TA= 25.C , Vcc = 5.0V
8TS
TEST CONDITIONS
PARAMETER
f MAX
Maximum clock frequency
tpLH
t pHL
Propagation delay
Latch Enable to output
t pLH
t pHL
C L =15pF , RL "'2800
Mln
Max
Waveform 6 , 8TS808
75
MHz
Waveform 1, 8TS807
14
",1 8
ns
Propagation delay
Data to output
Waveform 4, 8TS807
9
13
ns
t pLH
t pHL
Propagation delay
Clock to output
Waveform 6 , 8TS808
15
17
ns
t pZH
Enable time to HIGH level
Waveform 2
15
ns
t pZL
Enable time to LOW level
18
18
ns
t pHZ
Disable time from HIGH level
9
ns
12
ns
Waveform 3
88TS807
i-S8Õå
Waveform 2, C L = 5pF
Disable time from LOW level
Waveform 3, C L= 5pF
t pLZ
NOTE
Per industry conyention. 'MAX is the worst case yalue 01 the maximum device 。阳 rating Irequency with no constraints on
tr. 勺，
pulse width or duty
•
cyc 幅-
AC SETUP REQUIREMENTS TA=25.C , Vcc =5.0V
8TS
PARAMETER
TEST CONDITIONS
t w( H)
t w( L)
Latch Enable pulse width
Waveform 1, 8TS807
6
7.3
ns
ts
Setup time , Data to Latch Enable
Waveform 5, 8TS807
5
ns
th
Hold time , Data to Latch Enable
Waveform 5, 8T S807
10
ns
Clock pulse width
Waveform 6 , 8TS808
6
7.3
ns
ts
Setup time , Data to Clock
Waveform 7, 8TS808
5
ns
th
Hold time , Data to Clock
Waveform 7, 8TS808
4
ns
t叫 L)
Max
UNIT
25
一丰
t w( H)
Mln
TEST CIRCUITS AND WAVEFORMS
e-
HMT-BrHM?-
俨W
INPUT PULSE DEFINITIONS
陀、
hmphξf6
E』
''A''
。
帽AW
龟咀
Rb 吨
E『
'-
。
ed-T- FU RFHHM
T·-E
,
AMP(V
tw
ov
D
'TH L(lI)
tTLH('r'
'TLH('r)
'THL(t"
AMP(V)
sWITCH POSITION
.τ..1
-tpZH
tpZL
tpHZ
坦峰
Swllchl
Open
Closed
Closed
Closed
-
Swltch2
Closed
Open
Closed
'C losed
'w
ov
VM = 1.3V for 54LS/74LS , VM = 1.5V for all other TTL lamllies
DEFIN fTl ONS
RL = Load resístor to VcC; see AC CHARACTERISTICS lor value
CL = Load. capacitance includes jlg and probe capacltance; see AC
CHARACTERISTICS for value
RT = Termination resistance should be equal 10 ZOUT 01 Pulse
Generalor.
o = Di Od es are 1N916, 1N3064 , or equlvalenl
RX= lk口 lor 54/74 , 54S/74S , RX = 5kO lor 54LS/74LS
ITLHιITHL Values should be less Ihan or equal 10 Ihe lable enlnes
5-79
LOGIC PRODUCTS
LATCHE5/FLlp.FLOP5
8T5807 , 5808
电F
AC WAVEFORMS
LATCH ENABLE TO 。υTPUT DELAYS
AND LATCH ENABLE PULSE WIDTH
D-\
3.STATE ENABLE Tl ME TO HIGH LEVEL
AND DISABLE TIME FR。怕 HIGH LEVEL
L
/
ç.
面「fL
E
I_IPHZ汪二1.5V
F-
百n
Wav.form 1
W刷刷 orm
3.STATE ENABLE TIME TO LOW LEVEL
AND DISABLE Tl ME FROM LOW LEVEL
PAOPAGATION DELAY DATA
TO Q OUTPUTS
ç.
面一飞 VM
Dn
|;iTtsv
|义VM
2
。"
Lo.IV
W剧.form
3
Wav.form 4
CLOCK TO OUTPUT DELAYS
AND CLOCK PULSE WIDTH
DATA SETUP AND HOLD TIMES
CP
D
E
Wav.form 5
Wav.form
e
DATA SETUP AND HOLD TIMES
。"
CP
\飞
。"
Wav.form 7
f
VM=1.5V
The shaded .reas indicate when the input Is permitted to change for predlctable output performance
5-80