High Performance FSK/ASK Transceiver IC ADF7020-1 FEATURES On-chip VCO and fractional-N PLL On-chip 7-bit ADC and temperature sensor Fully automatic frequency control loop (AFC) compensates for lower tolerance crystals Digital RSSI Integrated TRx switch Leakage current <1 μA in power-down mode Low power, low IF transceiver Frequency bands 135 MHz to 650 MHz, direct output 80 MHz to 325 MHz, divide-by-2 mode Data rates supported 0.15 kbps to 200 kbps, FSK 0.15 kbps to 64 kbps, ASK 2.3 V to 3.6 V power supply Programmable output power −20 dBm to +13 dBm in 63 steps Receiver sensitivity −119 dBm at 1 kbps, FSK, 315 MHz −114 dBm at 9.6 kbps, FSK, 315 MHz −111.8 dBm at 9.6 kbps, ASK, 315 MHz Low power consumption 17.6 mA in receive mode 21 mA in transmit mode (10 dBm output) APPLICATIONS Low cost wireless data transfer Wireless medical applications Remote control/security systems Wireless metering Keyless entry Home automation Process and building control FUNCTIONAL BLOCK DIAGRAM RLNA RSET CREG(1:4) POLARIZATION LDO(1:4) ADCIN MUXOUT TEMP SENSOR OFFSET CORRECTION TEST MUX LNA RFIN MUX RSSI IF FILTER RFINB 7-BIT ADC FSK/ASK DEMODULATOR DATA SYNCHRONIZER GAIN OFFSET CORRECTION CE AGC CONTROL FSK MOD CONTROL RFOUT DIVIDERS/ MUXING Σ-Δ MODULATOR GAUSSIAN FILTER DIV P DATA CLK Tx/Rx CONTROL AFC CONTROL DATA I/O INT/LOCK N/N+1 SLE SERIAL PORT VCO DIV R L1 L2 VCOIN CPOUT SREAD SCLK PFD RING OSC1 OSC OSC2 CLK DIV CLKOUT 05669-001 CP SDATA Figure 1. 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ADF7020-1 TABLE OF CONTENTS Features .............................................................................................. 1 LNA/PA Matching...................................................................... 25 Applications....................................................................................... 1 Transmit Protocol and Coding Considerations ..................... 26 Functional Block Diagram .............................................................. 1 Device Programming after Initial Power-Up ......................... 26 Revision History ............................................................................... 2 Interfacing to Microcontroller/DSP ........................................ 26 General Description ......................................................................... 3 Serial Interface ................................................................................ 29 Specifications..................................................................................... 4 Readback Format........................................................................ 29 Timing Characteristics ................................................................ 8 Register 0—N Register............................................................... 30 Absolute Maximum Ratings.......................................................... 10 Register 1—Oscillator/Filter Register...................................... 31 ESD Caution................................................................................ 10 Register 2—Transmit Modulation Register (ASK/OOK Mode) ..................................................................... 32 Pin Configuration and Function Descriptions........................... 11 Typical Performance Characteristics ........................................... 13 Register 2—Transmit Modulation Register (FSK Mode) ..... 33 Frequency Synthesizer ................................................................... 15 Register 2—Transmit Modulation Register (GFSK/GOOK Mode)................................................................ 34 Reference Input........................................................................... 15 Register 3—Receiver Clock Register ....................................... 35 Choosing Channels for Best System Performance................. 17 Register 4—Demodulator Set-up Register.............................. 36 Transmitter ...................................................................................... 18 Register 5—Sync Byte Register................................................. 37 RF Output Stage.......................................................................... 18 Register 6—Correlator/Demodulator Register ...................... 38 Modulation Schemes.................................................................. 18 Register 7—Readback Set-up Register .................................... 39 Receiver Section.............................................................................. 20 Register 8—Power-Down Test Register .................................. 40 RF Front End............................................................................... 20 Register 9—AGC Register......................................................... 41 RSSI/AGC.................................................................................... 21 Register 10—AGC 2 Register.................................................... 42 FSK Demodulators on the ADF7020-1 ................................... 21 Register 11—AFC Register ....................................................... 42 FSK Correlator/Demodulator................................................... 21 Register 12—Test Register......................................................... 43 Linear FSK Demodulator .......................................................... 23 Register 13—Offset Removal and Signal Gain Register ....... 44 AFC Section ................................................................................ 23 Outline Dimensions ....................................................................... 45 Automatic Sync Word Recognition ......................................... 24 Ordering Guide .......................................................................... 45 Applications..................................................................................... 25 REVISION HISTORY 12/05—Revision 0: Initial Version Rev. 0 | Page 2 of 48 ADF7020-1 GENERAL DESCRIPTION The ADF7020-1 is a low power, highly integrated FSK/GFSK/ ASK/OOK/GOOK transceiver designed for operation in the low UHF and VHF bands. The ADF7020-1 uses an external VCO inductor that allows users to set the operating frequency anywhere between 135 MHz and 650 MHz. Using the divideby-2 circuit allows users to operate the device as low as 80 MHz. The typical range of the VCO is about 10% of the operating frequency. A complete transceiver can be built using a small number of external discrete components, making the ADF70201 very suitable for price-sensitive and area-sensitive applications. The transmit section contains a VCO and low noise fractional-N PLL with output resolution of <1 ppm. This frequency agile PLL allows the ADF7020-1 to be used in frequency-hopping spread spectrum (FHSS) systems. The VCO operates at twice the fundamental frequency to reduce spurious emissions and frequency pulling problems. A low IF architecture is used in the receiver (200 kHz), minimizing power consumption and the external component count and avoiding interference problems at low frequencies. The ADF7020-1 supports a wide variety of programmable features, including Rx linearity, sensitivity, and IF bandwidth, allowing the user to trade off receiver sensitivity and selectivity for current consumption, depending on the application. The receiver also features a patent-pending automatic frequency control (AFC) loop, allowing the PLL to compensate for frequency error in the incoming signal. An on-chip ADC provides readback of an integrated temperature sensor, an external analog input, the battery voltage, or the RSSI signal, which provides savings on an ADC in some applications. The temperature sensor is accurate to ±10°C over the full operating temperature range of −40°C to +85°C. This accuracy can be improved by doing a 1-point calibration at room temperature and storing the result in memory. The transmitter output power is programmable in 63 steps from −20 dBm to +13 dBm. The transceiver RF frequency, channel spacing, and modulation are programmable using a simple 3wire interface. The device operates with a power supply range of 2.3 V to 3.6 V and can be powered down when not in use. Rev. 0 | Page 3 of 48 ADF7020-1 SPECIFICATIONS VDD = 2.3 V to 3.6 V, GND = 0 V, TA = TMIN to TMAX, unless otherwise noted. Typical specifications are at VDD = 3 V, TA = 25°C. All measurements are performed using the EVAL-ADF7020-1-DBX and PN9 data sequence, unless otherwise noted. Table 1. Parameter RF CHARACTERISTICS Frequency Ranges (Direct Output) Frequency Ranges (Divide-by-2 Mode) VCO Frequency Range Phase Frequency Detector Frequency TRANSMISSION PARAMETERS Data Rate FSK/GFSK OOK/ASK OOK/ASK Frequency Shift Keying GFSK/FSK Frequency Deviation 2, 3 Deviation Frequency Resolution Gaussian Filter BT Amplitude Shift Keying ASK Modulation Depth OOK-PA Off Feedthrough Transmit Power 4 Transmit Power Transmit Power Variation vs. Temp. Transmit Power Variation vs. VDD Programmable Step Size −20 dBm to +13 dBm Integer Boundary Reference Harmonics Second Harmonic Third Harmonic All Other Harmonics VCO Frequency Pulling, OOK Mode Optimum PA Load Impedance 5 Min Max Unit Test Conditions 135 650 MHz See Table 5 for VCO bias settings at different frequencies 80 325 MHz 20.96 Ratio MHz 0.15 0.15 0.3 200 64 1 100 kbps kbps kbaud Using Manchester biphase-L encoding 1 4.88 100 110 620 kHz kHz Hz PFD = 3.625 MHz PFD = 20 MHz PFD = 3.625 MHz 30 ±1 ±1 dB dBm dBm dBm dB dB VDD = 3.0 V, TA = 25°C, FRF > 200 MHz VDD = 3.0 V, TA = 25°C, FRF < 200 MHz From −40°C to +85°C From 2.3 V to 3.6 V at 315 MHz, TA = 25°C 0.3125 dB −55 −65 dBc dBc −27 −21 −35 30 79.4 + j64 109 + j64 40 + j47.5 dBc dBc dBc kHz rms 1.1 RF/256 Typ 1.2 FMAX/FMIN, using VCO bias settings in Table 5 PFD must be less than direct output frequency/31 0.5 −50 −20 −20 +13 +11 Rev. 0 | Page 4 of 48 See Figure 13 for how output power varies with PA setting 50 kHz loop BW Unfiltered conductive DR = 9.6 kbps FRF = 140 MHz FRF = 320 MHz FRF = 590 MHz ADF7020-1 Parameter RECEIVER PARAMETERS FSK/GFSK Input Sensitivity Sensitivity at 1 kbps Sensitivity at 9.6 kbps OOK Input Sensitivity Sensitivity at 1 kbps Sensitivity at 9.6 kbps LNA and Mixer, Input IP37 Enhanced Linearity Mode Low Current Mode High Sensitivity Mode Rx Spurious Emissions 8 AFC Pull-In Range Response Time Accuracy CHANNEL FILTERING Adjacent Channel Rejection (Offset = ±1 × IF Filter BW Setting) Second Adjacent Channel Rejection (Offset = ±2 × IF Filter BW Setting) Third Adjacent Channel Rejection (Offset = ±3 × IF Filter BW Setting) Image Channel Rejection CO-CHANNEL REJECTION Wideband Interference Rejection BLOCKING ±1 MHz ±5 MHz ±10 MHz ±10 MHz (High Linearity Mode) Saturation (Maximum Input Level) LNA Input Impedance RSSI Range at Input Linearity Absolute Accuracy Response Time Min Typ Max Unit −119.2 −114.2 dBm dBm −118.2 −111.8 dBm dBm 6.8 −3.2 −35 dBm dBm dBm dBm dBm −57 −47 Test Conditions At BER = 1E − 3, FRF = 315 MHz, LNA and PA matched separately 6 FDEV= 5 kHz, high sensitivity mode 7 FDEV = 10 kHz, high sensitivity mode At BER = 1E − 3, FRF = 315 MHz High sensitivity mode High sensitivity mode Pin = −20 dBm, 2 CW interferers, FRF = 315 MHz, F1 = FRF + 3 MHz, F2 = FRF + 6 MHz, maximum gain <1 GHz at antenna input >1 GHz at antenna input ±50 48 1 kHz Bits kHz IF_BW = 200 kHz Modulation index = 0.875 27 dB 50 dB IF filter BW settings = 100 kHz, 150 kHz, 200 kHz; desired signal 3 dB above the input sensitivity level; CW interferer power level increased until BER = 10−3; image channel excluded 55 dB 35 −2 70 dB dB dB 60 dB 68 65 72 12 237 − j193 101.4 − j161.6 49.3 − j104.6 dB dB dB dBm Ω Ω Ω FSK mode, BER = 10−3 FRF = 130 MHz, RFIN to GND FRF = 310 MHz FRF = 610 MHz −100 to −36 ±2 ±3 150 dBm dB dB μs See the RSSI/AGC section Rev. 0 | Page 5 of 48 Image at FRF − 400 kHz Swept from 100 MHz to 2 GHz, measured as channel rejection Desired signal 3 dB above the input sensitivity level, CW interferer power level increased until BER = 10−2 ADF7020-1 Parameter PHASE-LOCKED LOOP VCO Gain Unit Test Conditions 40 MHz/V 35 MHz/V 16.5 MHz/V Phase Noise (In-Band) −89 dBc/Hz 433 MHz, VCO adjust = 0, VCO_BIAS_SETTING = 2 315 MHz, VCO adjust = 0, VCO_BIAS_SETTING = 2 135 MHz, VCO adjust = 0, VCO_BIAS_SETTING = 1 PA = 0 dBm, VDD = 3.0 V, PFD = 10 MHz, FRF = 315 MHz, VCO_BIAS_SETTING = 2 Normalized In-Band Phase Noise Floor 9 Phase Noise (Out-of-Band) Residual FM PLL Settling −198 dBc/Hz −110 128 40 dBc/Hz Hz μs 1 MHz offset From 200 Hz to 20 kHz, FRF = 315 MHz Measured for a 10 MHz frequency step to within 5 ppm accuracy, PFD = 20 MHz, LBW = 50 kHz MHz MHz pF ms Must ensure PFD maximum is not exceeded REFERENCE INPUT Crystal Reference External Oscillator Load Capacitance Crystal Start-Up Time Min Typ Max 3.625 3.625 24 24 33 2.1 1.0 ms CMOS levels ±1 ±1 LSB LSB From 2.3 V to 3.6 V, TA = 25°C From 2.3 V to 3.6 V, TA = 25°C 10 3.0 150 μs + (5 × TBIT) μs ms CREG = 100 nF See Table 13 for more details Time to synchronized data out, includes AGC settling. See AGC Information and Timing section for more details. Input Level ADC PARAMETERS INL DNL TIMING INFORMATION Chip Enabled to Regulator Ready Chip Enabled to RSSI Ready Tx-to-Rx Turnaround Time LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINH/IINL Input Capacitance, CIN Control Clock Input LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL CLKOUT Rise/Fall CLKOUT Load TEMPERATURE RANGE—TA 0.7 × V DD 0.2 × V DD ±1 10 50 V V μA pF MHz 0.4 5 10 +85 V V ns pF °C DVDD − 0.4 −40 Refer to the crystal’s data sheet 11.0592 MHz crystal, using 33 pF load capacitors Using 16 pF load capacitors See the Reference Input section Rev. 0 | Page 6 of 48 IOH = 500 μA IOL = 500 μA ADF7020-1 Parameter POWER SUPPLIES Voltage Supply VDD Transmit Current Consumption 433 MHz, 0 dBm/5 dBm/10 dBm Receive Current Consumption Low Current Mode High Sensitivity Mode Power-Down Mode Low Power Sleep Mode Min Typ 2.3 Max Unit Test Conditions 3.6 V 13/16/21 mA All VDD pins must be tied together FRF = 315 MHz, VDD = 3.0 V, PA is matched to 50 Ω VCO_BIAS_SETTING = 2 17.6 20.1 mA mA VCO_BIAS_SETTING = 2 VCO_BIAS_SETTING = 2 0.1 1 1 μA Higher data rates are achievable, depending on local regulations. For definition of frequency deviation, see the Register 2—Transmit Modulation Register (FSK Mode) section. 3 For definition of GFSK frequency deviation, see the Register 2—Transmit Modulation Register (GFSK/GOOK Mode) section. 4 Measured as maximum unmodulated power. Output power varies with both supply and temperature. 5 For matching details, see the LNA/PA Matching section. 6 Sensitivity for combined matching network case is typically 2 dB less than separate matching networks. See Table 11 for sensitivity values at various data rates and frequencies. 7 See Table 6 for a description of different receiver modes. 8 Follow the matching and layout guidelines to achieve the relevant FCC/ETSI specifications. 9 This figure can be used to calculate the in-band phase noise for any operating frequency. Use the following equation to calculate the in-band phase noise performance as seen at the PA output: –198 + 10 log(fPFD) + 20 log N. 2 Rev. 0 | Page 7 of 48 ADF7020-1 TIMING CHARACTERISTICS VDD = 3 V ± 10%, VGND = 0 V, TA = 25°C, unless otherwise noted. Guaranteed by design, but not production tested. Table 2. Parameter t1 t2 t3 t4 t5 t6 t8 t9 t10 Limit at TMIN to TMAX <10 <10 <25 <25 <10 <20 <25 <25 <10 Unit ns ns ns ns ns ns ns ns ns Test Conditions/Comments SDATA-to-SCLK set-up time SDATA-to-SCLK hold time SCLK high duration SCLK low duration SCLK-to-SLE set-up time SLE pulse width SCLK-to-SREAD data valid, readback SREAD hold time after SCLK, readback SCLK-to-SLE disable time, readback t3 t4 SCLK t1 SDATA DB31 (MSB) t2 DB30 DB1 (CONTROL BIT C2) DB2 DB0 (LSB) (CONTROL BIT C1) t6 05669-002 SLE t5 Figure 2. Serial Interface Timing Diagram t1 t2 SCLK SDATA REG7 DB0 (CONTROL BIT C1) SLE t3 t10 t8 RV16 RV15 RV2 RV1 05669-003 X SREAD t9 Figure 3. Readback Timing Diagram Rev. 0 | Page 8 of 48 ADF7020-1 ±1 × DATA RATE/32 1/DATA RATE RxCLK RxDATA 05669-004 DATA Figure 4. RxData/RxCLK Timing Diagram 1/DATA RATE TxCLK DATA FETCH SAMPLE 05669-005 TxDATA NOTES 1. TxCLK ONLY AVAILABLE IN GFSK MODE. Figure 5. TxData/TxCLK Timing Diagram Rev. 0 | Page 9 of 48 ADF7020-1 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter VDD to GND 1 Analog I/O Voltage to GND Digital I/O Voltage to GND Operating Temperature Range Industrial (B Version) Storage Temperature Range Maximum Junction Temperature MLF θJA Thermal Impedance Reflow Soldering Peak Temperature Time at Peak Temperature 1 Rating −0.3 V to +5 V −0.3 V to AVDD + 0.3 V −0.3 V to DVDD + 0.3 V −40°C to +85°C −65°C to +125°C 150°C 26°C/W Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. This device is a high performance RF-integrated circuit with an ESD rating of <2 kV. It is ESD sensitive; proper precautions should be taken for handling and assembly. 260°C 40 sec GND = CPGND = RFGND = DGND = AGND = 0 V. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 0 | Page 10 of 48 ADF7020-1 48 47 46 45 44 43 42 41 40 39 38 37 CVCO GND1 L1 GND L2 VDD CPOUT CREG3 VDD3 OSC1 OSC2 MUXOUT PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VCOIN CREG1 1 2 ADF7020-1 TOP VIEW (Not to Scale) 36 35 34 33 32 31 30 29 28 27 26 25 CLKOUT DATA CLK DATA I/O INT/LOCK VDD2 CREG2 ADCIN GND2 SCLK SREAD SDATA SLE 05669-006 MIX_I MIX_I MIX_Q MIX_Q FILT_I FILT_I GND4 FILT_Q FILT_Q GND4 TEST_A CE 13 14 15 16 17 18 19 20 21 22 23 24 VDD1 3 RFOUT 4 RFGND 5 RFIN 6 RFINB 7 RLNA 8 VDD4 9 RSET 10 CREG4 11 GND4 12 PIN 1 INDICATOR Figure 6. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 Mnemonic VCOIN 2 CREG1 3 VDD1 4 RFOUT 5 6 RFGND RFIN 7 8 9 10 11 RFINB RLNA VDD4 RSET CREG4 12 13 to 18 GND4 MIX/FILT 19, 22 20, 21, 23 24 GND4 FILT/TEST_A 25 SLE 26 SDATA CE Description VCO Input Pin. The tuning voltage on this pin determines the output frequency of the voltage controlled oscillator (VCO). The higher the tuning voltage, the higher the output frequency. Regulator Voltage for PA Block. A 100 nF in parallel with a 5.1 pF capacitor should be placed between this pin and ground for regulator stability and noise rejection. Voltage Supply for PA Block. Decoupling capacitors of 0.1 μF and 10 pF should be placed as close as possible to this pin. All VDD pins should be tied together. PA Output Pin. The modulated signal is available at this pin. Output power levels are from −20 dBm to +13 dBm. The output should be impedance matched to the desired load using suitable components. See the Transmitter section. Ground for Output Stage of Transmitter. All GND pins should be tied together. LNA Input for Receiver Section. Input matching is required between the antenna and the differential LNA input to ensure maximum power transfer. See the LNA/PA Matching section. Complementary LNA Input. See the LNA/PA Matching section. External Bias Resistor for LNA. Optimum resistor is 1.1 kΩ with 5% tolerance. Voltage Supply for LNA/MIXER Block. This pin should be decoupled to ground with a 10 nF capacitor. External Resistor to Set Charge Pump Current and Some Internal Bias Currents. Use 3.6 kΩ with 5% tolerance. Regulator Voltage for LNA/MIXER Block. A 100 nF capacitor should be placed between this pin and GND for regulator stability and noise rejection. Ground for LNA/MIXER Block. Signal Chain Test Pins. These pins are high impedance under normal conditions and should be left unconnected. Ground for LNA/MIXER Block. Signal Chain Test Pins. These pins are high impedance under normal conditions and should be left unconnected. Chip Enable. Bringing CE low puts the ADF7020-1 into complete power-down. Register values are lost when CE is low, and the part must be reprogrammed once CE is brought high. Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the four latches. A latch is selected using the control bits. Serial Data Input. The serial data is loaded MSB first, with the 2 LSBs as the control bits. This pin is a high impedance CMOS input. Rev. 0 | Page 11 of 48 ADF7020-1 Pin No. 27 Mnemonic SREAD 28 SCLK 29 30 GND2 ADCIN 31 CREG2 32 33 VDD2 INT/LOCK 34 35 DATA I/O DATA CLK 36 CLKOUT 37 MUXOUT 38 OSC2 39 40 OSC1 VDD3 41 CREG3 42 CPOUT 43 44, 46 VDD L2, L1 45, 47 48 GND, GND1 CVCO Description Serial Data Output. This pin is used to feed readback data from the ADF7020-1 to the microcontroller. The SCLK input is used to clock each readback bit (AFC, ADC readback) from the SREAD pin. Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the 24-bit shift register on the CLK rising edge. This pin is a digital CMOS input. Ground for Digital Section. Analog-to-Digital Converter Input. The internal 7-bit ADC can be accessed through this pin. Full scale is 0 to 1.9 V. Readback is made using the SREAD pin. Regulator Voltage for Digital Block. A 100 nF in parallel with a 5.1 pF capacitor should be placed between this pin and ground for regulator stability and noise rejection. Voltage Supply for Digital Block. A decoupling capacitor of 10 nF should be placed as close as possible to this pin. Bidirectional Pin. In output mode (interrupt mode), the ADF7020-1 asserts the INT/LOCK pin when it has found a match for the preamble sequence. In input mode (lock mode), the microcontroller can be used to lock the demodulator threshold when a valid preamble has been detected. Once the threshold is locked, NRZ data can be reliably received. In this mode, a demodulator lock can be asserted with minimum delay. Transmit Data Input/Received Data Output. This is a digital pin and normal CMOS levels apply. Transmit/Receive Clock Pin. In receive mode, the pin outputs the synchronized data clock. The positive clock edge is matched to the center of the received data. In GFSK transmit mode, the pin outputs an accurate clock to latch the data from the microcontroller into the transmit section at the exact required data rate. See the Gaussian Frequency Shift Keying (GFSK) section. A Divided-Down Version of the Crystal Reference with Output Driver. The digital clock output can be used to drive several other CMOS inputs such as a microcontroller clock. The output has a 50:50 mark-space ratio. Multiplexer Output Pin. This pin provides the Lock_Detect signal, which is used to determine if the PLL is locked to the correct frequency. Other signals include Regulator_Ready, which is an indicator of the status of the serial interface regulator. Oscillator Output Pin. The reference crystal should be connected between this pin and OSC1. A TCXO reference can be used by driving this pin with CMOS levels and disabling the crystal oscillator. Oscillator Input Pin. The reference crystal should be connected between this pin and OSC2. Voltage Supply for the Charge Pump and PLL Dividers. This pin should be decoupled to ground with a 0.01 μF capacitor. Regulator Voltage for Charge Pump and PLL Dividers. A 100 nF in parallel with a 5.1 pF capacitor should be placed between this pin and ground for regulator stability and noise rejection. Charge Pump Output. This output generates current pulses that are integrated in the loop filter. The integrated current changes the control voltage on the input to the VCO. Voltage Supply for VCO Tank Circuit. This pin should be decoupled to ground with a 0.01 μF capacitor. External VCO Inductor Pins. A chip inductor should be connected across these pins to set the VCO operating frequency. See the Voltage Controlled Oscillator (VCO) section for details on choosing the appropriate value. Grounds for VCO Block. VCO Noise Compensation Node. A 22 nF capacitor should be placed between this pin and CREG1 to reduce VCO noise. Rev. 0 | Page 12 of 48 ADF7020-1 TYPICAL PERFORMANCE CHARACTERISTICS CARRIER POWER –0.28dBm REF –70.00dBc/Hz 10.00 dB/ ATTEN 0.00dB MKR1 REF 10dBm PEAK 1 LOG 10dB/ 10.0000kHz –87.80dBc/Hz MKR4 3.482GHz SWEEP 16.52ms (601pts) ATTEN 20dB 1 3 4 FREQUENCY OFFSET 10MHz START 100MHz RES BW 3MHz Figure 7. Phase Noise Response at 315 MHz, VDD = 3.0 V, ICP = 1.5 mA VBW 3MHz Figure 10. Harmonic Response, RFOUT Matched to 50 Ω, No Filter REF 15dBm REF 20dBm NORM LOG 10 dB/ ATTEN 30dB STOP 10.000GHz SWEEP 16.52ms (601pts) 05669-010 1kHz 05669-007 REF LEVEL 10.00dBm ATTEN 30dB Δ Mkr1 1.834GHz –62.57dB NORM 1R LOG 10dB/ MARKER Δ 1.834000000GHz –62.57dB FSK LgAv W1 S2 S3 FC AA £(f): FTun Swp GFSK CENTER 415.000 0 MHz SPAN 400 kHz #RES BW 300 Hz VBW 300 Hz SWEEP 5.359 s (601pts) 05669-058 V1 V2 S3 FC AA £(f): f>50k SWP START 800MHz #RES BW 30kHz 0 STOP 5.000GHz SWEEP 5.627s (601pts) ATTEN 30dB REF 20dBm NORM LOG 10 dB/ 200kHz FILTER BW –10 –15 –20 –25 OOK –30 –35 ASK –40 150kHz FILTER BW V1 V2 S3 FC AA £(f): f>50k SWP –50 –55 –60 100kHz FILTER BW –65 –70 –400 –300 –200 –100 0 100 200 300 400 500 600 –350 –250 –150 –50 50 150 250 350 450 550 IF FREQ (kHz) Figure 9. IF Filter Response GOOK CENTER 415.000 0 MHz SPAN 300 kHz #RES BW 360 Hz VBW 360 Hz SWEEP 2.791 s (601pts) 05669-059 –45 LgAv 05669-009 ATTENUATION LEVEL (dB) VBW 30kHz Figure 11. Harmonic Response, Murata Dielectric Filter Figure 8. Output Spectrum in FSK and GFSK Modulation –5 1 05669-011 LgAv Figure 12. Output Spectrum in ASK, OOK, and GOOK Modes, DR = 10 kbps Rev. 0 | Page 13 of 48 ADF7020-1 0 20 9μA 15 +3.6V,+85°C 11μA 10 –2 5μA 0 7μA –5 +2.3V,–40°C +3.6V,–40°C –3 LOG (BER) 5 PA OUTPUT POWER +2.3V,+85°C +2.3V,+25°C –1 +3.6V,+25°C +3.0V,–40°C –4 –5 –10 –6 –15 –7 –20 5 9 13 17 21 25 29 33 37 41 45 49 53 57 61 PA SETTING –8 –127 –126 –125 –124 –123 –122 –121 –120 –119 –118 –117 –116 –115 INPUT POWER (dBm) Figure 16. Sensitivity vs. VDD and Temperature, RF = 315 MHz, DR = 1 kBPS, Correlator Demod Figure 13. PA Output Power vs. Setting CARRIER POWER 10.75dBm REF –70.00dBc/Hz 10.00 dB/ ATTEN 6.00dB MKR1 05669-016 1 05669-013 –25 0 10.0000kHz –86.20dBc/Hz –1 200.8k DATA RATE –2 BER –3 –4 1.002k DATA RATE 9.760k DATA RATE –5 –6 10MHz FREQUENCY OFFSET 05669-017 1kHz 05669-057 –8 –122 –121 –120 –119 –118 –117 –116 –115 –114 –113 –112 –111 –110 –109 –108 –107 –106 –105 –104 –103 –102 –101 –100 –99 –98 –97 –96 –95 –94 –93 –92 –91 –90 –7 RF I/P LEVEL (dBm) Figure 14. Wideband Interference Rejection. Wanted Signal (880 MHz) at 3 dB above Sensitivity Point Interferer = FM Jammer (9.76 kbps, 10k Deviation) Figure 17. BER vs. Data-Rate (Combined Matching Network) Separate LNA and PA Matching Paths Typically Improve Performance by 2 dB –60 20 –65 0 –70 ACTUAL INPUT LEVEL LINEAR AFC OFF –75 RF I/P LEVEL (dBm) –40 RSSI READBACK LEVEL –60 –80 –80 –85 CORRELATION AFC ON –90 –95 CORRELATION AFC OFF LINEAR AFC ON –100 –105 –100 –80 –60 –40 RF I/P (dB) –20 0 20 FREQUENCY ERROR (kHz) Figure 18. Sensitivity vs. Frequency Error with AFC On/Off Figure 15. Digital RSSI Readback Linearity Rev. 0 | Page 14 of 48 05669-018 –100 –110 –100 –90 –80 –70 –60 –50 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 100 110 –110 –120 –120 05669-015 RSSI LEVEL (dB) –20 ADF7020-1 FREQUENCY SYNTHESIZER REFERENCE INPUT R Counter The on-board crystal oscillator circuitry (see Figure 19) can use an inexpensive quartz crystal as the PLL reference. The oscillator circuit is enabled by setting R1_DB12 high. It is enabled by default on power-up and is disabled by bringing CE low. Errors in the crystal can be corrected using the automatic frequency control (see the AFC Section) feature or by adjusting the fractional-N value (see the N Counter section). A single-ended reference (TCXO, CXO) can also be used. The CMOS levels should be applied to OSC2 with R1_DB12 set low. The 3-bit R counter divides the reference input frequency by an integer from 1 to 7. The divided-down signal is presented as the reference clock to the phase frequency detector (PFD). The divide ratio is set in Register 1. Maximizing the PFD frequency reduces the N value. This reduces the noise multiplied at a rate of 20 log(N) to the output, as well as reducing occurrences of spurious components. The R Register defaults to R = 1 on power-up: PFD [Hz] = XTAL/R MUXOUT and Lock Detect The MUXOUT pin allows the user to access various digital points in the ADF7020-1. The state of MUXOUT is controlled by Bits R0_DB (29:31). OSC2 CP2 5669-019 OSC1 CP1 Regulator Ready Figure 19. Oscillator Circuit on the ADF7020-1 Two parallel resonant capacitors are required for oscillation at the correct frequency; their values are dependent on the crystal specification. They should be chosen so that the series value of capacitance added to the PCB track capacitance adds up to the load capacitance of the crystal, usually 20 pF. Track capacitance values vary from 2 pF to 5 pF, depending on board layout. Where possible, choose capacitors that have a very low temperature coefficient to ensure stable frequency operation over all conditions. Regulator ready is the default setting on MUXOUT after the transceiver has been powered up. The power-up time of the regulator is typically 50 μs. Because the serial interface is powered from the regulator, the regulator must be at its nominal voltage before the ADF7020-1 can be programmed. The status of the regulator can be monitored at MUXOUT. When the regulator ready signal on MUXOUT is high, programming of the ADF7020-1 can begin. DVDD CLKOUT Divider and Buffer The CLKOUT circuit takes the reference clock signal from the oscillator section (see Figure 19) and supplies a divided-down 50:50 mark-space signal to the CLKOUT pin. An even divide from 2 to 30 is available. This divide number is set in R1_DB (8:11). On power-up, the CLKOUT defaults to the divide-by-8 block. REGULATOR READY DIGITAL LOCK DETECT ANALOG LOCK DETECT MUX R COUNTER OUTPUT MUXOUT CONTROL N COUNTER OUTPUT PLL TEST MODES Σ-Δ TEST MODES CLKOUT ENABLE BIT DGND DIVIDER 1 TO 15 ÷2 CLKOUT 05669-020 OSC1 Figure 21. MUXOUT Circuit Digital Lock Detect Figure 20. CLKOUT Stage To disable CLKOUT, set the divide number to 0. The output buffer can drive up to a 20 pF load with a 10% rise time at 4.8 MHz. Faster edges can result in some spurious feedthrough to the output. A small series resistor (50 Ω) can be used to slow the clock edges to reduce these spurs at FCLK. Digital lock detect is active high. The lock detect circuit is located at the PFD. When the phase error on five consecutive cycles is less than 15 ns, lock detect is set high. Lock detect remains high until 25 ns phase error is detected at the PFD. Because no external components are needed for digital lock detect, it is more widely used than analog lock detect. Rev. 0 | Page 15 of 48 05669-021 DVDD ADF7020-1 Analog Lock Detect This N-channel, open-drain lock detect should be operated with an external pull-up resistor of 10 kΩ nominal. When a lock has been detected, this output is high with narrow low-going pulses. For GFSK, it is recommended that an LBW of 2.0 to 2.5 times the data rate be used to ensure that sufficient samples are taken of the input data while filtering system noise. The free design tool ADIsimPLL can be used to design loop filters for the ADF7020-1. Voltage Regulators N Counter The ADF7020-1 contains four regulators to supply stable voltages to the part. The nominal regulator voltage is 2.3 V. Each regulator should have a 100 nF capacitor connected between CREG and GND. When CE is high, the regulators and other associated circuitry are powered on, drawing a total supply current of 2 mA. Bringing the chip-enable pin low disables the regulators, reduces the supply current to less than 1 μA, and erases all values held in the registers. The serial interface operates from a regulator supply; therefore, to write to the part, the user must have CE high and the regulator voltage must be stabilized. Regulator status (CREG4) can be monitored using the regulator ready signal from muxout. The feedback divider in the ADF7020-1 PLL consists of an 8-bit integer counter and a 15-bit Σ-Δ fractional-N divider. The integer counter is the standard pulse-swallow type common in PLLs. This sets the minimum integer divide value to 31. The fractional divide value gives very fine resolution at the output, where the output frequency of the PLL is calculated as FOUT = Fractional − N XTAL × (Integer − N + ) 215 R REFERENCE IN 4\R PFD/ CHARGE PUMP VCO Loop Filter The loop filter integrates the current pulses from the charge pump to form a voltage that tunes the output of the VCO to the desired frequency. It also attenuates spurious levels generated by the PLL. A typical loop-filter design is shown in Figure 22. 4\N FRACTIONAL-N INTEGER-N 05669-023 THIRD-ORDER Σ-Δ MODULATOR Figure 23. Fractional-N PLL VCO The combination of the integer-N (maximum = 255) and the fractional-N (maximum = 16,383/16,384) give a maximum N divider of 255 + 1. Therefore, the minimum usable PFD is 05669-022 CHARGE PUMP OUT Figure 22. Typical Loop-Filter Configuration In FSK, the loop should be designed so that the loop bandwidth (LBW) is approximately 5 times the data rate. Widening the LBW excessively reduces the time spent jumping between frequencies, but can cause insufficient spurious attenuation. For ASK systems, a wider LBW is recommended. The sudden large transition between two power levels might result in VCO pulling and can cause a wider output spectrum than is desired. By widening the LBW to more than 10 times the data rate, the amount of VCO pulling is reduced, because the loop settles quickly back to the correct frequency. The wider LBW might restrict the output power and data rate of ASK-based systems more than it would that of FSK-based systems. Narrow-loop bandwidths can result in the loop taking long periods of time to attain lock. Careful design of the loop filter is critical to obtaining accurate FSK/GFSK modulation. PFDMIN [Hz] = Maximum Required Output Frequency/(255 + 1) For example, when operating at 620 MHz, PFDMIN equals 2.42 MHz. Voltage Controlled Oscillator (VCO) The ADF7020-1 features an on-chip VCO with external tank inductor, which is used to set the frequency range. The center frequency of the VCO is set by the internal varactor capacitance and the combined inductance of the external chip inductor, bond wire, and PCB track. A plot of VCO operating range vs. total external inductance (chip inductor + PCB track) is shown in Figure 24. The inductance for a PCB track using FR4 material is approximately 0.57 nH/mm. This should be subtracted from the total value to determine the correct chip inductor value. An additional frequency divide-by-2 block is included to allow operation from 80 MHz to 325 MHz. To enable the divide-by-2 block, set R1_DB13 to 1. Rev. 0 | Page 16 of 48 ADF7020-1 The VCO can be recentered, depending on the required frequency of operation, by programming the VCO adjust bits R1_DB (20:21). CHOOSING CHANNELS FOR BEST SYSTEM PERFORMANCE The fractional-N PLL allows the selection of any channel within 80 MHz to 650 MHz to a resolution of <300 Hz. This also facilitates frequency-hopping systems. The VCO is enabled as part of the PLL by the PLL-enable bit, R0_DB28. Careful selection of the RF transmit channels must be made to achieve best spurious performance. The architecture of fractional-N results in some level of the nearest integer channel moving through the loop to the RF output. These beat-note spurs are not attenuated by the loop if the desired RF channel and the nearest integer channel are separated by a frequency of less than the LBW. The VCO needs an external 22 nF between the VCO and the regulator to reduce internal noise. 750 700 FREQUENCY (MHz) 650 FMAX (MHz) 600 550 The occurrence of beat-note spurs is rare, because the integer frequencies are at multiples of the reference, which is typically >10 MHz. 500 450 400 350 300 250 200 0 5 The amplitude of beat-note spurs can be significantly reduced by using the frequency doubler to avoid very small or very large values in the fractional register. By having a channel 1 MHz away from an integer frequency, a 100 kHz loop filter can reduce the level to <−45 dBc. 05669-024 FMIN (MHz) 10 15 20 25 30 TOTAL EXTERNAL INDUCTANCE (nH) Figure 24. External Inductance vs. Frequency VCO Bias Current VCO bias current can be adjusted using Bits R1_DB19 to R1_DB16. To minimize current consumption, the bias current setting should be as indicated in Table 5. Table 5. Recommended VCO Bias Currents Direct Frequency Output (f) f < 200 MHz 200 MHz < f < 450 MHz f > 450 MHz VCO BIAS R1_DB (16:19) LOOP FILTER VCO Bias R1_DB(19:16) 0001 0010 0011 TO N DIVIDER VCO ÷2 ÷2 MUX TO PA 220μF VCO SELECT BIT 05669-025 CVCO PIN Figure 25. Voltage Controlled Oscillator (VCO) Rev. 0 | Page 17 of 48 ADF7020-1 TRANSMITTER RF OUTPUT STAGE The PA of the ADF7020-1 is based on a single-ended, controlled current, open-drain amplifier that has been designed to deliver up to 13 dBm into a 50 Ω load at a maximum frequency of 650 MHz. The PA output current and, consequently, the output power are programmable over a wide range. The PA configurations in FSK/GFSK and ASK/OOK modulation modes are shown in Figure 26 and Figure 27, respectively. In FSK/GFSK modulation mode, the output power is independent of the state of the DATA_IO pin. In ASK/OOK modulation mode, it is dependent on the state of the DATA_IO pin and Bit R2_DB29, which selects the polarity of the TxData input. For each transmission mode, the output power can be adjusted as follows: • The PA is equipped with overvoltage protection, which makes it robust in severely mismatched conditions. Depending on the application, users can design a matching network for the PA to exhibit optimum efficiency at the desired radiated output power level for a wide range of different antennas, such as loop or monopole antennas. See the LNA/PA Matching section for details. PA Bias Currents Control Bits R2_DB (30:31) facilitate an adjustment of the PA bias current to further extend the output power control range, if necessary. If this feature is not required, the default value of 9 μA is recommended. The output stage is powered down by resetting Bit R2_DB4. To reduce the level of undesired spurious emissions, the PA can be muted during the PLL lock phase by toggling this bit. MODULATION SCHEMES FSK/GFSK: The output power is set using bits R2_DB (9:14). Frequency Shift Keying (FSK) • ASK: The output power for the inactive state of the TxData input is set by Bits R2_DB (15:20). The output power for the active state of the TxData input is set by Bits R2_DB (9:14). • OOK: The output power for the active state of the TxData input is set by Bits R2_DB (9:14). The PA is muted when the TxData input is inactive. Frequency shift keying is implemented by setting the N value for the center frequency and then toggling this with the TxData line. The deviation from the center frequency is set using Bits R2_DB (15:23). The deviation from the center frequency in hertz is FSK DEVIATION [Hz] = PFD × Modulation Number 214 R2_DB(30:31) where Modulation Number is a number from 1 to 511 (R2_DB (15:23)). 2 IDAC 6 R2_DB(9:14) Select FSK using Bits R2_DB (6:8). RFOUT R2_DB4 + DIGITAL LOCK DETECT RFGND FROM VCO 05669-026 R2_DB5 Figure 26. PA Configuration in FSK/GFSK Mode 4R PFD/ CHARGE PUMP PA STAGE VCO FSK DEVIATION FREQUENCY ÷N ASK/OOK MODE DATA I/O R2_DB29 +FDEV 6 IDAC 6 TxDATA R2_DB(9:14) FRACTIONAL-N 6 R2_DB4 R2_DB5 DIGITAL LOCK DETECT RFGND FROM VCO 05669-027 + INTEGER-N Figure 28. FSK Implementation R2_DB(15:23) 0 RFOUT THIRD-ORDER Σ-Δ MODULATOR Figure 27. PA Configuration in ASK/OOK Mode Rev. 0 | Page 18 of 48 05669-028 –FDEV R2_DB(30:31) ADF7020-1 Gaussian Frequency Shift Keying (GFSK) Amplitude Shift Keying (ASK) Gaussian frequency shift keying reduces the bandwidth occupied by the transmitted spectrum by digitally prefiltering the TxData. A TxCLK output line is provided from the ADF7020-1 for synchronization of TxData from the microcontroller. The TxCLK line can be connected to the clock input of a shift register that clocks data to the transmitter at the exact data rate. Amplitude shift keying is implemented by switching the output stage between two discrete power levels. This is accomplished by toggling the DAC, which controls the output level between two 6-bit values set up in Register 2. A 0 TxData bit sends Bits R2_DB (15:20) to the DAC. A high TxData bit sends Bits R2_DB (9:14) to the DAC. A maximum modulation depth of 30 dB is possible. Setting Up the ADF7020-1 for GFSK On-off keying is implemented by switching the output stage to a certain power level for a high TxData bit and switching the output stage off for a low TxData bit. For OOK, the transmitted power for a high input is programmed using Bits R2_DB (9:14). To set up the frequency deviation, set the PFD and the modulator control bits according to the following equation: GFSK DEVIATION [Hz] = PFD × 2 m 212 Gaussian On-Off Keying (GOOK) where m is GFSK_MOD_CONTROL set using R2_DB (24:26). To set up the GFSK data rate, set the PFD and the modulator control bits according to the following equation: DR [bps] = On-Off Keying (OOK) PFD DIVIDER _ FACTOR × INDEX _ COUNTER Gaussian on-off keying represents a prefiltered form of OOK modulation. The usually sharp symbol transitions are replaced with smooth Gaussian filtered transitions, the result being a reduction in frequency pulling of the VCO. Frequency pulling of the VCO in OOK mode can lead to a wider than desired BW, especially if it is not possible to increase the loop-filter BW > 300 kHz. The GOOK sampling clock samples data at the data rate. (See the Setting Up the ADF7020-1 for GFSK section.) where DIVIDER_FACTOR and INDEX_COUNTER are programmed in Bits R2_DB (15:21) and R2_DB (27:28), respectively. For further information, see the Using GFSK on the ADF7010 section in the EVAL-ADF7010EB1 data sheet. Rev. 0 | Page 19 of 48 ADF7020-1 RECEIVER SECTION RF FRONT END The ADF7020-1 is based on a fully integrated, low IF receiver architecture. The low IF architecture facilitates a very low external component count and does not suffer from power-lineinduced interference problems. Figure 29 shows the structure of the receiver front end. The many programming options allow users to trade off sensitivity, linearity, and current consumption for each other in the most suitable way for their applications. To achieve a high level of resilience against spurious reception, the LNA features a differential input. Switch SW2 shorts the LNA input when transmit mode is selected (R0_DB27 = 0). This feature facilitates the design of a combined LNA/PA matching network, avoiding the need for an external Rx/Tx switch. See the LNA/PA Matching section for details on the design of the matching network. I (TO FILTER) RFIN Tx/Rx SELECT [R0_DB27] RFINB SW2 LNA LO Q (TO FILTER) LNA MODE [R6_DB15] MIXER LINEARITY [R6_DB18] LNA CURRENT [R6_DB(16:17)] 05669-029 LNA GAIN [R9_DB(20:21)] LNA/MIXER ENABLE [R8_DB6] Figure 29. ADF7020-1 RF Front End The LNA is followed by a quadrature down conversion mixer, which converts the RF signal to the IF frequency of 200 kHz. It is important to consider that the output frequency of the synthesizer must be programmed to a value 200 kHz below the center frequency of the received channel. The LNA has two basic operating modes: high gain/low noise mode and low gain/low power mode. To switch between these two modes, use the LNA_mode bit, R6_DB15. The mixer is also configurable between a low current and an enhanced linearity mode using the mixer_linearity bit, R6_DB18. Based on the specific sensitivity and linearity requirements of the application, it is recommended to adjust control bits LNA_mode (R6_DB15) and mixer_linearity (R6_DB18) as outlined in Table 6. The gain of the LNA is configured by the LNA_gain field, R9_DB (20:21), and can be set by either the user or the automatic gain control (AGC) logic. IF Filter Settings/Calibration Out-of-band interference is rejected by means of a fourth-order Butterworth polyphase IF filter centered around a frequency of 200 kHz. The bandwidth of the IF filter can be programmed between 100 kHz and 200 kHz by means of Control Bits R1_DB (22:23); it should be chosen as a compromise between interference rejection, attenuation of the desired signal, and the AFC pull-in range. To compensate for manufacturing tolerances, the IF filter should be calibrated once after power-up. The IF filter calibration logic requires that the IF filter divider in Bits R6_DB (20:28) be set dependent on the crystal frequency. Once initiated by setting Bit R6_DB19, the calibration is performed automatically without any user intervention. The calibration time is 200 μs, during which the ADF7020-1 should not be accessed. It is important not to initiate the calibration cycle before the crystal oscillator has fully settled. If the AGC loop is disabled, the gain of IF filter can be set to three levels using the filter_gain field, R9_DB (22:23). The filter gain is adjusted automatically, if the AGC loop is enabled. Table 6. LNA/Mixer Modes Receiver Mode High Sensitivity Mode (default) RxMode2 Low Current Mode Enhanced Linearity Mode RxMode5 RxMode6 LNA Mode (R6_DB15) 0 1 1 1 1 0 LNA Gain Value R9_DB (21:20) 30 10 3 3 10 30 Mixer Linearity (R6_DB18) 0 0 0 1 1 1 Rev. 0 | Page 20 of 48 Sensitivity (DR = 9.6 kbps, fDEV = 10 kHz) −112.5 −105.8 −92.2 −102.5 −99 −105 Rx Current Consumption (mA) 20.1 19.0 17.6 17.6 19.0 20.1 Input IP3 (dBm) −35 −15.9 −3.2 +6.8 −8.25 −28.8 ADF7020-1 RSSI/AGC AGC _ Wait _ Time = The RSSI is implemented as a successive compression log amp following the base-band channel filtering. The log amp achieves ±3 dB log linearity. It also doubles as a limiter to convert the signal-to-digital levels for the FSK demodulator. The RSSI itself is used for amplitude shift keying (ASK) demodulation. In ASK mode, extra digital filtering is performed on the RSSI value. Offset correction is achieved using a switched capacitor integrator in feedback around the log amp. This uses the BB offset clock divide. The RSSI level is converted for user readback and digitally controlled AGC by an 80-level (7-bit) flash ADC. This level can be converted to input power in dBm. IFWR A IFWR A IFWR LATCH IFWR FSK DEMOD CLK ADC RSSI ASK DEMOD R 05669-030 A AGC Settling = AGC_Wait_Time × Number of Gain Changes Thus, in the worst case, if the AGC loop has to go through all five gain changes, AGC delay = 10, and SEQ_CLK = 200 kHz, then AGC settling = 10 × 5 μs × 5 = 250 μs. Minimum AGC_Wait_Time must be at least 25 μs. RSSI Formula (Converting to dBm) Input_Power [dBm] = −120 dBm + (Readback_Code + Gain_Mode_Correction) × 0.5 where: Readback_Code is given by Bits RV7 to RV1 in the readback register (see Readback Format section). Gain_Mode_Correction is given by the values in Table 7. LNA gain and filter gain (LG2/LG1, FG2/FG1) are also obtained from the readback register. OFFSET CORRECTION 1 AGC _ DELAY × SEQ _ CLK _ DIVIDE XTAL Figure 30. RSSI Block Diagram RSSI Thresholds When the RSSI is above AGC_HIGH_THRESHOLD, the gain is reduced. When the RSSI is below AGC_LOW_THRESHOLD, the gain is increased. A delay (AGC_DELAY) is programmed to allow for settling of the loop. The user programs the two threshold values (recommended defaults, 30 and 70) and the delay (default, 10). The default AGC set-up values should be adequate for most applications. The threshold values must be more than 30 settings apart for the AGC to operate correctly. Table 7. Gain Mode Correction LNA Gain (LG2, LG1) H (1, 1) M (1, 0) M (1, 0) M (1, 0) L (0, 1) EL (0, 0) Filter Gain (FG2, FG1) H (1, 0) H (1, 0) M (0, 1) L (0, 0) L (0, 0) L (0, 0) Gain Mode Correction 0 24 45 63 90 105 An additional factor should be introduced to account for losses in the front-end matching network/antenna. FSK DEMODULATORS ON THE ADF7020-1 Offset Correction Clock The two FSK demodulators on the ADF7020-1 are In Register 3, the user should set the BB offset clock divide bits R3_DB (4:5) to give an offset clock between 1 MHz and 2 MHz, where: • FSK correlator/demodulator • Linear demodulator BBOS_CLK (Hz) = XTAL/(BBOS_CLK_DIVIDE) Select these using the demodulator select bits, R4_DB (4:5). BBOS_CLK_DIVIDE can be set to 4, 8, or 16. FSK CORRELATOR/DEMODULATOR AGC Information and Timing The quadrature outputs of the IF filter are first limited and then fed to a pair of digital frequency correlators that perform bandpass filtering of the binary FSK frequencies at (IF + FDEV) and (IF − FDEV). Data is recovered by comparing the output levels from each of the two correlators. The performance of this frequency discriminator approximates that of a matched filter detector, which is known to provide optimum detection in the presence of AWGN. AGC is selected by default, and operates by selecting the appropriate LNA and filter gain settings for the measured RSSI level. It is possible to disable AGC by writing to Register 9 if you want to enter one of the modes listed in Table 6, for example. The time for the AGC circuit to settle and hence the time it takes to take an accurate RSSI measurement is typically 150 μs, although this depends on how many gain settings the AGC circuit has to cycle through. After each gain change, the AGC loop waits for a programmed time to allow transients to settle. This wait time can be adjusted to speed up this settling by adjusting the appropriate parameters. Rev. 0 | Page 21 of 48 ADF7020-1 LIMITERS Q IF – FDEV IF + FDEV SLICER POST DEMOD FILTER IF DATA SYNCHRONIZER FREQUENCY CORRELATOR I Rx DATA Rx CLK DB(4:13) DB(14) 05669-031 0 DB(8:15) Figure 31. FSK Correlator/Demodulator Block Diagram Postdemodulator Filter A second-order digital low-pass filter removes excess noise from the demodulated bit stream at the output of the discriminator. The bandwidth of this postdemodulator filter is programmable and must be optimized for the user’s data rate. If the bandwidth is set too narrow, performance is degraded due to intersymbol interference (ISI). If the bandwidth is set too wide, excess noise degrades the receiver’s performance. Typically, the 3 dB bandwidth of this filter is set at approximately 0.75 times the user’s data rate, using Bits R4_DB (6:15). Bit Slicer The received data is recovered by the threshold detecting the output of the postdemodulator low-pass filter. In the correlator/ demodulator, the binary output signal levels of the frequency discriminator are always centered on zero. Therefore, the slicer threshold level can be fixed at zero, and the demodulator performance is independent of the run-length constraints of the transmit data bit stream. This results in robust data recovery, which does not suffer from the classic baseline wander problems that exist in the more traditional FSK demodulators. Frequency errors are removed by an internal AFC loop that measures the average IF frequency at the limiter output and applies a frequency correction value to the fractional-N synthesizer. This loop should be activated when the frequency errors are greater than approximately 40% of the transmit frequency deviation (see the AFC Section). where: DEMOD_CLK is as defined in the Register 3—Receiver Clock Register section, Note 2. K = round(200e3/FSK deviation) To optimize the coefficients of the FSK correlator, two additional bits, R6_DB14 and R6_DB29, must be assigned. The value of these bits depends on whether K (as defined above) is odd or even. These bits are assigned according to the conditions listed in Table 8 and Table 9. Table 8. When K Is Even K Even Even K Odd Odd The discriminator BW is controlled in Register 6 by R6_DB (4:13) and is defined as R6_DB29 0 1 (K + 1)/2 Even Odd R6_DB14 1 1 R6_DB29 0 1 Postdemodulator Bandwidth Register Settings The 3 dB bandwidth of the postdemodulator filter is controlled by Bits R4_ DB (6:15) and is given by Post _ Demod _ BW _ Setting = 2 10 × 2 π × FCUTOFF DEMOD _ CLK where FCUTOFF is the target 3 dB bandwidth in hertz of the postdemodulator filter. This should typically be set to 0.75 times the data rate (DR). Some sample settings for the FSK correlator/demodulator are DEMOD_CLK = 5 MHz DR = 9.6 kbps FDEV = 20 kHz Therefore FCUTOFF = 0.75 × 9.6 × 103 Hz Post_Demod_BW = 211 π 7.2 × 103 Hz/(5 MHz) Post_Demod_BW = Round(9.26) = 9 and K = Round(200 kHz)/20 kHz) = 10 Discriminator_BW = (5 MHz × 10)/(800 × 103) = 62.5 = 63 (rounded to nearest integer) FSK Correlator Register Settings To enable the FSK correlator/demodulator, Bits R4_DB (5:4) should be set to [01]. To achieve best performance, the bandwidth of the FSK correlator must be optimized for the specific deviation frequency that is used by the FSK transmitter. R6_DB14 0 0 Table 9. When K Is Odd Data Synchronizer An oversampled digital PLL is used to resynchronize the received bit stream to a local clock. The oversampled clock rate of the PLL (CDR_CLK) must be set at 32 times the data rate. See the notes for the Register 3—Receiver Clock Register section for a definition of how to program the various on-chip clocks. The clock recovery PLL can accommodate frequency errors of up to ±2%. K/2 Even Odd Table 10. Register Settings Setting Name Post_Demod_BW Discriminator_BW Dot Product Rx Data Invert Discriminator _ BW = (DEMOD _ CLK × K ) /(800 × 10 3 ) Rev. 0 | Page 22 of 48 Register Address R4_DB (6:15) R6_DB (4:13) R6_DB14 R6_DB29 Value 0x09 0x3F 0 1 ADF7020-1 LINEAR FSK DEMODULATOR Post_Demod_BW_Setting = Figure 32 shows a block diagram of the linear FSK demodulator. 7 LEVEL Q FREQUENCY LINEAR DISCRIMINATOR FREQUENCY READBACK AND AFC LOOP DB(6:15) 05669-032 LIMITER ENVELOPE DETECTOR Rx DATA IF AVERAGING FILTER I Figure 32. Block Diagram of Frequency Measurement System and ASK/OOK/Linear FSK Demodulator This method of frequency demodulation is useful when very short preamble length is required and the system protocol cannot support the overhead of the settling time of the internal feedback AFC loop settling. A digital frequency discriminator provides an output signal that is linearly proportional to the frequency of the limiter outputs. The discriminator output is then filtered and averaged using a combined averaging filter and envelope detector. The demodulated FSK data is recovered by comparing the filter output with its average value, as shown in Figure 32. In this mode, the slicer output shown in Figure 32 is routed to the data synchronizer PLL for clock synchronization. To enable the linear FSK demodulator, set Bits R4_DB (4:5) to [00]. The 3 dB bandwidth of the postdemodulation filter is set in the same way as the FSK correlator/demodulator, which is set in R4_DB (6:15) and is defined as Post _ Demod _ BW _ Setting = DEMOD_CLK where FCUTOFF is the target 3 dB bandwidth in hertz of the postdemodulator filter. SLICER MUX 1 ADC RSSI OUTPUT 210 × 2π × FCUTOFF It is also recommended to use Manchester encoding in ASK/OOK mode to ensure the data run length limit (RLL) is 2 bits. If a longer RLL, up to a maximum of 4 bits, is required, users should disable the extra-low gain setting by writing 0x3C00C to the test mode register. AFC SECTION The ADF7020-1 supports a real-time AFC loop, which is used to remove frequency errors that can arise due to mismatches between the transmit and receive crystals. The AFC loop uses the frequency discriminator block as described in the Linear FSK Demodulator section (see Figure 32). The discriminator output is filtered and averaged to remove the FSK frequency modulation using a combined averaging filter and envelope detector. In FSK mode, the output of the envelope detector provides an estimate of the average IF frequency. Two methods of AFC, external and internal, are supported on the ADF7020-1 (in FSK mode only). External AFC The user reads back the frequency information through the ADF7020-1 serial port and applies a frequency correction value to the fractional-N synthesizer’s N divider. The frequency information is obtained by reading the 16-bit signed AFC_readback, as described in the Readback Format section, and applying the following formula: FREQ_RB [Hz] = (AFC_READBACK × DEMOD_CLK)/215 210 × 2π × FCUTOFF Note that while the AFC_READBACK value is a signed number, under normal operating conditions it is positive. In the absence of frequency errors, the FREQ_RB value is equal to the IF frequency of 200 kHz. DEMOD _ CLK where: FCUTOFF is the target 3 dB bandwidth in hertz of the postdemodulator filter. DEMOD_CLK is as defined in the Register 3—Receiver Clock Register section, Note 2. Internal AFC ASK/OOK demodulation is activated by setting Bits R4_DB (4:5) to [10]. The ADF7020-1 supports a real-time internal automatic frequency control loop. In this mode, an internal control loop automatically monitors the frequency error and adjusts the synthesizer N divider using an internal PI control loop. ASK/OOK demodulation is performed by digitally filtering the RSSI output, and then comparing the filter output with its average value in a similar manner to FSK demodulation. The bandwidth of the digital filter must be optimized to remove any excess noise without causing ISI in the received ASK/OOK signal. The internal AFC control loop parameters are controlled in Register 11. The internal AFC loop is activated by setting R11_DB20 to 1. A scaling coefficient must also be entered, based on the crystal frequency in use. This is set up in R11_DB (4:19) and should be calculated using ASK/OOK Operation The 3 dB bandwidth of this filter is typically set at approximately 0.75 times the user data rate and is assigned by R4 _DB (6:15) as AFC_Scaling_Coefficient = (500 × 224)/XTAL Therefore, using a 10 MHz XTAL yields an AFC scaling coefficient of 839. Rev. 0 | Page 23 of 48 ADF7020-1 AFC Performance The improved sensitivity performance of the Rx when AFC is enabled and in the presence of frequency errors is shown in Figure 18. The maximum AFC pull-in range is ±50 kHz, which corresponds to ±58 ppm at 868 MHz. This is the total error tolerance allowed in the link. For example, in a point-to-point system, AFC can compensate for two ±29 ppm crystals or one ±50 ppm crystal and one ±8 ppm TCXO. AFC settling typically takes 48 bits to settle within ±1 kHz. This can be improved by increasing the postdemodulator bandwidth in Register 4 at the expense of Rx sensitivity. When AFC errors have been removed using either the internal or external AFC, further improvement in the receiver’s sensitivity can be obtained by reducing the IF filter bandwidth using Bits R1_DB (22:23). AUTOMATIC SYNC WORD RECOGNITION The ADF7020-1 also supports automatic detection of the sync or ID fields. To activate this mode, the sync (or ID) word must be preprogrammed in the ADF7020-1. In receive mode, this preprogrammed word is compared to the received bit stream, and the external pin INT/LOCK is asserted by the ADF7020-1 when a valid match is identified. This feature can be used to alert the microprocessor that a valid channel has been detected. It relaxes the computational requirements of the microprocessor and reduces the overall power consumption. The INT/LOCK is automatically deasserted again after nine data clock cycles. The automatic sync/ID word detection feature is enabled by selecting Demodulator Mode 2 or 3 in the demodulator set-up register. Do this by setting R4_DB (25:23) = [010] or [011]. Bits R5_DB (4:5) are used to set the length of the sync/ID word, which can be 12, 16, 20, or 24 bits long. The transmitter must transmit the MSB of the sync byte first and the LSB last to ensure proper alignment in the receiver sync byte detection hardware. For systems using FEC, an error tolerance parameter can also be programmed that accepts a valid match when up to three bits of the word are incorrect. The error tolerance value is assigned in R5_DB (6:7). Table 11. Sensitivity Values for Varying RF Frequency and Data Rates Frequency 135 MHz 135 MHz 315 MHz 315 MHz 610 MHz 610 MHz Data Rate (NRZ) 9.6 kbps 1.0 kbps 9.6 kbps 1.0 kbps 9.6 kbps 1.0 kbps Deviation in FSK Mode ±10 kHz ±5 kHz ±10 kHz ±5 kHz ±10 kHz ±5 kHz FSK Sensitivity at BER = 1E-3, Correlator Demodulator −113.2 dBm −119.5 dBm −114.2 dBm −120 dBm −113.2 dBm −119.8 dBm Rev. 0 | Page 24 of 48 FSK Sensitivity at BER = 1E-3, Linear Demodulator −106.2 dBm −109.2 dBm −108.0 dBm −110.1 dBm −107.0 dBm −109.0 dBm ASK Sensitivity at BER = 1E-3 −110.8 −116.8 dBm −111.8 dBm −118 dBm −110.5 dBm −116.8 dBm ADF7020-1 APPLICATIONS LNA/PA MATCHING The ADF7020-1 exhibits optimum performance in terms of sensitivity, transmit power, and current consumption only if its RF input and output ports are properly matched to the antenna impedance. For cost-sensitive applications, the ADF7020-1 is equipped with an internal Rx/Tx switch, which facilitates the use of a simple combined passive PA/LNA matching network. Alternatively, an external Rx/Tx switch, such as the Analog Devices ADG919, can be used, which yields a slightly improved receiver sensitivity and lower transmitter power consumption. External Rx/Tx Switch Figure 33 shows a configuration using an external Rx/Tx switch. This configuration allows an independent optimization of the matching and filter network in the transmit and receive path and is therefore more flexible and less difficult to design than the configuration using the internal Rx/Tx switch. The PA is biased through Inductor L1, and C1 blocks the dc current. Both elements, L1 and C1, also form the matching network, which transforms the source impedance into the optimum PA load impedance, ZOPT_PA. VBAT L1 PA_OUT OPTIONAL LPF PA ANTENNA in a back-to-back configuration. Due to the asymmetry of the network with respect to ground, a compromise between the input reflection coefficient and the maximum differential signal swing at the LNA input must be established. The use of appropriate CAD software is strongly recommended for this optimization. Depending on the antenna configuration, the user might need a harmonic filter at the PA output to satisfy the spurious emission requirement of the applicable government regulations. The harmonic filter can be implemented in various ways, such as a discrete LC pi or T-stage filter. The immunity of the ADF7020-1 to strong out-of-band interference can be improved by adding a band-pass filter in the Rx path, or alternatively by selecting one of the high linearity modes outlined in Table 6. Internal Rx/Tx Switch Figure 34 shows the ADF7020-1 in a configuration where the internal Rx/Tx switch is used with a combined LNA/PA matching network. This is the configuration used in the ADF7020-1DBX Evaluation boards. For most applications, the slight performance degradation of 1 dB to 2 dB caused by the internal Rx/Tx switch is acceptable, allowing the user to take advantage of the cost saving potential of this solution. The design of the combined matching network must compensate for the reactance presented by the networks in the Tx and the Rx paths, taking the state of the Rx/Tx switch into consideration. ZOPT_PA VBAT ZIN_RFIN CA RFIN L1 PA_OUT PA ADG919 LNA RFINB ANTENNA ZIN_RFIN CA ZIN_RFIN CB ZOPT_PA OPTIONAL BPF OR LPF ADF7020-1 RFIN LA Figure 33. ADF7020-1 with External Rx/Tx Switch ZOPT_PA depends on various factors, such as the required output power, the frequency range, the supply voltage range, and the temperature range. Selecting an appropriate ZOPT_PA helps to minimize the Tx current consumption in the application. The Specifications section lists a number of ZOPT_PA values for representative conditions. Under certain conditions, however, it is recommended to obtain a suitable ZOPT_PA value by means of a load-pull measurement. Due to the differential LNA input, the LNA matching network must be designed to provide both a single-ended to differential conversion and a complex conjugate impedance match. The network with the lowest component count that can satisfy these requirements is the configuration shown in Figure 33, which consists of two capacitors and one inductor. A first-order implementation of the matching network can be obtained by understanding the arrangement as two L type matching networks LNA RFINB ZIN_RFIN CB ADF7020-1 05669-034 LA Rx/Tx – SELECT C1 05669-033 OPTIONAL BPF (SAW) Figure 34. ADF7020-1 with Internal Rx/Tx Switch The procedure typically requires several iterations until an acceptable compromise is reached. The successful implementation of a combined LNA/PA matching network for the ADF7020-1 is critically dependent on the availability of an accurate electrical model for the PC board. In this context, the use of a suitable CAD package is strongly recommended. To avoid this effort, however, a small form-factor reference design for the ADF7020-1 is provided, including matching and harmonic filter components. The design is on a 2-layer PCB to minimize cost. Gerber files are available on the www.analog.com website. Rev. 0 | Page 25 of 48 ADF7020-1 TRANSMIT PROTOCOL AND CODING CONSIDERATIONS DATA FIELD CRC Figure 35. Typical Format of a Transmit Protocol A dc-free preamble pattern is recommended for FSK/ASK/ OOK demodulation. The recommended preamble pattern is a dc-free pattern such as a 10101010 … pattern. Preamble patterns with longer run-length constraints, such as 11001100…, can also be used. However, this results in a longer synchronization time of the received bit stream in the receiver. Manchester coding can be used for the entire transmit protocol. However, the remaining fields that follow the preamble header do not have to use dc-free coding. For these fields, the ADF7020-1 can accommodate coding schemes with a runlength of up to 6 bits without any performance degradation. If longer run-length coding must be supported, the ADF7020-1 has several other features that can be activated. These involve a range of programmable options that allow the envelope detector output to be frozen after preamble acquisition. MISO Table 12 lists the minimum number of writes needed to set up the ADF7020-1 in either Tx or Rx mode after CE is brought high. Additional registers can also be written to tailor the part to a particular application, such as setting up sync byte detection or enabling AFC. When going from Tx to Rx or vice versa, the user needs to write only to the N register to alter the LO by 200 kHz and to toggle the Tx/Rx bit. Table 12. Minimum Register Writes Required for Tx/Rx Setup Reg 0 Reg 0 Reg 1 Reg 1 Registers Reg 2 Reg 2 Reg 4 Reg 6 Reg 0 Reg 1 Reg 2 Reg 4 Reg 6 Reg 0 Figure 38 and Figure 39 show the recommended programming sequence and associated timing for power-up from standby mode. Rev. 0 | Page 26 of 48 TxRxDATA MOSI SCLOCK RxCLK SS P3.7 P3.2/INT0 GPIO CE INT/LOCK P2.4 SREAD P2.5 SLE P2.6 SDATA P2.7 SCLK Figure 36.ADuC84x to ADF7020-1 Connection Diagram ADSP-BF533 SCK ADF7020-1 SCLK MOSI SDATA MISO SREAD PF5 RSCLK1 DT1PRI SLE TxRxCLK TxRxDATA DR1PRI RFS1 DEVICE PROGRAMMING AFTER INITIAL POWER-UP Mode Tx Rx (OOK) Rx (G/FSK) Tx <-> Rx ADF7020-1 ADuC84x 05669-036 ID FIELD Low level device drivers are available for interfacing to the ADF7020-1, the ADI ADuC84x microcontroller parts, or the Blackfin ADSP-BF53x DSPs using the hardware connections shown in Figure 36 and Figure 37. INT/LOCK PF6 CE VCC VCC GND GND Figure 37.ADSP-BF533 to ADF7020-1 Connection Diagram 05669-037 SYNC WORD 05669-035 PREAMBLE INTERFACING TO MICROCONTROLLER/DSP ADF7020-1 IDD ADF7020-1 17.6mA TO 20.1mA 14mA _XTAL T0 3.65mA 2.0mA AFC T10 T1 WR3 WR4 WR6 WR0 WR1 T2 T3 VCO T4 T5 T6 AGC/ RSSI T7 T8 CDR T9 TIME RxDATA T11 TON 05669-038 REG. READY TOFF Figure 38. Rx Programming Sequence and Timing Diagram Table 13. Power-Up Sequence Description Parameter T0 Value 2 ms T1 10 μs T2, T3, T5, T6, T7 T4 32 × 1/SPI_CLK 1 ms T8 150 μs T9 5 × Bit_Period T10 16 × Bit_Period T11 Packet Length Description/Notes Crystal starts power-up after CE is brought high. This typically depends on the crystal type and the load capacitance specified. Time for regulator to power up. The serial interface can be written to after this time. Time to write to a single register. Maximum SPI_CLK is 25 MHz. The VCO can power-up in parallel with the crystal. This depends on the CVCO capacitance value used. A value of 22 nF is recommended as a trade-off between phase noise performance and power-up time. This depends on the number of gain changes the AGC loop needs to cycle through and AGC settings programmed. This is described in more detail in the AGC Information and Timing section. This is the time for the clock and data recovery circuit to settle. This typically requires 5-bit transitions to acquire sync and is usually covered by the preamble. This is the time for the automatic frequency control circuit to settle. This typically requires 16-bit transitions to acquire lock and is usually covered by an appropriate length preamble. Number of bits in payload by the bit period. Rev. 0 | Page 27 of 48 Signal to Monitor CLKOUT pin MUXOUT pin CVCO pin Analog RSSI on TEST_A pin (available by writing 0x3800 000C) ADF7020-1 IDD ADF7020-1 15mA TO 30mA 14mA 3.65mA 2.0mA T1 WR0 WR1 T2 T3 WR2 XTAL + VCO T4 TIME TxDATA T5 T12 TON Figure 39. Tx Programming Sequence and Timing Diagram Rev. 0 | Page 28 of 48 TOFF 05669-039 REG. READY ADF7020-1 SERIAL INTERFACE RSSI Readback The serial interface allows the user to program the eleven 32-bit registers using a 3-wire interface (SCLK, SDATA, and SLE). It consists of a voltage level shifter, a 32-bit shift register, and 11 latches. Signals should be CMOS compatible. The serial interface is powered by the regulator and therefore is inactive when CE is low. The RSSI readback operation yields valid results in Rx mode with ASK or FSK signals. The format of the readback word is shown in Figure 40. It is comprised of the RSSI level information (Bits RV1 to RV7), the current filter gain (FG1, FG2), and the current LNA gain (LG1, LG2) setting. The filter and LNA gain are coded in accordance with the definitions in Register 9. With the reception of ASK modulated signals, averaging of the measured RSSI values improves accuracy. The input power can be calculated from the RSSI readback value as outlined in the RSSI/AGC. Data is clocked into the register MSB first on the rising edge of each clock (SCLK). Data is transferred to one of the 11 latches on the rising edge of SLE. The destination latch is determined by the value of the four control bits (C4 to C1). These are the bottom 4 LSB, DB3 to DB0, as shown in the timing diagram in Figure 2. Data can also be read back on the SREAD pin. Battery Voltage ADCIN/Temperature Sensor Readback The battery voltage is measured at Pin VDD4. The readback information is contained in Bits RV1 to RV7. This also applies for the readback of the voltage at the ADCIN pin and the temperature sensor. From the readback information, the battery or ADCIN voltage can be determined using READBACK FORMAT The readback operation is initiated by writing a valid control word to the readback register and setting the readback-enable bit (R7_DB8 = 1). The readback can begin after the control word has been latched with the SLE signal. SLE must be kept high while the data is read out. Each active edge at the SCLK pin clocks the readback word out successively at the SREAD pin, as shown in Figure 3, starting with the MSB first. The data appearing at the first clock cycle following the latch operation must be ignored. VBATTERY = (Battery_Voltage_Readback)/21.1 VADCIN = (ADCIN_Voltage_Readback)/42.1 Silicon Revision Readback The silicon revision readback word is valid without setting any other registers, especially directly after power-up. The silicon revision word is coded with four quartets in BCD format. The product code (PC) is coded with three quartets extending from Bits RV5 to RV16. The revision code (RV) is coded with one quartet extending from Bits RV1 to RV4. The product code for the ADF7020-1 should read back as PC = 0x200. The current revision code should read back as RC = 0x6. AFC Readback The AFC readback is valid only during the reception of FSK signals with either the linear or correlator demodulator active. The AFC readback value is formatted as a signed 16-bit integer comprised of Bits RV1 to RV16 and is scaled according to the following formula: FREQ_RB [Hz] = (AFC_READBACK × DEMOD_CLK)/215 Filter Calibration Readback The filter calibration readback word is contained in Bits RV1 to RV8 and is for diagnostic purposes only. Using the automatic filter calibration function, accessible through Register 6, is recommended. Before filter calibration is initiated Decimal 32 should be read back. In the absence of frequency errors, the FREQ_RB value is equal to the IF frequency of 200 kHz. Note that the down-converted input signal must not fall outside the bandwidth of the analogue IF filter for the AFC readback to yield a valid result. At lowinput signal levels, the variation in the readback value can be improved by averaging. READBACK MODE DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 AFC READBACK RV16 RV15 RV14 RV13 RV12 RV11 RV10 RV9 RV8 RV7 RV6 RV5 RV4 RV3 RV2 RV1 RSSI READBACK X X X X X LG2 LG1 FG2 FG1 RV7 RV6 RV5 RV4 RV3 RV2 RV1 BATTERY VOLTAGE/ADCIN/ TEMP. SENSOR READBACK X X X X X X X X X RV7 RV6 RV5 RV4 RV3 RV2 RV1 SILICON REVISION RV16 RV15 RV14 RV13 RV12 RV11 RV10 RV9 RV8 RV7 RV6 RV5 RV4 RV3 RV2 RV1 FILTER CAL READBACK 0 0 0 0 0 0 0 0 RV8 RV7 RV6 RV5 RV4 RV3 RV2 RV1 Figure 40. Readback Value Table Rev. 0 | Page 29 of 48 05669-040 READBACK VALUE ADF7020-1 M14 M13 ... M3 M2 M1 FRACTIONAL DIVIDE RATIO 0 0 0 . . . 1 1 1 1 0 0 0 . . . 1 1 1 1 0 0 0 . . . 1 1 1 1 ... ... ... ... ... ... ... ... ... ... 0 0 0 . . . 1 1 1 1 0 0 1 . . . 0 0 1 1 0 1 0 . . . 0 1 0 1 0 1 2 . . . 32764 32765 32766 32767 N7 N6 N5 N4 N3 N2 N1 N COUNTER DIVIDE RATIO 0 0 . . . 1 0 0 . . . 1 0 1 . . . 1 1 0 . . . 1 1 0 . . . 1 1 0 . . . 1 1 0 . . . 0 1 0 . . . 1 31 32 . . . 253 1 1 1 1 1 1 1 0 254 1 1 1 1 1 1 1 1 255 Figure 41. Notes 1. The Tx/Rx bit (R0_DB27) configures the part in Tx or Rx mode and also controls the state of the internal Tx/Rx switch. 2. FOUT = Rev. 0 | Page 30 of 48 05669-041 M15 N8 XTAL Fractional -N × ( Integer-N + ). R 215 C1 (0) DB0 C2 (0) DB1 C3 (0) DB2 C4 (0) DB3 DB4 DB12 M9 M1 DB13 DB5 DB14 M11 M10 DB6 DB15 M12 M2 DB16 M13 REGULATOR READY (DEFAULT) R DIVIDER OUTPUT N DIVIDER OUTPUT DIGITAL LOCK DETECT ANALOG LOCK DETECT THREE-STATE PLL TEST MODES Σ-Δ TEST MODES M3 DB17 M14 MUXOUT 0 1 0 1 0 1 0 1 DB7 DB18 M15 M1 0 0 1 1 0 0 1 1 M4 DB19 N1 M2 0 0 0 0 1 1 1 1 DB8 DB20 N2 M3 M5 DB21 N3 PLL OFF PLL ON DB9 DB22 N4 0 1 M6 DB23 N5 PLE1 PLL ENABLE DB11 DB24 N6 TRANSMIT RECEIVE DB10 DB25 N7 0 1 M7 DB26 N8 TRANSMIT/ RECEIVE M8 Tx/Rx TR1 ADDRESS BITS 15-BIT FRACTIONAL-N DB27 DB29 M1 8-BIT INTEGER-N TR1 DB30 M2 PLE1 DB28 DB31 M3 MUXOUT PLL ENABLE REGISTER 0—N REGISTER ADF7020-1 850–920 860–930 870–940 880–950 VB3 0 0 . 1 IR2 IR1 FILTER BANDWIDTH 0 0 1 1 100kHz 150kHz 200kHz NOT USED 0 1 0 1 VB2 0 1 . 1 VB1 1 0 . 1 CP2 0 0 1 1 0 1 VCO BIAS CURRENT 0.375mA 0.625mA DB8 DB7 DB6 DB5 DB4 CL1 D1 R3 R2 R1 D1 0 1 3.875mA CP1 RSET 0 1 0 1 ICP(MA) 3.6kΩ 0.3 0.9 1.5 2.1 CL4 0 0 0 . . . 1 C1 (1) DB0 DB9 CL2 DIRECT OUTPUT DIVIDE-BY-2 OUTPUT R1 1 0 . . . 1 C2 (0) DB1 DB10 CL3 VCO DIV-BY-2 R2 0 1 . . . 1 C3 (0) DB2 DB11 CL4 R3 0 0 . . . 1 C4 (0) DB3 XTAL DOUBLER XOSC ENABLE VCO BAND DB13 V1 V1 VB4 0 0 . 1 DB12 DB14 DD1 X1 XTAL OSC 0 OFF 1 ON ADDRESS BITS R COUNTER RF R COUNTER DIVIDE RATIO 1 2 . . . 7 XTAL DOUBLER DISABLE ENABLED CL3 0 0 0 . . . 1 CL2 0 0 1 . . . 1 CL1 0 1 0 . . . 1 CLKOUT DIVIDE RATIO OFF 2 4 . . . 30 05669-042 0 1 0 1 DB15 DB17 VB2 0 0 1 1 DB16 DB18 VB3 FREQUENCY OF OPERATION VB1 DB19 VB4 VA1 DD2 DB20 VA1 VA2 CLOCKOUT DIVIDE X1 CP CURRENT VCO ADJUST DB21 VCO BIAS VA2 DB22 IR1 IR2 DB23 IF FILTER BW REGISTER 1—OSCILLATOR/FILTER REGISTER Figure 42. Notes 1. Set the VCO adjust bits R1_DB (20:21) to 0 for normal operation. 2. See Table 5 for the recommended VCO bias settings. 3. The divide-by-2 block is enabled by setting R1_DB13. As this divide block is outside the PLL loop, users must program an N-value that corresponds to twice the divide-by-2 output frequency. The deviation frequency is also halved when divide-by-2 is enabled. Rev. 0 | Page 31 of 48 ADF7020-1 X X X X X MUTE PA UNTIL LOCK PA ENABLE C1 (0) DB0 C2 (1) DB1 C3 (0) DB2 C4 (0) DB3 ADDRESS BITS PE1 POWER AMPLIFIER 0 1 OFF ON MUTE PA UNTIL MP1 LOCK DETECT HIGH DI1 TxDATA TxDATA OFF ON 0 1 PA2 PA1 PA BIAS S3 S2 S1 MODULATION SCHEME 0 0 1 1 0 1 0 1 5μA 7μA 9μA 11μA 0 0 0 0 1 0 0 1 1 1 0 1 0 1 1 FSK GFSK ASK OOK GOOK POWER AMPLIFIER OUTPUT LOW LEVEL D1 D2 D5 . D6 X 0 0 0 0 . . 1 X X 0 0 . . . 1 . . . . . . . . X X 0 0 1 . . 1 X X 0 1 0 . . 1 OOK MODE PA OFF –16.0dBm –16 + 0.45dBm –16 + 0.90dBm . . 13dBm POWER AMPLIFIER OUTPUT HIGH LEVEL P1 P2 . . P6 0 0 0 0 . . 1 . . . . . . 1 . . . . . . . X 0 0 1 . . 1 X 0 1 0 . . 1 PA OFF –16.0dBm –16 + 0.45dBm –16 + 0.90dBm . . 13dBm 05669-043 0 1 DB4 DB12 P4 IC2 IC1 MC3 MC2 MC1 PE1 DB13 P5 DB5 DB14 P6 DB6 DB15 D1 S1 DB16 D2 DB7 DB17 D3 S2 DB18 D4 DB8 DB19 D5 DB9 DB20 D6 S3 DB21 D7 P1 DB22 D8 DB11 DB23 D9 DB10 DB24 MC1 P2 DB25 P3 DB26 MC2 MP1 MODULATION SCHEME POWER AMPLIFIER MC3 DB28 IC2 INDEX COUNTER DB29 DI1 MODULATION PARAMETER DB27 DB30 PA1 GFSK MOD CONTROL IC1 DB31 PA2 PA BIAS TxDATA INVERT REGISTER 2—TRANSMIT MODULATION REGISTER (ASK/OOK MODE) Figure 43. Notes 1. Figure 13 shows how the PA bias affects the power amplifier level. The default level is 9 μA. If you need maximum power, program this value to 11 μA. 2. In ASK/OOK, Manchester encoding is recommended to keep the data run length limit to 2 bits. See the ASK/OOK Operation section for more details on dealing with longer run lengths. 3. D7, D8, and D9 are don’t care bits. Rev. 0 | Page 32 of 48 ADF7020-1 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 D7 D6 D5 D4 D3 D2 D1 P6 P5 P4 P3 P2 P1 S3 S2 S1 MP1 PA2 PA1 PA BIAS 0 0 1 1 0 1 0 1 5μA 7μA 9μA 11μA D1 F DEVIATION 0 0 0 0 . 1 0 1 0 1 . 1 PLL MODE 1 × FSTEP 2 × FSTEP 3 × FSTEP . 511 × FSTEP 0 0 0 0 . 1 0 0 1 1 . 1 PE1 POWER AMPLIFIER 0 1 OFF ON MUTE PA UNTIL MP1 LOCK DETECT HIGH FOR FSK MODE, D9 D3 .... D2 .... .... .... .... .... .... C1 (0) DB0 DB22 D8 TxDATA TxDATA X C2 (1) DB1 DB23 D9 DI1 X C3 (0) DB2 DB24 MC1 X DB4 DB25 MC2 X PE1 DB26 MC3 X ADDRESS BITS C4 (0) DB3 DB27 IC2 IC1 MC3 MC2 MC1 0 1 MUTE PA UNTIL LOCK PA ENABLE MODULATION SCHEME POWER AMPLIFIER DB28 MODULATION PARAMETER IC1 DB29 DI1 GFSK MOD CONTROL IC2 DB30 PA1 TxDATA INVERT DB31 PA2 PA BIAS INDEX COUNTER REGISTER 2—TRANSMIT MODULATION REGISTER (FSK MODE) OFF ON 0 1 S3 S2 S1 MODULATION SCHEME 0 0 0 0 1 0 0 1 1 1 0 1 0 1 1 FSK GFSK ASK OOK GOOK 0 0 0 0 . . 1 Figure 44. Notes 1. FSTEP = PFD/214. 2. PA bias default = 9 μA. Rev. 0 | Page 33 of 48 . . . . . . 1 . . . . . . . X 0 0 1 . . 1 X 0 1 0 . . 1 PA OFF –16.0dBm –16 + 0.45dBm –16 + 0.90dBm . . 13dBm 05669-044 POWER AMPLIFIER OUTPUT LEVEL P6 . . P2 P1 ADF7020-1 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 P5 P4 P3 P2 P1 S3 S2 PA1 PA BIAS 0 0 1 1 0 1 0 1 5μA 7μA 9μA 11μA 0 0 1 1 IC2 IC1 INDEX_COUNTER 0 0 1 1 0 1 0 1 16 32 64 128 D8 0 1 0 1 GAUSSIAN – OOK MODE NORMAL MODE OUTPUT BUFFER ON BLEED CURRENT ON BLEED/BUFFER ON C1 (0) DB0 C2 (1) DB1 S3 S2 S1 MODULATION SCHEME 0 0 0 0 1 0 0 1 1 1 0 1 0 1 1 FSK GFSK ASK OOK GOOK 0 0 0 0 . . 1 0 1 . 7 . . . . . . 1 . . . . . . . X 0 0 1 . . 1 X 0 1 0 . . 1 PA OFF –16.0dBm –16 + 0.45dBm –16 + 0.90dBm . . 13dBm 05669-045 0 1 . 1 OFF ON POWER AMPLIFIER OUTPUT LEVEL P1 P2 . . P6 MC3 MC2 MC1 GFSK_MOD_CONTROL 0 0 . 1 PE1 MUTE PA UNTIL MP1 LOCK DETECT HIGH 0 1 D9 C3 (0) DB2 OFF ON C4 (0) DB3 POWER AMPLIFIER 0 1 DB4 PE1 INVALID 1 2 3 . 127 TxDATA TxDATA PA2 0 0 . 1 MUTE PA UNTIL LOCK PA ENABLE DIVIDER_FACTOR 0 1 0 1 . 1 DB5 D1 0 0 1 1 . 1 DB6 D2 0 0 0 0 . 1 S1 D3 ... ... ... ... ... ... MP1 DB15 P6 DB21 D7 ... 0 0 0 0 . 1 D1 DB22 D8 DB16 DB23 D9 D7 D2 DB24 MC1 DB17 DB25 MC2 DB18 DB26 MC3 D3 DB27 IC1 D4 DB28 IC2 DB19 DB29 DI1 0 1 ADDRESS BITS D5 DB30 PA1 DI1 MODULATION SCHEME POWER AMPLIFIER DB20 DB31 MODULATION PARAMETER D6 INDEX COUNTER GFSK MOD CONTROL PA2 PA BIAS TxDATA INVERT REGISTER 2—TRANSMIT MODULATION REGISTER (GFSK/GOOK MODE) Figure 45. Notes 1. GFSK_DEVIATION = (2GFSK_MOD_CONTROL × PFD)/212. 2. Data rate = PFD/(INDEX_COUNTER × DIVIDER_FACTOR). 3. PA bias default = 9 μA. Rev. 0 | Page 34 of 48 ADF7020-1 SK7 0 0 . 1 1 0 0 . 1 1 DB0 DB5 BK2 C1(1) DB6 OK1 DB1 DB7 OK2 C2(1) DB8 FS1 DB2 DB9 FS2 DB3 DB10 FS3 C3(0) DB11 FS4 ADDRESS BITS C4(0) DB12 FS5 BB OFFSET CLOCK DIVIDE DB13 FS6 DB4 DB14 FS7 BK1 DB15 FS8 DB16 SK1 DB18 SK3 DB17 DB19 SK2 DB20 SK4 ... ... ... ... ... ... CDR CLOCK DIVIDE SK3 SK2 SK1 SEQ_CLK_DIVIDE BK2 BK1 BBOS_CLK_DIVIDE 0 0 . 1 1 0 1 . 1 1 1 0 . 0 1 1 2 . 254 255 0 0 1 0 1 x 4 8 16 OK2 OK1 DEMOD_CLK_DIVIDE 0 0 1 1 0 1 0 1 4 1 2 3 FS8 FS7 ... FS3 FS2 FS1 CDR_CLK_DIVIDE 0 0 . 1 1 0 0 . 1 1 ... ... ... ... ... 0 0 . 1 1 0 1 . 1 1 1 0 . 0 1 1 2 . 254 255 05669-046 SK8 SK5 DB21 DB22 SK7 SK6 DB23 SK8 SEQUENCER CLOCK DIVIDE DEMOD CLOCK DIVIDE REGISTER 3—RECEIVER CLOCK REGISTER Figure 46. Notes 1. Baseband offset clock frequency (BBOS_CLK) must be greater than 1 MHz and less than 2 MHz, where BBOS _ CLK = 2. XTAL . BBOS _ CLK _ DIVIDE The demodulator clock (DEMOD_CLK) must be <12 MHz for FSK and <6 MHz for ASK, where DEMOD _ CLK = 3. XTAL . DEMOD _ CLK _ DIVIDE Data/clock recovery frequency (CDR_CLK) should be within 2% of (32 × data rate), where CDR _ CLK = DEMOD _ CLK . CDR _ CLK _ DIVIDE Note that this might affect your choice of XTAL, depending on the desired data rate. 4. The sequencer clock (SEQ_CLK) supplies the clock to the digital receive block. It should be close to 100 kHz for FSK and close to 40 kHz for ASK: SEQ _ CLK = XTAL . SEQ _ CLK _ DIVIDE Rev. 0 | Page 35 of 48 ADF7020-1 0 0 0 0 1 1 0 0 1 1 0 1 DEMOD SELECT DEMOD LOCK/ DB24 SYNC WORD MATCH 0 1 0 1 X DL8 ADDRESS BITS DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DW2 DW1 DS2 DS1 C4(0) C3(1) C2(0) C1(0) DB9 DW3 DB16 DL1 – – OUTPUT OUTPUT INPUT – DW4 DB17 DL2 INT/LOCK PIN SERIAL PORT CONTROL—FREE RUNNING SERIAL PORT CONTROL—LOCK THRESHOLD SYNC WORD DETECT—FREE RUNNING SYNC WORD DETECT—LOCK THRESHOLD INTERRUPT/LOCK PIN LOCKS THRESHOLD DEMOD LOCKED AFTER DL8–DL1 BITS DW5 DB10 DB18 DL3 DEMOD LOCK/SYNC WORD MATCH DW6 DB11 DB19 DL4 DW7 DB12 DB20 DL5 DW8 DB13 DB21 DL6 DW9 DB14 DB22 DW10 DB15 DB23 DL7 POSTDEMODULATOR BW DL8 LM1 DEMOD MODE LM2 LM1 DL8 0 1 2 3 4 5 DEMODULATOR LOCK SETTING DB25 DB26 LM2 DB27 DB28 DB29 DB30 DB31 REGISTER 4—DEMODULATOR SET-UP REGISTER DS2 DS1 DEMODULATOR TYPE 0 0 1 1 0 1 0 1 LINEAR DEMODULATOR CORRELATOR/DEMODULATOR ASK/OOK INVALID MODE5 ONLY DL7 ... DL3 DL2 DL1 LOCK_THRESHOLD_TIMEOUT 0 0 0 . 1 1 0 0 0 . 1 1 ... ... ... ... ... ... 0 0 0 . 1 1 0 0 1 . 1 1 0 1 0 . 0 1 0 1 2 . 254 255 05669-047 DL8 Figure 47. Notes 1. Demodulator Modes 1, 3, 4, and 5 are modes that can be activated to allow the ADF7020-1 to demodulate data-encoding schemes that have run-length constraints greater than 7. 2. Post_Demod_BW = 211 π FCUTOFF/DEMOD_CLK, where the cutoff frequency (FCUTOFF) of the postdemodulator filter should typically be 0.75 times the data rate. 3. For Mode 5, the timeout delay to lock threshold = (LOCK_THRESHOLD_SETTING)/SEQ_CLK, where SEQ_CLK is defined in the Register 3—Receiver Clock Register section. Rev. 0 | Page 36 of 48 ADF7020-1 DB4 DB3 DB2 DB1 DB0 C4(0) C3(1) C2(0) C1(1) CONTROL BITS PL1 DB5 DB6 MT1 PL2 DB7 MT2 DB8 DB9 DB10 DB11 DB12 DB13 DB14 DB15 DB16 DB17 DB18 DB19 DB20 DB21 DB22 DB23 DB24 DB25 DB26 DB27 DB28 DB29 DB30 DB31 SYNC BYTE SEQUENCE SYNC BYTE LENGTH MATCHING TOLERANCE REGISTER 5—SYNC BYTE REGISTER PL2 PL1 SYNC BYTE LENGTH 0 0 1 1 0 1 0 1 12 BITS 16 BITS 20 BITS 24 BITS 0 0 1 1 0 1 0 1 0 ERRORS 1 ERROR 2 ERRORS 3 ERRORS 05669-048 MATCHING MT2 MT1 TOLERANCE Figure 48. Notes 1. Sync byte detect is enabled by programming Bits R4_DB (25:23) to [010] or [011]. 2. This register allows a 24-bit sync byte sequence to be stored internally. If the sync byte detect mode is selected, the INT/LOCK pin goes high when the sync byte is detected in Rx mode. Once the sync word detect signal goes high, it goes low again after nine data bits. 3. The transmitter must transmit the MSB of the sync byte first and the LSB last to ensure proper alignment in the receiver sync byte detection hardware. 4. Choose a sync byte pattern that has good autocorrelation properties, for example, an unequal amount of digital 1s and 0s. Rev. 0 | Page 37 of 48 ADF7020-1 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 TD7 TD6 TD5 TD4 TD3 TD2 TD1 C4(0) C3(1) C2(1) C1(0) DB14 DP1 TD8 DB15 LG1 DB12 DB16 LI1 TD9 DB17 LI2 TD10 DB13 DB18 ML1 DOT PRODUCT DB19 CA1 LNA MODE DB20 FC1 LNA CURRENT IF FILTER CAL MIXER LINEARITY DB21 DB24 FC5 DB22 DB25 FC6 RxDATA RxDATA FC2 DB26 FC7 0 1 FC3 DB27 FC8 RI1 RxDATA INVERT DB23 DB28 FC9 DP1 DOT PRODUCT 0 1 0 1 CROSS PRODUCT DOT PRODUCT ML1 MIXER LINEARITY LG1 LNA MODE 0 1 0 1 DEFAULT REDUCED GAIN NO CAL CALIBRATE DEFAULT HIGH LI2 LI1 LNA BIAS 0 0 800μA (DEFAULT) . FC6 FC5 FC4 FC3 FC2 FC1 FILTER CLOCK DIVIDE RATIO 0 0 . . . . 1 . . . . . . . 0 0 . . . . 1 0 0 . . . . 1 0 0 . . . . 1 0 0 . . . . 1 0 1 . . . . 1 1 0 . . . . 1 1 2 . . . . 511 05669-049 FC9 ADDRESS BITS DISCRIMINATOR BW CA1 FILTER CAL DEMOD RESET CDR RESET FC4 DB29 IF FILTER DIVIDER RI1 DB30 DB31 Rx RESET RxDATA INVERT REGISTER 6—CORRELATOR/DEMODULATOR REGISTER Figure 49. Notes 1. See the FSK Correlator/Demodulator section for an example of how to determine register settings. 2. Nonadherence to correlator programming guidelines results in poorer sensitivity. 3. The filter clock is used to calibrate the IF filter. The filter clock divide ratio should be adjusted so that the frequency is 50 kHz. The formula is XTAL/FILTER_CLOCK_DIVIDE. 4. The filter should be calibrated only when the crystal oscillator is settled. The filter calibration is initiated every time Bit R6_DB19 is set high. 5. Discriminator_BW = (DEMOD_CLK × K)/(800 × 103). See the FSK Correlator/Demodulator section. Maximum value = 600. 6. When LNA Mode = 1 (reduced gain mode), this prevents the Rx from selecting the highest LNA gain setting. This might be used when linearity is a concern. See Table 6 for details of the Rx modes. Rev. 0 | Page 38 of 48 ADF7020-1 REGISTER 7—READBACK SET-UP REGISTER CONTROL BITS ADC MODE DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 RB3 RB2 RB1 AD2 AD1 C4(0) C3(1) C2(1) C1(1) RB3 READBACK AD2 AD1 ADC MODE 0 1 0 0 1 1 DISABLED ENABLED RB2 RB1 READBACK MODE 0 0 1 1 0 1 0 1 AFC WORD ADC OUTPUT FILTER CAL SILICON REV 0 1 0 1 MEASURE RSSI BATTERY VOLTAGE TEMP SENSOR TO EXTERNAL PIN 05669-050 READBACK SELECT Figure 50. Notes 1. Readback of the measured RSSI value is valid only in Rx mode. To enable readback of the battery voltage, the temperature sensor, or the voltage at the external pin in Rx mode, users must disable the AGC function in Register 9. To read back these parameters in Tx mode, users must first power up the ADC using Register 8, because it is off by default in Tx mode to save power. This is the recommended method of using the battery readback function since most configurations typically require use of the AGC function. 2. Readback of the AFC word is valid in Rx mode only if either the linear demodulator or the correlator/demodulator is active. 3. See the Readback Format section for more information. Rev. 0 | Page 39 of 48 ADF7020-1 PA (Rx MODE) 0 1 PA OFF PA ON ADC ENABLE FILTER ENABLE LNA/MIXER ENABLE VCO ENABLE SYNTH ENABLE DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 PD7 SW1 LR2 LR1 PD6 PD5 PD4 PD3 PD2 PD1 C4(1) C3(0) C2(0) C1(0) LOG AMP/ RSSI SW1 Tx/Rx SWITCH DEFAULT (ON) OFF 0 1 CONTROL BITS PLE1 (FROM REG 0) PD2 PD1 LOOP CONDITION 0 0 0 0 1 0 0 1 1 X 0 1 0 1 X VCO/PLL OFF PLL ON VCO ON PLL/VCO ON PLL/VCO ON LR2 LR1 RSSI MODE PD3 LNA/MIXER ENABLE X X 0 1 RSSI OFF RSSI ON 0 1 LNA/MIXER OFF LNA/MIXER ON PD6 DEMOD ENABLE PD4 FILTER ENABLE 0 1 DEMOD OFF DEMOD ON 0 1 FILTER OFF FILTER ON PD5 ADC ENABLE 0 1 ADC OFF ADC ON 05669-051 PD7 DEMOD ENABLE DB14 INTERNAL Tx/Rx SWITCH ENABLE DB15 PA ENABLE Rx MODE REGISTER 8—POWER-DOWN TEST REGISTER Figure 51. Notes 1. For a combined LNA/PA matching network, Bit R8_DB12 should always be set to 0. This is the power-up default condition. 2. It is not necessary to write to this register under normal operating conditions. Rev. 0 | Page 40 of 48 ADF7020-1 FG1 FILTER GAIN GC1 GAIN CONTROL 0 0 1 1 0 1 0 1 8 24 72 INVALID 0 1 AUTO USER DB6 DB5 DB4 DB3 DB2 DB1 DB0 GL2 GL1 C4(1) C3(0) C2(0) C1(1) DB7 GL3 DB9 DB8 DB10 GL6 GL4 FG2 GL5 AUTO AGC HOLD SETTING GL7 DB13 GH3 0 1 DB11 DB14 GH4 GS1 AGC SEARCH LOW HIGH GH1 DB15 GH5 FILTER CURRENT 0 1 DB12 DB16 GH6 FI1 ADDRESS BITS AGC LOW THRESHOLD GH2 DB17 DB19 GC1 AGC HIGH THRESHOLD GH7 DB20 LG1 DB18 DB21 LG2 GS1 DB22 FG1 GAIN CONTROL AGC SEARCH DB23 FG2 LNA GAIN DB24 FILTER GAIN FI1 DB25 DB26 DB27 DB28 DB29 DB30 DB31 DIGITAL TEST IQ FILTER CURRENT REGISTER 9—AGC REGISTER GL7 GL6 GL5 GL4 GL3 GL2 GL1 AGC LOW THRESHOLD 0 0 0 0 . . . 1 1 1 0 0 0 0 . . . 1 1 1 0 0 0 0 . . . 1 1 1 0 0 0 0 . . . 1 1 1 0 0 0 1 . . . 1 1 1 0 1 1 0 . . . 0 1 1 1 0 1 0 . . . 1 0 1 1 2 3 4 . . . 61 62 63 LG2 LG1 LNA GAIN 0 0 1 1 0 1 0 1 <1 3 10 30 0 0 0 0 . . . 1 1 1 0 0 0 0 . . . 0 0 0 0 0 0 0 . . . 0 0 1 0 0 0 0 . . . 1 1 0 0 0 0 1 . . . 1 1 0 0 1 1 0 . . . 1 1 0 1 0 1 0 . . . 0 1 0 1 2 3 4 . . . 78 79 80 Figure 52. Notes 1. Default AGC_LOW_THRESHOLD = 30, default AGC_HIGH_THRESHOLD = 70. See the RSSI/AGC for details. 2. AGC high and low settings must be more than 30 settings apart to ensure correct operation. 3. LNA gain of 30 is available only if the LNA mode bit, R6_DB15, is set to 0. Rev. 0 | Page 41 of 48 05669-052 RSSI LEVEL GH7 GH6 GH5 GH4 GH3 GH2 GH1 CODE ADF7020-1 DB17 DB16 DB15 DB14 DB13 DB12 GC2 GC1 DH4 DH3 DH2 DH1 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 GL7 GL6 GL5 GL4 PR4 PR3 PR2 PR1 DEFAULT = 0xA GAIN TO I CHANNEL GAIN TO Q CHANNEL DEFAULT = 0xA 05669-053 0 1 PHASE TO I CHANNEL PHASE TO Q CHANNEL ADDRESS BITS PEAK RESPONSE C1 (0) DB0 DB18 GC3 SIQ2 SELECT IQ 0 1 LEAK FACTOR C2 (1) DB1 DB19 GC4 SIQ2 SELECT IQ AGC DELAY C3 (0) DB2 DB20 GC5 I/Q GAIN ADJUST C4 (1) DB3 UP/DOWN DB23 R1 DB21 DB24 PH1 UD1 DB25 PH2 SELECT I/Q RESERVED DB26 PH3 SIQ1 DB22 DB27 I/Q PHASE ADJUST PH4 DB29 SIQ2 DB28 DB30 DB31 SELECT I/Q REGISTER 10—AGC 2 REGISTER DEFAULT = 0x2 Figure 53. Notes 1. This register is not used under normal operating conditions. DB20 AFC ENABLE DB19 DB18 DB17 AE1 M16 M15 M14 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 M12 M11 M10 M9 M8 M7 M6 M5 M4 M3 M2 M1 C4(0) C3(0) C2(1) C1(0) 05669-054 INTERNAL AE1 AFC 0 1 CONTROL BITS AFC SCALING COEFFICIENT M13 DB21 DB22 DB23 DB24 DB25 DB26 DB27 DB28 DB29 DB30 DB31 REGISTER 11—AFC REGISTER OFF ON Figure 54. Notes 1. See the Internal AFC section to program AFC scaling coefficient bits. 2. The AFC scaling coefficient bits can be programmed using the following formula: AFC_Scaling_Coefficient = Round((500 × 224)/XTAL). Rev. 0 | Page 42 of 48 ADF7020-1 PRESCALER 0 1 4/5 (DEFAULT) 8/9 CS1 CAL SOURCE 0 1 INTERNAL SERIAL IF BW CAL ADDRESS BITS DB1 DB0 C1(0) DB5 T2 C2(0) DB6 T3 DB2 DB7 T4 C3(1) DB8 T5 DB3 DB9 T6 DB4 DB10 T7 T1 DB11 T8 C4(1) DB12 PLL TEST MODES T9 COUNTER RESET DB13 DB18 SF1 DB14 DB19 SF2 DB15 DB20 SF3 DB17 DB21 DB22 SF5 SF4 DB23 SF6 DB16 SOURCE DB24 OSC TEST DB25 CS1 DEFAULT = 32. INCREASE NUMBER TO INCREASE BW IF USER CAL ON Σ-Δ TEST MODES CR1 COUNTER RESET 0 1 DEFAULT RESET 05669-055 P DIGITAL TEST MODES IMAGE FILTER ADJUST QT1 FORCE LD HIGH DB26 DB27 DB28 DB29 DB30 ANALOG TEST MUX PRE DB31 PRESCALER REGISTER 12—TEST REGISTER Figure 55. Using the Test DAC on the ADF7020-1 to Implement Analog FM Demodulation and Measuring of SNR The test DAC allows the output of the postdemodulator filter for both the linear and correlator/demodulators (Figure 31 and Figure 32) to be viewed externally. It takes the 16-bit filter output and converts it to a high frequency, single-bit output using a second-order error feedback Σ-Δ converter. The output can be viewed on the CLKOUT pin. This signal, when IF filtered appropriately, can then be used to • • Monitor the signals at the FSK/ASK postdemodulator filter output. This allows the demodulator output SNR to be measured. Eye diagrams can also be constructed of the received bit stream to measure the received signal quality. Programming the test register, Register 12, enables the test DAC. In correlator mode, this can be done by writing Digital Test Mode 7 or 0x0001C00C. To view the test DAC output when using the linear demodulator, the user must remove a fixed offset term from the signal using Register 13. This offset is nominally equal to the IF frequency. The user can determine the value to program by using the frequency error readback to determine the actual IF and then programming half this value into the offset removal field. It also has a signal gain term to allow the usage of the maximum dynamic range of the DAC. Setting Up the Test DAC • Digital test modes = 7: enables the test DAC, with no offset removal (0x0001 C00C). • Digital test modes = 10: enables the test DAC, with offset removal (needed for linear demod only, 0x02 800C). Provide analog FM demodulation. While the correlators and filters are clocked by DEMOD_CLK, CDR_CLK clocks the test DAC. Note that, although the test DAC functions in a regular user mode, the best performance is achieved when the CDR_CLK is increased up to or above the frequency of DEMOD_CLK. The CDR block does not function when this condition exists. The output of the active demodulator drives the DAC; that is, if the FSK correlator/demodulator is selected, the correlator filter output drives the DAC. Rev. 0 | Page 43 of 48 ADF7020-1 REGISTER 13—OFFSET REMOVAL AND SIGNAL GAIN REGISTER 05669-056 DB3 DB2 DB1 DB0 C4(1) C3(1) C2(0) C1(1) NORMAL PULSE WIDTH 2 × PULSE WIDTH 3 × PULSE WIDTH . . . 16 × PULSE WIDTH DB4 PULSE EXTENSION 0 1 0 . . . 1 DB6 PE1 0 0 1 . . . 1 DB7 PE2 0 0 0 . . . 1 DB8 DB12 PE1 PE3 0 0 0 . . . 1 CONTROL BITS KP DB9 DB13 PE2 DB11 DB14 PE3 PE4 DB10 DB15 PE4 DB16 DB17 DB19 DB18 DB20 DB21 DB22 DB23 DB24 DB25 KI DB5 PULSE EXTENSION TEST DAC OFFSET REMOVAL DB26 DB27 DB28 DB29 DB30 DB31 TEST DAC GAIN Figure 56. Notes 1. Because the linear demodulator’s output is proportional to frequency, it usually consists of an offset combined with a relatively low signal. Up to a maximum of a 300 kHz offset can be removed and gained to use the full dynamic range of the DAC: DAC_input = (2Test_DAC_Gain) × (Signal − Test_DAC_Offset_Removal/4096). Rev. 0 | Page 44 of 48 ADF7020-1 OUTLINE DIMENSIONS 7.00 BSC SQ 0.60 MAX 0.60 MAX 37 36 PIN 1 INDICATOR TOP VIEW 48 4.25 4.10 SQ 3.95 (BOTTOM VIEW) 25 24 12 13 0.25 MIN 5.50 REF 0.80 MAX 0.65 TYP 12° MAX PIN 1 INDICATOR 1 EXPOSED PAD 6.75 BSC SQ 0.50 0.40 0.30 1.00 0.85 0.80 0.30 0.23 0.18 0.05 MAX 0.02 NOM 0.50 BSC SEATING PLANE 0.20 REF COPLANARITY 0.08 COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2 Figure 57. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 7 mm × 7 mm Body, Very Thin Quad (CP-48-3) Dimensions shown in millimeters ORDERING GUIDE Model ADF7020-1BCPZ 1 ADF7020-1BCPZ-RL1 ADF7020-1BCPZ-RL71 EVAL-ADF70XXMB EVAL-ADF70XXMB2 EVAL-ADF7020-1DB4 EVAL-ADF7020-1DB5 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Control Mother Board Evaluation Platform 400 MHz to 435 MHz Daughter Board 135 MHz to 650 MHz Daughter Board Z = Pb-free part. Rev. 0 | Page 45 of 48 Package Option CP-48-3 CP-48-3 CP-48-3 ADF7020-1 NOTES Rev. 0 | Page 46 of 48 ADF7020-1 NOTES Rev. 0 | Page 47 of 48 ADF7020-1 NOTES © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05669–0–12/05(0) Rev. 0 | Page 48 of 48