PFC与 PWM控
-9-
制 器二 合 一 芯片 ML4819及 其应 用
●新 特 器 件 应 用
PWM控
PFc与
制 器 二 合
悲 泞 ML0s19殷 其 殛用
毛兴武
一
0
摘要 :ML481g是 PFC与 pwM控 制二合一 IC。 其中的 PFC电 路同 ML481z类 似
PWM采 用电流或 电压模式控制,并 且 PFC电 路和 PWM共 用一个振荡器,使 用简
单、灵 活、功 能强。本文简要介 绍了该 混合型 IC的 功能、工作原理 ,重 点剖析 了用
MI'4819组 成的开关电源的工作原理。
关键 词 :PFC PWM控 制器 双 开关正激变换器
,
为满 足 IECssS-z等 标准和 EMC法 规
中关于谐波限量的要求 ,近 几年来 ,在 开关电
综合效率。PWM部 分包含逐周限流、单端变
源中,出 现了将功率 因数控制器 (PFC)和
PWM控 制器合二为一的集成芯片。本 文介
绍 美 国 Micr° hnear公 司生产 的 ML4819
Cσ 9
oVP
sND
MU1TIPLlER
EA0UT^
lNV A
型开关电源控制器 IC。
DUTΥ
PGND A
oUt A
I(slNE,
CVCLE
oUT B
PGND B
l(sENsE)B
Rσ )
MI'4819采 用 zO脚 DIP和 ⒛ 脚
sOIC封 装 ,顶 视图如图 1,图 2为 ML4819
V(REF1
V∝
PWMB
1.ML鲳 19的 内部结构及基本特征
内部方框 图,各 引脚功能如表
ML0819中 的 PFC
电路 与 ML481z控 制 器
I(sENsE,A
图
R^MP∞
!(uM)
"P
1 ML0s19封 装顶视图
1。
类似 ,Mu819内 PWM
控制器采用电流或电压模
式 控 制 。,由 于 PFC和
PWM电 路共用一个振荡
器 ,故 很容易实现两部分
该 IC输 出峰
电路的同步 。
值电流为 lA,因 而可使
MOSFET的 栅极电容迅
sV
EA0U了 A
∶
sV
;廴
速充电与放电。PFC单 元
是一个峰值电流传感控制
器 ,利 用电流互感器或取
PGND
K"U1T冫
‘
￠
图2
M侣 19内 部结构框图
一灬
样FET,r在 平均电流传感
控制方法上 ,改进了系统
功牢因虫
边10△
"NV A
-10-
〈国外电子元器件〉1998年 第 1期 19,B年 1月
换器和斜率补偿 ,实 现了占空比的精确控制。
大幅值振荡器和电流输 人乘法器增强了噪声
抗扰性。斜率补偿电路可编程,过 电压比较器
达到门限值时 ,内 部 比较器改变状态 ,电 容器
通过 内部的晶体管放电。在电容器放电过程
在负载断开时可避免失控。
ML4819的 极 限参 数 如下 :电 源 电压
Vcc是 ssV;脚 1z源 极吸收输 出电流 (DC,
电压周期和死区时间决定
为 1A;乘 法器 I(sINE)输 人 (脚 ω 电流为
1.2mA;误 差放大 器输 入 电流 (脚 3)为
1h认 ;振 荡器充电电流是 zmA;脚
1、
脚 4与
脚 5的 模拟输入 电压为 -0.3~十 5.5Ⅴ ;结
温是 1∞ ℃。
ML4819的 工作 电流为 zSmA,最 大值
是 ssmA,工 作温度为 0~+⒛ ℃。
2.功 能概述
ML4819的 PFC电 路与 PWM控 制器
共用同一个振荡器。该振荡器用等于 s/RET
的电流 愆r对 外接电容 CT充 电。当 CT电 压
表 1
中 ,产 生一个时钟脉冲。振荡器周期由斜坡
=TRAMP十
Tc)“
式 中
Vc・ 巛
,TRAMP=%巛
:
TDEADT【 IvfE
AMP/玉
AMP)/(8。 HmA-凡
田
汀
,‰
),%“
ADTME=
AMP,为 斜
坡
电压最大变化值。PWM最 大 占空比由 7脚
上的门电压限制 。当 C(T)上 斜坡电压达到
7脚 所加门限电压时 ,PWM输 出关断 ,触 发
器置位 ,占 空 比为
:
厶Ⅲ
式 中 ,R税 为振荡器占空 比。
ML4819的 PFC电 路 中的误差放大器
为高开环增益宽带放大器 ,单 位增益带宽为
1MHz。 PFC电 路中的线性电流输人乘法器
,
对大功率开关管引起的噪声有很好的抑制作
ML/I819引 脚功能
引脚符号
从 PFC电 流互感器到 PWM比 较 器 (十 )输 人。该脚 电压达到 5V时
产生电流限制
到过电压 比较器输人
电流乘法器输 出。该脚有 一 只电阻到地 ,将 电流转换 为电压
误差放大器输 出端
误差放大器反
I(E;I)N∞ )A
DW CYCLE
K$N$)B
ItAMP鲰
,
|电 流乘法器输人端
占空 比调整控制器 ,调 整该脚 电压 ,可 以改变 pwM控 制器的占空 比
误差电压反馈翰八端
电流型工作电流传感电阻输人或电压傈
振荡器定时电阻,该 电阻两端的电压为 5V,对 α t)设 定充 电电流
逐月 PWM电 流限制。该脚超过 1V门 限时 ,PWM周 期结束
确而丁两罹而面而丽而石币 币面
可
甲
堍薷币噙啄熏丌寥
|PWM控 制器的大电流推拉输出返回端
=丁
T环
F孬 丁
而
F需 丁
面
雨
两
匚
薯
F瓦 百
F页 鬲
弦
元
IC正 电源
ⅡC控 制器推拉输 出
HC控 制器推拉大
5V的 基准电压缓 冲输 出
模拟信号 地
振荡器定时电容
PFC与 PWM控
制 器二 合 一 芯 片
-11-
ML4819及 其应 用
路
增
PFc龇
⒈丿狂
m丿
m
υ
￡
,
"ˇ
^
ls1~o
ouIVCC
∝
m〓
otmr tvctt otJ△ B
●
●
C~o0
卩
加
邯
⒏哐 △冂
图 3 利用 Mu819设 计的 180W高 功率因数开关电源电路
用。输人 正弦波电压经整流后通过降压电阻
转换为电流 I(SINE),比 例系数在 0~1之
间 ,且 与误差放大器的输 出电压成正比。乘
法器 的输 出电流 通过脚 3到 地 的电阻 ,经
PWM比 较器转换成基准电压信号。
斜率补偿是通过增加从脚 1z到 脚 1(对
刭V∝
"出
PFC单元电路)或 到脚 Ⅸ对 PWM部 分)的 电
脚 1或 脚 9到 地的阻抗为 R~。
流的来完成的。
由于大多数占空比都限制到 sO%,所 以 PWM
部分一般不需要斜率补偿。
当 ML4819的 电源 电压达 1sV时 ,IC
进入 正常工作状态。当电源 电压 ⒒℃降到
10V以 下时 ,产 生欠压锁定。在欠压封锁期
间 ,5V的 VRE「 脚断开。 IC的 启动电流典型
值是 0.smA,正 常工作后 ,电 源电流典型值
为 zsmA,最 大值为 ssmA。
3.ML胡 19典 型应用电跷
图 3为 用
'・
ML0819组 成 的开关 电源 电
图4启 动电路
路,主 要由桥式整流器、升压型变换器、有源
PFC和 PWM稳 压器等部分组成。ML4819
的内部 PFC控 制器与图 3中 电感器 L1、 电流
互感器 T1、 功率开关管 Q1、 升压二极管 “ 、
滤波电容 Cz等 组成有源 pFc。 ML4:19内
PWM控 制器与图 3中 的 T2、 Qz、 V、 高频隔
离变压器 T3和 D13、 L2、 C18及 R28、 R29、
V3、 V2等 纽成
PWM稳 压器。
3.2电 路分析
3.2.1启 动电路与偏王电源
图 4为 开关电源的启动电路 ,启 动电路
-12-
国外电子元器件》1998年 第 1期 1998年 1月
《
也可以用 s9kΩ /2W的 泄放电阻来实现。该
方案虽然简单且成本较低 ,但 易产生过长的
导通延时。当 IC的 15脚 (⒒ o电 压达 1sV
时 ;IC启 动。电容 C10【 ssOuF)中 贮存的能
PFC增 强电路 ,如 图 3左 上角虚线框内的网
络所示。PFC增 强电路可大大地提高系统功
率 因数 ,减 小输人电流波形畸变。PFC增 强
电路能够产生并且 自动调节很小的 DC偏 置
量施加于 IC,直 到变压器 T3的 辅助绕组产
生电压 ,经 D9和 C10整 流滤波后支持 IC
工作。
电流,注 人到 IC的 6脚 ,用来改善过零电流
失真。实践表明 ,在 输入电压 2⒛ ‰ 上的偏
置量比 1⒛ VAc上 的偏置量约高 4倍 以上 ,具
体的 比率可 以通过选择电阻值和齐纳二极管
3.2.2振 荡电路
Mu819中 振荡器为 PFC与
撒 用。定时元件 R〓
PWM控 制
R6,G=G。 振荡器频
率 3℃ =1.3“ (R× G)。 在 另∝=100kHz和
占空比为 9s%条 件下 ,关 断时间 bFF=sOOns,
振 荡器 电压 V。 E〓 4.zV,放 电电流 ID‘ =
8.0mA,故 CT〓 (TO″ ×brs,/%∞ =1000pF。
定时电阻可用公式 R=1.3“ (允 ∝×CT)求
出。将
rosc〓
10弦 Hz和
CT=1000pF代 人
的电压来确定。
输人到 IC的 I(sINE)脚 的偏 置 电流
IIslNE(vN,是 该
脚 电 压 ‰
lNE的
函 数
,V1sNE
典型值是 0。 Ⅳ 。
Q4基 -射 电压 ‰ 〓0。 Ⅳ
设 r为 在 zzO VAc输 人与 120VAc输 人偏置电流
比率,下 列等式成立
,
:
Vc3阳m=工 L号
丝 (1)
垦
阝
胃
吕
簧
玄
,
R=13。 &⒐ 可选 R=⒕ 仇
3.2.3PFC升 压型变换器
ML4819脚 “(α 刀u)输 出高频 PWM
驱动脉冲,使 Q1工 作在开关状态。Q1导 通期
间 ,二 极管 D6截 止 ;Q1关 断时 ,D6导 通。升
压电感 L1是 一个非常重要的元件,如 果电感
量太小 ,输人电流将出现较大畸变 ,功 率因数
过低 ;如 果 L1数 值过大 ,则 需要过大的磁芯
和过多的线圈匝数。根据有源 PFC(升 压变换
器 )有 关公式 ,不 难求出 L1=加 H。 对磁芯的
要求是饱和 成 较高且在 工 作频率上损耗较
小 ,并 且能承受 4A峰 值电流。实践证明 ,L1
可选用 4zz9-sC8铁 氧体磁 芯 ,艹 z0AWG
导线绕 150匝 ,间 隙 0.15寸 。
有源功率因数校正 (APFC)的 一个特点
之 一是 增加 电流 互 感器 T1。 T1选 用直径
0.5寸 的 F41206冖 TC磁 芯 ,初 级绕组 № =
sOT;次 级绕组 Ns=1T。 次级绕组用来传感
Q1的 开关电流 ,该 电流通过电阻 R10转 换
脚 1。 只 1脚 上的 压达
罕
宥
鐾 紧 ,i罟瓮 霭茫
APFC变 换器 的另一个特点 就是 带 有
IIs小法阳 N,=J匕
r=
r=l窝
凵EI￥
⊥鱼
迎E
芸廴亍 =Iy⊥
(2)
。(3)
茭{子畲#羊夸||≡ ￥智⒊三;钅 f∶;斧苏罨 (4)
根据以上公式,只 要先求出 Vc3(2⒛ VAc)
和 Vc3(1⒛ VAc),就 可以求得 D8的 齐纳电压
Vz。 利用公式 (2)可 求出 R⒊ R1与 R4可 用
公式 (1)求 得。加人 PFC增 强电路后,在
”O VAc下 ,功 率因数可达 0.99以 上。
APFC变 换器 ∝ 输出电压经 R久 R6
组成的分压器后,馈 送到 IC脚 又IC内 误差
放大器反相输人端)。 b可 由两只 l/HW电 、
阻串联而成。误差放大器的输人端偏置电流约
为 sJtA,R5功 耗设定在 0.仰 即可 ,于 是
R5=(ssOV,2/0.0W=狁 Ok,可 选用 17Bk
(1%)的 两只电阻串联。 R6=(VREF× Rω /
(380V-VREF)=(W× 17Bk× 2)(380V-5V)
=4。 9ZI瓜 ,可 选用 4.7驮 (1%)电 阻。 电容
CB(连 接于4脚 与 5脚 之间)是 电压调整环路
中的重要元件。电压环路带宽应抑制,C2输
出端上 1⒛Hz(工 频为 ωHz时 )的 纹波 ,在
PFC与
PWM控 制器二合一芯片 ML4819及 其应用
数 值上小 于 1sHz。 如 果选取 BW=zHz,则
C8=I/πR朔W=I/3.14×
0・
356k×
44uFo
ˉ
~
APFC变 换 器输 出 DC电 压 经过 电压 保
护 (oVID)电 路 ,馈送到 IC脚
定 在
2Hz=
s95V,R7=ssOk,则
2。
输 出过 电压
取佯 Γ
R⑴
R8=(VREF×
RV/(V。vP-VpE「 ) = (5V×
365k)/
(39sV-5V)=4.564k,可 选用 4.53k(1%)
图 6 电压模 式工 作
的电阻。
3.2.4PWM稳 压 器
图 3电 路 中的 PWM稳 压器采用电流型
控制。Q2、 Q3等 组成双开关管正激变换器
如图 5所 示 。Q3源 极 电阻 R4作 电流传感
器。高频噪声滤波和脉冲前沿传输 由 Rz~s、
,
C“ 完成。主调整回路 由 IC的 PWM B完
成。TL431(U3)用 作电压基准和误差放大。
U2提 供一个 电流指令 信号 ,加 到 IC的 8
脚。Rz9和 C20提 供 回路补偿 ,输 出电压
%uT=2。 “ 1+R29/R28)。 在 R24上 的电
压为 1V时 ,限 流值为 zA。 为防止 T3饱 和
占空 比限 制 在 sO%以 下 。利 用脚 7上 的
VREF/2门 限 电压 ,可 将 占空 比限 制 为
,
图 5 双开关正激变换器
45%。
在图 3所 示 电路中,利 用脚 9的 斜坡电
流可以实现 电压控制 ,如 图 6所 示。
脚 9的 三
角波电压幅值为 VR=玉 昭⒓ ×R(V)。 式中
R18为 斜率补偿电阻。
'
T2采 用与 T1相 同的磁芯、 Ns〓
Np=
1sT(双 线 绕 制 );隔 离 变 压 器 T3采 用
4229-3C8磁 芯 ,Ns=44T,Np=4T,辅 助
绕组 NAL,x=2T;L2=1ouH。
。
3.3设 计制作与装配
高频开关电源应采用双面印制电路板 ,并
且接地端集中到一个面上。所有的开关引线
(功 率 FET、 输出二极管、Ic输 出、
接地线、旁
路电容 )应 尽可能短 ,以 限制开关噪声。
感性耦合噪声主要 由开关电流的快速变
化 (高 由/dt)引 起。
C3、 α 应选用高频电容。
电压的快 速变化 (高 dv/dt)也 引起噪声 ,功
率开关 FET的 漏极是主要 的噪声源 。FET
产生的辐射噪声,可 以通过在散热器到 FET
的 源极 之 间连 接 一 只 高频 电容 来 抑 制 。
ML4819的 PWR GND与 信号 GND两 个接
地脚应在印制板引出端点上用非常短的引线
连在一起。
咨询编号 :9gO103
May 1997
ML4819*
Power Factor and PWM Controller “Combo”
GENERAL DESCRIPTION
FEATURES
The ML4819 is a complete boost mode Power factor
Controller (PFC) which also contains a PWM controller.
The PFC circuit is similar to the ML4812 while the PWM
controller can be used for current or voltage mode control
for a second stage converter. Since the PWM and PFC
circuits share the same oscillator, synchronization of the
two stages is inherent. The outputs of the controller IC
provide high current (>1A peak) and high slew rate to
quickly charge and discharge MOSFET gates. Special care
has been taken in the design of the ML4819 to increase
system noise immunity.
■
The PWM section includes cycle by cycle current limiting,
precise duty cycle limiting for single ended converters,
and slope compensation.
e
e
S
e
s
a
Ple
BLOCK DIAGRAM
■
■
■
■
Wide common mode range in current sense
compensators for better noise immunity
Under-Voltage Lockout circuit with 6V hysteresis
w
e
N
for
* Some Packages Are Obsolete
4
2
8
Ml4
PWM
CONTROLLER
OSC
CT
RAMP COMP
s
n
g
i
Des
DUTY CYCLE
ILIM
–
12
■
SLOPE
COMPENSATION
+
20
RT
■
+
10
■
Two 1A peak current totem-pole output drivers
Precision buffered 5V reference (±1%)
Large oscillator amplitude for better noise immunity
Precision duty cycle limit for PWM section
Current input gain modulator improves noise immunity
Programmable Ramp Compensation circuit
Over-Voltage comparator helps prevent output
“runaway”
–
The PFC section is of the peak current sensing boost type,
using a current sense transformer or current sensing
MOSFETs to non-dissipatively sense switch current. This
gives the system overall efficiency over average current
sensing control method.
■
0.7V
–
5V
R
–
3
2
5
19
Q
INV A
ISINE
OUT B
PGND B
8
14
13
–
EA OUT A
UNDER
VOLTAGE
LOCKOUT
+
5V
6
S
+
5V
4
PWM B
VCC
GM OUT
OVP
9
–
+
POWER FACTOR
CONTROLLER
+
ISENSE A
11
1V
ISENSE B
1
7
–
ERROR
AMP
IEA
VREF
VCC
18
15
R
VCC
OUT A
GAIN MODULATOR
S
GND
Q
PGND A
IMULT
16
17
1
ML4819
PIN CONFIGURATION
ML4819
20-Pin PDIP
ISENSE A
1
20
CT
OVP
2
19
GND
GM OUT
3
18
VREF
EA OUT A
4
17
PGND A
INV A
5
16
OUT A
ISINE
6
15
VCC
DUTY CYCLE
7
14
OUT B
PWM B
8
13
PGND B
ISENSE B
9
12
RAMP COMP
RT
10
11
ILIM
TOP VIEW
PIN DESCRIPTION
PIN
NAME
FUNCTION
PIN
1
ISENSE A
Input form the PFC current sense
transformer to the PWM comparator
(+). Current Limit occurs when this
point reaches 5V.
11 ILIM
2
OVP
Input to Over-Voltage comparator.
3
GM OUT
Output of Gain Modulator. A resistor
to ground on this pin converts the
current to a voltage.
4
EA OUT A
Output of error amplifier.
5
INV A
Inverting input to error amplifier.
6
ISINE
Current Multiplier input.
7
DUTY CYCLE PWM controller duty cycle is limited
by setting this pin to a fixed voltage.
8
PWM B
Error voltage feedback input.
9
ISENSE B
Input for Current Sense resistor for
current mode operation or for
Oscillator ramp for voltage mode
operation.
10 RT
2
Oscillator timing resistor pin. A 5V
source across this resistor sets the
charging current for CT
NAME
FUNCTION
Cycle by cycle PWM current limit.
Exceeding 1V threshold on this pin
terminates the PWM cycle.
12 RAMP COMP Buffered output from the Oscillator
Ramp (CT). A resistor to ground sets a
current, 1/2 of which is sourced on
pins 9 and 11.
13 GND B
Return for the high current totem pole
output of the PWM controller.
14 OUT B
PWM controller totem pole output.
15 VCC
Positive Supply for the IC.
16 OUT A
PFC controller totem pole output.
17 GND A
Return for the high current totem pole
output of the PFC controller.
18 VREF
Buffered output for the 5V voltage
reference
19 GND
Analog signal ground.
20 CT
Timing Capacitor for the Oscillator.
ML4819
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings are those values beyond which
the device could be permanently damaged. Absolute
maximum ratings are stress ratings only and functional
device operation is not implied.
Supply Voltage (VCC) ................................................. 35V
Output Current, Source or Sink (RAMP COMP)
DC ....................................................................... 1.0A
Output Energy (capacitive load per cycle)................... 5mJ
Multiplier ISINE Input (ISINE) ................................... 1.2mA
Error Amp Sink Current (GM OUT) ......................... 10mA
Oscillator Charge Current ......................................... 2mA
Analog Inputs (ISENSE A, EA OUT A, INV A)
............................................................... –0.3V to 5.5V
Junction Temperature ............................................ 150×C
Storage Temperature Range ..................... –65×C to 150×C
Lead Temperature (soldering 10 sec.) ..................... 260×C
Thermal Resistance (qJA)
Plastic DIP or SOIC .......................................... 60×C/W
OPERATING CONDITIONS
Temperature Range
ML4819C .................................................. 0×C to 70×C
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, RT = 14kW, CT = 1000pF, TA = Operating Temperature Range, VCC = 15V (Notes 1, 2).
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
90
97
104
kHz
OSCILLATOR
Initial Accuracy
TJ = 25×C
Voltage Stability
12V < VCC < 18V
Temperature Stability
Total Variation
Line, temp.
0.2
%
2
%
88
106
kHz
Ramp Valley
0.9
V
Ramp Peak
4.3
V
RT Voltage
Discharge Current (PWM B open)
4.8
5.0
5.2
V
TJ = 25×C, VOUT A = 2V
7.5
8.4
9.3
mA
VOUT A = 2V
7.2
8.4
9.5
mA
15
mV
–2
–10
mA
DUTY CYCLE LIMIT COMPARATOR
Input Offset Voltage
–15
Input Bias Current
Duty Cycle
VDUTY CYCLE = VREF/2
43
45
49
%
Output Voltage
TJ = 25×C, IO = 1mA
4.95
5.00
5.05
V
Line Regulation
12V < VCC < 25V
2
20
mV
Load Regulation
1mA < IO < 20mA
8
25
mV
REFERENCE
Temperature Stability
0.4
4.9
%
Total Variation
Line, load, temperature
Output Noise Voltage
10Hz to 10kHz
50
Long Term Stability
TJ = 125×C, 1000 hours, (Note 1)
5
25
mV
Short Circuit Current
VREF = 0V
–85
–180
mA
15
mV
–1.0
mA
–30
5.1
V
mV
ERROR AMPLIFIER
Input Offset Voltage
–15
Input Bias Current
–0.1
Open Loop Gain
1 < VEA OUT A < 5V
60
75
dB
PSRR
12V < VCC < 25V
60
90
dB
Output Sink Current
VEA OUT A = 1.1V, VINV A = 5.2V
2
12
mA
Output Source Current
VEA OUT A = 5.0V, VINV A = 4.8V
–0.5
–1.0
mA
3
ML4819
ELECTRICAL CHARACTERISTICS
(Continued)
PARAMETER
CONDITIONS
MIN
TYP
6.5
7.0
MAX
UNITS
ERROR AMPLIFIER (continued)
Output High voltage
IEA OUT A = –0.5mA, VINV A = 4.8V
Output Low Voltage
IEA OUT A = 2mA, VINV A = 5.2V
0.7
Unity Gain Bandwidth
V
1.0
1.0
V
MHz
GAIN MODULATOR
ISINE Input Voltage
ISINE = 500mA
0.4
0.7
0.9
V
Output Current (GM OUT)
ISINE = 500mA, INV A = VREF –20mV
460
495
505
mA
0
10
mA
990
1005
mA
ISINE = 500mA, INV A = VREF + 20mV
ISINE = 1mA, INV A = VREF – 20mV
900
Bandwidth
PSRR
12V < VCC < 25V
200
kHz
70
dB
VC(T) – 1
V
SLOPE COMPENSATION CIRCUIT
RAMP COMP Voltage
51
mA
15
mV
120
140
mV
Input Bias Current
–0.3
–3
mA
Propagation Delay
150
IOUT (ISENSE A or ISENSE B)
IRAMP COMP = 100mA (Note 3)
45
Input Offset Voltage
Output Off
–15
Hysteresis
Output On
100
48
OVP COMPARATOR
ns
ISENSE COMPARATORS
Input Common Mode Range
Input Offset Voltage
–0.2
5.5
V
ISENSE A
–15
15
mV
ISENSE B
0.4
0.7
0.9
V
–3
–10
mA
0
3
mA
Input Bias Current
Input Offset Current
–3
Propagation Delay
ILIMIT (A) Trip Point
150
VOVP = 5.5V
ns
4.8
5
5.2
V
.95
1.0
1.05
V
Input Bias Current
–2
–10
mA
Propagation Delay
150
ILIM COMPARATOR
ILIMIT Trip Point
ns
OUTPUT DRIVERS
Output Voltage Low
Output Voltage High
IOUT = –20mA
0.1
0.4
V
IOUT = –200mA
1.6
2.2
V
IOUT = 20mA
13
13.5
V
IOUT = 200mA
12
13.4
V
Output Voltage Low in UVLO
IOUT = –1mA, VCC = 8V
0.1
Output Rise/Fall Time
CL = 1000pF
50
4
0.8
V
ns
ML4819
ELECTRICAL CHARACTERISTICS
PARAMETER
(Continued)
CONDITIONS
MIN
TYP
MAX
UNITS
Start-Up Threshold
15
16
17
V
Shut-Down Threshold
9
10
11
V
UNDER-VOLTAGE LOCKOUT
VREF Good Threshold
4.4
V
SUPPLY
Supply Current
Note 1:
Note 2:
Note 3:
Start-Up, VCC = 14V
0.6
1.2
mA
Operating, TJ = 25×C
25
35
mA
Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions.
VCC is raised above the Start-Up Threshold first to activate the IC, then returned to 15V.
PWM comparator bias currents are subtracted from this reading.
FUNCTIONAL DESCRIPTION
OSCILLATOR
The ML4819 oscillator charges the external capacitor (CT)
with a current (ISET) equal to 5/RSET. When the capacitor
voltage reaches the upper threshold, the comparator
changes state and the capacitor discharges to the lower
threshold through Q1. While the capacitor is discharging,
the clock provides a high pulse.
+5V
DUTY CYCLE
7
+
ISET
5V
VREF
10
RT
ISET
The oscillator period can be described by the following
relationship:
20
tOSC = tRAMP + tDEADTIME
+
CT
CLOCK
–
TO PWM
LATCHES
8.4mA
where:
t RAMP =
TO PWM
LATCH B
–
C(Ramp Valley to Peak)
ISET
Q1
and:
t DEADTIME =
C(Ramp Valley to Peak)
8.4mA - ISET
The maximum duty cycle of the PWM section can be
limited by setting a threshold on pin 7. when the CT ramp
is above the threshold at pin 7, the PWM output is held
off and the PWM flip-flop is set:
DLIMIT ≅
D OSC × (VPIN7 - 0.9)
3.4
CLOCK
tD
RAMP PEAK
CT
RAMP VALLEY
where:
DLIMIT = Desired duty cycle limit
DOSC = Oscillator duty cycle
Figure 1. Oscillator Block Diagram
5
VCC = 15V
TA = 25 C
10
0p
RT, TIMING RESISTOR (kΩ)
30
20
F
90%
0p
20
50
0p
1n
F
10
F
F
85%
2n
F
8
5n
5
F
10
nF
100
0
80
GAIN
60
30
50
100
200
300
fOSC, OSCILLATOR FREQUENCY (kHz)
MAX DUTY CYCLE
–30
60
90
40
PHASE
20
120
0
150
–20
10
3
20
VCC = 15V
VO = 1.0V TO 5.0V
RL = 100kΩ
TA= 25 C
100
1.0k
500
10k
100k
f, FREQUENCY (Hz)
1.0M
φ, EXCESS PHASE (DEGREES)
95%
50
AVOL, OPEN-LOOP VOLTAGE GAIN (dB)
ML4819
180
10M
Figure 5. Error Amplifier Open-Loop Gain and
Phase vs Frequency
Figure 2. Oscillator Timing Resistance vs. Frequency
GAIN MODULATOR
VSAT, OUTPUT SATURATION VOLTAGE (V)
0
SOURCE SATURATION
(LOAD TO GROUND)
VCC
–1.0
–2.0
VCC = 15V
80µs PULSED LOAD
120 Hz RATE
TA = 25 C
The output of the gain modulator is a current of the form:
3.0
TA = 25 C
2.0
IOUT is proportional to ISINE ¥ IEA
SINK SATURATION
(LOAD TO VCC)
1.0
GND
0
The ML4819 gain modulator is a linear current input
multiplier to provide high immunity to the disturbances
caused by high power switching. The rectified line input
sine wave is converted to a current via a dropping resistor.
In this way, small amounts of ground noise produce an
insignificant effect on the reference to the PWM
comparator.
0
200
400
600
800
IO, OUTPUT LOAD CURRENT (mA)
Figure 3. Output Saturation Voltage vs. Output Current
ERROR AMPLIFIER
The ML4819 error amplifier is a high open loop gain, wide
bandwidth amplifier.
+5V
where ISINE is the current in the dropping resistor, and IEA
is a current proportional to the output of the error
amplifier. When the error amplifier is saturated high, the
output of the gain modulator is approximately equal to
the ISINE input current.
The gain modulator output current is converted into the
reference voltage for the PWM comparator through a
resistor to ground on the gain modulator output. The gain
modulator output is clamped to 5V to provide current
limiting.
+8V
ISINE
+
6
IERR
ERROR
VOLTAGE
0.5mA
9V
4
3
INV
6
ISINE 3 IERR
–
EA OUT
Figure 4. Error Amplifier Configuration
GAIN MODULATOR
3
MULTIPLIER
Figure 6. Gain Modulator Block Diagram
ML4819
SLOPE COMPENSATION
Slope compensation is accomplished by adding 1/2 of the
current flowing out of pin 12 to pin 1 (for the PFC section
and pin 9 (for the PWM section). The amount of slope
compensation is equal to (IRAMP COMP/2) ¥ RL where RL is
the impedance to GND on pin 1 or pin 9. Since most of
the PWM applications will be limited to 50% duty cycle,
slope compensation should not be needed for the PWM
section. This can be defeated by using a low impedance
load to the current sense on pin 9.
ENABLE
VREF
VREF
GEN.
5V VREF
9V
INTERNAL
BIAS
–
VCC
+
20
OSC
Figure 9. Under-Voltage Lockout Block Diagram
CT
VREF
IR(SC)
9V
IR(SC) 4 2
40
TO PIN 9
Q1
RAMP COMP
12
ICC, SUPPLY CURRENT (mA)
10
RT
TO PIN 1
IR(SC) 4 2
RSC
SLOPE
COMPENSATION
Figure 7. Slope Compensation Circuit
20
10
TA = 25 C
4.5V
0
400
4.0V
3.5V
300
3.0V
200
2.5V
100
2.0V
E/A OUTPUT VOLTAGE (V)
MULTIPLIER OUTPUT CURRENT (µA)
500
30
0
10
20
VCC, SUPPLY VOLTAGE (V)
30
40
Figure 10a. Total Supply Current vs. Supply Voltage
1. 5V
0
0
100
200
300
SINE INPUT CURRENT (µA)
400
35
500
30
UNDER VOLTAGE LOCKOUT
On power-up the ML4819 remains in the UVLO condition;
output low and quiescent current low. The IC becomes
operational when VCC reaches 16V. When VCC drops
below 10V, the UVLO condition is imposed. During the
UVLO condition, the 5V VREF pin is “off”, making it
usable as a status flag.
ICC — SUPPLY CURRENT
Figure 8. Gain Modulator Linearity
25
OPERATING
CURRENT
20
15
10
5
START-UP
0
0
10
20
30
40
50
60
70
TEMPERATURE ( C)
Figure 10b. Supply Current (ICC) vs. Temperature
7
∆VREF, REFERENCE VOLTAGE CHANGE (mV)
ML4819
Where DON is the duty cycle [TON/(TON + TOFF)]. The
input boost inductor will dry out when the following
condition is satisfied:
0
VCC = 15V
–4.0
[
(2)
VINDRY = 1− DON(MAX) × VOUT
(3)
or
–12
[
–16
–20
–24
0
20
40
60
80
100
120
Figure 11. Reference Load Regulation
For example:
POWER FACTOR SECTION
The power factor section in the ML4819 is similar to the
power factor section in the ML4812 with the exception of
the operation of the slope compensation circuit. Please
refer to the ML4812 data sheet for more information.
The following calculations refer to Figure 12 in this data
sheet. The component designators in the equations below
refer to the following components in Figure 12:
RT = R16, CT = C6.
INPUT INDUCTOR (L1) SELECTION
The central component in the regulator is the input boost
inductor. The value of this inductor controls various
critical operational aspects of the regulator. If the value is
too low, the input current distortion will be high and will
result in low power factor and increased noise at the
input. This will require more input filtering. In addition,
when the value of the inductor is low the inductor dries
out (runs out of current) at low currents. Thus the power
factor will decrease at lower power levels and/or higher
line voltages. If the inductor value is too high, then for a
given operating current the required size of the inductor
core will be large and/or the required number of turns will
be high. So a balance must be reached between distortion
and core size.
One more condition where the inductor can dry out is
analyzed below where it is shown to be maximum duty
cycle dependent.
if: VOUT = 380V and
DON(MAX) = 0.95
then substituting in (3) yields VINDRY = 20V. The effect of
drying out is an increase in distortion at low input voltages.
For a given output power, the instantaneous value of the
input current is a function of the input sinusoidal voltage
waveform. As the input voltage sweeps from zero volts to
its maximum value and back, so does the current.
The load of the power factor regulator is usually a
switching power supply which is essentially a constant
power load. As a result, an increase in the input voltage
will be offset by a decrease in the input current.
By combining the ideas set forth above, some ground
rules can be obtained for the selection and design of the
input inductor:
Step 1:
Find minimum operating current.
IIN(MIN)PEAK =
1.414 × PIN(MIN)
VIN(MAX)
(4)
VIN(MAX) = 260V
PIN(MIN) = 50W
then:
IIN(MIN)PEAK = 0.272A
For the boost converter at steady state:
VIN
1− DON
Effectively, the above relationship shows that the resetting
volt-seconds are more than setting volt-seconds. In energy
transfer terms this means that less energy is stored in the
inductor during the ON time than it is asked to deliver during
the OFF time. The net result is that the inductor dries out.
The recommended maximum duty cycle is 95% at
100KHz to allow time for the input inductor to dump its
energy to the output capacitors.
APPLICATIONS
VOUT =
]
VINDRY: Voltage where the inductor dries out.
VOUT: Output dc voltage.
TA = 25 C
IREF, REFERENCE SOURCE CURRENT (mA)
8
]
VIN(t) < VOUT × 1− DON(MAX)
–8.0
(1)
Step 2: Choose a minimum current at which point the
inductor current will be on the verge of drying
out. For this example 40% of the peak current
found in step 1 was chosen.
R14
4.7kΩ
R13
4.7kΩ
VREF
VREF
R4
C7 12kΩ
10µF
35V
R1
330kΩ
R15
4.3kΩ
C12
1µF
R3
5.6kΩ
D8
3V
Q4
2N2222
VREF
PFC
ENHANCEMENT
R9
27kΩ
R6
4.75kΩ
R5
357kΩ
R2
510kΩ
C8
1
R8
4.53kΩ
R7
357kΩ
C1
0.6µF
R10
33kΩ
R16
15kΩ
ILIM 11
RAMP COMP 12
9 ISENSE B
10 RT
PGND B 13
OUT B 14
VCC 15
OUT A 16
PGND A 17
VREF 18
GND 19
CT 20
8 PWM B
7 DUTY CYCLE
6 ISINE
5 INV A
4 EA OUT A
–
PGND
UI
ML4819
3 GM OUT
2 OVP
1 ISENSE A
B+ 380V
F1
D1 - D4 +
1N5406
0.1µF
VREF
R11
91Ω
VCC
T2
PWM REGULATOR
D13
D14
65kΩ
R18
C13 1µF R17, 3Ω
C9
C6
1000pF
C5
1000pF
IN
VREF
R22
10Ω
C11
1µF
C14
2200pF
R21
3kΩ
R20
7.5Ω
D12
MUR150
C11
1µF
R25
1Ω
R24
1Ω
C4
6800pF
Q1
IRF840
T1
D6
MUR850
1N5406
D5
R23, 100Ω
D11
MUR150
D10
1N4148
R19, 3kΩ
NP
L1
OUT
R12
10Ω
D7
1N4148
STARTUP
CIRCUIT
Q3
IRF840
T3
Q3
IRF840
MOC
8102
U3
TL431
U2
2.26kΩ
R29
0.1µF
C20
R26
1.5kΩ
R27
1.2kΩ
C16
1µF
D9
MUR110
C2
330µF
400VDC
T3
C19
4.7µF
D13
D83
–004
C3
0.62µF
R28
8.66kΩ
C18
1500µF
C10
330µF
25VDC
+
B+ 380 VDC
POWER FACTOR CORRECTION
VOUT–
VIN+
+12V
ML4819
Figure 12. Typical Application, 180W Power Factor Corrected 12V Output Power Supply
9
ML4819
then:
ILDRY = 100mA
CURRENT SENSE AND SLOPE (RAMP) COMPENSATION
COMPONENT SELECTION
Step 3: The value of the inductance can now be found
using previously calculated data.
L1 =
=
VINDRY × DON(MAX)
IL(DRY) × fOSC
20V × 0.95
= 2mH
100mA × 100kHz
(5)
The inductor can be allowed to decrease in value when
the current sweeps from minimum to maximum value.
This allows the use of smaller core sizes. The only
requirement is that the ramp compensation must be
adequate for the lower inductance value of the core so
that there is adequate compensation at high current.
Step 4: The presence of the ramp compensation will
change the dry out point, but the value found
above can be considered a good starting point.
Based on the amount of power factor correction
the value of L1 can be optimized after a few
iterations.
Gapped Ferrites, Molypermalloy, and Powdered Iron cores
are typical choices for core material. The core material
selected should have a high saturation point and
acceptable losses at the operating frequency.
One ferrite core that is suitable at around 200W is the
#4229PL00-3C8 made by Ferroxcube. This ungapped core
will require a total gap of 0.180" for this application.
OSCILLATOR COMPONENT SELECTION
The oscillator timing components can be calculated by
using the following expression:
fOSC =
1.36
R T × CT
(6)
Slope compensation in the ML4819 is provided internally.
A current equal to VCT/2(R18) is added to ISENSE A (pin 1).
this is converted to a voltage by R10, adding slope to the
sensed current through T1. The amount of slope
compensation should be at least 50% of the downslope of
the inductor current during the off time as reflected on pin
1. Note that slope compensation is a requirement only if
the inductor current is continuous and the duty cycle is
more than 50%. The highest inductor downslope is found
at the point of inductor discontinuity:
diL VB − VIN DRY 380V − 20V
=
=
= 0.18 A / µs
dt
L
2mH
The downslope as reflected to the input of the PWM
comparator is given by:
SPWM =
VB − VIN DRY
t
×I
CT = OFF DIS = 1000pF
VOSC
(7)
1.36 =
1.36
fOSC × CT 100kHz × 1000pF
= 13.6kΩ. Choose R T = 14kΩ.
10
×
R11
NC
The value of the ramp compensation (SCPWM) as seen at
pin 1 is:
SCPWM =
2.5 × R 9
R16 × C6 × R18
The required value for R18 can therefore be found by
equating:
where ASC is the amount of slope compensation and
solving for R18.
(8)
(10)
Current-sensing MOSFETs or resistive sensing can also be
used to sense the switch current. In these cases, the
sensed signal has to be amplified to the proper level
before it is applied to the ML4819.
SCPWM = ASC × SPWM
Step 2: Calculate the required value of the timing
resistor.
RT =
L1
Where NC is the turns ratio of the current transformer (T1)
used. In general, current transformers simplify the sensing of
switch currents, especially at high power levels where the
use of sense resistors is complicated by the amount of
power they have to dissipate. Normally the primary side
of the transformer consists of a single turn and the
secondary consists of several turns of either enameled
magnet wire or insulated wire. The diameter of the ferrite
core used in this example is 0.5" (SPANG/Magnetics
F41206-TC). The rectifying diode at the output of the
current transformer can be a 1N4148 for secondary
currents up to 75mA average.
For example:
Step 1: At 100kHz with 95% duty cycle TOFF = 500ns
calculate CT using the following formula:
(9)
(11)
ML4819
The value of R9 (pin 3) depends on the selection of R2
(pin 6).
R2 =
R9 >
VIN(MAX) PEAK
ISINE (PEAK)
= 260 × 1.414 = 510kΩ
0.72mA
VCLAMP × R2 4.8 × 510kΩ
= 22kΩ
=
80 × 1.414
VIN(MIN) PEAK
(12)
(13)
Choose R9 = 27kW
The peak of the inductor current can be found
approximately by:
ILPEAK =
1.414 × POUT 1.414 × 200
=
= 3.14A
VIN (MIN) RMS
90
VCLAMP × NC 4.9 × 80
=
= 100Ω
ILPEAK
4
2
(14)
(15)
Having calculated R11 the value SPWM and of R18 can
now be calculated:
SPWM = 380V − 20 × 100 = 0.225V / µs
2mH
80
R18 =
(17)
Choose two 178kW, 1% connected in series.
Where R11 is the sense resistor, and VCLAMP is the current
clamp at the inverting input of the PWM comparator. This
clamp is internally set to 5V. In actual application it is a
good idea to assume a value less than 5V to avoid
unwanted current limiting action due to component
tolerances. In this application VCLAMP was chosen as 4.8V.
R18 =
The values of the voltage regulation loop components are
calculated based on the operating output voltage. Note
that voltage safety regulations require the use of sense
resistors that have adequate voltage rating. As a rule of
thumb if 1/4W through-hole resistors are used, two of
them should be put in series. The input bias current of the
error amplifier is approximately 0.5µA, therefore the
current available from the voltage sense resistors should
be significantly higher than this value. Since two 1/4W
resistors have to be used the total power rating is 1/2W.
The operating power is set to be 0.4W then with 380V
output voltage the value can be calculated as follows:
R5 = (380V) / 0.4W = 360kΩ
Next select NC, which depends on the maximum switch
current. Assume 4A for this example. NC is 80 turns.
R11 =
VOLTAGE REGULATION COMPONENTS
Then R6 can be calculated using the formula below:
V × R5 5V × 356kΩ
R6 = REF
=
= 4.747kΩ
VB − VREF
380V − 5V
(18)
Choose 4.75kW, 1%. One more critical component in the
voltage regulation loop is the feedback capacitor for the
error amplifier. The voltage loop bandwidth should be set
such that it rejects the 120Hz ripple which is present at
the output. If this ripple is not adequately attenuated it
will cause distortion on the input current waveform.
Typical bandwidths range anywhere from a few Hertz to
15Hz. The main compromise is between transient
response and distortion. The feedback capacitor can be
calculated using the following formula:
C8 =
1
3.142 × R5 × BW
C8 =
1
= 0.44µF
3.142 × 356kΩ × 2Hz
(19)
2.5 × R 9
ASC × SPWM × R T × CT
2.5 × 28.8k
6
0.7 × (0.225 × 10 ) × 14kΩ × 1nF
≅ 30kΩ
(16)
Choose R18 = 33kW
The following values were used in the calculation:
R9 = 27kW
RT = 14kW
ASC = 0.7
CT = 1nF
11
ML4819
OVERVOLTAGE PROTECTION (OVP) COMPONENTS
PWM SECTION
The OVP loop should be set so that there is no interaction
with the voltage control loop. Typically it should be set to
a level where the power components are safe to operate.
Ten to fifteen volts above VOUT seems to be adequate.
This sets the maximum transient output voltage to about
395V.
The PWM section in Figure 12 is a two switch forward
converter, shown in Figure 14 below for clarity. This fully
clamped circuit eliminates the need for very high
voltage MOSFETs. Flyback topology is also possible with
the ML4819.
By choosing the high voltage side resistor of the OVP
circuit the same way as above i.e. R7 = 356K then R8 can
be calculated as:
R8 =
VREF × R7
= 5V × 356kΩ = 4.564kΩ
VOVP − VREF
395V − 5V
385VDC
Q2
T2
D12
(20)
D11
T3
Choose 4.53kW, 1%.
Note that R5, R6, R7 and R8 should be tight tolerance
resistors such as 1% or better.
Q3
ML4819
T2
OFF-LINE START-UP AND BIAS SUPPLY GENERATION
The Start-Up circuit in Figure 12 can be either a “bleed
resistor” (39kW, 2W) or the circuit shown in Figure 13. The
bleed resistor method offers advantage of simplicity and
lowest cost, but may yield excessive turn-on delay at low
line.
When the voltage on pin 15 (VCC) exceeds 16V, the IC
starts up. The energy stored on the C21 supplies the IC
with running power until the supplemental winding on T3
can provide the power to sustain operation.
IN
START-UP
CIRCUIT
R33
2kΩ
VREF
R30
4.3kΩ
R31
510kΩ
R32
2kΩ
OUT
C21
0.1
D16
22V
TO VCC
D15
1N4001
Figure 13. Start-Up Circuit
ENHANCEMENT CIRCUIT
The power factor enhancement circuit (inside the dotted
lines) in Figure 11 is described in Application Note 11. It
improves the power factor and lowers the input current
harmonics. Note that the circuit meets IEC1000-3-2
specifications (with the enhancement circuit installed) on
the harmonics by a large margin while correcting the
input power factor to better than 0.99 under most steady
state operating conditions.
12
This regulator (Figure 12) uses current mode control.
Current is sensed through R24 and filtered for high
frequency noise and leading edge transient through T23
and C14. The main regulation loop is through PWM B. The
TL431 (U3) in the secondary serves as both the voltage
reference and error amplifier. Galvanic isolation is
provided by an optocoupler (U2) which provides a current
command signal on pin 8. Loop compensation is provided
by R29 and C20. The output voltage is set by:
R
VOUT = 2.5 1+ 29
R28
Q6
IRF821
Q5
2N2222
Figure 14. Two-Switch Forward Converter
(21)
The control loop is compensated using standard
compensation techniques.
Current is limited to a threshold of 2A (1V on R24). The duty
cycle is limited in this circuit to below 50% to prevent
transformer (T3) core saturation. The maximum duty cycle
limit of 45% is set using a threshold of VREF/2 on pin 7.
the circuit in Figure 12 can be modified for voltage mode
operation by utilizing the slope current which appears on
pin 9 as show in figure 15 below.
The ramp amplitude appearing on pin 9 will be:
I
VR = R18 × R(V)
2
(22)
where R18 is the slope compensation resistor. Since this
circuit operates with a constant input voltage (as supplied
by the PFC section) voltage feed-forward is unnecessary.
ML4819
VREF
OSC
SLOPE
COMP.
CT
IRSC
C6
20
2
R13
+
–
DUTY CYCLE
ILIM
+
–
7
11
FROM
R23, C14
R14
1V
ISENSE B
–
9
RV
0.7V
+
+
–
PWM B
8
FROM U2, R15
Figure 15. Voltage Mode Configuration
CONSTRUCTION AND LAYOUT TIPS
High frequency power circuits require special care during
breadboard construction and layout. Double sided printed
circuit boards with ground plane on one side are highly
recommended. All critical switching leads (power FET,
output diode, IC output and ground leads, bypass
capacitors) should be kept as small as possible. This is to
minimize both the transmission and pickup of switching
noise.
There are two kinds of noise coupling; inductive and
capacitive. As the name implies inductive coupling is
due to fast changing (high di/dt) circulating switching
currents. The main source is the loop formed by Q1, D6,
and
C3–C4. Therefore this loop should be as small as possible,
and the above capacitors should be good, high frequency
types.
The second form of noise coupling is due to fast changing
voltages (high dv/dt). The main source in this case is the
drain of the power FET. The radiated noise in this case can
be minimized by insulating the drain of the FET from the
heatsink and then tying the heatsink to the source of the
FET with a high frequency capacitor.
The IC has two ground pins named PWR GND and Signal
GND. These two pins should be connected together with a
very short lead at the printed circuit board exit point. In
general grounding is very important and ground loops
should be avoided. Star grounding schemes are preferred.
13
ML4819
Component Values/Bill of Materials for Figure 12
Reference
Reference
Description
C1, C3
0.6µF, 630V Film (250 VAC)
C2
330µF 25V Electrolytic
C4
6800pF 1KV Ceramic
C5, C6
1000pF
C7
10µF 35V
C8, C11, C13, C15, C16 1µF Ceramic
C9, C20, C21
0.1µF Ceramic
C10
1500µF 25V Electrolytic
C12, C17
1µF Ceramic
C14
2200 pF
C18
1500µF 16V Electrolytic
C19
4.7µF
D1- D5
1N5406
D6
MUR850
D7, D10
1N4148
D8
3V Zener diode or 4 x 1N4148
in series
D9
MUR110
D11, D12
MUR150
D13
D83-004K
D15
1N4001
D16, D14
1N5818 or 1N5819
F1
5A, 250V, 3AG
L1
2mH, 4A IPEAK
Core: Ferroxcube 4229-3CB
150 Turns #24 AWG
0.150" gap
L2
10mH
Core: Spang OF 43019 UG00
8 Turns #15AWG gap 0.05"
Description
R4
12ký
R5, R7
357ký, 1%
R6
4.57ký, 1%
R8
4.53ký, 1%
R9
27ký
R10, R18
33ký
R11
91ý
R12, R22
10ý
R13, R14
4.7ký
R15
4.3ký
R16
15ký
R17
3ý
R20
7.5ý
R21,R19
3ký
R23
100ý
R24, R25
1ý
R26
1.5ký
R27
1.2ký
R28
8.66ký, 1%
R29
2.26ký, 1%
R30
2ký, 1W
R32, R33
2ký
T1
Spang F41206-TC or
Siemens B64290-K45-X27 or X830 or
Ferroxcube 768T188-38
NS = 80, NP = 1
T2
Same core as T1
NS = NP = 15 bifilar
T3
Core: Ferroxcube 4229-3C8
Pri. 44 Turns #18 Litz wire
Sec. 4 Turns of copper strip
Aux. 2 Turns #24 AWG
Q1-Q3
IRF840
Q4, Q5
2N2222
Q6
IRF821
U2
MOC8102
R1
330ký
U3
TL431
R2, R31
510ký
R3
5.6ký
14
ML4819
PHYSICAL DIMENSIONS inches (millimeters)
Package: P20
20-Pin PDIP
1.010 - 1.035
(25.65 - 26.29)
20
0.240 - 0.260 0.295 - 0.325
(6.09 - 6.61) (7.49 - 8.26)
PIN 1 ID
1
0.060 MIN
(1.52 MIN)
(4 PLACES)
0.055 - 0.065
(1.40 - 1.65)
0.100 BSC
(2.54 BSC)
0.015 MIN
(0.38 MIN)
0.170 MAX
(4.32 MAX)
0.125 MIN
(3.18 MIN)
0.016 - 0.022
(0.40 - 0.56)
SEATING PLANE
0.008 - 0.012
(0.20 - 0.31)
0º - 15º
ORDERING INFORMATION
PART NUMBER
ML4819CP
ML4819CS (Obsolete)
TEMPERATURE RANGE
0°C to 70°C
0°C to 70°C
PACKAGE
Molded DIP (P20)
Molded SOIC (S20)
© Micro Linear 1997
is a registered trademark of Micro Linear Corporation
Products described in this document may be covered by one or more of the following patents, U.S.: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940;
5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; Japan: 2598946; 2619299. Other patents are pending.
Micro Linear reserves the right to make changes to any product herein to improve reliability, function or design.
Micro Linear does not assume any liability arising out of the application or use of any product described herein,
neither does it convey any license under its patent right nor the rights of others. The circuits contained in this
data sheet are offered as possible applications only. Micro Linear makes no warranties or representations as to
whether the illustrated circuits infringe any intellectual property rights of others, and will accept no responsibility
or liability for use of any application herein. The customer is urged to consult with appropriate legal counsel
before deciding on a particular application.
2092 Concourse Drive
San Jose, CA 95131
Tel: 408/433-5200
Fax: 408/432-0295
DS4819-01
15