MR25H10 FEATURES 1Mb Serial SPI MRAM • No write delays • Unlimited write endurance • Data retention greater than 20 years • Automatic data protection on power loss • Fast, simple SPI interface with up to 40 MHz clock rate • 2.7 to 3.6 Volt power supply range • 3 μA sleep mode standby current • Industrial, automotive temperatures • Small footprint 8-pin DFN RoHS-compliant package • Direct replacement for serial EEPROM, Flash, FeRAM INTRODUCTION The MR25H10 is a 1,048,576-bit magnetoresistive random access memory (MRAM) device organized as 131,072 words of 8 bits. The MR25H10 offers serial EEPROM and serial Flash compatible read/write timing with no write delays and unlimited read/write endurance. RoHS Unlike other serial memories, both reads and writes can occur randomly in memory with no delay between writes. The MR25H10 is the ideal memory solution for applications that must store and retrieve data and programs quickly using a small number of I/O pins The MR25H10 is available in a small footprint 5 mm x 6 mm 8-pin DFN package that is compatible with serial EEPROM, Flash, and FeRAM products. The MR25H10 provides highly reliable data storage over a wide range of temperatures. The product is offered with industrial temperature (-40° to +85 °C), and automotive temperature (-40° to +125° C) range options. CONTENTS 1. DEVICE PIN ASSIGNMENT.........................................................................2 2. SPI COMMUNICATIONS PROTOCOL...................................................... 4 3. ELECTRICAL SPECIFICATIONS.................................................................10 4. TIMING SPECIFICATIONS.......................................................................... 12 5. ORDERING INFORMATION.......................................................................12 6. MECHANICAL DRAWING..........................................................................13 7. REVISION HISTORY......................................................................................15 How to Reach Us..........................................................................................15 Everspin Technologies © 2009 1 Document Number: MR25H10 Rev. 5, 5/2010 MR25H10 1. DEVICE PIN ASSIGNMENT Overview The MR25H10 is a serial MRAM with memory array logically organized as 128Kx8 using the four pin interface of chip select (CS), serial input (SI), serial output (SO) and serial clock (SCK) of the serial peripheral interface (SPI) bus. Serial MRAM implements a subset of commands common to today’s SPI EEPROM and Flash components allowing MRAM to replace these components in the same socket and interoperate on a shared SPI bus. Serial MRAM offers superior write speed, unlimited endurance, low standby & operating power, and more reliable data retention compared to available serial memory alternatives. Figure 1.1 Block Diagram Instruction Decode Clock Generator Control Logic Write Protect WP CS HOLD SCK 128KB MRAM ARRAY Instruction Register 17 Address Register Counter 8 SO Data I/O Register SI 4 Nonvolatile Status Register System Configuration Single or multiple devices can be connected to the bus as show in Figure 1.2. Pins SCK, SO and SI are common among devices. Each device requires CS and HOLD pins to be driven seperately. Figure 1.2 System Configuration SCK MOSI MISO SO SPI Micro Controller SI SCK EVERSPIN SPI MRAM 1 HOLD CS SO SI SCK EVERSPIN SPI MRAM 2 CS HOLD CS1 HOLD 1 CS2 HOLD 2 MOSI = Master Out Slave In MISO = Master In Slave Out Everspin Technologies © 2009 2 Document Number: MR25H10 Rev. 5, 5/2010 MR25H10 DEVICE PIN ASSIGNMENT Figure 1.3 Pin Diagrams (Top View) CS 1 8 VDD SO 2 7 HOLD WP 3 6 SCK VSS 4 5 SI 8-Pin DFN Table 1.1 Pin Functions Signal Name Pin I/O Function Description CS 1 Input Chip Select An active low chip select for the serial MRAM. When chip select is high, the memory is powered down to minimize standby power, inputs are ignored and the serial output pin is Hi-Z. Multiple serial memories can share a common set of data pins by using a unique chip select for each memory. SO 2 Output Serial Output The data output pin is driven during a read operation and remains Hi-Z at all other times. SO is Hi-Z when HOLD is low. Data transitions on the data output occur on the falling edge of SCK. WP 3 Input Hold A low on the write protect input prevents write operations to the Status Register. VSS 4 Supply Ground Power supply ground pin. SI 5 Input Serial Input All data is input to the device through this pin. This pin is sampled on the rising edge of SCK and ignored at other times. SI can be tied to SO to create a single bidirectional data bus if desired. SCK 6 Input Serial Clock Synchronizes the operation of the MRAM. The clock can operate up to 40 MHz to shift commands, address, and data into the memory. Inputs are captured on the rising edge of clock. Data outputs from the MRAM occur on the falling edge of clock. The serial MRAM supports both SPI Mode 0 (CPOL=0, CPHA=0) and Mode 3 (CPOL=1, CPHA=0). In Mode 0, the clock is normally low. In Mode 3, the clock is normally high. Memory operation is static so the clock can be stopped at any time. HOLD 7 Input Hold A low on the Hold pin interrupts a memory operation for another task. When HOLD is low, the current operation is suspended. The device will ignore transitions on the CS and SCK when HOLD is low. All transitions of HOLD must occur while CS is low. VDD 8 Supply Power Supply Power supply voltage from +2.7 to +3.6 volts. Everspin Technologies © 2009 3 Document Number: MR25H10 Rev. 5, 5/2010 MR25H10 2. SPI COMMUNICATIONS PROTOCOL MR25H10 can be operated in either SPI Mode 0 (CPOL=0, CPHA =0) or SPI Mode 3 (CPOL=1, CPHA=1). For both modes, inputs are captured on the rising edge of the clock and data outputs occur on the falling edge of the clock. When not conveying data, SCK remains low for Mode 0; while in Mode 3, SCK is high. The memory determines the mode of operation (Mode 0 or Mode 3) based upon the state of the SCK when CS falls. All memory transactions start when CS is brought low to the memory. The first byte is a command code. Depending upon the command, subsequent bytes of address are input. Data is either input or output. There is only one command performed per CS active period. CS must go inactive before another command can be accepted. To ensure proper part operation according to specifications, it is necessary to terminate each access by raising CS at the end of a byte (a multiple of 8 clock cycles from CS dropping) to avoid partial or aborted accesses. Table 2.1 Command Codes Instruction Description Binary Code Hex Code Address Bytes Data Bytes WREN Write Enable 0000 0110 06h 0 0 WRDI Write Disable 0000 0100 04h 0 0 RDSR Read Status Register 0000 0101 05h 0 1 WRSR Write Status Register 0000 0001 01h 0 1 READ Read Data Bytes 0000 0011 03h 3 1 to ∞ WRITE Write Data Bytes 0000 0010 02h 3 1 to ∞ SLEEP Enter Sleep Mode 1011 1001 B9h 0 0 WAKE Exit Sleep Mode 1010 1011 ABh 0 0 Status Register The status register consists of the 8 bits listed in table 2.1. As seen in table 2.2, the Status Register Write Disable bit (SRWD) is used in conjunction with bit 1 (WEL) and the Write Protection pin (WP) to provide hardware memory block protection. Bits BP0 and BP1 define the memory block arrays that are protected as described in table 2.3. The fast writing speed of MR25H10 does not require write status bits. The state of bits 6,5,4, and 0 can be user modified and do not affect memory operation. All bits in the status register are pre-set from the factory in the “0” state. Table 2.2 Status Register Bit Assignments Bit 7 SRWD Bit 6 Don’t Care Bit 5 Don’t Care Everspin Technologies © 2009 Bit 4 Don’t Care Bit 3 BP1 4 Bit 2 BP0 Bit 1 WEL Bit 0 Don’t Care Document Number: MR25H10 Rev. 5, 5/2010 MR25H10 SPI COMMUNICATIONS PROTOCOL Table 2.3 Memory Protection Modes WEL 0 1 1 1 SRWD WP Protected Blocks Unprotected Blocks X 0 1 1 X X Low High Protected Protected Protected Protected Protected Writable Writable Writable Status Register Protected Writable Protected Writable Table 2.4 Block Memory Write Protection BP1 0 0 1 1 Status Register BP0 0 1 0 1 Memory Contents Unprotected Area All Memory Lower Three-Quarters Lower Half None Protected Area None Upper Quarter Upper Half All Block Protection The memory enters hardware block protection when the WP input is low and the Status Register Write Disable (SRWD) bit is set to 0. The memory leaves hardware block protection only when the WP pin goes high. While WP is low, the write protection blocks for the memory are determined by the status register bits BP0 and BP1 and cannot be modified without taking the WP signal high again. If the WP signal is high (independent of the status of SRWD bit), the memory is in software protection mode. This means that block write protection is controlled solely by the status register BP0 and BP1 block write protect bits and this information can be modified using the WRSR command. Read Status Register (RDSR) The Read Status Register (RDSR) command allows the Status Register to be read. The Status Register can be read at any time to check the status of write enable latch bit, status register write protect bit, and block write protect bits. For MR25H10, the write in progress bit (bit 0) is not written by the memory because there is no write delay. The RDSR command is entered by driving CS low, sending the command code, and then driving CS high. Figure 2.1 RDSR CS 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 SCK SI Mode 3 Mode 0 0 0 0 0 0 1 0 1 MSB Status Register Out SO High Impedance 7 6 5 4 3 2 1 0 High Z MSB Everspin Technologies © 2009 5 Document Number: MR25H10 Rev. 5, 5/2010 MR25H10 SPI COMMUNICATIONS PROTOCOL Write Enable (WREN) The Write Enable (WREN) command sets the Write Enable Latch (WEL) bit in the status register (bit 1). The Write Enable Latch must be set prior to writing either bit in the status register or the memory. The WREN command is entered by driving CS low, sending the command code, and then driving CS high. Figure 2.2 WREN CS Mode 3 SCK 0 1 2 3 4 5 6 7 Mode 3 Mode 0 Mode 0 Instruction (06h) SI 0 0 0 0 0 1 1 0 High Impedance SO Write Disable (WRDI) The Write Disable (WRDI) command resets the Write Enable Latch (WEL) bit in the status register (bit 7). This prevents writes to status register or memory. The WRDI command is entered by driving CS low, sending the command code, and then driving CS high. The Write Enable Latch (WEL) is reset on power-up or when the WRDI command is completed. Figure 2.3 WRDI CS Mode 3 SCK 0 1 2 3 4 5 6 7 Mode 3 Mode 0 Mode 0 Instruction (04h) SI SO 0 0 0 0 0 1 0 0 High Impedance Write Status Register (WRSR) The Write Status Register (WRSR) command allows new values to be written to the Status Register. The WRSR command is not executed unless the Write Enable Latch (WEL) has been set to 0 by executing a WREN command while pin WP and bit SRWD correspond to values that make the status register writable as seen in table 2.2. Status Register bits are non-volatile when the Write Status Register (WRSR) command is issued immediately following a fresh power-up and WREN command. If the WRSR command is issued in a different sequence, i.e. not immediately following power-up and WREN, then upon power cycling the state of the status register bits must be reset before any other part operation. Everspin Technologies © 2009 6 Document Number: MR25H10 Rev. 5, 5/2010 MR25H10 SPI COMMUNICATIONS PROTOCOL The WRSR command is entered by driving CS low, sending the command code and status register write data byte, and then driving CS high. Figure 2.4 WRSR CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 Mode 3 14 SCK Mode 0 Instruction (01h) SI 0 0 0 0 0 Status Register In 0 0 1 7 6 5 4 3 2 1 0 MSB High Impedance SO Read Data Bytes (READ) The Read Data Bytes (READ) command allows data bytes to be read starting at an address specified by the 24-bit address. Only address bits 0-16 are decoded by the memory. The data bytes are read out sequentially from memory until the read operation is terminated by bringing CS high The entire memory can be read in a single command. The address counter will roll over to 0000h when the address reaches the top of memory. The READ command is entered by driving CS low and sending the command code. The memory drives the read data bytes on the SO pin. Reads continue as long as the memory is clocked. The command is terminated by bring CS high. Figure 2.5 READ CS 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 32 32 32 32 32 32 32 SCK Instruction (03h) SI 0 0 0 0 0 24-Bit Address 0 1 1 X X X 3 2 1 0 MSB SO Data Out 1 High Impedance 7 6 5 4 3 Data Out 2 2 1 0 7 MSB Everspin Technologies © 2009 7 Document Number: MR25H10 Rev. 5, 5/2010 MR25H10 SPI COMMUNICATIONS PROTOCOL Write Data Bytes (WRITE) The Write Data Bytes (WRITE) command allows data bytes to be written starting at an address specified by the 24-bit address. Only address bits 0-16 are decoded by the memory. The data bytes are written sequentially in memory until the write operation is terminated by bringing CS high. The entire memory can be written in a single command. The address counter will roll over to 0000h when the address reaches the top of memory. Unlike EEPROM or Flash Memory, MRAM can write data bytes continuously at its maximum rated clock speed without write delays or data polling. Back to back WRITE commands to any random location in memory can be executed without write delay. MRAM is a random access memory rather than a page, sector, or block organized memory so it is ideal for both program and data storage. The WRITE command is entered by driving CS low, sending the command code, and then sequential write data bytes. Writes continue as long as the memory is clocked. The command is terminated by bringing CS high. Figure 2.6 WRITE CS 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 32 32 32 32 32 32 32 SCK Instruction (02h) SI 0 0 0 0 0 24-Bit Address 0 1 0 X X X 3 2 1 MSB 0 7 6 5 4 3 2 1 0 MSB High Impedance SO CS 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 Mode 3 55 SCK Mode 0 Data Byte 2 SI 7 6 5 4 3 Data Byte 3 2 1 0 7 6 5 4 3 MSB Data Byte N 2 1 0 7 6 5 4 3 2 1 0 MSB High Impedance SO Everspin Technologies © 2009 8 Document Number: MR25H10 Rev. 5, 5/2010 MR25H10 SPI COMMUNICATIONS PROTOCOL Enter Sleep Mode (SLEEP) The Enter Sleep Mode (SLEEP) command turns off all MRAM power regulators in order to reduce the overall chip standby power to 3 μA typical. The SLEEP command is entered by driving CS low, sending the command code, and then driving CS high. The standby current is achieved after time, tDP. Figure 2.7 SLEEP CS t DP 0 1 2 3 4 5 6 Mode 3 7 SCK Mode 0 Instruction (B9h) SI 1 0 1 1 1 0 0 1 Active Current Standby Current Sleep Mode Current SO Exit Sleep Mode (WAKE) The Exit Sleep Mode (WAKE) command turns on internal MRAM power regulators to allow normal operation. The WAKE command is entered by driving CS low, sending the command code, and then driving CS high. The memory returns to standby mode after tRDP. The CS pin must remain high until the tRDP period is over. Figure 2.8 WAKE CS t RDP 0 1 2 3 4 5 6 7 SCK Mode 3 Mode 0 Instruction (ABh) SI 1 0 1 0 1 0 1 Sleep Mode Current 1 Standby Current SO Everspin Technologies © 2009 9 Document Number: MR25H10 Rev. 5, 5/2010 MR25H10 3. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings This device contains circuitry to protect the inputs against damage caused by high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage greater than maximum rated voltages to these high-impedance (Hi-Z) circuits. The device also contains protection against external magnetic fields. Precautions should be taken to avoid application of any magnetic field more intense than the field intensity specified in the maximum ratings. Table 3.1 Absolute Maximum Ratings1 Parameter Symbol Value Unit Supply voltage2 VDD -0.5 to 4.0 V Voltage on any pin2 VIN -0.5 to VDD + 0.5 V Output current per pin IOUT ±20 mA Package power dissipation PD 0.600 W Temperature under bias MR25H10C (Industrial) MR25H10M (Automotive)4 TBIAS -45 to 95 -45 to 130 °C Storage Temperature Tstg -55 to 150 °C Lead temperature during solder (3 minute max) TLead 260 °C Maximum magnetic field during write Hmax_write 12,000 A/m Maximum magnetic field during read or standby Hmax_read 12,000 A/m 1 Permanent device damage may occur if absolute maximum ratings are exceeded. Functional operation should be restricted to recommended operating conditions. Exposure to excessive voltages or magnetic fields could affect device reliability. 2 All voltages are referenced to VSS. The DC value of VIN must not exceed actual applied VDD by more than 0.5V. The AC value of VIN must not exceed applied VDD by more than 2V for 10ns with IIN limited to less than 20mA. Power dissipation capability depends on package characteristics and use environment. 3 Automotive temperature profile assumes 10% duty cycle at maximum temperature (2-years out of 20-year life). 4 Everspin Technologies © 2009 10 Document Number: MR25H10 Rev. 5, 5/2010 MR25H10 ELECTRICAL SPECIFICATIONS Table 3.2 Operating Conditions Parameter Symbol Min Power supply voltage VDD 2.7 Input high voltage VIH 2.2 Input low voltage VIL Temperature under bias MR25H10C (Industrial) MR25H10M (Automotive) TA Typical Max Unit 3.6 V - VDD + 0.3 V -0.5 - 0.8 V -40 -40 - 85 125 °C Table 3.3 DC Characteristics Parameter Symbol Min Typical Max Unit Input leakage current ILI - - ±1 μA Output leakage current ILO - - ±1 μA Output low voltage (IOL = +4 mA) (IOL = +100 μA) VOL - - 0.4 VDD + 0.2 V Output high voltage (IOH = -4 mA) (IOH = -100 μA) VOH 2.4 VDD - 0.2 - - V Table 3.4 Power Supply Characteristics 1 Parameter Symbol Typical Max Unit Active Read Current (@ 1 MHz) IDDR 2.5 TBD mA Active Read Current (@ 40 MHz) IDDR 10 TBD mA Active Write Current (@ 1 MHz) IDDW 6.5 TBD mA Active Write Current (@ 40 MHz) IDDW 12 TBD mA Standby Current (CS High) ISB1 90 TBD μA Standby Sleep Mode Current (CS High)1 ISB2 3 10 μA Automotive ISB2 TBD. Everspin Technologies © 2009 11 Document Number: MR25H10 Rev. 5, 5/2010 MR25H10 4. TIMING SPECIFICATIONS Table 4.1 Capacitance1 1 Parameter Symbol Typical Max Unit Control input capacitance CIn - 6 pF Input/Output capacitance CI/O - 8 pF ƒ = 1.0 MHz, dV = 3.0 V, TA = 25 °C, periodically sampled rather than 100% tested. Table 4.2 AC Measurement Conditions Parameter Value Unit Logic input timing measurement reference level 1.5 V Logic output timing measurement reference level 1.5 V Logic input pulse levels 0 or 3.0 V Input rise/fall time 2 ns Output load for low and high impedance parameters See Figure 4.1 Output load for all other timing parameters See Figure 4.2 Figure 4.1 Output Load for Impedance Parameter Measurements ZD= 50 Ω Output RL = 50 Ω VL = 1.5 V Figure 4.2 Output Load for all Other Parameter Measurements 3.3 V 590 Ω Output 30 pF 435 Ω Everspin Technologies © 2009 12 Document Number: MR25H10 Rev. 5, 5/2010 MR25H10 TIMING SPECIFICATIONS Power-Up Timing The MR25H10 is not accessible for a start-up time, tPU= 400 μs after power up. Users must wait this time from the time when VDD (min) is reached until the first CS low to allow internal voltage references to become stable. The CS signal should be pulled up to VDD so that the signal tracks the power supply during power-up sequence. Table 4.3 Power-Up Parameter Symbol Min Typical Max Unit Write Inhibit Voltage VWI 2.2 - 2.7 V Startup Time tPU 400 - - μs Figure 4.3 Power-Up Timing VDD VDD(max) Chip Selection not allowed VDD(min) Reset state of the device t PU Normal Operation VWI Time Everspin Technologies © 2009 13 Document Number: MR25H10 Rev. 5, 5/2010 MR25H10 TIMING SPECIFICATIONS Synchronous Data Timing Table 4.4 AC Timing Parameters1 Parameter Symbol Min Typical Max Unit SCK Clock Frequency fSCK 0 - 40 MHz Input Rise Time tRI - - 50 ns Input Fall Time tRF - - 50 ns SCK High Time tWH 11 - - ns SCK Low Time tWL 11 - - ns Synchronous Data Timing (See figure 4.4) CS High Time tCS 40 - - ns CS Setup Time tCSS 10 - - ns CS Hold Time tCSH 10 - - ns Data In Setup Time tSU 5 - - ns Data In Hold Time tH 5 - - ns Output Valid2 tV 0 - 9 ns Output Hold Time tHO 0 - - ns HOLD Setup Time tHD 10 - - ns HOLD Hold Time tCD 10 - - ns HOLD to Output Low Impedance tLZ - - 20 ns HOLD to Output High Impedance tHZ - - 20 ns WP Setup To CS tWPS 5 - - ns WP Hold From CS tWPH 5 - - ns Sleep Mode Entry Time tDP 3 - - μs Sleep Mode Exit Time tRDP 400 - - μs Output Disable Time tDIS 12 - - ns HOLD Timing (See figure 4.5) Other Timing Specifications 1 2 Operating Temperature Range, VDD=2.7 to 3.6 V, CL= 30 pF Automotive tV is TBD. Everspin Technologies © 2009 14 Document Number: MR25H10 Rev. 5, 5/2010 MR25H10 TIMING SPECIFICATIONS Figure 4.4 Synchronous Data Timing CS tCS V IH V IL tCSS SCK tCSH V IH tWH V IL tSU SI SO tWL tH V IH V IL V IH tV tHO tDIS High Impedance V IL Figure 4.5 HOLD Timing CS tCD tCD SCK tHD tHD HOLD tHZ tLZ SO Everspin Technologies © 2009 15 Document Number: MR25H10 Rev. 5, 5/2010 MR25H10 5. ORDERING INFORMATION Figure 4.1 Part Numbering System MR 25H 10 M DC Package Options DC 8 Pin DFN on Tray DCR 8 Pin DFN on Tape and Reel Temperature Range C Industrial (-40 to +85 °C ambient) M Automotive (-40 to +125 °C ambient) Memory Density 10 1 Mb Interface 25H High Speed Serial SPI Family Product Type MR Magnetoresistive RAM Table 4.1 Available Parts Part Number Description Temperature MR25H10CDC MR25H10MDC MR25H10CDCR MR25H10MDCR 3 V 1Mb Serial MRAM 8-DFN 3 V 1Mb Serial MRAM 8-DFN 3 V 1Mb Serial MRAM 8-DFN Tape and Reel 3 V 1Mb Serial MRAM 8-DFN Tape and Reel Industrial Automotive Industrial Automotive Preliminary - This is a product in development that has fixed target specifications that are subject to change pending characterization results. Everspin Technologies © 2009 16 Document Number: MR25H10 Rev. 5, 5/2010 MR25H10 6. MECHANICAL DRAWINGS Figure 6.1 DFN Package Exposed metal Pad. Do not connect anything except VSS A 8 5 DAP Size 4.4 x 4.4 J B I L G H M C Pin 1 Index D Unit A mm - Max 5.10 - Min 4.90 Detail A 1 4 F K J E B C D E 6.10 1.00 0.45 1.27 BSC 5.9 0.90 0.35 K Detail A F G H 0 0.70 0.35 Ref. 0.05 0.50 I 4.20 4.00 J 4.20 4.00 K L M 0.261 C0.35 R0.20 0.195 NOTE: 1. Angles in degrees. 2. Coplanarity applies to the exposed pad as well as the terminals. Coplanarity shall not exceed 0.08 mm. 3. Warpage shall not exceed 0.10 mm. 4. Refer to JEDEC MO-229 Everspin Technologies © 2009 17 Document Number: MR25H10 Rev. 5, 5/2010 MR25H10 7. REVISION HISTORY Revision Date Description of Change 0 Sep 12, 2008 Initial Advance Information Release 1 Jul 10, 2009 Change ac load resistance, tPU to 400 us, tRDP to 400 us, Change # of Address Bytes in Table 2 to 3, New Package Drawing, Make Preliminary 2 Jul 16, 2009 Increase Absolute Max Magnetic Field during write, read, and standby to 12,000 A/m 3 Jan 5, 2010 Described block protect in detail with power sequencing. 4 Feb 5, 2010 Added section system configuration. 5 May 17, 2010 Removed commercial specifications. All parts meet industrial specifications. Preliminary - This is a product in development that has fixed target specifications that are subject to change pending characterization results. How to Reach Us: Home Page: www.everspin.com E-Mail: [email protected] [email protected] [email protected] USA/Canada/South and Central America Everspin Technologies 1300 N. Alma School Road, CH-409 Chandler, Arizona 85224 +1-877-347-MRAM (6726) +1-480-347-1111 Europe, Middle East and Africa [email protected] Wokingham, United Kingdom +44 (0)118 907 6155 Japan [email protected] Yokohama, Japan +81 (0) 45-846-6299 Information in this document is provided solely to enable system and software implementers to use Everspin Technologies products. There are no express or implied licenses granted hereunder to design or fabricate any integrated circuit or circuits based on the information in this document. Everspin Technologies reserves the right to make changes without further notice to any products herein. Everspin makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Everspin Technologies assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters, which may be provided in Everspin Technologies data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters including “Typicals” must be validated for each customer application by customer’s technical experts. Everspin Technologies does not convey any license under its patent rights nor the rights of others. Everspin Technologies products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Everspin Technologies product could create a situation where personal injury or death may occur. Should Buyer purchase or use Everspin Technologies products for any such unintended or unauthorized application, Buyer shall indemnify and hold Everspin Technologies and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Everspin Technologies was negligent regarding the design or manufacture of the part. Everspin™ and the Everspin logo are trademarks of Everspin Technologies, Inc. All other product or service names are the property of their respective owners. ©Everspin Technologies, Inc. 2009 Asia Pacific [email protected] Document Control Number: M25H10 Revision 5.1, 5/2010 File Name: EST_MR25H10_prod.pdf Everspin Technologies © 2009 18 Document Number: MR25H10 Rev. 5, 5/2010