ETC VS1005

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VS1005g Datasheet
VS1005g - Audio Processing Platform IC
Analog Hardware Features
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Three channels of 24-bit audio ADC
Two 24-bit audio DACs
Stereo earphone driver for 30 Ω load
Internal microphone amplifiers
Stereo FM radio receiver with RDS
10-bit ADC, 3-5 external inputs
Operation from single power supply,
four programmable internal regulators
Digital Hardware Features
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Portable recorders
Digital docking stations
MP3 players
Internet radio
Wireless headphones
Audio co-processor
Overview
VS1005g is a flexible audio platform device.
It is built around VS_DSP4 , which is a powerful DSP (Digital Signal Processor) core. The
digital interfaces provide flexible access to external devices in standalone applications and
flexible digital audio data inputs and outputs
when the device is used as an audio signal
processor in more complex systems. The analog interfaces provide high-quality audio inputs and outputs, and the control ADC can
be used for example for interfacing a resistive touch panel.
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100 MIPS VS_DSP4 processor core
128 KiB program RAM (32 KiWord)
128 KiB data RAM (2×32 KiWord)
Protected 8 Mi-bit FLASH (Optional)
USB 2.0 Hi-Speed (480 Mbit/s)
Device / Host
I2S and SPDIF digital audio interfaces
NAND FLASH interface with EEC
SD Card interface
2 SPI bus interfaces
10BaseT Ethernet controller
UART interface
All digital pins are user configurable for
general purpose IO
Flexible clock selection, default operation from 12.288 MHz
Internal PLL clock multiplier for digital
logic
RTC with battery backed memory
Reed-Solomon error correction
HW debug support with VSIDE via JTAG
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Applications
Firmware and VSOS Features
VS1005g has an embedded FLASH memory of 8 Mi-bits (1 MiByte) for customization
by VLSI, customers or third parties. The firmware and hardware are designed to prevent
access to the embedded FLASH in protected
mode. After FLASH memory programming
VS1005g can be booted from it as a fully customized stand-alone audio processor.
VS1005g is offered in six different variants
(see Chapter 4 for details).
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• Decoders: MP3, WMA, Ogg Vorbis, AAC,
HE-AAC, FLAC, WAV PCM
• Encoders: MP3, Ogg Vorbis, WAV PCM
• File I/O for SD cards and NAND flash
• FM tuner and RDS decoder
• USB host and slave libraries
• Graphical display with resistive touch panel
• Extensive audio DSP library
• IP stack of Ethernet
• Flexible boot options
• Pre-emptive multitasking
• Easy-to-write software interface with VSIDE
Note: All VSOS features not available yet.
Version: 0.52, 2012-11-07
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Contents
VS1005g Front Page
CONTENTS
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VS1005g Datasheet
1
Table of Contents
2
List of Figures
6
1 Disclaimer
7
2 Licenses
7
3 Definitions
7
4 Product Variants
7
5 Characteristics & Specifications
8
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . .
9
5.3
Analog Characteristics of Audio Outputs . . . . . . . . . . . . . . . . . . . . . .
10
5.4
Analog Characteristics of Audio Inputs . . . . . . . . . . . . . . . . . . . . . . .
11
5.5
SAR Characteristics
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11
5.6
FM Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11
5.7
Analog Characteristics of Regulators . . . . . . . . . . . . . . . . . . . . . . . .
12
Analog Characteristics of VHIGH voltage monitor . . . . . . . . . . . . . . . . .
13
Analog Characteristics of CVDD voltage monitor . . . . . . . . . . . . . . . . . .
13
8
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5.1
14
6.1
LFGA-88 Package
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14
6.2
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16
6.3
VS1005g Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17
5.8
5.9
5.10 Power Button Characteristics
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
13
5.11 Digital Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13
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6 Package and Pin Descriptions
6.3.1
PCB Layout Recommendations . . . . . . . . . . . . . . . . . . . . .
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2
7 Example Schematic
20
8 VS1005g General Description
8.1
8.2
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VS1005g Internal Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21
22
8.1.1
Regulator Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22
8.1.2
I/O Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23
8.1.3
Digital Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23
Analog Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25
9 Oscillator and Reset Configuration
10 Firmware Operation
26
27
27
10.2 NAND FLASH Probe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28
10.3 UART Boot/Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
29
10.4 Default Firmware Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
30
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10.1 SPI Boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
30
10.4.2 USB Mass Storage and Audio Device . . . . . . . . . . . . . . . . . .
30
10.5 Supported Audio Decoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
31
10.5.1 Supported MP3 (MPEG layer III) Decoder Formats . . . . . . . . . .
31
10.6 Supported Audio Encoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32
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10.4.1 SD Card Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.6.1 Supported MP3 (MPEG layer III) Encoder Formats . . . . . . . . . .
11 VS1005g Peripherals and Registers
33
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
33
11.2 VS1005g Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
33
11.3 VS1005g Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
34
11.4 Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
36
11.4.1 Interrupt Controller Registers . . . . . . . . . . . . . . . . . . . . . .
37
11.4.2 Interrupt Enable INT_ENABLE[0/1]_[H/L]P . . . . . . . . . . . . . . .
37
11.4.3 Interrupt Origin INT_ORIGIN[0/1] . . . . . . . . . . . . . . . . . . . .
38
11.4.4 Interrupt Vector INT_VECTOR . . . . . . . . . . . . . . . . . . . . . .
38
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11.1 The Processor Core
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11.4.6 Interrupt Global Disable INT_GLOB_DIS . . . . . . . . . . . . . . . .
38
11.4.7 Interrupt Global Enable INT_GLOB_ENA . . . . . . . . . . . . . . . .
39
11.5 DSP Clock Domain Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . .
40
11.5.1 General Purpose Software Registers . . . . . . . . . . . . . . . . . .
40
11.5.2 Peripheral I/O Control . . . . . . . . . . . . . . . . . . . . . . . . . . .
40
11.5.3 PLL Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
40
11.6 XTALI Clock Domain Registers . . . . . . . . . . . . . . . . . . . . . . . . . . .
42
11.6.1 Analog Control Registers . . . . . . . . . . . . . . . . . . . . . . . . .
42
11.6.2 Regulator and Peripheral Clock Control Registers . . . . . . . . . . .
44
11.7 Audio Playback Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
46
11.7.1 Primary Audio Path 24-bit Sample Rate Upconverter with Filters:
DAC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
47
11.7.2 Primary Audio Path Volume Control . . . . . . . . . . . . . . . . . . .
48
11.7.3 Secondary Audio Path: DAOSET Registers . . . . . . . . . . . . . .
49
11.7.4 Filterless Sample Rate Converter (SRC) Registers . . . . . . . . . .
50
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11.4.5 Interrupt Enable Counter INT_ENCOUNT . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . .
51
11.8.1 Configuring Signal Paths for ADC1, ADC2 and ADC3 . . . . . . . . .
52
11.8.2 Digital Filter Operation Modes . . . . . . . . . . . . . . . . . . . . . .
54
11.9 FM Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
56
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11.8 24-bit Analog to Digital Converters (ADC)
56
11.9.2 Configuring the FM Demodulator . . . . . . . . . . . . . . . . . . . .
57
11.9.3 Radio Data System (RDS) . . . . . . . . . . . . . . . . . . . . . . . .
59
11.10 SPI Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
61
11.11 Common Data Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
65
11.11.1 Ethernet Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . .
68
11.11.2 Reed-Solomon Codec . . . . . . . . . . . . . . . . . . . . . . . . . .
71
11.11.3 Nand Flash Interface . . . . . . . . . . . . . . . . . . . . . . . . . . .
75
11.11.4 SD Card Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
77
11.12 USB Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
79
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11.9.1 Configuring RF and Analog Modules for FM Receiver Mode . . . . .
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11.12.2 USB Clocking Modes . . . . . . . . . . . . . . . . . . . . . . . . . . .
83
11.12.3 USB Host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
83
11.13 Interruptable General Purpose IO Ports 0-2 . . . . . . . . . . . . . . . . . . . .
84
11.14 S/PDIF Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
86
11.14.1 S/PDIF Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
86
11.14.2 S/PDIF Receiver Registers . . . . . . . . . . . . . . . . . . . . . . . .
87
11.14.3 S/PDIF Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . .
89
11.14.4 S/PDIF Transmitter Registers . . . . . . . . . . . . . . . . . . . . . .
90
11.15 UART Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
93
11.15.1 UART Peripheral Registers . . . . . . . . . . . . . . . . . . . . . . . .
93
11.16 Watchdog Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
95
11.16.1 Watchdog Registers . . . . . . . . . . . . . . . . . . . . . . . . . . .
95
11.17 I2S Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
96
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11.12.1 USB Peripheral Registers . . . . . . . . . . . . . . . . . . . . . . . .
11.17.1 I2S Peripheral Registers . . . . . . . . . . . . . . . . . . . . . . . . .
96
11.18 Timer Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
98
11.18.1 Timer Peripheral Registers . . . . . . . . . . . . . . . . . . . . . . . .
98
11.19 Real Time Clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
11.19.1 RTC Peripheral Registers . . . . . . . . . . . . . . . . . . . . . . . . 100
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11.20 10-Bit Successive Approximation Register Analog-to-Digital Converter (SAR) . 102
11.21 Pulse Width Modulation Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
11.22 Special Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
11.22.1 Software Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
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12 VS1005g Debugger
106
13 Document Version Changes
109
14 Contact Information
111
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VS1005g Datasheet
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LIST OF FIGURES
List of Figures
VS1005g top view, LFGA-88. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14
2
VS1005g bottom view, LFGA-88. . . . . . . . . . . . . . . . . . . . . . . . . . . .
15
3
VS1005g side view, LFGA-88 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15
4
VS1005g 88-pin LFGA pin assignment. . . . . . . . . . . . . . . . . . . . . . . .
16
5
VS1005g default pin usage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20
6
VS1005g external interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21
7
VS1005g block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22
8
User’s memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
33
9
VS1005g playback (DA) audio paths. . . . . . . . . . . . . . . . . . . . . . . . . .
46
10
VS1005g recording (AD and FM) signal paths . . . . . . . . . . . . . . . . . . . .
51
11
Block diagram of FM receiver, RF and analog section
. . . . . . . . . . . . . . .
56
12
RDS data structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
59
13
Block diagram of data interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . .
65
14
VS1005g USB block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
79
15
VS1005g UTM functional block diagram. . . . . . . . . . . . . . . . . . . . . . . .
80
16
S/PDIF frame format.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
86
17
S/PDIF sub-frame format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
86
18
RS232 serial interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . .
93
19
I2S frame format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20
JTAG state machine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
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VS1005g Datasheet
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PRODUCT VARIANTS
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Disclaimer
This is a preliminary datasheet. All properties and figures are subject to change.
2
Licenses
MPEG Layer-3 audio coding (VS1205) / decoding (VS1005) technology licensed from Fraunhofer IIS and Thomson.
Supply of this product does not convey a license nor imply any right to distribute MPEG Layer-3
compliant content created with this product in revenue-generating broadcast systems (terrestrial, satellite, cable and/or other distribution channels), streaming applications (via Internet,
intranets and/or other networks), other content distribution systems (pay-audio of audio-ondemand applications and the like) or on physical media (compact discs, digital versatile discs,
semiconductior chips, hard drives, memory cards and the like). An independent license for
such use is required. For details, please visit http://mp3licensing.com.
Definitions
B Byte, 8 bits.
b Bit.
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Ki “Kibi” = 210 = 1’024 (IEC 60027-2).
Mi “Mebi” = 220 = 1’048’576 (IEC 60027-2).
Gi “Gibi” = 230 = 1’073’741’824 (IEC 60027-2).
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VS_DSP VLSI Solution’s DSP core.
VSOS VLSI Solution’s Operating System
W Word. In VS_DSP, instruction words are 32-bit and data words are 16-bit wide.
4
Product Variants
PR
Device ID (Order Code)
VS1005G-Q
VS1005G-F-Q
VS1205G-Q
VS1205G-F-Q
VS8005G-Q
VS8005G-F-Q
Version: 0.52, 2012-11-07
MP3 Encoder
X
X
MP3 Decoder
X
X
X
X
Embedded 8 Mi-bit Flash
X
X
X
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VS1005g Datasheet
5
5.1
Characteristics & Specifications
Absolute Maximum Ratings
Parameter
Regulator input voltage
Analog Positive Supply
Digital Positive Supply
Digital RTC Supply
I/O Positive Supply
Voltage at Any Digital Input 3
Voltage at power Button
Voltage at RTC Pins
Total Injected Current on Pins
Operating Temperature
Storage Temperature
1
2
3
Must not exceed 3.6 V
Latch-up limit
Except RTC and PWRBTN pin
Must not exceed 1.95 V
Symbol
VHIGH
AVDD
CVDD
RTCVDD
IOVDD
PWRBTN
XTALI_RTC, XTALO_RTC
Min
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-40
-65
Max
5.25
3.6
1.95
1.95
3.6
IOVDD+0.31
3.6
CVDD+0.34
±200 2
+85
+150
Unit
V
V
V
V
V
V
V
V
mA
◦C
◦C
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CHARACTERISTICS & SPECIFICATIONS
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5.2
CHARACTERISTICS & SPECIFICATIONS
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Recommended Operating Conditions
Voltage Specification
Parameter
Symbol
Min
Operating temperature
-40
1
Analog and digital ground
AGND DGND
Regulator input voltage2
VHIGH
AVDD+0.3
Analog positive supply3
AVDD
2.75
3
Digital positive supply
CVDD
1.65
Digital RTC supply
RTCVDD
1.2
3
I/O positive supply
IOVDD
1.8
1
2
3
Typ
0.0
4.0
2.8
1.8
1.5
2.8
Max
+85
5.25
3.6
1.95
1.95
3.6
Unit
◦C
V
V
V
V
V
V
Must be connected together as close the device as possible for latch-up immunity.
At least 4.0 V is required for compliant USB level.
Regulator output of the device.
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Oscillator Specification
Parameter
Symbol
1
Input clock frequency
XTALI
Input clock duty cycle
Oscillator frequency tolerance
Startup time
Internal clock frequency, USB connected
CLKU
Internal clock frequency, USB disconnected
CLKI
3
RTC clock frequency
XTALI_RTC
RTC frequency tolerance
RTC oscillator startup time
1
Min
11
40
Typ
12.2882
50
+/-10
1
60
Max
13
60
60
98
32768
+/-100
1000
Unit
MHz
%
ppm
ms
MHz
MHz
Hz
ppm
ms
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The maximum sample rate that can be played with correct speed is XTALI/128. With 11 MHz
XTALI sample rates over 85937 Hz are played at 85937 Hz.
2 When full speed (FS) or Hi-Speed (HS) USB is used it is recommended that XTALI of
12.288 MHz or 12.0 MHz is used. The ROM USB firmware assumes XTALI = 12.288 MHz.
3 The 32 kHz crystal is optional, but required for RTC time counter.
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VS1005g Datasheet
5.3
CHARACTERISTICS & SPECIFICATIONS
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Analog Characteristics of Audio Outputs
Unless otherwise noted: AVDD=3.6V, CVDD=1.8V, IOVDD=2.8V, Vref=1.6 V, TA=+25◦ C, XTALI=12 MHz,
Internal Clock Multiplier 3.0×. DAC tested with full-scale output sinewave, measurement bandwidth 20..20000 Hz, analog output load: LEFT to CBUF 30 Ω, RIGHT to CBUF 30 Ω. Microphone test amplitude 50 mVpp, f=1 kHz, Line input test amplitude 2.2 Vpp, f=1 kHz. FM test
signal input level -70 dBm, deviation 75 kHz, pre-emphasis 50 us, f=1 kHz.
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DAC Characteristics
Parameter
Symbol
DAC Resolution
Dynamic range (DAC unmuted, A-weighted, min gain)
IDR
S/N ratio (full scale signal, no load)
SNR
S/N ratio (full scale signal, 30 ohm load)
SNRL
Total harmonic distortion, -3dB level, no load
THD
Total harmonic distortion, -3dB level, 30 ohm load
THDL
Crosstalk (L/R to R/L), 30 ohm load, without CBUF 1
XTALK1
Crosstalk (L/R to R/L), 30 ohm load, with CBUF
XTALK2
Gain mismatch (L/R to R/L)
GERR
Frequency response
AERR
Full scale output voltage
LEVEL
Deviation from linear phase
PH
Analog output load resistance
AOLR
Analog output load capacitance
AOLC
DC level, Vref =1.2 V (CBUF, LEFT, RIGHT)
DC level, Vref =1.6 V (CBUF, LEFT, RIGHT)
CBUF disconnect current (short-circuit protection)
1
Min
Typ
24
100
92
90
0.01
0.05
-75
-54
-0.5
-0.05
Max
0.5
0.05
1.0
0
302
5
1003
1.1
1.5
130
1.3
1.7
200
Unit
bits
dB
dB
dB
%
%
dB
dB
dB
dB
Vrms
◦
Ω
pF
V
V
mA
Loaded from Left/Right pin to analog ground via 100 µF capacitors.
AOLR may be lower than Typical, but distortion performance may be compromised. Also,
there is a maximum current that the internal regulators can provide.
3 CBUF must have external 10 Ω + 47 nF load, LEFT and RIGHT must have external 20 Ω +
10 nF load for optimum stability and ESD tolerance.
PR
EL
2
Version: 0.52, 2012-11-07
10
VS1005g Datasheet
5.4
CHARACTERISTICS & SPECIFICATIONS
IN
AR
Y
5
Analog Characteristics of Audio Inputs
ADC Characteristics
Parameter
Symbol Min
ADC Resolution
Microphone input amplifier gain
MICG
Microphone input amplitude
Microphone Total Harmonic Distortion
MTHD
Microphone S/N Ratio, A-weighted
MSNR
502
Line input amplitude
Line input Total Harmonic Distortion
LTHD
Line input S/N Ratio
LSNR
802
Sample rate
24
Line and Microphone input impedances
1
2
SAR Characteristics
5.6
EL
XTALI dependent
Max
IM
SAR Characteristics
Parameter
Symbol Min
Typ
SAR resolution
10
Input amplitude range
0
SAR sample rate 1
Integral Nonlinearity
INL
+/-2
Differential Nonlinearity
DNL
+/-0.5
AVDD
100
1401
0.10
28001
0.10
100
192
100
Unit
bits
dB
mVpp AC
%
dB
mVpp AC
%
dB
kHz
kΩ
Unit
bits
V
kHz
LSB
LSB
FM Characteristics
PR
FM Characteristics
Parameter
Channel frequency range, 10 kHz steps
FM mono S/N Ratio, deviation 22kHz, Input level -50dBm 1
FM stereo S/N Ratio, deviation 45kHz, Input level -50dBm 1
FM mono S/N Ratio, deviation 22kHz, Input level -90dBm 1
FM stereo S/N Ratio, deviation 45kHz, Input level -90dBm 1
Total harmonic distortion, deviation 75 kHz
Stereo separation
1
Max
Above typical amplitude the Harmonic Distortion increases.
Limit Min due to noise level of production tester.
5.5
1
Typ
24
20
50
0.02
75
2200
0.015
90
Symbol
LSNR
LSNR
LSNR
LSNR
THD
Min
76
Typ
72
47
45
27
0.1
40
Max
108
0.3
Unit
MHz
dB
dB
dB
dB
%
dB
Measured over whole FM band
Version: 0.52, 2012-11-07
11
VS1005g Datasheet
5.7
CHARACTERISTICS & SPECIFICATIONS
IN
AR
Y
5
Analog Characteristics of Regulators
Symbol
Min
1.7
55
1.7
55
Typ
60
1.8
1.8/3.63
4.0
2.0
304
60
1.8
1.8/3.63
4.0
2.0
304
1.65
25
1
EL
IM
Parameter
IOVDD
Recommended voltage setting range
Voltage setting step size
Default setting, reset mode 1
Default setting, active mode 2
Load regulation
Line regulation from VHIGH
Continuous current
IOVDD2
Recommended voltage setting range
Voltage setting step size
Default setting, reset mode 1
Default setting, active mode 2
Load regulation
Line regulation from VHIGH
Continuous current
CVDD
Recommended voltage setting range
Voltage setting step size
Default setting, reset mode 1
Default setting, active mode 2
Continuous current
Load regulation
Line regulation from VHIGH
AVDD
Recommended voltage setting range
Voltage setting step size
Default setting, reset mode 1
Default setting, active mode 2
Continuous current
Load regulation
Line regulation from VHIGH
PWRBTN
Minimum startup voltage
Minimum startup pulse
2.6
35
30
1.8
1.8
254
2.0
2.0
40
2.5
2.7
304
1.5
2.0
0.9
100
Max
Unit
3.6
65
V
mV
V
V
mV/mA
mV/V
mA
60
3.6
65
60
1.95
35
70
3.6
45
70
V
mV
V
V
mV/mA
mV/V
mA
V
mV
V
V
mA
mV/mA
mV/V
V
mV
V
V
mA
mV/mA
mV/V
V
ms
Device enters reset mode when XRESET pin is pulled low.
Device enters active mode when XRESET pin is pulled high after reset mode. Regulator
settings can be modified when booted from external memory (see Section 10).
3 Depends on GPIO0_7 pin status in boot (see Section 10).
4 Device is tested with a 30 mA load.
PR
2
Version: 0.52, 2012-11-07
12
VS1005g Datasheet
5.8
Analog Characteristics of VHIGH voltage monitor
Parameter
Trigger voltage
Hysteresis
5.9
Symbol
AMON
Min
Typ
1.07×AVDD
50
Max
Unit
V
mV
Analog Characteristics of CVDD voltage monitor
Parameter
Trigger voltage
Hysteresis
5.10
CHARACTERISTICS & SPECIFICATIONS
IN
AR
Y
5
Symbol
CMON
Min
1.40
Typ
1.45
2
Power Button Characteristics
Max
Unit
V
mV
Unless otherwise noted: VHIGH = 4.0..5.3 V
Parameter
Power button activation threshold
Digital Characteristics
EL
Parameter
High-Level Input Voltage
Low-Level Input Voltage
High-Level Output Voltage, -1.0 mA load 1
Low-Level Output Voltage, 1.0 mA load 1
XTALO high-level output voltage, -0.1 mA load
XTALO low-level output voltage, 0.1 mA load
Input leakage current
Rise time of all output pins, load = 30 pF 1
Typ
1.0
Symbol
Max
Unit
V
Min
0.7×IOVDD
-0.2
0.7×IOVDD
Typ
Max
IOVDD+0.3
0.3×IOVDD
0.3×IOVDD
0.7×IOVDD
-1.0
0.3×IOVDD
1.0
50
Unit
V
V
V
V
V
V
µA
ns
Pins GPIO0_[15:0], GPIO1_[15:0], GPIO2_[13:0].
PR
1
Min
IM
5.11
Symbol
PBTHR
Version: 0.52, 2012-11-07
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VS1005g Datasheet
6
6.1
PACKAGE AND PIN DESCRIPTIONS
IN
AR
Y
6
Package and Pin Descriptions
LFGA-88 Package
LFGA-88 is a 10x10x0.8 mm, lead (Pb) free and RoHS-compliant package. RoHS is a short
name of Directive 2002/95/EC on the restriction of the use of certain hazardous substances in
electrical and electronic equipment.
LFGA package and pin dimensions are shown in Figures 1, 2 and 3. For more information
about the LFGA-88 package and its dimensions visit http://www.vlsi.fi/ .
PR
EL
IM
Note that the pins do not extend to the sides of the IC (see Figures 2 and 3).
Figure 1: VS1005g top view, LFGA-88.
Version: 0.52, 2012-11-07
14
VS1005g Datasheet
PACKAGE AND PIN DESCRIPTIONS
EL
IM
IN
AR
Y
6
PR
Figure 2: VS1005g bottom view, LFGA-88.
Figure 3: VS1005g side view, LFGA-88
Version: 0.52, 2012-11-07
15
VS1005g Datasheet
Pin Assignments
EL
IM
6.2
PACKAGE AND PIN DESCRIPTIONS
IN
AR
Y
6
PR
Figure 4: VS1005g 88-pin LFGA pin assignment.
Version: 0.52, 2012-11-07
16
VS1005g Datasheet
VS1005g Pin Descriptions
Pin Name
GPLATE
Pin Name
XTALO
XTALI
AVDD
VHIGH
CVDD
IO2VDD
IOVDD
XRESET
NFDIO0 / GPIO0_0
NFDIO1 / GPIO0_1
NFDIO2 / GPIO0_2
NFDIO3 / GPIO0_3
NFDIO4 / GPIO0_4
NFDIO5 / GPIO0_5
NFDIO6 / GPIO0_6
NFDIO7 / GPIO0_7
NFRDY / GPIO0_8
NFRD / GPIO0_9
XCS1 / GPIO1_4
SCLK1 / GPIO1_5
CVDD1
MISO1 / GPIO1_6
Pin Name
Function
LFGA
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Pin Type
Function
AO
AI
APWR
PWR
CPWR
IO2PWR
IOPWR
DI
DIOPD
DIOPD
DIOPD
DIOPD
DIOPD
DIOPD
DIOPD
DIOPD
DIO
DIO
DIOPD
DIOPD
CPWR
DIOPD
Crystal output
Crystal input
Analog power supply, Regulator output
Power supply, Regulator input
Core power supply, Regulator output
Serial Flash power supply, Regulator output
I/O power supply, Regulator output
Active low asynchronous reset, schmitt-trigger input
Nand-flash IO0 / General-purpose IO Port 0, bit 0
Nand-flash IO1 / General-purpose IO Port 0, bit 1
Nand-flash IO2 / General-purpose IO Port 0, bit 2
Nand-flash IO3 / General-purpose IO Port 0, bit 3
Nand-flash IO4 / General-purpose IO Port 0, bit 4
Nand-flash IO5 / General-purpose IO Port 0, bit 5
Nand-flash IO6 / General-purpose IO Port 0, bit 6
Nand-flash IO7 / General-purpose IO Port 0, bit 7
Nand-flash READY / General-purpose IO Port 0, bit 8
Nand-flash RD / General-purpose IO Port 0, bit 9
SPI1 XCS / General-Purpose I/O Port 1, bit 4
SPI1 CLK / General-Purpose I/O Port 1, bit 5
Core power supply, connect to regulator CPWR
SPI1 MISO / General-Purpose I/O Port 1, bit 6
LFGA
Pin
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
Pin Type
Function
DIOPD
DIO
IOPWR
DIOPD
DIOPD
DIOPD
DIOPD
DIOPD
DIOPD
DIOPD
DIOPD
DIOPD
DIOPD
CPWR
DIO
38
39
40
41
42
43
44
DIO
DIOPD
DIOPD
DIOPD
DIOPD
IOPWR
DIOPD
SPI1 MOSI / General-Purpose I/O Port 1, bit 7
Nand-flash WR / General-purpose IO Port 0, bit 10
I/O power supply, connect to regulator IOPWR
Nand-flash CE / General-purpose IO Port 0, bit 11
SPI0 XCS / General-Purpose I/O Port 1, bit 0
SPI0 CLK / General-Purpose I/O Port 1, bit 1
SPI0 MISO / General-Purpose I/O Port 1, bit 2
SPI0 MOSI / General-Purpose I/O Port 1, bit 3
JTAG TMS / General-Purpose I/O Port 2, bit 0
JTAG TDI / General-Purpose I/O Port 2, bit 1
JTAG TDO / General-Purpose I/O Port 2, bit 2
JTAG TCK / General-Purpose I/O Port 2, bit 3
Debug interrupt / General-Purpose I/O Port 2, bit 4
Core power supply, connect to regulator CPWR
UART RX / General-Purpose I/O Port 1, bit 8
(connect with 100 kΩ to IOVDD if not used for UART)
UART TX / General-Purpose I/O Port 1, bit 9
I2S data in / General-Purpose I/O Port 1, bit 10
I2S data out / General-Purpose I/O Port 1, bit 11
I2S bit clock / General-Purpose I/O Port 1, bit 12
I2S frame sync / General-Purpose I/O Port 1, bit 13
I/O power supply, connect to regulator IOPWR
I2S XTALI clock output / General-Purpose I/O Port 1, bit 14
Center ground plate, use multiple vias to create lowimpedance connection to ground network on PCB!
PR
EL
MOSI1 / GPIO1_7
NFWR / GPIO0_10
IOVDD1
NFCE / GPIO0_11
XCS0 / GPIO1_0
SCLK0 / GPIO1_1
MISO0 / GPIO1_2
MOSI0 / GPIO1_3
TMS / GPIO2_0
TDI / GPIO2_1
TDO / GPIO2_2
TCK / GPIO2_3
DBGREQ / GPIO2_4
CVDD2
RX / GPIO1_8
LFGA Pin Type
Pin
(0)
PWR
IM
6.3
PACKAGE AND PIN DESCRIPTIONS
IN
AR
Y
6
TX / GPIO1_9
I2S_DI / GPIO1_10
I2S_DO / GPIO1_11
I2S_BCK / GPIO1_12
I2S_FRM / GPIO1_13
IOVDD2
I2S_12M / GPIO1_14
Version: 0.52, 2012-11-07
17
VS1005g Datasheet
Pin Name
PACKAGE AND PIN DESCRIPTIONS
IN
AR
Y
6
LFGA
Pin
SD_CLK / GPIO2_5
45
SD_DAT0 / GPIO2_6
46
SD_DAT1 / GPIO2_7
47
SD_DAT2 / GPIO2_8
48
SD_DAT3 / GPIO2_9
49
SD_CMD / GPIO2_10
50
ETH_RXP / GPIO2_11 / DIA3 51
Pin Type
Function
DIOPD
DIO
DIO
DIO
DIO
DIO
DIOPD
GPIO1_15
DIOPD
DIOPD
ETH_TXN / GPIO2_13 / DIA2 55
IOPWR
DIOPD
SPDIF_IN / GPIO0_12
SPDIF_OUT / GPIO0_13
GPIO0_14
GPIO0_15
CVDD3
DBG
TEST
PWRBTN
RTCVDD
XTALO_RTC
XTALI_RTC
56
57
58
59
60
61
62
63
64
65
66
DIOPD
DIOPD
DIOPD
DIOPD
CPWR
DI
DI
AIO
RTCPWR
AO
AI
SD card clock / General-Purpose I/O Port 2, bit 5
SD card data line 0 / General-Purpose I/O Port 2, bit 6
SD card data line 1 / General-Purpose I/O Port 2, bit 7
SD card data line 2 / General-Purpose I/O Port 2, bit 8
SD card data line 3 / General-Purpose I/O Port 2, bit 9
SD card cmd line / General-Purpose I/O Port 2, bit 10
Ethernet RXP / General-Purpose I/O Port 2, bit 11 /
Digital ADC 1 input
General-Purpose I/O Port 1, bit 15
Ethernet TXP / General-Purpose I/O Port 2, bit 12 / Digital ADC 1 input
I/O power supply, connect to regulator IOPWR
Ethernet TXN / General-Purpose I/O Port 2, bit 13 /
Digital ADC 1 input
S/PDIF data in / General-Purpose I/O Port 0, bit 12
S/PDIF data out / General-Purpose I/O Port 0, bit 13
General-Purpose I/O Port 0, bit 14
General-Purpose I/O Port 0, bit 15
Core power supply, connect to regulator CPWR
Debug mode enable (active high), connect to ground
Test mode input (active high), connect to ground
Power button for Regulator startup (and Power Key)
Real time clock power supply
Real time clock crystal output
Real time clock crystal input
LFGA
Pin
67
68
69
70
Pin Type
Function
AI
AI
AI
AI
SAR AD input 0 / Line 2 input 2
SAR AD input 1 / Line 2 input 1
SAR AD input 2 / Line 1 input 3
71
AI
52
ETH_TXP / GPIO2_12 / DIA1 53
54
Pin Name
AUX0 / LINE2_2
AUX1 / LINE2_1
AUX2 / LINE1_3
MIC2P / AUX3 / LINE3_2
Microphone 2 pos. differential input, self-biasing / SAR AD
input 3 / Line 3 input 2
Microphone 2 neg. differential input, self-biasing / SAR AD
input 4 / Line 3 input 1
Microphone 1 pos. differential input, self-biasing / Line 1 input 2
Microphone 1 neg. differential input, self-biasing / Line 1 input 1
EL
MIC2N / AUX4 / LINE3_1
IM
IOVDD3
72
73
74
75
76
77
AI
AI
APWR1V8
AI
AI
APWR
RCAP
AVDD0
RIGHT
N/A
CBUF
LEFT
AVDD1
USBP
USBN
GNDUSB
78
79
80
81
82
83
84
85
86
87
AIO
APWR
AO
N/A
AO
AO
APWR
AIO
AIO
APWR
PWM
88
DO
PR
MIC1P / LINE1_2
MIC1N / LINE1_1
AVDDRF
RF_N
RF_P
AGND
Version: 0.52, 2012-11-07
1.8V RF power supply, connect to regulator CPWR
RF FM antenna negative differential input
RF FM antenna positive differential input
Analog reference ground, connect to both GPLATE and
RCAP capacitor without vias in PCB
Filtering capacitance for reference
Analog power supply, connect to regulator APWR
Right channel output
Not connected pin
Common voltage buffer for headphones
Left channel output
Analog power supply, connect to regulator APWR
USB differential + in / out, controllable 1.5kΩ pull-up
USB differential - in / out
USB ground, connect to ground network in PCB and
GPLATE
PWM output
18
VS1005g Datasheet
Pin type descriptions:
Type
DI
DIPD
DO
DIO
DIOPD
PACKAGE AND PIN DESCRIPTIONS
IN
AR
Y
6
Description
Digital input, CMOS input pad
Digital input with weak pull-down resistor (approx. 1 MΩ)
Digital output, CMOS output pad
Digital input/output
Digital input/output with weak pulldown resistor in input (approx. 1 MΩ)
Type
AI
AO
AIO
APWR
APWR1V8
RTCPWR
CPWR
IOPWR
Description
Analog input
Analog output
Analog input/output
Analog power supply pin or ground
Analog power supply pin, 1.8V
Real time clock power supply pin, 1.8V
Core power supply pin
I/O power supply pin
Package bottom plate is a ground net and it is connected to ground network in PCB.
NOTE: Unused inputs should not be left floating. Tie either HIGH or LOW as appropriate. At
power-up all GPIO is three stated and current leakage from IOVDD is cut. Outputs that are
three-statable should only be pulled high or low to ensure signals at power-up and in standby.
Analog Line input 1
Analog Line input 2
Alternate pin functions in VS1005g package
LFGA Pin Type
Function
Pin
71
AI
Alternate analog input pin for Line input 1
70
AI
Alternate analog input pin for Line input 2
6.3.1
68
67
52
32
33
53
55
51
31
32
33
34
35
AI
AI
DO
DO
DO
DIPD
DIPD
DIPD
DIPD
DIPD
DO
DIPD
DO
EL
Analog Line input 1
Analog Line input 2
Digital DA/AD Clock
Digital DAC Right
Digital DAC Left
DIA1
DIA2
DIA3
TMS
TDI
TDO
TCK
DBGREQ
Alternate analog input pin for Line input 1
Alternate analog input pin for Line input 2
Digital DA/AD clock output, XTALI/2/4
DAC right channel digital output, XTALI/2
DAC left channel digital output, XTALI/2
Digital ADC 1 input, XTALI/2
Digital ADC 2 input, XTALI/2
Digital ADC 3 input, XTALI/2
Jtag Test Mode Select
Jtag Test Data In
Jtag Test Data Out
Jtag Test Clock
Hardware debug state pin
IM
Pin Name
PCB Layout Recommendations
PR
The following recommendations should be followed to ensure reliable operation.
• Analog power nets that are connected to regulator APWR/CPWR output should have
bypass capacitors.
• USBP and USBN traces should be kept within 2mm of each other and with preferred
length of 20-30mm (max 75mm). A solid ground plane is preferred under USBP and
USBN traces.
• USBP and USBN traces should be very close to same length, drawn together and their
characteristic differential impedance 90 Ohms
• No vias are allowed in USBP or USBN traces, only 45 degree angles should be used.
• USBP and USBN traces should be isolated from all other signal traces.
• RF_P and RF_N traces should be isolated from all other signal traces.
Version: 0.52, 2012-11-07
19
VS1005g Datasheet
7
Example Schematic
PR
EL
IM
Default pin usage is shown in Figure 5.
EXAMPLE SCHEMATIC
IN
AR
Y
7
Version: 0.52, 2012-11-07
Figure 5: VS1005g default pin usage.
20
VS1005g Datasheet
8
VS1005G GENERAL DESCRIPTION
IN
AR
Y
8
VS1005g General Description
EL
IM
VS1005g architecture is based on VS_DSP core. VS_DSP core architecture is described in
VS_DSP User’s Manual. Chip is powered with internal regulator which provides voltages for
three separate power domains. The core and periphery I/O power domains can be driven off
separately, allowing simple I/O interfacing and minimizing power consumption. RTC has its own
power supply which enables the RTC usage when the rest of the chip is powered down. RTC
also includes a small backup ram. VS1005g has two clock domains which are clocked by PLL.
Analog interfaces are clocked with a XTALI clock but the dsp, digital intarfaces and memories
are clocked with a multiplied clock. VS1005g external interfaces are shown in Figure 6.
PR
Figure 6: VS1005g external interfaces
Version: 0.52, 2012-11-07
21
VS1005g Datasheet
8.1
VS1005g Internal Architecture
VS1005G GENERAL DESCRIPTION
IN
AR
Y
8
EL
IM
VS1005g block diagram is shown in Figure 7.
Figure 7: VS1005g block diagram
8.1.1
Regulator Section
PR
The VHIGH pin in the regulator section is used as a common main power supply for voltage
regulation. This input is connected to three internal regulators, which are activated when the
PWRBTN pin voltage is kept above 0.9 V for about one millisecond, so that AVDD starts to rise
and reaches about 1.5 V. After the PWRBTN has given this initial start current, the regulators
reach their default voltages even if the PWRBTN is released. VHIGH must be sufficiently (about
0.3 V) above the highest regulated power (normally AVDD) so that regulation can be properly
performed.
The PWRBTN state can also be read by software, so it can be used as one of the user interface
Version: 0.52, 2012-11-07
22
VS1005g Datasheet
VS1005G GENERAL DESCRIPTION
IN
AR
Y
8
buttons.
A power-on reset monitors the core voltage and asserts reset if CVDD drops below the CMON
level. It is also possible to force a reset by keeping PWRBTN pressed for longer than approximately 5.6 seconds. This feature can be disabled by software. A watchdog counter and the
XRESET pin can also generate a reset for the device.
Resets do not cause the regulators to shut down, but they restore the default regulator voltages.
After boot the firmware and user software can change the voltages.
Return to power-off is possible only with active software control (VSDSP writes the regulator
shutdown bits), or when VHIGH voltage is removed for a sufficiently long time. In the default
firmware player the power button has to be pressed for 2 seconds to make the software powerdown the system and turn the regulators off.
8.1.2
I/O Section
IOVDD is used for the level-shifters of the digital I/O and crystal oscillator. The regulated IO
voltage is internally connected. The IOVDD regulator output must be connected to IOVDD1,
IOVDD2 and IOVDD3 input pins. Proper bypass capacitors should also be used.
8.1.3
Digital Section
IM
The firmware uses GPIO0_7 to select I/O voltage level. After reset the I/O voltage is 1.8 V. If
GPIO0_7 has a pull-down resistor, 1.8 V I/O voltage is used. If GPIO0_7 has a pull-up resistor,
3.3 V I/O voltage is used.
All digital logic except the real time clock is powered from core voltage CVDD. The regulated
core voltage is internally connected. The CVDD regulator output must be connected to CVDD1,
CVDD2 and CVDD3 input pins. CVDD pins should have proper bypass capacitors.
Clock
EL
Real time clock power pin can be connected to CVDD net or it can have its own power supply
which enables its use during chip power-down. The inputs and outputs of the RTC logic have
level shifters but the RTCVDD voltage should not exceed the CVDD voltage range.
PR
The crystal amplifier uses a crystal connected to XTALI and XTALO. An external logic-level
input clock can also be used. When VS1005g is used with FS USB, 12 MHz crystal allows
lower power consumption. With FS/HS USB the input clock of 12 MHz or 12.288 MHz is recommended.
An internal phase-locked loop (PLL) generates the internal clock by multiplying the input clock
by 1.0×, 1.5×, . . . , 8.0×. When USB is connected, the clock is 5.0×12 MHz = 60 MHz. When
the player is active, the clock will be automatically changed according to the requirements of
the song being played.
XRESET disables the clock buffer and puts the digital section into powerdown mode.
Version: 0.52, 2012-11-07
23
VS1005g Datasheet
VS1005G GENERAL DESCRIPTION
IN
AR
Y
8
In usb suspend state the core clock is switced to RTC clock and the clock oscillator is powered
down.
VSDSP4
VSDSP4 is VLSI Solution’s proprietary digital signal processor with a 32-bit instruction word,
two 16-bit data buses, and both 16-bit and 32/40-bit arithmetic.
IROM, XROM, and YROM contain the firmware, including the default player application. Most
of the instruction RAM and some of the X and Y data RAM’s can be used to customize and
extend the functionality of the player.
For software customization the firmware supports nand flash and SD card boot. The VS1005gxF
version can use also the internal serial flash as a boot device.
UART
An asynchronous serial port is used for debugging and special applications. The default speed
is 115200 bps. RX and TX pins can also be used for general-purpose I/O when the UART is
not required.
IM
SPIs
A synchronous serial port peripheral is used for SPIEEPROM boot, and can be used to access
other SPI peripherals (for example LCD or SED) by using another chip select. The SPI0 is only
used for boot if the XCS0 pin has a high level after reset (pull-up resistor attached). These pins
can also be used for general-purpose I/O when the SPI is not required.
The default player uses MISO0 and MOSI0 for LED outputs.
EL
NAND FLASH Interface
The NAND FLASH peripheral calculates a simple error-correcting code (ECC), and automates
some of the communication with a NAND FLASH chip. The firmware uses the peripheral to
access both small-page (512+16 B pages) and large-page (2048+64 B pages) NAND FLASH
chips. The first sector in the FLASH tells the firmware how it should be accessed.
PR
The NAND FLASH interface pins can also be used as general-purpose I/O. The default firmware
uses GPIO0_[4:0] for keys, and GPIO0_[7:6] for other purposes. Pull-up and pull-down resistors must be used for these connections so that the data transfer to and from the NAND FLASH
isn’t disturbed when keys are pressed.
SD Card Interface
The SD card interface automates some of the communication with an SD card. Peripheral
supports 1-bit and 4-bit data transfers.
The SD card interface pins can also be used as general-purpose I/O.
Version: 0.52, 2012-11-07
24
VS1005g Datasheet
VS1005G GENERAL DESCRIPTION
IN
AR
Y
8
Ethernet Controller
Ethernet Controller is an interface to 10base-t network. The interface uses digital signal levels
and external components are required to connect to ethernet. The core clock must be switched
to 60 MHz when ethernet peripheral is used.
The ethernet interface pins can also be used as general-purpose I/O.
USB
The USB peripheral handles USB 2.0 Full Speed and Hi-Speed harware protocols. Low speed
communication is not supported, but is correctly ignored. The USBP pin has a softwarecontrollable 1.5kΩ pull-up.
A control endpoint (1 IN and 1 OUT) and upto 6 other endpoints (3 IN and 3 OUT) can be
used simultaneously. Bulk, interrupt, and isochronous transfer modes are selectable for each
endpoint. USB receive from USB host to device (OUT) uses a 2 KiB buffer, thus allowing very
high transfer speeds. USB transmit from device to USB host (IN) also uses a 2 KiB buffer and
allows all IN endpoints to be ready to transmit simultaneously. Double-buffering is also possible,
but not usually required.
8.2
Analog Section
IM
The firmware uses the USB peripheral to implement both USB Mass Storage Device and USB
Audio Device. Which device is activated depends on the state of GPIO0_6 when the USB
connection is detected. If GPIO0_6 has a pull-up resistor, VS1005g appears as an USB Audio
Device. If GPIO0_6 has a pull-down resistor, VS1005g appears as an USB Mass Storage
Device.
The third regulator provides power for the analog section.
EL
The analog section consists of digital to analog converters, an earphone driver and FM receiver.
This includes a buffered common voltage generator (CBUF, around 1.2 V) that can be used as
a virtual ground for headphones.
The regulator AVDD output pin must be connected to AVDD1 and AVDD2 pins with proper
bypass capacitors, because they are not connected internally. The AVDDRF pin is connected
to regulator CVDD pin with proper bypass capacitors or with external regulator from VHIGH.
The USB pins use the internal AVDD voltage, and the firmware configures AVDD to 3.6 V when
USB is attached.
PR
AVDD voltage level can be monitored by software. Currently the firmware does not take advantage of this feature.
CBUF contains a short-circuit protection. It disconnects the CBUF driver if pin is shorted to
ground. In practise this only happens with external power regulation, because there is a limit to
how much power the internal regulators can provide.
Version: 0.52, 2012-11-07
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VS1005g Datasheet
9
OSCILLATOR AND RESET CONFIGURATION
IN
AR
Y
9
Oscillator and Reset Configuration
The reset module gathers reset sources and controls the system’s internal reset signals. Reset
Sources are:
• POR : Power-On reset and CVDD voltage monitor
• XRESET : External active low reset pin
• wdog_rst : Watchdog timer reset
• dbg_rst : Debugger reset
• PWRBTN : Power Button reset after 5 seconds
Two clock sources can be used :
• 11 MHz - 13 MHz oscillator (recommended 12.288 MHz)
PR
EL
IM
• 32 kHz RTC oscillator
Version: 0.52, 2012-11-07
26
VS1005g Datasheet
10
Firmware Operation
FIRMWARE OPERATION
IN
AR
Y
10
The firmware uses the following pins (see the example schematics in Section 7):
Pin
PWRBTN
GPIO0_0
GPIO0_1
GPIO0_2
GPIO0_3
GPIO0_4
GPIO0_6
GPIO0_7
NFCE
XCS
USBN
USBP
Description
High level starts regulator, is also read as the Power button Key.
external 1 MΩ pull-down resistor, Key 1 connects a 100 kΩ pull-up resistor 1
external 1 MΩ pull-down resistor, Key 2 connects a 100 kΩ pull-up resistor
external 1 MΩ pull-down resistor, Key 3 connects a 100 kΩ pull-up resistor
external 1 MΩ pull-down resistor, Key 4 connects a 100 kΩ pull-up resistor
external 1 MΩ pull-down resistor, Key 5 connects a 100 kΩ pull-up resistor
external pull-down resistor for USB Mass Storage Device, pull-up for USB
Audio Device
external pull-down resistor for 1.8 V I/O voltage, pull-up resistor for 3.3 V I/O
voltage
external pull-up resistor for normal operation
external pull-up to enable SPI EEPROM boot
external 1 MΩ pull-up
external 1 MΩ pull-up
1
Boot order:
Stage
Power on
Reset
SPI EEPROM boot
NAND FLASH probed
SD boot
Default firmware
SPI Boot
PR
10.1
Description
Power button (PWRBTN) pressed when VHIGH has enough voltage
Power-on reset, XRESET, or watchdog reset causes software
restart
Almost immediately after power-on UART can be used to enter
emulator mode. UART boot remains possible after the following
steps, too.
If XCS is high, SPI Boot is tried.
If NFCE is high, NAND FLASH is checked.
If VS1005G.SYS exists, it is used as a boot file.
The firmware in ROM takes control.
EL
UART Boot
IM
Smaller pull-down resistors may be needed for keys if the capacitance on the GPIO pins is
high.
The first boot method is SPI EEPROM. If GPIO1_0 is low after reset, SPI boot is skipped. If
GPIO1_0 is high, it is assumed to have a pull-up resistor and SPI boot is tried.
First the first four bytes of the SPI EEPROM are read using 16-bit address. If the bytes are
“VLS5” (for protected host) or “WLS5” (for unprotected host), a 16-bit EEPROM is assumed
and the boot continues. If the last 3 bytes are read as “VLS”, a 24-bit EEPROM is assumed
and boot continues in 24-bit mode. Both 16-bit and 24-bit EEPROM should have the “VLS5” or
“WLS5” string starting at address 0, and the rest of the boot data starting at address 4. If no
Version: 0.52, 2012-11-07
27
VS1005g Datasheet
FIRMWARE OPERATION
IN
AR
Y
10
identifier is found, SPI EEPROM boot is skipped.
Boot records are read from EEPROM until an execute record is reached. Unknown records are
skipped using the data length field.
Byte
0
1, 2
3, 4
5..
10.2
Description
type 0=I-mem 1=X-mem 2=Y-mem 3=execute
data len lo, hi – data length in bytes
address lo, hi – record address
data*
NAND FLASH Probe
If NAND FLASH chip select (NFCE) is high, a NAND FLASH is assumed to be present and the
first sector is read. The access methods (nandTypes 0..5) are tried in order to find the “VLN5”
identification. If the first bytes are “VLN5”, a valid boot sector is assumed. This sector gives the
necessary information about the NAND FLASH so that it can be accessed in the right way.
IM
Byte
0, 1, 2, 3
4, 5
NandFlash Header
Value
Description
0x56 0x4c 0x4E 0x35 ’V’ ’L’ ’N’ ’5’ – Identification
0x00 0x03
NandType (0x0003 = large-page with 3-byte
block address), See table
0x08
BlockSizeBits (28 ∗ 512 = 128 KiB per block)
0x13
FlashSizeBits (219 ∗ 512 = 256 MiB flash)
0x00 0x46
NandWaitNs – NAND FLASH access time in ns
(e.g. 0x46)
0x00 0x01
Number of 512-byte blocks for boot (e.g.
0x0001)
0x00 0x00
EWRD = How many words to skip before ’B’ ’o’
’O’ ’t’ string
Extra words (this field exists only if EWRD != 0)
6
7
8, 9
10, 11
EL
12, 13
14 ... 14+EWRD-1
(14, 15, 16, 17)
+ EWRD
18+EWRD ... 511
’B’ ’o’ ’O’ ’t’ – Optional boot ident
code
NandFlash Type Configuration
Description
PR
Low byte
(byte 0x4)
0
1
2
3
4
5
0x42 0x6f 0x4f 0x74
512+16 B small-page flash with 2-byte block address (≤ 32 MiB)
2048+64 B large-page flash with 2-byte block address (≤ 128 MiB)
512+16 B small-page flash with 3-byte block addr. (> 32 MiB, ≤ 8 GiB)
2048+64 B large-page flash with 3-byte bl.addr. (> 128 MiB, ≤ 32 GiB)
512+16 B small-page flash with 4-byte block address (> 8 GiB)
2048+64 B large-page flash with 4-byte block address (> 32 GiB)
Version: 0.52, 2012-11-07
28
VS1005g Datasheet
FIRMWARE OPERATION
IN
AR
Y
10
If bytes (14-16)+EWRD contain “BoOt”, the value in bytes 10 and 11 determines how many
sectors are read from NAND-flash. Note that 0 is interpreted as 1. After the data is read into
memory, the boot records in this data are processed, transferring code and data sections into
the right places in memory and possibly executed. If an unknown boot record is encountered,
booting is stopped and control returns to the firmware code.
Code byte
17, 16
19, 18
21, 20
22..
10.3
NandFlash Record Configuration
Description
type 0x8000=I-mem 0x8001=X-mem 0x8002=Y-mem 0x8003=execute
data length in (words -1) : 0 = 1 word, 1 = 2 words, etc.
address – record address
data
UART Boot/Monitor
When byte 0xef is sent to RX at 115200 bps, the firmware enters monitor mode and communicates with vs3emu. Memory contents can be displayed, executables can be loaded and run,
or the firmware code can be restarted or continued.
PR
EL
IM
The UART is also a convenient way to program the NAND FLASH boot sector(s) or the SPI
EEPROM.
Version: 0.52, 2012-11-07
29
VS1005g Datasheet
10.4
10.4.1
Default Firmware Features
SD Card Test
FIRMWARE OPERATION
IN
AR
Y
10
If an SD card is connected to VS1005g, the firmware searches for a boot file file called VS1005G.SYS.
If found, VS1005g executes the code in that file.
If VS1005G.SYS is not found, the firmware tries to open the file TEST.MP3. If successful, that
file is played back.
Note: Playback is provided only as a functional test. Playback quality is not indicative of
VS1005g default playback quality.
Note: MP3 playback is not supported by VS8005g.
10.4.2
USB Mass Storage and Audio Device
If no SD card boot or test file was found, the firmware goes into USB detection mode.
IM
When USB cable insertion is detected by the firmware, USB handling code is started. The
internal clock is configured to 48 MHz (assuming XTALI = 12.288 MHz), the analog power is
configured to 3.6 V, the USB peripheral is initialized, and the USB pull-up resistor is enabled.
If GPIO0_6 has a pull-up resistor, VS1005g appears as an USB Audio Device. The audio
device contains a HID interface which allows for code to be loaded to VS1005g with a custom
program. If GPIO0_6 has a pull-down resistor, VS1005g appears as an USB Mass Storage
Device.
PR
EL
If during power-on the NAND FLASH contained a valid boot sector, the NAND FLASH disk
will be used with the mass storage device. The NAND FLASH disk requires a filesystem-level
formatting before it can be used.
Version: 0.52, 2012-11-07
30
VS1005g Datasheet
10.5
Supported Audio Decoders
FIRMWARE OPERATION
IN
AR
Y
10
VS1005g ROM firmware supports decoding MP3 files (only VS1005 and VS1205). Support for
other file formats is implemented as link libraries.
Mark
+
-
10.5.1
Conventions
Description
Format is supported
Format exists but is not supported
Format doesn’t exist
Supported MP3 (MPEG layer III) Decoder Formats
The decoder supports all MP3 samplerates and bitrates.
MPEG 1.01 :
Samplerate / Hz
40
+
+
+
8
+
+
+
16
+
+
+
MPEG 2.01 :
Samplerate / Hz
24000
22050
16000
MPEG 2.51 :
12000
11025
8000
8
+
+
+
16
+
+
+
64
+
+
+
Bitrate / kbit/s
80 96 112 128
+
+
+
+
+
+
+
+
+
+
+
+
160
+
+
+
192
+
+
+
224
+
+
+
256
+
+
+
320
+
+
+
24
+
+
+
32
+
+
+
40
+
+
+
Bitrate / kbit/s
48 56 64 80
+
+
+
+
+
+
+
+
+
+
+
+
96
+
+
+
112
+
+
+
128
+
+
+
144
+
+
+
160
+
+
+
24
+
+
+
32
+
+
+
40
+
+
+
Bitrate / kbit/s
48 56 64 80
+
+
+
+
+
+
+
+
+
+
+
+
96
+
+
+
112
+
+
+
128
+
+
+
144
+
+
+
160
+
+
+
All variable bitrate (VBR) formats are also supported.
PR
1
56
+
+
+
EL
Samplerate / Hz
48
+
+
+
IM
48000
44100
32000
32
+
+
+
Version: 0.52, 2012-11-07
31
VS1005g Datasheet
10.6
FIRMWARE OPERATION
IN
AR
Y
10
Supported Audio Encoders
VS1005g ROM firmware supports encoding MP3 files (only VS1205). Support for other file
formats is implemented as link libraries.
10.6.1
Supported MP3 (MPEG layer III) Encoder Formats
VS1005g supports all MP3 samplerates and bitrates, in stereo and mono, both with constant
bitrate (CBR) or variable bitrate (VBR). The following tables apply to constant bitrate.
Symbol
++
+
x
v
<
-
Conventions
Description
Format is supported and recommended for this channel configuration and bitrate.
Format is supported.
Format is supported but use is strongly discouraged for quality reasons.
Format is supported but for best quality lower samplerate with same bitrate is recommended.
Format is supported but lower bitrate will give same quality.
Format exists but isn’t supported.
Format doesn’t exist.
MPEG 1.0 layer III (MP3 full rates), stereo:
Samplerate / Hz
40
v
v
v
48
v
v
v
56
v
v
v
64
v
v
v
Bitrate / kbit/s, stereo
80 96 112 128 160
v
v
+
+
++
v
+
+
+
+
+
+
++ ++ +
192
++
+
+
224
++
+
+
256
++
+
+
320
++
+
<
112
+
+
+
+
+
+
128
+
+
+
+
+
<
144
+
<
<
<
<
<
160
<
<
<
<
<
<
160
++
+
+
192
++
+
+
224
++
+
<
256
++
+
<
320
<
<
<
96
+
+
<
<
<
<
112
+
+
<
<
<
<
128
<
<
<
<
<
<
144
<
<
<
<
<
<
160
<
<
<
<
<
<
IM
48000
44100
32000
32
v
v
v
MPEG 2.0 & 2.5 layer III (MP3 low rates), stereo:
Samplerate / Hz
16
v
v
v
v
v
++
24
v
v
v
v
v
++
32
v
v
v
+
+
++
40
v
v
+
++
+
+
Bitrate / kbit/s, stereo
48 56 64 80 96
v
v
+
++ ++
v
+
+
+
+
+
+
++ +
+
++ ++ +
+
+
+
+
+
+
+
+
+
+
+
+
EL
24000
22050
16000
12000
11025
8000
8
x
x
x
v
v
++
MPEG 1.0 layer III (MP3 full rates), mono:
Samplerate / Hz
48000
44100
32000
32
v
v
+
40
v
v
+
48
v
v
+
56
+
+
++
64
+
+
++
Bitrate / kbit/s, mono
80 96 112 128
++ ++ ++ ++
+
+
+
+
+
+
+
+
PR
MPEG 2.0 & 2.5 layer III (MP3 low rates), mono:
Samplerate / Hz
24000
22050
16000
12000
11025
8000
8
v
v
v
v
v
++
16
v
v
v
v
v
++
Version: 0.52, 2012-11-07
24
+
+
+
++
+
+
32
+
+
++
+
+
+
40
+
+
++
+
+
+
Bitrate / kbit/s, mono
48 56 64 80
++ +
+
+
+
+
+
+
+
+
+
+
+
+
+
<
+
+
+
<
+
<
<
<
32
VS1005g Datasheet
11
11.1
VS1005G PERIPHERALS AND REGISTERS
IN
AR
Y
11
VS1005g Peripherals and Registers
The Processor Core
VS_DSP is a 16/32-bit DSP processor core that also has extensive all-purpose processor features. VLSI Solution’s free VSIDE Software Package contains all the tools and documentation
needed to write, simulate and debug Assembly Language or Extended ANSI C programs for the
VS_DSP processor core. VLSI Solution also offers a full Integrated Development Environment
VSIDE for full debug capabilities.
11.2
VS1005g Memory Map
PR
EL
IM
VS1005g’s Memory Map is shown in Figure 8.
Version: 0.52, 2012-11-07
Figure 8: User’s memory map.
33
VS1005g Datasheet
11.3
VS1005g Peripherals
VS1005G PERIPHERALS AND REGISTERS
IN
AR
Y
11
System peripherals are located in Y-address space. The peripherals that use PLL clock are in
addresses 0xFC00 - 0xFD3F and peripherals that use XTALI clock are in addresses 0xFE00 0xFEDF.
Peripheral address spaces are summarized in the following table:
PR
EL
IM
VS1005g peripheral address ranges
Address
Device
PLL clocked peripherals
0xFC00 - 0xFC1F
Interrupt controller
0xFC20 - 0xFC3F
DSP interface registers
0xFC40 - 0xFC4F
SPI 0
0xFC50 - 0xFC5F
SPI 1
0xFC60 - 0xFC65
10base-t ethernet controller
0xFC66 - 0xFC6C DSP interface for peripheral data buffer
0xFC70 - 0xFC76
Reed-Solomon codes
0xFC77 - 0xFC7A Nand flash interface
0xFC7B - 0xFC7F SD card interface
0xFC80 - 0xFC9F
Hi-Speed USB
0xFCA0 - 0xFCBF 16-bit GPIO port 0
0xFCC0 - 0xFCDF 16-bit GPIO port 1
0xFCE0 - 0xFCFF 14-bit GPIO port 2
0xFD00 - 0xFD1F
S/PDIF
XTALI clocked peripherals
0xFE00 - 0xFE1F
UART
0xFE20 - 0xFE3F
Watchdog
0xFE40 - 0xFE5F
FM and A/D interface
0xFE60 - 0xFE7F
I2S
0xFE80 - 0xFE9F
Timers
0xFEA0 - 0xFEBF RTC interface
0xFEC0 - 0xFEDF Control and configuration registers for 12 MHz clock
Version: 0.52, 2012-11-07
34
VS1005g Datasheet
VS1005G PERIPHERALS AND REGISTERS
IN
AR
Y
11
PR
EL
IM
VS1005g Peripheral Addresses
Address
Device
PLL clocked peripherals
0xFC00 - 0xFC1F
Interrupt controller
0xFC20 - 0xFC3F
DSP interface registers
0xFC40 - 0xFC4F
SPI 0
0xFC50 - 0xFC5F
SPI 1
0xFC60 - 0xFC65
10base-t ethernet controller
0xFC66 - 0xFC6C DSP interface for peripheral data buffer
0xFC70 - 0xFC76
Reed-Solomon codes
0xFC77 - 0xFC7A Nand flash interface
0xFC7B - 0xFC7F SD card interface
0xFC80 - 0xFC9F
Hi-Speed USB
0xFCA0 - 0xFCBF 16-bit GPIO port 0
0xFCC0 - 0xFCDF 16-bit GPIO port 1
0xFCE0 - 0xFCFF 14-bit GPIO port 2
0xFD00 - 0xFD1F
S/PDIF
XTALI clocked peripherals
0xFE00 - 0xFE1F
UART
0xFE20 - 0xFE3F
Watchdog
0xFE40 - 0xFE5F
FM and A/D interface
0xFE60 - 0xFE7F
I2S
0xFE80 - 0xFE9F
Timers
0xFEA0 - 0xFEBF RTC interface
0xFEC0 - 0xFEDF Control and configuration registers for 12 MHz clock
Version: 0.52, 2012-11-07
35
VS1005g Datasheet
11.4
Interrupt Controller
VS1005G PERIPHERALS AND REGISTERS
IN
AR
Y
11
VS1005g has 28 maskable interrupt vectors and 33 interrupt sources. The interrupt controller
is external to DSP and it prioritizes the requests before forwarding them to the DSP.
Interrupt controller has three levels of priority for simultaneous requests and a global disable/enable for all of the sources. Interrupt sources are divided so that interrupt sources 15-0
are mapped to low registers and 27-16 to high registers.
For an interrupt handler written in C, an assembly language stub that re-enables interrupts before RETI, should be written. The assembly language stub should call the C language handler
routine.
Vector
15
14
13
12
11
10
9
8
7
6
5
4
3
2
VS1005g interrupt vectors (continued)
Address Device
0x3b 10-bit ADC (SAR)
0x3a Pulse width modulator
0x39 Power button
0x37 S/PDIF transmitter
0x36 S/PDIF receiver
0x35 FM RDS
0x34 RTC time alarm
0x33 DAC offset
0x32 DAC sample rate converter
0x31 FM interrupt (192 kHz)
0x30 Timer 2
VS1005g interrupt vectors (continued)
Address Device
0x2f Timer 1
0x2e Timer 0
0x2d UART receive
0x2c UART transmit
0x2b I2S transmitter/receiver
0x2a A/D 3 (mono AD)
0x29 Gpio port 2
0x28 Gpio port 1
0x27 Gpio port 0
0x26 A/D 1/2 (stereo AD)
0x25 FM decimation-by-6 filter
0x24 SPI 1
0x23 SPI 0
0x22 Common Data Interfaces
(Ethernet, SPI, SD, Nand flash, ReedSolomon, Ethernet)
0x21 Full/Hi-Speed USB
0x20 DAC
PR
EL
Source
INT_TIMER1
INT_TIMER0
INT_UART_RX
INT_UART_TX
INT_I2S
INT_MAC2
INT_GPIO2
INT_GPIO1
INT_GPIO0
INT_MAC0
INT_MAC1
INT_SPI1
INT_SPI0
INT_XPERIP
Vector
27
26
25
23
22
21
20
19
18
17
16
IM
Source
INT_SAR
INT_PWM
INT_REGU
INT_STX
INT_SRX
INT_RDS
INT_RTC
INT_DAOSET
INT_SRC
INT_FM
INT_TIMER2
INT_USB
INT_DAC
1
0
Version: 0.52, 2012-11-07
Read also
Chapter 11.20
Chapter 11.21
Chapter 11.6.1
Chapter 11.14.3
Chapter 11.14.1
Chapter 11.9.3
Chapter 11.19
Chapter 11.7.3
Chapter 11.7.4
Chapter 11.9
Chapter 11.18
Read also
Chapter 11.18
Chapter 11.18
Chapter 11.15
Chapter 11.15
Chapter 11.17
Chapter 11.8
Chapter 11.13
Chapter 11.13
Chapter 11.13
Chapter 11.8
Chapter 11.8
Chapter 11.10
Chapter 11.10
Chapter 11.11
Chapter 11.12
Chapter 11.7.1
36
VS1005g Datasheet
11.4.1
Interrupt Controller Registers
VS1005G PERIPHERALS AND REGISTERS
IN
AR
Y
11
The interrupt controller has three type of registers:
• Enable registers, which contain enable/disable bits for each interrupt source. Bit pairs
configure the interrupt priority and disable.
• Origin registers, which contain the source flags for each interrupt. A request from an
interrupt source sets the corresponding bit. A bit is automatically reset when a request
for the source is generated.
• Enable counter register, which contains the value of the General Interrupt Enable counter,
and two registers for increasing and decreasing the value.
11.4.2
Type
r/w
r/w
r/w
r/w
r/w
r/w
r
r/w
w
w
Reset
0
0
0
0
0
0
0
0
0
0
IM
Address
0xFC02
0xFC00
0xFC03
0xFC01
0xFC04
0xFC05
0xFC06
0xFC07
0xFC08
0xFC09
Interrupt Controller Registers
Abbrev
Description
INT_ENABLE0_HP
Interrupt enable high priority for ints. 0..15
INT_ENABLE0_LP
Interrupt enable low priority for ints 0..15
INT_ENABLE1_HP
Interrupt enable high priority for ints 16..27
INT_ENABLE1_LP
Interrupt enable low priority for ints 16..27
INT_ORIGIN0
Interrupt origin for interrupts 0..15
INT_ORIGIN1
Interrupt origin for interrupts 16..27
INT_VECTOR[4:0]
Interrupt vector
INT_ENCOUNT[2:0] Interrupt enable counter
INT_GLOB_DIS[-]
Interrupt global disable
INT_GLOB_ENA[-]
Interrupt global enable
Interrupt Enable INT_ENABLE[0/1]_[H/L]P
EL
Interrupt enable registers selectively masks interrupt sources. Enable registers 0 contain sources
0..15 and enable registers 1 contain sources 16..27. Each source has two enable bits: one in
the enable high priority (_HP) and one in the enable low priority (_LP) register. If both bits are
zero, the corresponding interrupt source is not enabled, otherwise the bits select the interrupt
priority.
PR
_HP
0
0
1
1
_LP
0
1
0
1
Priority
Source disabled
Priority 1 (low)
Priority 2 (medium)
Priority 3 (high)
Priorities only matter when the interrupt controller decides which interrupt to generate for the
core next. This happens whenever two interrupt sources request interrupts at the same time,
or when interrupts become enabled after an interrupt handler routine or a part of code where
the interrupts have been disabled.
Version: 0.52, 2012-11-07
37
VS1005g Datasheet
11.4.3
VS1005G PERIPHERALS AND REGISTERS
IN
AR
Y
11
Interrupt Origin INT_ORIGIN[0/1]
If an interrupt source requests an interrupt, the corresponding bit in the interrupt origin register (INT_ORIGIN0 or INT_ORIGIN1) will be set to ’1’. If an interrupt source is enabled (using
INT_ENABLE[0/1]_[H/L]P registers), the interrupt controller generates an interrupt request signal for VSDSP with the corresponding vector value. The bit in the origin registers is reset
automatically after the interrupt is requested.
If the source is not enabled, the processor can read the origin register state and perform any
necessary actions without using interrupt generation, i.e. polling of the interrupt sources is also
possible. The bits in the interrupt origin registers can be cleared by writing ’1’ to them.
A read from the interrupt origin register returns the register state.
A write to the interrupt origin register clears the bits in the origin register that are set by the
write. In other words, writing b to INT_ORIGINx performs the logical operation
INT_ORIGINx = INT_ORIGINx and (not b).
Example:
If value for INT_ORIGIN0 is 0x00FF, writing 0xF00F to it will end up with
INT_ORIGIN0 = 0x00FF and (not 0xF00F) = 0x00FF and 0x0FF0 = 0x00F0.
Interrupt Vector INT_VECTOR
IM
11.4.4
The last generated vector value (0..27) can be read from the vector register.
11.4.5
Interrupt Enable Counter INT_ENCOUNT
EL
The global interrupt enable/disable register INT_ENCOUNT is used to control whether an interrupt request is sent to the processor or not. If the 3-bit counter is zero, interrupt signal
generation is enabled. While it is non-zero, interrupt requests are not forwarded to VSDSP. The
counter is increased by one whenever the interrupt controller generates an interrupt request for
VSDSP, or when the register INT_GLOB_DIS is written to. It is decresed by one if it is non-zero
and the register INT_GLOB_ENA is written to.
When read, the enable counter register returns the counter value.
PR
Don’t write directly to INT_ENCOUNT. Manipulate its value by writing to INT_GLOB_DIS and
INT_GLOB_ENA instead.
11.4.6
Interrupt Global Disable INT_GLOB_DIS
A write (of any value) to the global disable register increases the global interrupt enable/disable
counter INT_ENCOUNT by one, thus disabling interrupts.
Note: If an interrupt is generated during the same clock cycle as a write to the global disable
register, the interrupt enable counter is increased by two.
Version: 0.52, 2012-11-07
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VS1005g Datasheet
11.4.7
VS1005G PERIPHERALS AND REGISTERS
IN
AR
Y
11
Interrupt Global Enable INT_GLOB_ENA
If the global interrupt enable/disable counter INT_ENCOUNT is not zero, a write (of any value)
to INT_GLOB_ENA the counter by one.
PR
EL
IM
The user must write to this register once at the end of interrupt handlers to re-enable interrupts.
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39
VS1005g Datasheet
11.5
11.5.1
DSP Clock Domain Registers
VS1005G PERIPHERALS AND REGISTERS
IN
AR
Y
11
General Purpose Software Registers
SW_REG0, SW_REG1, SW_REG2 and SW_REG3 are software registers for user purposes.
They are zeroed in reset and do not control any logic.
Address
0xFC20
0xFC21
0xFC22
0xFC23
11.5.2
Type
r/w
r/w
r/w
r/w
Reset
0
0
0
0
Peripheral I/O Control
Software Registers
Abbrev
Description
SW_REG0 16-bit general purpose sw register
SW_REG1 16-bit general purpose sw register
SW_REG2 16-bit general purpose sw register
SW_REG3 16-bit general purpose sw register
VS1005g has three general purpose I/O ports. Ports 0 and 1 are 16-bits and port 2 is 14 bits.
GPIO pins can be used either in GP mode or they can have also a special peripheral function.
GPIO or peripheral function can be defined for each pin separately.
Type
r/w
r/w
r/w
GPIO Mode Registers
Reset Abbrev
Description
0 GPIO0_MODE Mode control for gpio port 0
0 GPIO1_MODE Mode control for gpio port 1
0 GPIO2_MODE Mode control for gpio port 2
IM
Address
0xFC30
0xFC31
0xFC32
11.5.3
EL
GPIO0_MODE, GPIO1_MODE and GPIO2_MODE registers are used to select current GPIO
mode. By default all VS1005g pins are at GPIO mode and all GPIOx_MODE register are reset.
If a peripheral mode is reguired the pin’s GPIOx_MODE bit must be set (’1’).
PLL Clock Control
VS1005g has two clock domains, the PLL clock domain and 12 MHz clock domain. The PLL is
controlled with one register.
Type
r/w
PR
Address
0xFC33
Version: 0.52, 2012-11-07
Clock Control Register
Reset Abbrev Description
0 CLK_CF PLL clock control register
40
VS1005g Datasheet
Name
CLK_CF_EXTOFF
CLK_CF_NFOFF
CLK_CF_USBOFF
CLK_CF_RTCSLP
CLK_CF_LCKST
CLK_CF_GDIV256
CLK_CF_GDIV2
CLK_CF_LCKCHK
CLK_CF_VCOOUT
CLK_CF_USBCLK
CLK_CF_FORCEPLL
CLK_CF_DIVI
CLK_CF_MULT
Bits
15
14
13
12
11
10
9
8
7
6
5
4
3:0
VS1005G PERIPHERALS AND REGISTERS
IN
AR
Y
11
CLK_CF Bits
type Description
r/w S/PDIF peripheral clock gate control
r/w NF, SD and R-S peripherals clock gate control
r/w USB peripheral clock gate control
r/w RTC power down mode enable
r/w PLL vco lock status
r/w Global Clock 256-divider enable
r/w Global clock 2-divider enable
r/w PLL vco lock check initialization
r/w Enable PLL clock output pad driver
r/w Hi-Speed usb clock mode control
r/w PLL clock switch control
r/w PLL input clock divider control
r/w Pll clock multiplier factor
CLK_CF_MULT determines the clock multiplier for input clock. Multiplier is value+1 i.e. value 1
means clock is multiplied by 2. Value 0 disables the PLL.
CLK_CF_DIVI controls the input divider of PLL’s vco. If CLK_CF_DIVI is set the vco input clock
is divided by two. If CLK_CF_DIVI is reset the vco input clock is the XTALI oscillator clock.
When divider is used the CLK_CF_MULT can be programmed with values 1-15.
IM
CLK_CF_FORCEPLL register controls the output clock switch. When set the output clock is
PLL’s vco clock. When reset the output clock is XTALI oscillator clock. It should be noted that
the vco must be locked when CLK_CF_CKSW is modified.
CLK_CF_USBCLK selects Hi-Speed USB clock (UTM) insted of PLL vco clock. This clock
must be selected before CLK_CF_FORCEPLL is modified. CLK_CF_MULT must have some
value other than 0 when this clock mode is used. Also the Hi-Speed USB must be configured
properly to output 60 MHz clock for core.
EL
CLK_CF_VCOOUT enables the vco clock’s output pad driver. The pad must be in peripheral
mode in order to output clock. The output driver has glitch removal.
CLK_CF_LCKCHK and CLK_CF_LCKST are used to poll vco lock status. When CLK_CF_LCKCHK
is first set and reset the lock status can be read from CLK_CF_LCKST. If CLK_CF_LCKST remains set the PLL vco is locked.
CLK_CF_GDIV256 and CLK_CF_GDIV2 are the global clock dividers. These divider divide
also the 12 MHz clock domain clock. PLL must be disabled when these dividers are used.
CLK_CF_RTCSLP enables RTC clocking mode.
PR
CLK_CF_EXTOFF, CLK_CF_NFOFF and CLK_CF_USBOFF control peripheral clock gates.
CLK_CF_NFOFF controls Nand flash, SD card, ethernet, Reed-Solomon codecs and peripeheral
data buffer clocks. CLK_CF_EXTOFF controls S/PDIF peripheral clock. CLK_CF_USBOFF
controls USB peripheral clock.
Version: 0.52, 2012-11-07
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VS1005g Datasheet
11.6
VS1005G PERIPHERALS AND REGISTERS
IN
AR
Y
11
XTALI Clock Domain Registers
Peripheral control registers control the logic that is clocked with the XTALI clock (12.288 MHz).
11.6.1
Analog Control Registers
Reg
0xFECC
0xFECB
0xFED2
0xFED3
Type
r/w
r/w
r/w
r/w
Name
ANA_CF0_M1LIN
ANA_CF0_M2LIN
Bits
15:11
10
9
8:6
5
4
3
2
1
0
ANA_CF0 Bits
Description
Reserved, use ’00000’
Line input mode select for ADC 1
Line input mode select for ADC 2
Reserved, use ’000’
Mic input mode select for ADC 2
2 GHz vco lock status
2 GHz vco lock check init
Mic input mode select for ADC 1
FM input mode select for ADC 2
FM input mode select for ADC 1
IM
ANA_CF0_M2MIC
ANA_CF0_LCKST
ANA_CF0_LCKCHK
ANA_CF0_M1MIC
ANA_CF0_M2FM
ANA_CF0_M1FM
Analog Control Registers
Reset Abbrev
Description
0 ANA_CF0 Analog Control register 0
0 ANA_CF1 Analog Control register 1
0 ANA_CF2 Analog Control register 2
0 ANA_CF3 Analog Control register 3
ANA_CF0_LCKCHK and ANA_CF0_LCKST are used to poll 2 GHz vco lock status. When
ANA_CF0_LCKCHK is first set and reset the lock status can be read from ANA_CF0_LCKST.
If ANA_CF0_LCKST remains set the 2 GHz VCO is locked.
PR
EL
For details on how to program register bits ANA_CF0_M[1/2]LIN, ANA_CF0_M[1/2]MIC, and
ANA_CF0_M[1/2]FM, see Chapter 11.8.1 on Page 52.
Version: 0.52, 2012-11-07
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VS1005g Datasheet
Name
ANA_CF1_VHMON
ANA_CF1_PWRBTN
ANA_CF1_BTNDIS
ANA_CF1_DBG
ANA_CF1_XTDIV
ANA_CF1_SAR_ENA
ANA_CF1_DA_ENA
ANA_CF1_DRV_ENA
ANA_CF1_DAGAIN
Bits
15
14
13
12
11
10
9
8
7
6
5:4
3
2
1:0
VS1005G PERIPHERALS AND REGISTERS
IN
AR
Y
11
ANA_CF1 Bits
Description
Reserved, use ’0’
Regulator input voltage monitor (VHIGH)
Power button pin state
Power button reset disable
Reserved, use ’1’
Debug mode pin state
Input clock divider for 24.576 MHz XTALI oscillator
SAR power and enable
Reserved, Use ’0’
DAC power and enable
Reserved, use ’00’
DAC driver power enable
Reserved, use ’0’
DAC gain control
IM
DAC Gain ANA_CF1_DAGAIN Values
Name
Value
Gain Description
ANA_CF1_DAGAIN_M6DB
3
-6 dB
2
-2 dB Causes distortion in sound, do not use
ANA_CF1_DAGAIN_M12DB
1 -12 dB
ANA_CF1_DAGAIN_0DB
0
0 dB
ANA_CF1_XTDIV is the input clock prescaler control register. When register is set the input
clock is divided by 2. ANA_CF1_SAR_ENA, ANA_CF1_DA_ENA and ANA_CF1_DRV_ENA
are analog module’s enable signals. When register is set the module is enabled.
Name
EL
ANA_CF2_TSTE
ANA_CF2_VCMST
ANA_CF2_VCMDIS
ANA_CF2_UTM_ENA
ANA_CF2_LNA_ENA
ANA_CF2_2G_ENA
ANA_CF2_AMP1_ENA
ANA_CF2_AMP2_ENA
Bits
15:14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ANA_CF2 Bits
Description
Reserved , use ’0’
Hardware debug test enable, read only
Ground buffer short circuit monitor
Ground buffer driver short circuit protection disable
Hi-Speed USB UTM enable
Low Noise Amplifier enable
2 GHz VCO enable
Microphone amplifier 1 enable
Microphone amplifier 2 enable
Reserved, use ’0’
Analog reference voltage, 1.2 V (0) or 1.6 V (1)
Analog reference power enable
ADC 3 power enable
ADC 2 power enable
ADC 1 power enable
PR
ANA_CF2_HIGH_REF
ANA_CF2_REF_ENA
ANA_CF2_M3_ENA
ANA_CF2_M2_ENA
ANA_CF2_M1_ENA
ANA_CF2 register controls several analog module power enables. Each module is enabled
when the power enable register bit is set.
Version: 0.52, 2012-11-07
43
VS1005g Datasheet
Name
ANA_CF3_480_ENA
ANA_CF3_UTMBIAS
ANA_CF3_FMDIV[1:0]
ANA_CF3_DIV[1:0]
ANA_CF3_GAIN2[2:0]
ANA_CF3_GAIN1[2:0]
ANA_CF3_2GCNTR[3:0]
VS1005G PERIPHERALS AND REGISTERS
IN
AR
Y
11
ANA_CF3 Bits
Bits Description
15 480 MHz clock enable
14 USB pad bias enable
13:12 FM divider selection 16, 20 or 24
11:10 VCO divider select register
9:7 ADC 2 gain register
6:4 ADC 1 gain register
3:0 VCO center frequency register
ANA_CF3_FMDIV is the VCO divider selection register for FM receiver. When the register is
set the VCO clock is divided by 20 (FM mode). When the register is reset the divider value is
16 (HS USB mode). ANA_CF3_FMDIV2 register selects the divider 24. In this divider mode
the ANA_CF3_FMDIV should be set. The VCO frequency is therefore FM tuning frequency
multiplied by 16, 20 or 24.
FMDIV[0]
1
0
1
0
IM
FMDIV[1]
1
1
0
0
FM Divider Bits
Divider Description
24
FM frequency is VCO frequency divided by 24
20
FM frequency is VCO frequency divided by 20
24
Don’t Use (reserved)
16
FM frequency is VCO frequency divided by 16
ANA_CF3_2GCNTR register is used to match VCO’s center frequency to programmed value
(CCF). ANA_CF3_DIV[1:0] controls the VCO’s dividers. These dividers are used to set VCO’s
output frequency range.
ANA_CF3_480ENA is the 480 MHz clock driver enable for UTM. When set the clock driver is
enabled.
EL
ANA_CF3_GAIN1 and ANA_CF3_GAIN2 set the ADC 1 and 2 gains. ADC gain can be adjusted to four values.
PR
Register value
001
010
100
000
11.6.2
ADC Gain
Gain
20 dB (max)
17 dB
14 dB
11 dB (min), default after reset
Regulator and Peripheral Clock Control Registers
VS1005g has four internal regulators, one regulator for each power domain. The voltage can
be adjusted in about 50mV step size. To save power some of the peripheral clocks can be
switched off.
Version: 0.52, 2012-11-07
44
VS1005g Datasheet
Reg
0xFECE
0xFED0
Type
r/w
r/w
Regulator and Clock Control
Reset Abbrev
Description
0 REGU_CF
Regulator control register
0 REGU_VOLT Regulator voltage register
Name
REGU_VOLT_AVDD[4:0]
REGU_VOLT_IOVDD[4:0]
REGU_VOLT_CVDD[4:0]
REGU_VOLT Bits
Bits Description
14:10 Analog voltage configuration 2.7V-3.6V
9:5 IO voltage configuration, 1.8V-3.6V
4:0 Core voltage configuration, 1.65V-1.9V
REGU_CF Bits
Bits Description
11:7 Serial Flash voltage configuration
6 Serial Flash voltage regulator shutdown
5 AD filter clock gate control
4 FM demodulator clock gate control
3 Regulator latch enable
2 Analog voltage regulator shutdown
1 IO voltage regulator shutdown
0 Core voltage regulator shut down
IM
Name
REGU_CF_SNFVOLT1
REGU_CF_SNFOFF
REGU_CF_ADOFF
REGU_CF_FMOFF
REGU_CF_REGCK
REGU_CF_AOFF
REGU_CF_IOOFF
REGU_CF_COFF
1
VS1005G PERIPHERALS AND REGISTERS
IN
AR
Y
11
User should not modify this register if embedded serial flash is used.
REGU_CF_ADOFF and REGU_CF_FMOFF control the AD and FM peripheral clocks. When
these registers are set the clocks are cut off.
REGU_CF_REGCK is used to latch in the regulator voltage and shutdown bits. Typical values
for voltages are calculated from equations:
EL
• CV DD = 1.24V + (30mV ∗ voltage register)
• IOV DD = 1.80V + (60mV ∗ voltage register)
PR
• AV DD = 2.48V + (40mV ∗ voltage register)
Version: 0.52, 2012-11-07
45
VS1005g Datasheet
11.7
Audio Playback Interfaces
Digital
DAOSET_CF
DAOSET_LEFT
DAOSET_RIGHT 24
Sample
and hold
upconverter
24
24
Sample rate
upconverter
with filters
Analog
LEFT
DAC_VOL
DAC_SRC
DAC_LEFT
DAC_RIGHT
VS1005G PERIPHERALS AND REGISTERS
IN
AR
Y
11
24
24
DAC +
output
drivers
24
RIGHT
CBUF
I2S_CF
I2S_LEFT
I2S_RIGHT
I2S_BCK,I2S_FRM
I2S_DO
32/16
24
SRC_CF
Filterless
sample rate
down−
converter
RED: Pin
BLUE: Register
SP_LDATA
SP_RDATA
S/PDIF
encoder
24
SRC_LEFT
SRC_RIGHT
24
SPDIF_OUT
24/16
IM
Figure 9: VS1005g playback (DA) audio paths.
The VS1005g playback audio paths are shown in Figure 9.
The nominal high-quality audio path egins from registers DAC_LEFT and DAC_RIGHT, then
goes through the Sample Rate Upconverter with Filters and the Volume Control to the DAC,
and finally to the LEFT and RIGHT output pins. CBUF is used as a ground reference.
EL
For lower-quality sound effects, secondary audio with a potentially different sample rate can be
independently added to the signal through the DAOSET_LEFT and DAOSET_RIGHT registers.
The upconverter for this path contains only sample-and-hold filtering, so using low sample rates
may result in audible aliasing.
The combined main and secondary audio path signal can optionally also be copied to the I2S
output. Alternatively the I2S output can be controlled directly using registers I2S_LEFT and
I2S_RIGHT.
PR
The main audio path may be intercepted and downsampled with the Filterless Sample Rate
Downconverter. Because the downconverter is filterless, the user has to take care to select
sample rates in such a way that doesn’t introduce audible aliasing. Aliasing does not occur if the
sample rate for the output (SRC_LEFT and SRC_RIGHT) is never lower than the sample rate
for the input (DAC_LEFT and DAC_RIGHT), but in special cases even lower Downconverter
sample rates may result in audio that is good enough for the application.
Not directly connected to any other part of the playback audio path is the S/PDIF signal path.
This signal path does not interact with the other ones, and it is only included in the figure to
show all available playback audio paths.
Version: 0.52, 2012-11-07
46
VS1005g Datasheet
11.7.1
VS1005G PERIPHERALS AND REGISTERS
IN
AR
Y
11
Primary Audio Path 24-bit Sample Rate Upconverter with Filters: DAC Registers
VS1005g has a 24-bit DAC with a programmable sample rate. Sample rates up to 96 kHz are
supported.
Address
0xFC34
0xFC35
0xFC36
0xFC37
0xFC38
0xFC39
Type
r/w
r/w
r/w
r/w
r/w
r/w
Reset
0
0
0
0
0
0
DAC Interface Registers
Abbrev
Description
DAC_SRCL
DAC sample rate, bits 15-0
DAC_SRCH[3:0]
DAC sample rate, bits 19-16
DAC_LEFT_LSB[15:8]
DAC left sample, bits 7-0
DAC_LEFT
DAC left sample, bits 23-8
DAC_RIGHT_LSB[15:8] DAC right sample, bits 7-0
DAC_RIGHT
DAC right sample, bits 23-8
The DAC interpolator frequency is defined with registers DAC_SRCH and DAC_SRCL. Output
sample rate is derived from the rollover frequency of a 20-bit interpolator accumulator. Its
accumulation rate is specified by ifreq.
Input sample rate fs can be calculated from the equation
fs = (fclk /227 ) × if req
IM
where Ifreq can have values from 1 to 1048575 (0xFFFFF) and fclk is the XTALI clock frequency. Value zero of ifreq places the DAC in idle mode. In idle mode all logic is halted. Also
the analog clock is halted.
Note that the DAC clock is not controlled by the PLL.
The exact sample rate is xtal dependent and a sample rate of e.g exactly 48 kHz requires that
XTALI = 12.288 MHz.
EL
24-bit samples are written to registers DAC_LEFT, DAC_LEFT_LSB, DAC_RIGHT and DAC_RIGHT_LSB
after each DAC interrupt.
Configuring Analog DAC Modules
Example values of analog configuration registers with 1.6 V reference are given in next table.
Analog Control Register example for DAC Operation
Register
Value Description
ANA_CF1 0x0048 DAC and output driver power down
ANA_CF2 0x0018 Reference voltage select and reference power down
PR
Address
0xFECB
0xFED2
Version: 0.52, 2012-11-07
47
VS1005g Datasheet
11.7.2
VS1005G PERIPHERALS AND REGISTERS
IN
AR
Y
11
Primary Audio Path Volume Control
In VS1005g the DAC’s volume level can be adjusted in -0.5dB steps.
Reg
0xFEC0
Type
r/w
DAC Volume Registers
Reset Abbrev
Description
0 DAC_VOL DAC volume control register
DAC_VOL Bits
Name
Bits Description
DAC_VOL_LADD[3:0] 15:12 Left channel +0.5dB steps
DAC_VOL_LSFT[3:0]
11:8 Left channel -6dB steps
DAC_VOL_RADD[3:0]
7:4 Right channel +0.5dB steps
DAC_VOL_RSFT[3:0]
3:0 Right channel -6dB steps
DAC_VOL_LSFT and DAC_VOL_RSFT are the coarse volume control registers. They suppress
channel volume by -6dB steps.
PR
EL
IM
DAC_VOL_LADD and DAC_VOL_RADD are the fine volume control registers. They add channel volume level by +0.5dB steps. Allowed values are from 0 to 11, i.e. maximum is +5.5dB.
Values between 12-15 equal to 0dB.
Version: 0.52, 2012-11-07
48
VS1005g Datasheet
11.7.3
VS1005G PERIPHERALS AND REGISTERS
IN
AR
Y
11
Secondary Audio Path: DAOSET Registers
In VS1005g a secondary audio source can be mixed to the main audio path output. This is
done with DAC offset registers. The sample rate is programmable.
Reg
0xFEC1
0xFEC2
0xFEC3
0xFEC4
0xFEC5
Type
r/w
r/w
r/w
r/w
r/w
DAC Offset Registers
Abbrev
DAOSET_CF
DAOSET_LEFT_LSB[15:12]
DAOSET_LEFT
DAOSET_RIGHT_LSB[15:12]
DAOSET_RIGHT
Reset
0
0
0
0
0
Description
DAC offset configuration register
DAC left offset bits [3:0]
DAC left offset bits [19:4]
DAC right offset bits [3:0]
DAC right offset bits [19:4]
DAOSET_CF Bits
Name
Bits Description
DAOSET_CF_URUN
14 Data register underrun flag
DAOSET_CF_FULL
13 Data register full flag
DAOSET_CF_ENA
12 Enable for DAC offset
DAOSET_CF_FS
11:0 DAC offset sample rate
IM
DAOSET_CF_URUN is an underrun flag register. The register is set if data register was read
when the full flag was not set.
DAOSET_CF_FULL is a data status register. Flag is set when data is written to DAOSET_LEFT
and DAOSET_RIGHT registers and reset when DAC reads the register.
DAOSET_CF_ENA enables DAC offset module.
EL
DAOSET_CF_FS is used to set DAC offset sample rate. This register defines the interval in
clock cycles where the samples are added to DAC output. When new samples are read from
data registers also an interrupt request is generated.
Sample rate can be calculated from equation:
f s = Fclk /(dacof f set_cf _f s + 1)) where
dacoffset_cf_fs can have values from 0 to 4095 (0xFFF) and Fclk is the XTALI clock frequency.
E.g. value 0xFFF gives sample rate of 12.288 MHz / (0xFFF+1) = 3.0 kHz.
PR
DAC and DAC offset mixing logic uses saturation to limit samples to 20-bit signed values. The
mixed values should not exceed 75% of the full scale values or the signal to noise ratio may be
degraded.
Version: 0.52, 2012-11-07
49
VS1005g Datasheet
11.7.4
VS1005G PERIPHERALS AND REGISTERS
IN
AR
Y
11
Filterless Sample Rate Converter (SRC) Registers
VS1005g has a programmable sample rate converter which can be used to convert DAC’s input
sample rate to an other sample rate which is higher than the original sample rate.
SRC Characteristics
Value
Description
11.0 MHz - 13.0 MHz Clock frequency
24
Input data width
24
Output data width
0 Hz - 96 kHz
Input sample rate
0.97 ×F Sin - 192 kHz Output sample rate
19 input samples
0.78
Item
XTALI Clock
DAC bit width
SRC bit width
DAC sample rate 1
Output sample rate 1
Filter delay 2
Gain
2
Assuming 12.288 MHz XTALI clock.
In start-up the SRC output is valid after 19 DAC interrupts.
Reg
0xFEC6
0xFEC7
0xFED8
0xFED9
0xFEDA
Type
r/w
r/w
r/w
r/w
r/w
Reset
0
0
0
0
0
SRC Registers
Abbrev
SRC_CF
SRC_LEFT_LSB[15:12]
SRC_LEFT
SRC_RIGHT_LSB[15:12]
SRC_RIGHT
Description
SRC sampler configuration register
SRC left sample bits [7:0]
SRC left sample bits [23:8]
SRC right sample bits [7:0]
SRC right sample bits [23:8]
IM
1
SRC_CF Bits
Bits Description
15 SRC overrun flag
14 Right data register full flag
13 Left data register full flag
12 Enable for sample rate convertter
11:0 SRC sample rate
EL
Name
SRC_CF_ORUN
SRC_CF_RFULL
SRC_CF_LFULL
SRC_CF_ENA
SRC_CF_FS
SRC_CF_ORUN is set if data register was full when data registers were modified.
SRC_CF_RFULL and SRC_CF_LFULL status registers for new samples. Flags are set as
SRC_LEFT and SRC_RIGHT are modified and reset as they are read.
SRC_CF_ENA enables sample rate converter when set.
PR
SRC_CF_FS is used to set src sample rate. This register defines the interval in clock cycles
when the samples are generated. When new samples are stored to data registers also an
interrupt request is generated.
Output sample rate can be calculated from equation:
f s = XT ALI/(2 ∗ (src_cf _f s + 1))
where src_cf_fs can be between 0 and 4095 (0xFFF).
Example: With src_cf_fs = 0x7FF, the sample rate fs = 12.288 MHz / (2*(0x7FF+1)) = 3000 Hz.
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VS1005g Datasheet
11.8
VS1005G PERIPHERALS AND REGISTERS
IN
AR
Y
11
24-bit Analog to Digital Converters (ADC)
DIA1
Analog and RF
LINE1_1
Digital
ANA_CF0
LINE2_1
RED: Pin
BLUE: Register or register bit(s)
FM_CF_UAD1
LINE3_1
MIC1N
ANA_CF0 ANA_CF3
_GAIN1
MIC1P
AD_CF_
ADENA
AD_CF_ADFS
AD_LEFT
AD1
24
24
RF_N
RF_P
ANA_CF0 ANA_CF3
_GAIN2 ANA_CF0
AD_CF_
AD23_FLP
VCO
MIC2N
FM_CF_UAD2
AD_CF_
AD_CF_ADFS
ADENA
24
24
AD_CF_
AD3ENA
MIC2P
AD_RIGHT
AD2
AD_CF_AD3FS
AD_MONO
AD3
LINE1_2
24
24
LINE2_2
AD_CF_DEC6SEL
LINE3_2
FM_CF_UAD3
LINE1_3
IM
DIA2
I
Q
DIA3
FM
demod.
FML
FMR
Left
Right
Mono
AD_CF_DEC6ENA
DEC6_LEFT
L
18
18
6 DEC6_RIGHT
R
18
18
S/PDIF
decoder
SPDIF_IN
SP_LDATA
24
SP_RDATA
24
Figure 10: VS1005g recording (AD and FM) signal paths
EL
VS1005g has three 24-bit AD input channels and an FM receiver. The signal paths for them
are shown in Figure 10.
ADs 1 and 2 can be configured for mic or line input mode (stereo AD). AD 3 can be used as a
line input (mono AD). However, if AD_CF_AD23_FLP is set, then analog channels 2 and 3 are
crossed before the analog-to-digital converters. This makes it possible to use AD3 as a mono
microphone input (e.g. pins MIC2N and MIC2P), potentially at a different sample rate from a
stereo line input to AD1 and AD2 (e.g. to pins LINE1_1 and LINE1_3).
When the FM receiver is used only AD 3 is available for other uses because the FM demodulator
reserves the signal paths of ADs 1 and 2.
PR
All of the logic is clocked directly with the XTALI (11-13 MHz). FM and AD digital peripheral
clocks can be switched off to save power. In order to use FM or/and AD channels the master
clock enable registers REGU_CF_ADOFF and REGU_CF_FMOFF must be reset. Analog and
RF logic clocking is automatically switched on when blocks are enabled.
The front end of the ADs (analog section, i.e. ADC) always operates at XTALI / 2. The digital
logic has a programmable sample rate. Sample rates are between 24 kHz and 192 kHz. It
should be noted that the exact sample rates are XTALI-dependent and here it is assumed that
XTALI = 12.288 MHz.
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VS1005g Datasheet
VS1005G PERIPHERALS AND REGISTERS
IN
AR
Y
11
Note that the S/PDIF interface does not interact with any other audio paths. It is only included
to show all available audio input paths, digital or analog.
AD filter’s control and data registers are listed in following table.
Reg
0xFE40
Type
r/w
0xFE41
0xFE46
0xFE47
0xFE48
0xFE49
0xFE4A
0xFE4B
0xFE4E
0xFE4F
0xFE50
0xFE51
r/w
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
Configuring Signal Paths for ADC1, ADC2 and ADC3
IM
11.8.1
A/D Control and Data Registers
Abbrev
Description
FM_CF
FM demodulator and AD filter configuration register
AD_CF
AD filter configuration register
AD_LEFT_LSB[15:8]
AD1 filter (left) channel bits [7:0]
AD_LEFT
AD1 filter (left) channel bits [23:8]
AD_RIGHT_LSB[15:8]
AD2 filter (right) channel bits [7:0]
AD_RIGHT
AD2 filter (right) channel bits [23:8]
AD_MONO_LSB[15:8]
AD3 filter (mono) channel bits [7:0]
AD_MONO
AD3 filter (mono) channel bits [23:8]
DEC6_LEFT_LSB[15:14]
FM filter left channel bits [1:0]
DEC6_LEFT
FM filter left channel bits [17:2]
DEC6_RIGHT_LSB[15:14] FM filter right channel bits [1:0]
DEC6_RIGHT
FM filter right channel bits [17:2]
Reset
0
Analog signal paths for ADCs are configured using registers ANA_CF0 (see Chapter 11.6.1 on
Page 42) and AD_CF (see Chapter 11.8.2, Page 54).
PR
EL
ADC1 Signal Path Configuration
Note: Always set ANA_CF2 bits ANA_CF2_REF_ENA and ANA_CF2_M1_ENA.
ANA_CF0_
Input Input
Set/Check Also
M1FM M1LIN M1MIC Pin(s) Pin Name(s)
0
1
0
73 LINE1_1
0
0
0
68 LINE2_1
1
1
0
71 LINE3_1
1
0
1
72,73 MIC1P
ANA_CF2_AMP1_ENA
MIC1N
ANA_CF3_GAIN1[2:0]
1
0
0
75,76 RF_N & RF_P ANA_CF2_AMP1_ENA
(I signal)
ANA_CF2_LNA_ENA
ANA_CF2_2G_ENA
ANA_CF3_FMDIV[1:0]
ANA_CF3_DIV[1:0]
ANA_CF3_GAIN1[2:0]
ANA_CF3_2GCNTR[3:0]
AD_CF_DEC6ENA
AD_CF_DEC6SEL[1:0]
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VS1005g Datasheet
VS1005G PERIPHERALS AND REGISTERS
IN
AR
Y
11
ADC2 Signal Path Configuration
Note: Always set ANA_CF2 bits ANA_CF2_REF_ENA and ANA_CF2_M2_ENA.
ANA_CF0_
AD_CF_
Input Input
Set/Check Also
M2FM M2LIN M2MIC AD23_FLP Pin(s) Pin Name(s)
0
1
0
0
72 LINE1_2
0
0
0
0
67 LINE2_2
1
1
0
0
70 LINE3_2
1
0
1
0
70,71 MIC2P &
ANA_CF2_AMP2_ENA
MIC2N
ANA_CF3_GAIN2[2:0]
1
0
0
0
75,76 RF_N & RF_P ANA_CF2_AMP2_ENA
(Q signal)
ANA_CF2_LNA_ENA
ANA_CF2_2G_ENA
ANA_CF3_FMDIV[1:0]
ANA_CF3_DIV[1:0]
ANA_CF3_GAIN2[2:0]
ANA_CF3_2GCNTR[3:0]
AD_CF_DEC6ENA
AD_CF_DEC6SEL[1:0]
x
x
x
1
69 LINE1_3
EL
IM
ADC3 Signal Path Configuration
Note: Always set ANA_CF2 bits ANA_CF2_REF_ENA and ANA_CF2_M2_ENA.
ANA_CF0_
AD_CF_
Input Input
Set/Check Also
M2FM M2LIN M2MIC AD23_FLP Pin(s) Pin Name(s)
x
x
x
0
69 LINE1_3
0
1
0
1
72 LINE1_2
0
0
0
1
67 LINE2_2
1
1
0
1
70 LINE3_2
1
0
1
1
70,71 MIC2P &
ANA_CF2_AMP2_ENA
MIC2N
ANA_CF3_GAIN2[2:0]
1
0
0
1
75,76 RF_N & RF_P ANA_CF2_AMP2_ENA
(Q signal)
ANA_CF2_LNA_ENA
(NOTE: There ANA_CF2_2G_ENA
is no hardware ANA_CF3_FMDIV[1:0]
to decode
ANA_CF3_DIV[1:0]
signals from
ANA_CF3_GAIN2[2:0]
this path.)
ANA_CF3_2GCNTR[3:0]
PR
Note: Decoding FM transmissions is only possible if both ADC1 and ADC2 are configured for
FM reception (RF pins), and if ANA_CF3_GAIN1 = ANA_CF3_GAIN2.
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VS1005g Datasheet
11.8.2
Digital Filter Operation Modes
VS1005G PERIPHERALS AND REGISTERS
IN
AR
Y
11
The FM_CF register has four bits that have effect on AD functionality. FM_CF_ENABLE activates digital filters. When the register is set the digital filters are operable. This register bit can
also be used to synchronize the stereo and mono AD filters when three channels are used with
same sample rate (no phase error). To do this, clear FM_CF_ENABLE (if not already cleared),
then set it again.
The input to digital filters can also be selected from external ADCs. With FM_CF_UAD1,
FM_CF_UAD2 and FM_CF_UAD3 registers the filter’s input can be taken from an external
source (pins DIA1, DIA2, and DIA3, respectively). In this mode the AD input sample rate must
be XTALI/2 or XTALI/4 and the input must be synchronized to VS1005g the XTALI oscillator
clock. VS1005g can provide both the XTAL, XTAL/2, and XTAL/4 clocks to external circuits.
FM_CF Bits for Digital Filters (see Chapter 11.9.2 for other bits)
Name
Bits Description
FM_CF_UAD2
14 External input enable for stereo AD, right channel
FM_CF_UAD1
13 External input enable for stereo AD, left channel
FM_CF_UAD3
12 External input enable for mono AD
FM_CF_ENABLE
6 Software reset for AD and FM demodulator
IM
The AD configuration register has bits to enable filters and to select sample rates. When the
filter is enabled also the interrupt request is generated and forwarded to the interrupt controller.
The decimation filter is included to decimate the demodulated FM signals downto 32 kHz sample rate but its input can be selected from other sources also. The filter’s input bit width is 18
bits.
Bits
9
8:7
6:5
4:3
EL
Name
AD_CF_AD23_FLP
AD_CF_DEC6SEL[1:0]
AD_CF_AD3FS[1:0]
AD_CF_ADFS[1:0]
AD_CF Bits
Description
Flip AD2 and AD3 inputs
Input selection for FM filter (decimation-by-6)
Sample rate selection for AD filter 3 (mono AD)
Sample rate selection for AD filters 1 and 2 (stereo
AD)
FM decimation-by-6 filter enable
AD filter 3 enable (mono AD, line input 3)
AD filter 1 and 2 enable (stereo AD, line input 1
and 2)
AD_CF_DEC6ENA
AD_CF_AD3ENA
AD_CF_ADENA
2
1
0
AD_CF_AD23_FLP register flips the input of filters 2 and 3.
PR
The FM decimation filter is used when FM is enabled and it decimates the FM signals to 32 kHz.
However, the filter can also be used with other inputs. Register AD_CF_DEC6SEL is used to
select the filter input.
Decimation filter input selection
Name
AD_CF_DEC6SEL Filter input
AD_CF_DEC6SEL_MONO
11 or 10 mono AD (left = right)
AD_CF_DEC6SEL_STEREO
01 stereo ADs
AD_CF_DEC6SEL_FM
00 FM demodulator
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VS1005g Datasheet
VS1005G PERIPHERALS AND REGISTERS
IN
AR
Y
11
Sample rate selection for AD filters 1 and 2 (stereo AD)
Name
AD_CF_ADFS Decimation factor1 Sample rate2
AD_CF_ADFS_24K
11
256
24 kHz
AD_CF_ADFS_48K
10
128
48 kHz
AD_CF_ADFS_96K
01
64
96 kHz
AD_CF_ADFS_192K
00
32
192 kHz
1
2
The filter input is XTALI/2, or nominally 6.144 MHz.
Sample rate when XTALI = 12.288 MHz.
Sample rate selection for AD filters 3 (mono AD)
Name
AD_CF_AD3FS Decimation factor1 Sample rate2
AD_CF_AD3FS_24K
11
256
24 kHz
AD_CF_AD3FS_48K
10
128
48 kHz
AD_CF_AD3FS_96K
01
64
96 kHz
AD_CF_AD3FS_192K
00
32
192 kHz
1
2
The filter input is XTALI/2, or nominally 6.144 MHz.
Sample rate when XTALI = 12.288 MHz.
PR
EL
IM
AD_LEFT, AD_LEFT_LSB, AD_RIGHT, AD_RIGHT_LSB, AD_MONO and AD_MONO_LSB
are the output data registers of the three AD filters. As a new data sample is calculated also an
interrupt request is generated.
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VS1005g Datasheet
11.9
FM Receiver
VS1005G PERIPHERALS AND REGISTERS
IN
AR
Y
11
The FM receiver in VS1005g is capable of receiving frequency modulated (FM) signals from
76 MHz to 108 MHz. The operation of FM receiver requires several modules:
• RF modules : VCO, LNA and Mixer
• Analog modules : Muxes, amplifiers and ADCs
• Digital modules : Digital filters and FM demodulator
As was shown in Figure 10. the FM receiver uses partially the same signal paths as the ADCs.
When FM demodulator is used the stereo AD filter must be configured to 192 kHz sample rate
and the decimation filter enabled with input selection from FM demodulator. Other modules
must be powered up and FM path is selected to analog output.
11.9.1
Configuring RF and Analog Modules for FM Receiver Mode
PR
EL
IM
The front end configuration of the FM receiver is shown in Figure 11. The VCO is digitally
controlled and set to an FM band as is explained in section “Configuring FM Demodulator”.
Figure 11: Block diagram of FM receiver, RF and analog section
To see how to configure the A/D converters for FM reception usage, see Chapter 11.8.1 on
Page 52.
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VS1005g Datasheet
11.9.2
VS1005G PERIPHERALS AND REGISTERS
IN
AR
Y
11
Configuring the FM Demodulator
The FM demodulator has several configuration registers that must be initialized in order to
receive an FM channel. FM demodulator’s control and data registers are listed in next table.
Reg
0xFE40
0xFE41
0xFE42
0xFE43
0xFE44
0xFE45
0xFE4E
0xFE4F
0xFE50
0xFE51
0xFE52
0xFE53
0xFE5B
Type
r/w
r/w
r/w
r/w
r/w
r/w
r
r
r
r
r
r
r
FM Control and Data Registers
Abbrev
Description
FM_CF
FM demodulator control
AD_CF
AD filter configuration
FMPLL_LO
FM PLL carrier frequency bits [15:0]
FMPLL_HI
FM PLL carrier frequency bits [28:16]
FMCCF_LO
Carrier center frequency bits [15:0]
FMCCF_HI[10:0]
Carrier center frequency bits [26:16]
DEC6_LEFT_LSB[15:14]
FM filter left channel bits [1:0]
DEC6_LEFT
FM filter left channel bits [17:2]
DEC6_RIGHT_LSB[15:14] FM filter right channel bits [1:0]
DEC6_RIGHT
FM filter right channel bits [17:2]
RDS_DATA
FM RDS data
RDS_CHK[12:0]
FM RDS checkwork and block status
FM_PHSCL
FM I/Q phase error scaling factor
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
Name
Bits
15
14
13
12
11:8
7
6
5
4
3
2
1
0
FM_CF Bits
Description
Reserved, use 0
Enable AD2 digital input
Enable AD1 digital input
Enable AD3 digital input
Reserved, Use “000”
Enable for FM I- and Q-signal scaling
Enable & synchronize AD filters and FM demodulator
FM RDS forced to keep synchronization
FM receiver mono (1) / stereo (0) selection
FM de-emphasis filter configuration 75µs or 50µs
FM RDS enable
FM carrier lock enable
FM demodulator enable
EL
FM_CF_UAD2
FM_CF_UAD1
FM_CF_UAD3
IM
FM_CF register is a configuration register which is used to select demodulator operation modes.
The FMCCF_HI and FMCCF_LO are used to tune FM receiver to a certain channel. The FMPLL_HI and FMPLL_LO registers are used to match xtal frequency to the stereo subcarrier
frequency (38 kHz).
PR
FM_CF_PHCOMP
FM_CF_ENABLE
FM_CF_RDSSYNC
FM_CF_MONO
FM_CF_DEEMP
FM_CF_RDSENA
FM_CF_CCFLCK
FM_CF_FM_ENA
In FM mode the registers FM_CF_UAD2 and FM_CF_UAD1 must be reset.
FM_CF_PHCOMP is the enable signal for FM input scaling.
FM_CF_ENABLE is the global enable for FM demodulator and AD filters. When zero, demodulators and mono/stereo AD filters are reset. To synchronize and use the demodulators, first
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57
VS1005g Datasheet
clear this bit, then set it.
VS1005G PERIPHERALS AND REGISTERS
IN
AR
Y
11
FM_CF_RDSSYNC forces the RDS decoder to keep current symbol synchronization. When
sync search is enabled (i.e. FM_CF_RDSSYNC is reset) the RDS decoder tries to find best
symbol synchronization at all times, even when the FM signal is lost.
FM_CF_MONO register selects between mono and stereo receive modes. When set the mode
is mono.
FM_CF_DEEMP register selects between 75µs (North America) or 50µs (Europe, Australia)
de-emphasis filters. When set the de-emphasis is 75µs.
FM_CF_RDSENA register enables the rds calculation logic when set.
FM_CF_CCFLCK register enables automatic FM fine tuning when set. When reset the FM
band frequency is always at fixed value (as defined in FMCCF register).
FM_CF_FM_ENA is the FM demodulator enable. The register must be set when FM is used.
To receive in stereo mode the FM_PLL registers must be initialized correctly. These registers (FMPLL_HI and FMPLL_LO) set the FM stereo carrier PLL frequency. This factor is xtal
dependent and is defined as:
(64×228 ×38000Hz)
XT AL_f reqHz
IM
pll_f actor =
PLL value examples for most typical xtals
XTALI frequency FMPLL register
12.0 MHz 54402918 = 0x033E 1F66
12.288 MHz 53127850 = 0x032A AAAA
13.0 MHz 50218079 = 0x02FE 445F
EL
FMCCF_HI and FMCCF_LO are used to set FM tuning frequency (FM Carrier Center Frequency). These registers hold a 27-bit signed value which controls the frequency inside the
selected VCO center frequency range. This VCO center frequency is set with divider registers
ANA_CF3_DIV[1:0] and ANA_CF3_FMDIV[1:0].
PR
VCO Divider Register
ANA_CF3_DIV[1:0] VCO Divider
“00” 36
“01” = “10” 30
“11” 25
Version: 0.52, 2012-11-07
FM divider
ANA_CF3_FMDIV[1:0]
“00”
“10”
“11” = “01”
FM divider
16
20
24
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VS1005g Datasheet
VS1005G PERIPHERALS AND REGISTERS
IN
AR
Y
11
The VCO frequency is 24, 20 or 16 times the FM tuning frequency, i.e. for 95.0 MHz FM channel
the VCO frequency must be set to 1.900 GHz. The target VCO frequency can be calculated
from equation :
Fvco = (4 × V COdiv + CCF ) × Fxtal where CCF is defined as CCF =
F M CCFreg
221
+ 16
and the FM channel frequency can be given as:
FF M = ((4 × V COdiv + CCF ) × Fxtal )/F Mdiv
For Hi-Speed USB FMCCF registers must be reset when XTALI = 12.000 MHz is used. When
XTALI = 12.288 MHz is used the registers are initialized to 0xFF87, 0xFFFF (-7864321). FM_CF
register is initialized to value 0x0041. This makes VCO frequency of 1.92GHz which results to
480 MHz USB clock.
Name
FM_PHSCL_I[7:0]
FM_PHSCL_Q[7:0]
FM_PHSCL Bits
Bits Description
15:8 I scaling factor
7:0 Q scaling factor
IM
FM_PHSCL register is used to compensate I and Q signal’s phase and amplitude error. This
error depends from several factors and values should be calculated for each FM band. The
compensation logic is enabled when FM_CF_PHCOMP register is set. Typical values are 111
for I-scaling and 137 for Q-scaling.
DEC6_LEFT, DEC6_LEFT_LSB, DEC6_RIGHT and DEC6_RIGHT_LSB are the FM demodulator output data registers. Sample rate @12.288 MHz is 32 kHz (XTALI / 384).
11.9.3
Radio Data System (RDS)
PR
EL
FM demodulator includes an RDS module. This module decodes the RDS bits from baseband
signal to form bit groups. When a full block is decoded the 16-bit data and 10-bit checkword
are stored to registers and an RDS-interrupt is generated. RDS data structure is shown in
Figure 12. RDS data rate is 1187.5 bits per second.
Version: 0.52, 2012-11-07
Figure 12: RDS data structure
59
VS1005g Datasheet
VS1005G PERIPHERALS AND REGISTERS
IN
AR
Y
11
RDS module’s control bits are in register FM_CF.
RDS Control Bits in Register FM_CF (address 0xFE40)
Name
Bit Index Description
FM_CF_RDSSYNC
5 FM RDS forced to keep current bit synchronization
FM_CF_RDSENA
2 FM RDS enable
Reg
0xFE52
0xFE53
Type
r
r
FM Control and Data Registers
Reset Abbrev
Description
0 RDS_DATA[15:0] FM RDS data register
0 RDS_CHK[12:0] FM RDS checkwork and block status
RDS_DATA and RDS_CHK registers store the last decoded RDS block. RDS module finds
automatically bit and block synhronization but it does not do any data correction if crc errors
exist. This must be done by software.
IM
Bit index
12:3
2
1:0
PR
EL
Reg
RDS_CHK_CHKW
RDS_CHK_ST
RDS_CHK_BLK
RDS_CHK Register Bits
Name
Description
CHECKWORD Checkword of the last received block data
STATUS
Validity of the last received block
BLOCK
Index of the last received block, 0-3
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VS1005g Datasheet
11.10
SPI Peripherals
VS1005G PERIPHERALS AND REGISTERS
IN
AR
Y
11
VS1005g has two SPI (serial-to-paralle) peripherals which can be configured as a master or a
slave. Before SPIs can be used the VS1005g I/Os must be configured to peripheral mode:
• set I/O pins to peripheral mode : GPIO1_MODE register selects between spi mode or
gpio mode
• Embedded Serial Flash disabled : SYSTEMPD_SFENA bit reset when using SPI0 (also
boot device)
• Buffered SPI slave disabled : ETH_RXLEN_PMODE bit reset when using SPI1
SPI0 and SPI1 pins are mapped to GPIO1 port. To select peripheral mode the bits in GPIOx_MODE
register must be set HIGH.
VS1005g pin
XCS0/GPIO1[0]
SCLK0/GPIO1[1]
MISO0/GPIO1[2]
MOSI0/GPIO1[3]
XCS1/GPIO1[4]
SCLK1/GPIO1[5]
MISO1/GPIO1[6]
MOSI1/GPIO1[7]
SPI pins and their GPIOx_MODE register
Type SPI pin GPIO_MODE register Description
i/o
xcs
GPIO1_MODE[0]
Master/slave chip select
i/o
sclk
GPIO1_MODE[1]
Master/slave clock
i/o
miso
GPIO1_MODE[2]
Master input / slave output
i/o
mosi
GPIO1_MODE[3]
Master output / slave input
i/o
xcs
GPIO1_MODE[4]
Master/slave chip select
i/o
sclk
GPIO1_MODE[5]
Master/slave clock
i/o
miso
GPIO1_MODE[6]
Master input / slave output
i/o
mosi
GPIO1_MODE[7]
Master output / slave input
IM
SPI id
SPI0
SPI0
SPI0
SPI0
SPI1
SPI1
SPI1
SPI1
The SPIs are mapped in Y addresses 0xFC40 (SPI0) and 0xFC50 (SPI1).
SPI1 address
0xFC50
0xFC51
0xFC52
0xFC53
0xFC54
0xFC55
PR
EL
SPI0 address
0xFC40
0xFC41
0xFC42
0xFC43
0xFC44
0xFC45
SPI Registers, Prefix SPIx_
Type Reset Abbrev
r/w
0 CF[10:0]
r/w
0 CLKCF
r/w
0 STATUS[7:0]
r/w
0 DATA
r/w
0 FSYNC
r/w
0 DEFAULT
Version: 0.52, 2012-11-07
Description
Configuration
Clock configuration
Status
Sent / received data
SSI Sync data in master mode
Data to send (slave) if
SPIx_ST_TXFULL=’0’
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VS1005g Datasheet
VS1005G PERIPHERALS AND REGISTERS
IN
AR
Y
11
Main Configuration SPIx_CF Bits
Name
Bits Description
SPI_CF_SRESET
11 SPI software reset
SPI_CF_RXFIFOMODE
10 ’0’ = interrupt always when a word is received,
’1’ = Interrupt only when FIFO register full or CS
deasserted with receive register full
SPI_CF_RXFIFO_ENA
9 Receive FIFO enable
SPI_CF_TXFIFO_ENA
8 Transmit FIFO enable
SPI_CF_XCSMODE
7:6 xCS mode in slave mode
SPI_CF_MASTER
5 Master mode
SPI_CF_DLEN
4:1 Data length in bits
SPI_CF_FSIDLE
0 Frame sync idle state
SPI_CF_XCSMODE selects xCS mode for slave operation. ’00’ is interrupted xCS mode, ’10’
is falling edge xCS mode, and ’11’ is rising edge xCS mode.
SPI_CF_MASTER sets master mode. If not set, slave mode is used.
SPI_CF_DLEN+1 is the length of SPI data in bits. Example: For 8-bit data transfers, set
SPI_CF_DLEN to 7.
IM
SPI_CF_FSIDLE contains the state of FSYNC when SPI_ST_TXRUNNING is clear. This bit is
only valid in master mode.
Clock Configuration SPIx_CLKCF Bits
Name
Bits Description
SPI_CC_CLKDIV
9:2 Clock divider
SPI_CC_INV_CLKPOL
1 Inverse clock polarity selection
SPI_CC_INV_CLKPHASE
0 Inverse clock phase selection
EL
In master mode, SPI_CC_CLKDIV is the clock divider for the SPI block. The generated SCLK
fm
frequency f = 2×(c+1)
, where fm is the master clock frequency and c is SPI_CC_CLKDIV.
Example: With a 12 MHz master clock, SPI_CC_CLKDIV=3 divides the master clock by 4, and
12 M Hz
the output/sampling clock would thus be f = 2×(3+1)
= 1.5 M Hz.
SPI_CC_INV_CLKPOL reverses the clock polarity. If SPI_CC_INV_CLKPOL is clear the data
is read at rise edge and written at fall edge if SPI_CC_INV_CLKPHASE is clear. When
SPI_CC_INV_CLKPHASE is set the data is written at rise edge and read at fall edge.
PR
SPI_CC_INV_CLKPHASE defines the data clock phase. If clear the first data is written when
xcs is asserted and data is sampled at first clock edge (rise edge when SPI_CC_INV_CLKPOL
= 0 and fall edge if SPI_CC_INV_CLKPOL = 1). If SPI_CC_INV_CLKPHASE is set the first
data is written a the first data clock edge and sampled at second.
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VS1005g Datasheet
Name
SPI_ST_RXFIFOFULL
SPI_ST_TXFIFOFULL
SPI_ST_BREAK
SPI_ST_RXORUN
SPI_ST_RXFULL
SPI_ST_TXFULL
SPI_ST_TXRUNNING
SPI_ST_TXURUN
VS1005G PERIPHERALS AND REGISTERS
IN
AR
Y
11
Status SPIx_STATUS Bits
Bits Description
7 Receiver FIFO register full
6 Transmitter FIFO register full
5 Chip select deasserted mid-transfer
4 Receiver overrun
3 Receiver data register full
2 Transmitter data register full
1 Transmitter running
0 Transmitter underrun
SPI_ST_BREAK is set in slave mode if chip select was deasserted in interrupted xCS mode or
a starting edge is encountered in xCS edge modes while a data transfer was in progress. This
bit has to be cleared manually.
SPI_ST_RXORUN is set if a received byte overwrites unread data when it is transferred from
the receiver shift register to the data register. This bit has to be cleared manually.
SPI_ST_RXFULL is set if there is unread data in the data register.
SPI_ST_TXFULL is set if the transmit data register is full.
SPI_ST_TXRUNNING is set if the transmitter shift register is in operation.
IM
SPI_ST_TXURUN is set if an external data transfer has been initiated in slave mode and the
transmit data register has not been loaded with new data to shift out. This bit has to be cleared
manually.
Note: Because TX and RX status bits are implemented as separate entities, it is relatively easy
to make asynchronous software implementations, which do not have to wait for an SPI cycle to
finish.
EL
SPIx_DATA[SPI_CF_DLEN:0] may be written to whenever SPI_ST_TXFULL is clear. In master
mode, writing will initiate an SPI transaction cycle of SPI_CF_DLEN+1 bits. In slave mode,
data is output as soon as suitable external clocks are offered. Writing to SPI_DATA sets
SPI_ST_TXFULL, which will again be cleared when the data word was put to the shift register. If SPI_ST_TXRUNNING was clear when SPI_DATA was written to, data can immediately
be transferred to the shift register and SPI_ST_TXFULL won’t be set at all.
When SPI_ST_RXFULL is set, SPI_DATA may be read. Bits SPI_CF_DLEN:0 contain the
received data. The rest of the 16 register bits are set to 0.
PR
SPIx_FSYNC is meant for generation of potentially complex synchronization signals, including
several SSI variants as well as a simple enough automatic chip select signal. SPIx_FSYNC is
only valid in master mode.
If a write to SPIx_DATA is preceded by a write to SPIx_FSYNC, the data written to SPIx_FSYNC
is sent to FSYNC pin with the same synchronization as the data written to SPIx_DATA is written
to MOSI. When SPI_ST_TXRUNNING is clear, the value of SPI_CF_FSIDLE is set to FSYNC
pin.
If SPIx_DATA is written to without priorly writing to SPIx_FSYNC, the last value written to
SPIx_FSYNC is sent.
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VS1005g Datasheet
VS1005G PERIPHERALS AND REGISTERS
IN
AR
Y
11
SPIx_FSYNC is double-buffered like SPIx_DATA.
PR
EL
IM
The SPI block has one interrupt. Interrupt 0 request is sent when SPI_ST_BREAK is asserted,
or when SPI_ST_TXFULL or SPI_ST_TXRUNNING is cleared. This allows for sending data in
an interrupt-based routine, and turning chip select off when the device becomes idle.
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VS1005g Datasheet
11.11
Common Data Interfaces
VS1005G PERIPHERALS AND REGISTERS
IN
AR
Y
11
VS1005g has a 3 KiB data buffer which is a dedicated peripheral memory. The memory can be
configured to be used with:
• Ethernet interface
• Nand Flash Interface
• SD Card Interface
• Reed-Solomon Codecs
IM
Block diagram of the data interfaces is shown in Figure 13.
EL
Figure 13: Block diagram of data interfaces.
PR
Each peripheral can be configured to use its own address space. The DSP interface has a
read and write port with auto incrementing address register. The read operation is pipelined
and requires two reads to fill the pipeline. After that the memory can be read on each instruction
cycle. It should be noted that the memory is time multiplexed between the peripherals, with the
DSP having absolute highest priority. Because of this, some idle cycles are required during
long DSP read/write operations. As a guideline at least every 16th read cycle should be left
idle by the DSP. The DSP interface has Error Correction Code (ECC) registers for nand flash.
It uses 2D xor to protect and correct data.
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VS1005g Datasheet
Reg
0xFC66
0xFC67
Type
r
r
0xFC68
0xFC69
0xFC6A
0xFC6B
0xFC6C
r/w
r/w
r/w
r
r/w
VS1005G PERIPHERALS AND REGISTERS
IN
AR
Y
11
DSP Interface Registers for Peripheral Memory
Reset Abbrev
Description
0 ECC_LP_LOW
ECC line parity register bits [15:0]
0 ECC_CP_LP_HIGH ECC column parity bits [5:0]
and line parity bits [17:16]
0 XP_CF
Dsp interface control
0 XP_ADDR
Memory address register for dsp interface, 11 bits
0 XP_ODATA
Memory write port for dsp
0 XP_IDATA
Memory read port for dsp
0 XP_ST
Interrupt status register for data buffer peripherals
ECC_LP_LOW and ECC_CP_LP_HIGH are the error correction code data registers. They are
modified when DSPI_ODATA or DSPI_IDATA ports are accessed. The DSPI_CF_ECCENA
must be set in order to use ECC.
Name
XP_CF_ODAT
XP_CF_ECCRST
XP_CF_ECCENA
XP_CF_WRBUF
XP_CF_RDBUF
XP_CF Bits
Bits Description
15:12 RS_ODATA mux control
9 ECC reset
8 ECC enable
1 Data buffer write enable
0 Data buffer read enable
IM
XP_CF_ODAT is a control register for RS_ODATA register.
XP_CF_ECCRST and XP_CF_ECCENA control the ECC unit. XP_CF_ECCRST reset the unit
when set. THe register is reset automatically after one clock cycle.
XP_CF_ECCENA register enables the ECC calculation. column parity (CP) and line parity (LP)
registers are modified when data is read from XP_ODATA or written to XP_IDATA register and
XP_CF_ECCENA is set.
EL
XP_CF_WRBUF and XP_CF_RDBUF enable the dsp access to peripheral data buffer. When
either register is set the XP_ADDR is incremented on each memory access and data is read
(XP_ODATA) or written (XP_IDATA) to memory.
Data interfaces can generate only one interrupt request for the DSP. The interrupt source is
stored in interrupt status register.
PR
XP_ST register is used to track the interrupt source of the peripherals using data buffer memory.
The interrupt requests are reset when the register bit is set by software. Interrupt sources are
listed in the table.
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VS1005g Datasheet
Name
XP_ST_INT_ENA
XP_ST_ETXRB_FULL_INT
XP_ST_ETXRB_HALF_INT
XP_ST_ERXRB_FULL_INT
XP_ST_ERXRB_HALF_INT
XP_ST_SPIERR_INT
XP_ST_RSEC_RDY_INT
XP_ST_RSDEC_RDY_INT
XP_ST_RSENC_RDY_INT
XP_ST_SD_INT
XP_ST_NF_INT
XP_ST_SPI_STOP_INT
XP_ST_SPI_START_INT
XP_ST_ETHRX_INT
XP_ST_ETHTX_INT
VS1005G PERIPHERALS AND REGISTERS
IN
AR
Y
11
XP_ST Bits
Description
Interrupt enable for data buffer peripherals
Ethernet transmit ring buffer full
Ethernet transmit ring buffer half full
Ethernet receive ring buffer emptyl
Ethernet receive ring buffer half empty
SPI slave error, transfer was interrupted middle of byte
8 Reed-Solomon decode error correction data
ready
7 Reed-Solomon decode ready
6 Reed-Solomon encode ready
5 SD card interface ready interrupt
4 Nand flash interface ready interrupt
3 SPI slave stop interrupt, chip select to inactive
state
2 SPI slave start interrupt, chip select to active
state
1 Ethernet receiver new packet interrupt
0 Ethernet transmitter ready interrupt
Bits
14
13
12
11
10
9
IM
XP_ST_INT_ENA is the peripheral interrupt enable. When set the interrupt requests are forwarded to interrupt controller. Interrupt requests in XP_ST register are modified regardless the
value of XP_ST_INT_ENA.
PR
EL
The SPI slave error register (XP_ST_SPIERR_INT) is a read only register which is reset when
SPI start is detected in the SPI bus and set if data transfer was interrupted in the middle of a
byte.
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VS1005g Datasheet
11.11.1
Ethernet Controller
VS1005G PERIPHERALS AND REGISTERS
IN
AR
Y
11
VS1005g has a controller for interfacing 10base-t ethernet bus. Additionally this peripheral can
be configured to SPI slave mode to be used with VLSI Solution’s RF link. In this mode the
SPI1 pins are used and they must be configured to peripheral mode with GPIO1_MODE[7:4]
registers.
Reg
0xFC60
0xFC61
0xFC62
0xFC63
0xFC64
0xFC65
Type
r/w
r/w
r/w
r/w
r/w
r
Ethernet Controller Registers
Abbrev
Description
ETH_TXLEN
Ethernet transmitter packet length
ETH_TXPTR
Ethernet transmitter memory address pointer
ETH_RXLEN
Ethernet receiver packet length
ETH_RXPTR
Ethernet receiver memory address pointer
ETH_RBUF
Ethernet transmitter/receiver ring buffer configuration
ETH_RXADDR Ethernet receiver memory address, 11 bits
Reset
0
0
0
0
0
0
ETH_TXLEN Bits
Bits Description
15 SPI slave synhronization configuration
14 Set big endian SPI slave receiver bit order
13 Set big endian SPI slave transmitter bit order
11:0 Ethernet transmitter packet size in bytes
IM
Name
ETH_TXLEN_META
ETH_TXLEN_RX_BE
ETH_TXLEN_TX_BE
ETH_TXLEN_LEN[11:0]
ETH_TXLEN_META register enables the use of higher bit rate. If the SPI slave and master are
using same clock source this register can be set. The SPI slave synchronization is then made
simpler. It is recommended to keep this register in reset. In ethernet mode this register is don’t
care.
EL
ETH_TXLEN_RX_BE and ETH_TXLEN_TX_BE are used to reverse bit order in SPI mode.
When registers are reset the bits are sent/received lsb bit first (i.e. from 0 to 7). When registers
are set the bits are sent/received msb bit first (i.e. from 7 to 0). In ethernet mode these registers
are don’t care.
ETH_TXLEN[11:0] register is loaded with packet length (in bytes) before the transmitter is enabled. When transmitter is enabled this register is decremented after a byte has been sent.
When the length register reached zero the transmitter returns to idle state. In SPI slave mode
this register is zero.
PR
Name
ETH_TXPTR_SPI_TX_ENA
ETH_TXPTR_SPI_RX_ENA
ETH_TXPTR_BUSY
ETH_TXPTR_START
ETH_TXPTR_PTR[10:0]
ETH_TXPTR Bits
Bits Description
15 SPI slave transmitter enable
14 SPI slave receiver enable
13 Ethernet transmitter busy
12 Ethernet transmitter start-to-send packet
10:0 Ethernet transmitter memory address pointer
ETH_TXPTR_SPI_TX_ENA and ETH_TXPTR_SPI_RX_ENA are the SPI slave mode enables
for transmitter and receiver. SPI start and stop interrupts are generated even though these regVersion: 0.52, 2012-11-07
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VS1005g Datasheet
VS1005G PERIPHERALS AND REGISTERS
IN
AR
Y
11
isters would be reset. It should be noted that when ETH_TXPTR_SPIRE is set the transmitter
address pointer must be initialized to data start address. In ethernet mode these registers are
don’t care.
ETH_TXPTR_BUSY is the ethernet transmitter busy flag. In SPI slave mode this flag is set if
transmitter is enabled and chip select line is in its active state (low).
ETH_TXPTR_START enables the ethernet transmitter. When this register is set the transmitter
changes from idle to busy state and sends ETH_TXLEN[11:0] number of bytes. Before this
register is set the packet data must be stored in peripheral memory and tx address pointer and
tx packet length registers must be configured. In SPI slave mode this register is zero.
ETH_TXPTR[10:0] is the ethernet/SPI transmitter memory address pointer. This pointer is
loaded with packet start address before transmitter is enabled.
ETH_RXLEN Bits
Bits Description
15 Peripheral mode select: Ethernet (0) / SPI
slave mode (1)
ETH_RXLEN_SPIINVCLK 14 SPI slave transmitter clock configuration
ETH_RXLEN_LEN[11:0] 11:0 Ethernet receiver packet size in bytes
Name
ETH_RXLEN_SPIMODE
IM
ETH_RXLEN_SPIMODE register configures the peripheral to ethernet mode or to SPI slave
mode. When register is reset (default state) the peripheral is in ethernet mode.
ETH_RXLEN_SPIINTCLK selects SPI slave transmitter clock edge. When register is reset the
SPI out data is written after falling SPI clock edge. When register is set the data is written after
rise edge. With high SPI bit rates (SPI clock > core clock / 6) the rise edge should be used. It
should be noted that the SPI slave clock can not exceed core clock / 4 at any time. In ethernet
mode this register is don’t care.
EL
ETH_RXLEN_LEN[11:0] register is loaded with ethernet/SPI receiver packet length counter
when receiver returns from busy state to idle (packet end). Packet length is given in bytes.
Name
ETH_RXPTR_CRCOK
ETH_RXPTR_NEWPKT
ETH_RXPTR_BUSY
ETH_RXPTR_ENA
ETH_RXPTR_PTR[10:0]
ETH_RXPTR Bits
Bits Description
15 Ethernet receiver crc status flag
14 Ethernet receiver packet received flag
13 Ethernet receiver busy
12 Ethernet receiver enable
10:0 Ethernet receiver memory address pointer
PR
ETH_RXPTR_CRCOK is the received packet crc status flag. Receiver sets the flag if the
received packet crc was correct. Flag must be reset by user (write ’1’). In SPI slave mode the
crc flag is set if last four bytes were 0xFF.
ETH_RXPTR_NEWPKT is the flag for incoming packet. The receiver sets the flag when it
changes its state from busy to idle. Flag must be reset by user (write ’1’). In spi mode this
register is zero.
ETH_RXPTR_BUSY is a busy flag for ethernet/SPI slave receiver. This receiver sets the flag
when changes its state from idle to busy state.
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VS1005g Datasheet
VS1005G PERIPHERALS AND REGISTERS
IN
AR
Y
11
ETH_RXPTR_ENA register places the ethernet receiver on hold for incoming packet when set.
When packet start is detected the receiver switches from idle to busy state. Receiver address
pointer must be configured before this register is set. In SPI slave mode this register controls
the SPI receiver enable. When register is set the SPI transmit end automatically enables the
SPI receiver.
ETH_RXPTR[10:0] is the ethernet/SPI receiver memory pointer. This pointer is loaded with
packet start address before receiver is enabled. When receiver changes it state from idle to
busy this register is loaded to memory write address pointer register.
Name
ETH_RBUF_CLKCF
ETH_RBUF_TXENA
ETH_RBUF_TXCF
ETH_RBUF_RXENA
ETH_RBUF_RXCF
ETH_RBUF Bits
Bits Description
9:8 Reserved, use “00”
7 Ethernet receiver ring buffer enable
6:4 Ethernet receiver ring buffer configuration
3 Ethernet transmitter ring buffer enable
2:0 Ethernet transmitter ring buffer configuration
ETH_RBUF_TXENA and ETH_RBUF_RXENA are ring buffer enable registers for transmitters
and receiver respectively. Ring buffer size is defined with ETH_RBUF_TXCF and ETH_RBUF_RXCF
registers as explained in next table.
IM
CF register
111-100
011
010
001
000
Ring buffer configuration bits
Ring buffer size Locked bits Incremented bits
1024 words
[10]
[9:0]
512 words
[10:9]
[8:0]
256 words
[10:8]
[7:0]
128 words
[10:7]
[6:0]
64 words
[10:6]
[5:0]
EL
ETH_RXADDR register is the current memory address were receiver stores data. This register
is loaded with ETH_RXPTR[10:0] when new packet start is detected in bus.
PR
Ethernet controller generates an interrupt each time a new packet is received or transmitter
has finished sending a packet. When ring buffers are used the interrupt is given also when ring
buffer address pointer has reached middle or end of the configured buffer size.
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VS1005g Datasheet
11.11.2
Reed-Solomon Codec
VS1005G PERIPHERALS AND REGISTERS
IN
AR
Y
11
VS1005g has a Reed-Solomon encoder and decoder for error correction e.g. from nand flash
data. Reed Solomon is a forward error correction code which adds redundancy at the end of
the message. The code word length n is defined as k + 2*t where k is the maximum number of
data symbols (pay load) and 2*t is the number of parity check symbols. The algorithm can fix
up to t symbols from code word and detect 2*t errors.
The Reed Solomon codec in VS1005g supports two different code lengths
• NF: n = 1023 symbols and t = 4. This makes 2*t = 8 10-bit parity check symbols. The
data symbols are interpreted as 8-bit symbols where the two msb bits are always zero.
• RF: n = 255 symbols and t = 16. This makes 2*t = 32 8-bit parity check symbols. Also the
data symbols are 8 bits wide.
Codec
NF
RF
Data Symbols (k)
≤ 1015
≤ 223
VS1005g Reed Solomon Codecs
Symbol Width Check Symbols (2*t)
8 / 10 bits
8 (10 bits)
8 bits
32 (8 bits)
Typical Code Width (n)
518 + 8
223 + 32
IM
The NF codec is used for multi level cell (MLC) flash error detection and correction. Therefore
the symbol width is limited to 8 bits for data symbols. The R-S encoder generates eight 10-bit
parity check symbols (80 bits) which are stored with 518-byte user data. These check symbols
are organized as 10 8-bit symbols which are stored to memory chip. The code word would
therefore be a total of 528 bytes long.
NF Reed Solomon encoder check symbols are outputed as five 16-bit words (80 bits total).
These check symbol words can be read from RS_DATA port when the RS encoder has finished
calculation. The check symbol organization is as listed in the table.
PR
EL
NF Reed Solomon Encoder Check Symbol Organization
Check Symbol
RS Encoder output word bits
0
word[0](1:0)
& word[0](15:8)
1
word[1](11:8) & word[0](7:2)
2
word[1](5:0)
& word[1](15:12)
3
word[2](15:8) & word[1](7:6)
4
word[3](9:8)
& word[2](7:0)
5
word[3](3:0)
& word[3](15:10)
6
word[4](13:8) & word[3](7:4)
7
word[4](7:0)
& word[4](15:14)
RF Reed Solomon encoder outputs the 8-bit check symbols as 16 16-bit words. Here the 32
8-bit symbols are organized in big endian format. This codec provides a means to detect 32
symbo errors and to fix 16 symbols.
The NF Reed Solomon decoder makes it possible to detect 8 symbol errors and to fix a maximum of 4 symbols. The decoder first reads the data symbols and then the parity check words.
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VS1005G PERIPHERALS AND REGISTERS
IN
AR
Y
11
As the check symbols are 10 bits they must be organized into memory in this format before
check symbol decoding is started. The encoder expects them to be in LSB bits (9:0) in consecutive memory locations. The decoder returns the number of total errors and the number
of errors in data symbols. Only the data symbol errors are returned as location / magnitude
pairs when Reed Solomon decoder has finished the calculation. These errors must be fixed
by software to the code word by XORing magnitude to the error location data. The location /
magnitude pairs are stored in memory.
Reed Solomon codecs use a shared interrupt source INT_XPERIP. The source of interrupt is
stored in register XP_ST where the decoder has one bit for Reed Solomon encoder and two
bits for Reed Solomon decoder. To enable the interrupts the XP_ST_INT_ENA must be set.
Reed Solomon interrupts in XP_ST Register
Name
Bits Description
XP_ST_INT_ENA
14 Interrupt enable, active high
XP_ST_RSEC_RDY
8 Reed-Solomon decode error correction ready
XP_ST_RSDEC_RDY
7 Reed-Solomon decode ready
XP_ST_RSENC_RDY
6 Reed-Solomon encode ready
Reset
0
0
0
0
0
0
0
Reed-Solomon Registers
Abbrev
Description
RS_ST
Reed-Solomon status for encoder and decoder
RS_CF
Reed-Solomon control and configuration register
RS_EPTR Reed-Solomon encoder memory pointer
RS_ELEN Reed-Solomon encoder data length in bytes
RS_DPTR Reed-Solomon decoder memory pointer
RS_DLEN Reed-Solomon decoder data length
RS_DATA Data read port
IM
Type
r
r/w
r/w
r/w
r/w
r/w
r
RS_ST Bits
Description
Number of errors in decoded code word
Decoder fix algorithm found too many errors
Decoder fix algorithm completed
Decoder fix algorithm is calculating magnitude and location pairs
Decoder fix algorithm part 1 completed
Code word errors can not be fixed
Code word has errors
Code word does not contain errors
EL
Reg
0xFC70
0xFC71
0xFC72
0xFC73
0xFC74
0xFC75
0xFC76
Bits
12:8
6
5
4
RS_ST_DFRDY1
RS_ST_DFAIL
RS_ST_DERR
RS_ST_DOK
3
2
1
0
PR
Name
RS_ST_DNERR
RS_ST_DFFAIL
RS_ST_DFRDY2
RS_ST_DFBUSY
RS_ST_DNERR is the error count register. When R-S decoder fix algorithm has completed the
number of location/magnitude pairs is stored to this register.
RS_ST_DFFAIL register is set when the decoder algorithm could not fix all the errors in code
word.
RS_ST_DFRDY2, RS_ST_DFBUSY and RS_ST_DFRDY1 are monitoring the status of R-S
Version: 0.52, 2012-11-07
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VS1005G PERIPHERALS AND REGISTERS
IN
AR
Y
11
decoder. When both ready register are set the error correcting agorithm has completed and an
interrupt request is generated.
RS_ST_DFAIL is set when a fatal error was encountered. It is not possible to restore code
word. RS_ST_DFAIL is modified after code end was given (RS_CF_DEND set by user)
RS_ST_DERR flag is set if code word has errors. RS_ST_DERR is modified after code end
was given (RS_CF_DEND was set by user). If this flag was set the error correcting algorithm
is started automatically.
RS_ST_DOK flag is set if code word does not has errors. RS_ST_DOK is modified after code
end was given (RS_CF_DEND was set by user).
Bits
13
12
11
10
9
8
7:4
3
2
1
0
RS_CF Bits
Description
R-S decoder nand flash mode select
R-S decoder 10-bit input data
R-S decoder code end
R-S decoder code start
R-S decoder enable
R-S decoder mode control
R-S encoder parity select for RS_OPORT
R-S encoder nand flash mode select
R-S encoder code start
R-S encoder enable
R-S encoder mode control
IM
Name
RS_CF_DNF
RS_CF_D10B
RS_CF_DEND
RS_CF_DSTR
RS_CF_DENA
RS_CF_DMODE
RS_CF_SEL[3:0]
RS_CF_ENF
RS_CF_ESTR
RS_CF_EENA
RS_CF_EMODE
RS_CF_DNF selects between two data input modes. When set the decoder uses nand flash
input data register as input. When reset the data is fetched from peripheral memory.
EL
RS_CF_D10B selects between 10-bit and 8-bit input modes. Normally the symbols are 8-bit
and two MSB zero bits are added. When RS_CF_D10B is set the symbols are fetched from
peripheral memory as 10-bit and the two MSB bits are not zeroed. In 10-bit mode the data
is in bits [9:0] and it is fetched from memory in word format. This bit is set when NF parity
check symbols are decoded. When decoding the 10-bit check symbols the decoder does not
generate RS decoder interrupt XP_ST_RSDEC_RDY.
PR
RS_CF_DEND is a code end register for decoder. When this register is set the decoder stops
decoding current code word and the status can be read from RS_ST register. If code word
contained symbol errors the symbol error correction algorithm is started automatically. The
location and magnitude pairs needed to fix corrupted symbols are placed in memory from
RS_DPTR address onwards. The RS_DPTR value is not incremented during calculation and
it holds the start address of the location / magnitude pairs in memory. The progress of the
calculation is visible in RS_ST register. When the location / magnitude pairs are calculated an
XP_ST_RSEC_RDY interrupt is generated. RS_CF_DEND register is automatically reset after
one clock cycle.
RS_CF_DSTR initializes the R-S decoder i.e. starts a new decoding sequence. This register
is reset automatically when first symbol is decoded.
RS_CF_DENA enables the R-S decoder. When RS_CF_DNF is set the decoder is decoding
symbols as they are read from nand flash. If RS_CF_DNF is reset the decoder starts reading
Version: 0.52, 2012-11-07
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VS1005G PERIPHERALS AND REGISTERS
IN
AR
Y
11
symbols from peripheral memory from address RS_DPTR onwards. The symbols are fetched
from memory as 8-bit or 10-bit symbols but are always forwarded to decoder as 10-bit symbols
where bits [9:8] are zero if RS_CF_D10B is reset. The decoder decodes RS_DLEN number
of symbols and then reset RS_CF_DENA. Also an XP_ST_RSDEC_RDY interrupt request is
generated.
RS_CF_DMODE register should be set when decoding nand flash data (10-bit NF). When reset
the 8-bit code is used (RF).
RS_CF_SEL is used to select encoded parity symbols. The selected parity symbol can be read
from RS_DATA register.
RS_CF_ENF selects between two data input modes. When set the encoder uses nand flash
output data register as input. When reset the data is fetched from peripheral memory.
RS_CF_ESTR initializes the R-S encoder i.e. starts a new encoding sequence. This register
is reset automatically when first symbol is encoded. The encoder does not need encode-end
register as the check symbols are updated on-the-fly and are readable from the RS_DATA port
after the current operation has finished.
IM
RS_CF_EENA enables the R-S encoder. When RS_CF_ENF is set the encoder is encoding
symbols as they are written to nand flash. If RS_CF_ENF is reset the encoder starts reading
symbols from peripheral memory from address RS_EPTR onwards. The symbols are fetched
from memory as 8-bit data but are forwarded to encoder as 10-bit symbols where bits [9:8] are
always zero. The big endian byte order is expected. The encoder encodes RS_ELEN number
of symbols and then reset RS_CF_EENA. Also an XP_ST_RSENC_RDY interrupt request is
generated.
RS_CF_EMODE register should be set when encoding nand flash data (10-bit). When reset
the 8-bit code is used (RF).
EL
RS_EPTR and RS_DPTR are the 11-bit address registers for Reed-Solomon encoder and
decoder. The start address of data is written to these registers prior the encode or decode is
enabled. The big endian byte order is expected.
RS_ELEN and RS_DLEN are the code length registers for the encoder and decoder. The
length is given as the number of 8-bit symbols. For decoder the symbols can also be 10-bit
parity check symbols.
RS_DATA is a data read port for several data registers.
PR
XP_CF[15:12] register
1111-1100
1011
1010-0100
0011
0010
0001
0000
Version: 0.52, 2012-11-07
RS_OPORT Mux Control Bits
Mux input
Reserved
R-S decoder total errors (data + check symbols), 5 bits
Reserved
R-S decoder CSF index, 10 bits
R-S decoder BM index, 9 bits
R-S decoder syndrome index, 10 bits
R-S encoder parity word as selected with RS_CF[7:4], 16 bits
74
VS1005g Datasheet
11.11.3
Nand Flash Interface
Reg
0xFC77
0xFC78
0xFC79
0xFC7A
Type
r/w
r/w
r/w
r/w
VS1005G PERIPHERALS AND REGISTERS
IN
AR
Y
11
Nand Flash Controller Registers
Reset Abbrev
Description
0 NF_CF
Nand flash configuration register
0 NF_CTRL Nand flash control register
0 NF_PTR
Nand flash memory pointer
0 NF_LEN
Nand flash data length register (bytes)
Name
NF_CF_SCLK_INV
NF_CF_SLAVE
NF_CF_FLT_BUS
NF_CF_INT_ENA
NF_CF_WAITSTATES
Bits
9
8
7
6
5:0
NF_CF Bits
Description
Slave mode clock active edge select
Slave mode enable
Nand flash output bus float enable
Nand flash interface interrupt enable
Nand flash interface clock configuration
NF_CF_SCLK_INV selects slave mode active clock edge. If set the data bus is read at rising
edge of ready/busy line, when reset at falling edge.
IM
NF_CF_SLAVE configures the nand flash interface to slave input mode. In slave mode the nand
flash interface reads data from 8-bit bus and stores it to memory. The clock is the ready/bysy
input.
NF_CF_FLT_BUS leaves the data output bus (flash input bus) floating when set. When reset
the bus is driven to low or high state.
NF_CF_INT_ENA enables the nand flash interrupt request when set.
NF_CF_WAITSTATES configures the length of nand flash read enable and write enable pulses.
The cycle time is 2 x (NF_CONF_WS + 1) dsp clock cycles.
NF_CTRL Bits
Description
Status of nand flash ready line
Set to 0
Read (1) or write (0) select
Start nand flash read or write
Use peripheral memory
EL
Name
NF_CTRL_RDY
reserved
NF_CTRL_READSEL
NF_CTRL_ENA
NF_CTRL_USEPERIP
Bits
4
3
2
1
0
PR
NF_CTRL_RDY register is monitoring the current state of nand flash ready/busy line. The line
has pull-up and when it is in its low state the flash chip is busy.
NF_CTRL_READSEL is a read or write select. When this register is set the operation is a nand
flash read. When reset the nand flash interface writes to flash.
NF_CTRL_ENA starts nand flash read or write when set. When all bytes are transfered this
register is reset and an interrupt request is generated.
NF_CTRL_USEPERIP configures nand flash interface to use peripheral memory when set. If
NF_CTRL_USEPERIP is reset when nand flash interface is enabled, the data is read from
Version: 0.52, 2012-11-07
75
VS1005g Datasheet
VS1005G PERIPHERALS AND REGISTERS
IN
AR
Y
11
XP_IDATA register or written to XP_ODATA register. This is a one byte transaction and big
endian format is used.
Name
NF_PTR_RENA
NF_PTR_RCF
reserved
NF_PTR_PTR[10:0]
Bits
15
14:12
11
10:0
NF_PTR Bits
Description
Ring buffer enable for slave mode
Ring buffer configuration for slave mode
Set to 0
Nand flash memory pointer
NF_PTR[10:0] is the memory pointer register.
NF_PTR_RENA and NF_PTR_RCF configure a ring buffer for slave mode. In ring buffer mode
only the lower address bits are modified and higher bits are locked. E.g. when 512 word buffer
size is used the ring buffer uses memory addresses 0 - 511 when NF_PTR[10:9] bits are 0b00,
addresses 512-1023 when bits are 0b10 and so on.
Ring buffer configuration bits
Ring buffer size Locked bits Incremented bits
1024 words
[10]
[9:0]
512 words
[10:9]
[8:0]
256 words
[10:8]
[7:0]
128 words
[10:7]
[6:0]
64 words
[10:6]
[5:0]
IM
CF register
111-100
011
010
001
000
Ring buffer mode generates interrupt in the mid and end addresses of the buffer.
PR
EL
NF_LEN defines the number of bytes that are read from or written to nand flash. The length is
given in bytes. In read and write operations the data uses big endian format, i.e. the MSB part
is transmitted first.
Version: 0.52, 2012-11-07
76
VS1005g Datasheet
11.11.4
SD Card Interface
VS1005G PERIPHERALS AND REGISTERS
IN
AR
Y
11
VS1005g has a SD card interface which supports 1-bit and 4-bit data bus.
Reg
0xFC7C
0xFC7D
0xFC7E
0xFC7F
Type
r/w
r/w
r/w
r/w
SD Card Interface Registers
Reset Abbrev
Description
0 SD_PTR SD card memory address pointer
0 SD_LEN SD card data length, in bytes
0 SD_CF
SD card configuration register
0 SD_ST
SD card status register
SD_PTR is the 11-bit memory pointer register.
SD_LEN defines the number of bytes that are read from or written to SD card. The length is
given in bytes.
Bits
12
11
10
7
6
5
4
3
2
1
0
SD_CF Bits
Description
Do not send crc (continued operation)
Do not reset crc register (continued operation)
Use 4-bit data bus mode
Start SD card transfer
Read (1) or write (0) select
Command or data transfer select
Skip data start bit (continued operation)
Do not add data stop bit (continued operation)
Enable crc16 calculation during write
Enable crc7 calculation during write
Poll for start bit when read
IM
Name
SD_CF_NOCRCTX
SD_CF_NOCRCRST
SD_CF_4BIT
SD_CF_ENA
SD_CF_RDWRX
SD_CF_CMDDATX
SD_CF_NOSTARTB
SD_CF_NOSTOPB
SD_CF_CRC16
SD_CF_CRC7
SD_CF_POLL
SD_CF_NOCRCTX makes the interface to skip crc transfer.
EL
SD_CF_NOCRCRST makes the interface to continues crc calculation from previous transfer.
SD_CF_4BIT forces the interface to use 4-bit data transfer instead of 1-bit if set.
SD_CF_ENA start SD card read or write transfer when set.
SD_CF_RDWRX register selects between read and write transfers.
SD_CF_CMDDATX register selects between command and data transfers.
PR
SD_CF_NOSTARTB register forces the interface to skip start bit when set.
SD_CF_NOSTOPB register forces the interface to skip stop bit when set.
SD_CF_CRC16 and SD_CF_CRC7 enable the crc calculation. Crc is send automatically if
SD_CF_NOCRCTX is reset.
SD_CF_POLL forces the SD card interface to search for start bit when reading command response or data. If start bit is not found during 256 SD clock cycles the operation is cancelled
and SD_ST_NOSTR error flag is set.
Version: 0.52, 2012-11-07
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VS1005g Datasheet
Name
SD_ST_WAITSTATES
SD_ST_REPEAT
Reserved
SD_ST_CMDBRK
SD_ST_DAT0
SD_ST_NOSTOPB
SD_ST_CRC16
SD_ST_CRC7
SD_ST_NOSTARTB
Bits
12:8
7
6
5
4
3
2
1
0
VS1005G PERIPHERALS AND REGISTERS
IN
AR
Y
11
SD_ST Bits
Description
SD card clock configuration
Repeat mode enable
Use ’0’
cmd response during data transfer
SD card dat0 bus state
data stop bit missing error
crc16 error when reading data
crc7 error when reading command response
timeout error when reading, no start bit
SD_ST_WAITSTATES configures the length of SD card clock cycle. The cycle time is 2 x
(SD_ST_WAITSTATES + 1) dsp clock cycles.
SD_ST_RPM register sets the interface into a pattern generation mode. In this mode the SD
data lines repeat a 512 byte buffer continuously. The buffer’s location in memory can be set
with registers SD_PTR[10:8]. In this mode all other SD_ST and SD_CF registers should be
reset. The SD_ST_WS and SD_CF_4BIT have their usual meaning.
SD_ST_CMDBRK is set if a cmd start bit is found during data transfer. This register is reset at
the start of each SD card op.
IM
SD_ST_DAT0 register samples the SD cards data 0 line.
SD_ST_NOSTOPB is set if stop bit was not found when reading data from SD card.
SD_ST_CRC16 is set if crc16 error was detected when reading data from SD card.
SD_ST_CRC7 is set if command response had a crc7 error.
PR
EL
SD_ST_NOSTARTB is set if start bit was not found during 256 SD clocks.
Version: 0.52, 2012-11-07
78
VS1005g Datasheet
11.12
USB Peripheral
VS1005G PERIPHERALS AND REGISTERS
IN
AR
Y
11
VS1005g has a Full Speed / Hi-Speed Universal Serial Bus. The Universal Serial Bus Controller
handles USB 2.0 data traffic at 12 Mbit/s signalling speed and high speed USB data at 480
Mbit/s. The devices support a maximum of four endpoints.
The USB implementation is based on transceiver macromodel interface (UTMI). Block diagram
of usb modules is shown in Figure 14
IM
Simplified UTM module diagram is shown in Figure 15.
Figure 14: VS1005g USB block diagram.
The USB device can handle traffic for the control endpoint (0) plus three input and output
endpoints. Bulk, Isochronous and Interrupt transfer modes are supported at Full Speed (12
Mbit/s). The maximum packet size is 1023 bytes.
PR
EL
4 kilobytes of Y data memory is used as the USB packet buffer: 2 KiB for incoming packets
(X:0xF400-0xF7FF) and 2 KiB for outgoing packets (X:0xF800-0xFBFF). The input buffer is a
ring buffer with incoming packets consisting of a status word and n data words. The output
buffer has 16 possible start locations for outgoing packets at 128-byte (64-address) intervals
(note that all data addressing in VS1005g is based on 16-bit words).
Version: 0.52, 2012-11-07
79
VS1005g Datasheet
VS1005G PERIPHERALS AND REGISTERS
IN
AR
Y
11
11.12.1
IM
Figure 15: VS1005g UTM functional block diagram.
USB Peripheral Registers
PR
EL
Address
0xFC80
0xFC81
0xFC82
0xFC83
0xFC84
0xFC85
0xFC86
0xFC87
0xFC88
0xFC89
0xFC8A
0xFC8B
0xFC90
0xFC91
0xFC92
0xFC93
Universal Serial Bus Controller Registers
Register
Function
USB_CF
USB Device Config
USB_CTRL
USB Device Control
USB_ST
USB Device Status
USB_RDPTR[9:0] Receive buffer read pointer
USB_WRPTR[9:0] Receive buffer write pointer
USB_UTMIR
UTM read control
USB_UTMIW
UTM write control
USB_HOST
Host control
USB_EP_SEND0 EP0IN Transmittable Packet Info
USB_EP_SEND1 EP1IN Transmittable Packet Info
USB_EP_SEND2 EP2IN Transmittable Packet Info
USB_EP_SEND3 EP3IN Transmittable Packet Info
USB_EP_ST0
Flags for endpoints EP0IN and EP0OUT
USB_EP_ST1
Flags for endpoints EP1IN and EP1OUT
USB_EP_ST2
Flags for endpoints EP2IN and EP2OUT
USB_EP_ST3
Flags for endpoints EP3IN and EP3OUT
Version: 0.52, 2012-11-07
80
VS1005g Datasheet
Name
USB_CF_RST
USB_CF_HDTOG
USB_CF_DDTOG
USB_CF_NOHIGHSPEED
USB_CF_DTOGERR
USB_CF_MASTER
USB_CF_RSTUSB
USB_CF_USBENA
USB_CF_USBADDR
USB_CF Bits
Description
Reset Active
Reset value of host data toggle (set to 0)
Reset value of device data toggle (set to 0)
Reserved, use ’0’
Set to disable high speed functionality.
Data Toggle error control (set to 0)
Set for master/host mode
Reset receiver (set to 0)
Enable USB
Current USB address
USB_CTRL Bits
Bits Description
15 Interrupt mask for bus reset
14 Interrupt mask for start-of-frame
13 Interrupt mask for receive data
11 Interrupt mask for transmitter empty (idle)
10 Interrupt mask for NAK packet sent to host
9 Interrupt mask for bus timeout
8 Interrupt mask for suspend request
7 Interrupt mask for resume request
6 Interrupt mask for start of bus reset
5 Interrupt mask for usb disconnected
0 USB Configured. 0→1 transition loads dtogghost and dtogg-device
IM
Name
USB_CTRL_BUS_RESET
USB_CTRL_SOF
USB_CTRL_RX
USB_CTRL_TX
USB_CTRL_NAK
USB_CTRL_TIME
USB_CTRL_SUSP
USB_CTRL_RESM
USB_CTRL_BR_START
USB_CTRL_DCON
USB_CTRL_CF
Bits
15
14
13
12
11
10
9
8
7
6:0
VS1005G PERIPHERALS AND REGISTERS
IN
AR
Y
11
Bits
15
14
13
12
11
10
9
8
7
6
5
4
3:0
PR
EL
Name
USB_ST_BRST
USB_ST_SOF
USB_ST_RX
USB_ST_TX_HLD
USB_ST_TX_EMPTY
USB_ST_NAK
USB_ST_TIME
USB_ST_SUSPI
USB_ST_RES
USB_ST_MTERR
USB_ST_STAT
USB_ST_SPD
USB_ST_PID
USB_ST Bits
Description
Bus reset occurred
Start-of-frame
Receive data
Transmitter holding register empty
Transmitter empty (idle)
NAK packet sent to host
Bus time out
Device suspended
Device resumed
Bus reset start / USB master toggle error
Device disconnected / Status setup
USB speed
Packet id / Endpoint number of last rx/tx transaction
The USB_ST_PID can be used mainly for debugging purposes.
Version: 0.52, 2012-11-07
81
VS1005g Datasheet
Name
USB_RDPTR
VS1005G PERIPHERALS AND REGISTERS
IN
AR
Y
11
USB_RDPTR Bits
Bits Description
9:0 Packet Read Pointer
This buffer marks the index position of the last word that the DSP has successfully read from
the receive packet buffer. DSP should control this register and update the position after each
packet it has read from the receive buffer. After reset this register is zero.
Name
USB_WRPTR
USB_WRPTR Bits
Bits Description
9:0 Packet Write Pointer
After a packet has been received from the PC, the USB hardware updates this pointer to the
receive buffer memory. USB_WRPTR is index location of the next free word location in the USB
receive buffer. When USB_RDPTR equals to USB_WRPTR, the packet input buffer is empty.
After reset this register is zero.
IM
Name
USB_UTMIR_LSTATE
USB_UTMIR_CNT
USB_UTMIR Bits
Bits Description
15:14 USB bus line state
13:0 USB frame counter, master mode
USB_UTMIW Bits
Bits Description
15 Bus override
14 Reserved, use ’0’
USB_UTMIW_J
6 Drive chirp J
USB_UTMIW_HSHK
5 Reset handshake
USB_UTMIW_K
4 Drive chirp K
USB_UTMIW_RCVSEL
3 Receiver select
USB_UTMIW_TERMSEL
2 Termination select
USB_UTMIW_OPMOD
1:0 Operation mode
EL
Name
USB_UTMIW_ORIDE
PR
Name
USB_HOST_PID
USB_HOST_ISOC
USB_HOST_TX
Name
USB_EP_SEND_TXR
USB_EP_SEND_ADDR
USB_EP_SEND_LEN
Version: 0.52, 2012-11-07
USB_HOST Bits
Bits Description
15:12 USB host packet id
11 Disable NAK packet send
9 USB host send packet
USB_EP_SENDn Bits
Bits Description
15 Packet ready for transmission
13:10 Starting location of packet
9:0 Length of packet in bytes (0..1023)
82
VS1005g Datasheet
VS1005G PERIPHERALS AND REGISTERS
IN
AR
Y
11
When the DSP has written a packet into the transmit buffer, that is ready to be transmitted
to the PC by an endpoint, the DSP signals the USB firmware by setting the value of the
USB_EP_SENDn register of the endpoint that should transmit the packet (USB_EP_SEND0
for endpoint 0, USB_EP_SEND1 for endpoint 1 etc).
11.12.2
IM
USB_EP_STn Bits
Name
Bits Description
EPnOUT (PC → Device) endpoint (0 .. 3) flags
USB_EP_ST_OTYP
15:14 00=bulk 01=interrupt 11=isochronous
USB_EP_ST_OENA
13 1=enabled 0=disabled
USB_EP_ST_OSTL
12 Force STALL
USB_EP_ST_OSTL_SENT
11 At least 1 STALL sent
reserved
10:8 Use ’0’
EPnIN (Device → PC) endpoint (0 .. 3) flags
USB_EP_ST_ITYP
7:6 00=bulk 01=interrupt 11=isochronous
USB_EP_ST_INT_ENA
5 1=enabled 0=disabled
USB_EP_ST_ISTL
4 Force STALL
USB_EP_ST_ISTL_SENT
3 At least 1 STALL sent
USB_EP_ST_INAKSENT
2 At least 1 NAK sent
USB_EP_ST_IXMIT_EMP
1 Transmitter empty
reserved
0 Use ’0’
USB Clocking Modes
11.12.3
EL
USB usage requires a special clock setup. The core clock must be set to 60 MHz. If only Full
Speed USB is used the 60 MHz clock can be achieved byt placing the PLL to 5x clocking mode
and using 12.000 MHz XTAL. When Hi-Speed USB is used the core clock must also be 60 MHz
but this clock is generated with a PLL which can be programmed with fractional multiplier factors. The xtal oscillator frequencies of 12.000 MHz or 12.288 MHz are recommended in this
mode.
USB Host
USB module can be configured as an USB host. In USB host mode the 1.5kOhm pull up
resistor in D+ pin is replaced with 15kOhm pull down resistors in in both the D+ and D- pins.
USB host is capable of:
PR
• Send Start of Frame (SOF) packets
• Send SETUP, IN and OUT packets
• Schedule transfers within 1ms frames
• Signal USB bus reset
• Provide USB power management
Version: 0.52, 2012-11-07
83
VS1005g Datasheet
11.13
VS1005G PERIPHERALS AND REGISTERS
IN
AR
Y
11
Interruptable General Purpose IO Ports 0-2
VS1005g has 3 general purpose IO ports that can operate either in GP mode or in perip mode.
In order to use pins as gpio the GPIOx_MODE registers must be reset (default value).
GPIO port 0, 1 and register offsets are 0xFCA0, 0xFCC0 and 0xFCE0 accordingly. GPIO port
0 and 1 are 16-bits wide and GPIO port 2 is 14-bits wide.
Reg
0
1
2
3
4
5
6
7
8
9
10
Interruptable General I/O Registers, Prefix GPIOx_
Type Reset Abbrev
Description
r/w
0
DDR
Data direction
r/w
0
ODATA
Data output
r
0
IDATA
Data input (I/O pin state)
r/w
0
INT_FALL
Falling edge interrupt enable
r/w
0
INT_RISE
Rising edge interrupt enable
r/w
0
INT_PEND
Interrupt pending source
w
0
SET_MASK
Data set (→ 1) mask
w
0
CLEAR_MASK Data clear (→ 0) mask
r/w
0
BIT_CONF
Bit engine config 0 and 1
r/w
0
BIT_ENG0
Bit engine 0 read/write
r/w
0
BIT_ENG1
Bit engine 1 read/write
IM
GPIOx_DDR register configure the directions of each of the 16 I/O pins. A bit set to 1 in the
DDR turns the corresponding I/O pin to output mode, while a bit set to 0 sets the pin to input
mode. The register is set to all zeros in reset, i.e. all pins are inputs by default. The current
state of the DDR can also be read.
GPIOx_ODATA register sets the GPIO pin high or low. Only pins that are configured as outputs
are affected.
EL
GPIOx_IDATA monitiors the current state of a pin. The actual logical levels of the I/O pins are
seen in the input data register. Note: The pin state can be read even if the pin is in peripheral
mode (i.e. GPIOx_MODE[y] is set).
GPIOx_INT_RISE and GPIOx_INT_FALL configures an interrupt trigger edge. If a bit of the
falling edge interrupt enable register (GPIOx_INT_FALL) is set to 1, a falling edge in the corresponding pin (even when configured as output) will set the corresponding bit in the interrupt
pending source register (GPIOx_INT_PEND).
If a bit of the rising edge interrupt enable register (GPIOx_INT_RISE) is set to 1, a rising edge
in the corresponding pin (even when configured as output) will set the corresponding bit in the
interrupt pending source register (GPIOx_INT_PEND).
PR
GPIOx_INT_PEND defines the source of a pending interrupt. If any of the bits in the interrupt
pending source register (GPIOx_INT_PEND) are set, an interrupt request is generated. Bits in
GPIOx_INT_PEND can be cleared by writing a 1-bit to the bit that is to be cleared.
Note: the interrupt request will remain asserted until all GPIOx_INT_PEND bits are cleared.
GPIOx_SET_MASK register can be used to mask GPIO pins high when GPIOx_ODATA register
is written. All bits that are set in the mask register also set the corresponding bit in the data
output register. Other bits retain their old values.
Version: 0.52, 2012-11-07
84
VS1005g Datasheet
VS1005G PERIPHERALS AND REGISTERS
IN
AR
Y
11
GPIOx_CLEAR_MASK register can be used to mask GPIO pins low when GPIOx_ODATA register is written. All bits that are set in the mask clear the corresponding bit in the data output
register. Other bits retain their old values.
GPIOx_BIT_CONF is a bit engine configuration register and selects a mapping between an I/O
bit and a data output/input register bit for each of the bit engine registers.
GPIOx_BIT_CONF Bits
Bits Description
15:12 Data bit selection (0..15) for bit engine 1
11:8 I/O bit selection (0..15) for bit engine 1
7:4 Data bit selection (0..15) for bit engine 0
3:0 I/O bit selection (0..15) for bit engine 0
Name
GPIO_BE_DAT1
GPIO_BE_IO1
GPIO_BE_DAT0
GPIO_BE_IO0
GPIOx_BIT_ENG0 is a register used to read/write a GPIO pin specified in GPIOx_BIT_CONF
register.
When writing a value to the bit engine 0 register, the data bit specified in the configuration
register is copied to the data output register bit specified in the same register.
When reading a value from the bit engine 0 register, the data input register bit specified in the
configuration register is copied to the data bit specified in the same register, other bits read out
as 0.
PR
EL
IM
GPIOx_BIT_ENG1 works just like GPIOx_BIT_ENG0.
Version: 0.52, 2012-11-07
85
VS1005g Datasheet
11.14
S/PDIF Peripheral
11.14.1
S/PDIF Receiver
VS1005G PERIPHERALS AND REGISTERS
IN
AR
Y
11
S/PDIF receiver interface offers a receiver function for serial digital audio. S/PDIF supports
two channels which are multiplexed in one signal line. Synchronizing to S/PDIF input data bit
frequency is done by the digital frequency divider the clock of which is generated by the low
jitter programmable PLL. Supported sampling frequencies are 32.0 kHz, 44.1 kHz, 48.0 kHz,
96.0 kHz and 192.0 kHz.
S/PDIF Receiver peripheral device supports linear PCM sample recovery up to 24 bits, S/PDIF
subframe parity check, biphase channel coding check, subframe, frame, and block integrity
checks, and read miss notification. This version does not perform cyclic redundancy check
(CRC) for channel status bits in hardware. CRC check can be implemented by software if
needed.
IM
Frame format is depicted in Figure 16. X, Y, and Z are the allowed preambles of a subframe.
An X subframe and an Y subframe constitute a frame. X preamble is replaced by Z preamble
every 192 frames to indicate block limit.
Figure 16: S/PDIF frame format.
PR
EL
Subframe format is depicted in Figure 17. A Preamble is a signal pattern lasting 4 time slots.
S/PDIF Receiver decodes it and keeps track of frame and block integrity. A payload is max
24-bit sample word. Validity bit indicates whether the payload is valid audio sample. User data
bit allows simultaneous data send. Channel information is conveyed in channel status bits as
specified in IEC 60958-1 and IEC 60958-3. S/PDIF Receiver peripheral device uses the parity
bit to calculate parity check. The result is shown in SP_CTL register bits LPerr and RPerr. Each
bit occupies one time slot of the subframe.
Version: 0.52, 2012-11-07
Figure 17: S/PDIF sub-frame format.
86
VS1005g Datasheet
11.14.2
S/PDIF Receiver Registers
VS1005G PERIPHERALS AND REGISTERS
IN
AR
Y
11
The base address for S/PDIF Receiver interface registers is Y:0xFD00.
Address
0xFD00
0xFD01
0xFD02
0xFD03
0xFD04
0xFD05
0xFD06
0xFD07
Type
r/w
r/w
r
r
r
r
r/w
r
Reset
0x1FF0
0
0
0
0
0
0
0
S/PDIF Receiver Registers
Abbrev
Description
SP_RX_CF
S/PDif control and status register
SP_RX_CLKDIV
S/PDif receiver clock divider register
SP_LDATA_LSB
S/PDif input left input channel, bits 8-0
SP_LDATA
S/PDif left input channel, bits 23-8
SP_RDATA_LSB
S/PDif left input channel, bits 8-0
SP_RDATA
S/PDif right input channel, bits 23-8
SP_RX_STAT
S/PDif status register
SP_RX_BLFRCNT S/PDif frame status register
Name
SP_RX_CF_EN
SP_RX_CF_INT_ENA
SP_RX_CF Bits
Bits Description
3 S/PDIF enable
1 Interrupt enable
IM
SP_RX_CF_EN Enables S/PDIF Receiver peripheral. If disabled, i.e. ’0’, most of the peripheral
is resetted and synchronisation to S/PDIF stream is lost and must be re-acquired after enabling.
SP_RX_CF_INT_ENA, when set, enables S/PDIF receiver interrupt.
Name
SP_RX_CLKDIV
SP_RX_CLKDIV Bits
Bits Description
7:0 Receiver clock divider
EL
SP_RX_CLKDIV is an 8-bit clock divider value that is used to adjust the S/PDIF Receiver
peripheral to proper Fs according to master clock frequency. Default value is 8, resulting to Fs
= 48 kHz with master clock = 24.576 MHz. Values smaller than 4 are not allowed, since at least
4 samples per audio sample are needed (2 samples per biphase mark).
S/PDIF Receiver peripheral supports audio sampling frequencies up to 192 kHz.
The supported frequencies and corresponding bit rates are summarized in the following table.
Bit rate is sampling frequency multiplied by 64, which is channel number (2) times subframe
time slot count (32).
PR
While the divider value should be targeted to bit rate of the table below, the peripheral actually
operates with quadruple clock rate. This must be accounted for in the system clocking design.
The system clock must be at least four (4) times the bit rate if S/PDIF peripheral is to be used.
In other words, SP_CF_DIV values less than four ( < 4 ) are forbidden. Divider must be even
number.
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Fs
22.05 kHz
24 kHz
32 kHz
44.1 kHz
48 kHz
96 kHz
192 kHz
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AR
Y
11
S/PDIF Frequencies
bit rate (Fs x 64) Minimum system clock rate (4 x bit rate)
1.4112 MHz
5.6448 MHz
1.536 MHz
6.144 MHz
2.048 MHz
8.192 MHz
2.8224 MHz
11.2896 MHz
3.072 MHz
12.288 MHz
6.144 MHz
24.576 MHz
12.288 MHz
49.152 MHz
Divider = M aster clock / bit rate,
Divider > 3, even number.
SP_RX_LDATA, SP_RX_LDATA_LSB, SP_RX_RDATA and SP_RX_RDATA_LSB registers are
received data registers. S/PDIF data is 24 bits and it is divided in two registers. 16 MSB bits
are in registers SP_RX_LDATA and SP_RX_RDATA. The remaining 8 LSB bits are in registers
SP_RX_LDATA_LSB and SP_RX_RDATA_LSB.
Bits
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SP_RX_STAT Bits
type Description
r/w Channel Status Change
r
Frame receive
always zero
r/w Missed reading previous frame
r/w Block error, Z preamble every 192 frames failure
r/w Frame error, Y preamble after (X or Z) failure
r/w Subframe error, subframe /= 28 bits
r/w Biphase coding error
r/w Parity error, right channel
r/w Parity error, left channel
r
Validity bit, right channel
r
User data bit, right channel
r
Channel status bit, right channel
r
Validity bit, left channel
r
User data bit, left channel
r
Channel status bit, left channel
EL
IM
Name
SP_RX_STAT_CHSCH
SP_RX_STAT_FRCV
N/A
SP_RX_STAT_MISS
SP_RX_STAT_BERR
SP_RX_STAT_FERR
SP_RX_STAT_SFERR
SP_RX_STAT_BIPHERR
SP_RX_STAT_RPERR
SP_RX_STAT_LPERR
SP_RX_STAT_RV
SP_RX_STAT_RU
SP_RX_STAT_RC
SP_RX_STAT_LV
SP_RX_STAT_LU
SP_RX_STAT_LC
SP_RX_STAT_CHSCH is a poll bit for channel status change interrupt.
PR
SP_RX_STAT_FRCV is set by the peripheral when a frame is received, and cleared when
SP_RX_LDATA is read.
SP_RX_STAT_MISS bit is set if SP_RX_STAT_FRCV is set and new samples are written to
SP_RX_LDATA and SP_RX_RDATA. The time to read the samples is a few clock cycles less
than the sampling period.
SP_RX_STAT_BERR is set if the period between Z-preambles is not equal to 192 frames.
SP_RX_STAT_FERR is set if Y-preamble does not follow X-preamble or Z-preamble.
SP_RX_STAT_SFERR is set if the previous subframe has not been equal to 32 time slots.
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11
SP_BIPHERR is set if biphase coding of the S/PDIF channel is compromised.
SP_RX_STAT_RPERR and SP_RX_STAT_LPERR are set if the parity count is failed in the
respective subframe.
SP_RX_STAT_MISS, SP_RX_STAT_BERR, SP_RX_STAT_FERR, SP_RX_STAT_SFERR, SP_BIPHERR,
SP_RX_STAT_RPERR, and SP_RX_STAT_LPERR are “sticky” bits, i.e. if set they keep their
state until cleared by sw.
SP_RX_STAT_RV and SP_RX_STAT_LV are validity bits for right channel and left channel,
restectively. When validity bit is ’0’, sample word is a valid PCM sample.
SP_RX_STAT_RU and SP_RX_STAT_LU are user data bits. User data bits should be used as
specified in IEC 60958-3.
SP_RX_STAT_RC and SP_RX_STAT_LC are channel status bits. According to the S/PDIF
standard, both channels should convey the same bits. Again, for full description of channel
status bits, refer to IEC 60958-3.
Name
SP_RX_BLCNT
SP_RX_FRCNT
SP_RX_BLFRCNT Bits
Bits Type Description
15:8
r
Frame block count
7:0
r
Frame count
IM
SP_RX_BLCNT is a freame block counter. This counter increment each time a new frame is
received. It is zeroed after the 191th frame is received.
SP_RX_FRCNT is zeroed with every Z-preamble and incremented with every X-preamble.
EL
S/PDIF Receiver uses two interrupts, a frame received interrupt and a channel status chance
interrupt. Device issues an interrupt when it has received a frame. The interrupt is cleared
when SP_RX_LDATA is read. Channel status change interrupt is set when at least one of the
following conditions is satisfied:
• Channel status bit 0, selection between professional and consumer mode, is changed.
• Channel status bit 1, which indicates whether the sample word is linear PCM or not, is
changed.
• Validity bit for either channel, left or right, is changed.
PR
This interrupt is enabled by setting SP_RX_CF_INT_ENA bit.
11.14.3
S/PDIF Transmitter
S/PDIF is a serial digital audio transfer standard. Sampling frequencies up to 192 kHz and
sample word width of 16 - 24 bits are supported for two channels. S/PDIF transmitter peripheral
has a processor interface and one external output signal for digital audio. S/PDIF is described
in IEC 60958-1 and IEC 60958-3. Standard connectors are defined in IEC 60268-11:1987
although commercial products feature a variety of connectors both electrical and optical.
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AR
Y
11
The speed of the S/PDIF transmitter depends on the sampling frequency of the audio signal.
Since S/PDIF signal is often used to retrieve a clock signal at the receiving end, S/PDIF transmitter must produce an exact frequency with a very low jitter.
Supported sampling frequencies are 32 kHz, 48 kHz, 96 kHz and 192 kHz when master clock
frequency is n x 12.288 MHz. 44.1 kHz sampling frequency is supported.
11.14.4
S/PDIF Transmitter Registers
S/PDIF supports audio sample width of 16 to 24 bits. The exact figure is conveyed to the
receiver by channel status bits. If the the transmitted sample word is less than 24 bits wide, the
remaining LSB’s must be zero.
Channel status registers provide interface to the S/PDIF standard implementation channel status bits. The S/PDIF Transmitter inserts the corresponding bits to their proper places in the
transfer frame. Channel status data (byte 23) for cyclic redundancy check character (CRCC) is
not tested yet.
This document offers a terse description of the channel status bits. Full coverage in IEC 609583 is mandatory. Current implementation shares Channel Status Data bits (registers CHS0 and
CHS1) for both channels!
Reset
0
0
0
0
0
0
0
0x40
IM
Type
w
w
w
w
r/w
r/w
r/w
r/w
EL
Reg
0xFD02
0xFD03
0xFD04
0xFD05
0xFD08
0xFD09
0xFD0A
0xFD0B
S/PDIF Transmitter Registers
Abbrev
Description
SP_LDATA_LSB Left channel Audio sample bits 7-0
SP_LDATA
Left channel Audio sample bits 23-8
SP_RDATA_LSB Right channel Audio bits sample 7-0
SP_RDATA
Right channel Audio sample bits 23-8
SP_TX_CHST0
Channel Status 0
SP_TX_CHST1
Channel Status 1
SP_TX_CHST2
Channel Status 1
SP_TX_CF
Transmitter configuration
SP_TX_LDATA, SP_TX_LDATA_LSB, SP_TX_RDATA and SP_TX_RDATA_LSB registers are
transmitter data registers. S/PDIF data is 24 bits and it is divided in two registers. 16 MSB bits
are in registers SP_TX_LDATA and SP_TX_RDATA. The remaining 8 LSB bits are in registers
SP_TX_LDATA_LSB and SP_TX_RDATA_LSB.
Channel Status SP_TX_CHST0
Bits of data Bits of Chanword
nel status
SP_TX_CHST0_CAT
15:8
15:8
SP_TX_CHST0_MD0
7:6
7:6
SP_TX_CHST0_PCMM
5:3
5:3
SP_TX_CHST0_CP
2
2
SP_TX_CHST0_PCM
1
1
SP_TX_CHST0_PROCON
0
0
PR
Name
Description
Category Code
PCM Mode 0
Linear PCM Mode
Copyright
Linear PCM
Professional/Consumer
mode
SP_TX_CHST0_CAT indicates to which category the device belongs. Default value is “00000000”.
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The default value of SP_TX_CHST0_MD0 is “00”. No other states are defined yet.
When SP_TX_CHST0_PCM is ’0’, SP_TX_CHST0_PCMM selects linear PCM mode. The
default value is “000” which corresponds to 2 audio channels without pre-emphasis.
SP_TX_CHST0_CP is a copyright bit. When ’0’, copyright for current stream is asserted.
SP_TX_CHST0_PCM is ’0’ when the audio sample word is linear PCM.
SP_TX_CHST0_PROCON is ’0’ in S/PDIF defining consumer usage. If this bit is ’1’, channel is
for professional use and the interface would be called AES/EBU. However, the channel status
bits would be different in this case.
Channel Status SP_TX_CHST1
Bits of data Bits of Chanword
nel status
15:14
31:30
13:12
29:28
11:8
27:24
7:4
23:20
3:0
19:16
Name
SP_TX_CHST1_CLKA
SP_TX_CHST1_FS
SP_TX_CHST1_CH
SP_TX_CHST1_SRC
Description
Not specified, “00”
Clock Accuracy
Sampling Frequency
Channel Number
Source Number
SP_TX_CHST1_CLKA indicates the level of clock accuracy the S/PDIF transmitter is capable
of providing to its output.
IM
The sampling frequency of the audio sample stream is defined in SP_TX_CHST1_FS.
SP_TX_CHST1_CH is the number of channels in the transmission. “0011” indicates two channel stereo format.
SP_TX_CHST1_SRC is the number of sources. “0000” is defined as “do not take into account”.
Channel Status SP_TX_CHST2
Bits
of Bits of Chan- Description
data word nel status
SP_TX_CHST2_ST_NWRQ
13
New Word Request (read only bit)
SP_TX_CHST2_TX_ENA
12
Transmitter enable
SP_TX_CHST2_RS1_RU
11
User Data bit, right channel
SP_TX_CHST2_RS1_RV
10
Validity bit, right channel
SP_TX_CHST2_LS1_RU
9
User Data bit, left channel
SP_TX_CHST2_LS1_RV
8
Validity bit, left channel
SP_TX_CHST2_CH2_FSO
7:4
39:36
Original Sampling Frequency
SP_TX_CHST2_CH2_WRDL
3:1
35:33
Sample Word Length
SP_TX_CHST2_CH2_WRDLM 0
32
Maximum Sample Word Length
PR
EL
Name
SP_TX_CHST2_ST_NWRQ bit is set when new sample words must be written to sample word
registers. It is cleared when SP_TX_CHST2_TX_LDATA is written. Hence, SP_TX_CHST2_ST_NWRQ
has the same function as S/PDIF Interrupt, but this bit is not controlled by SP_TX_CHST2_CF_IE.
SP_TX_CHST2_TX_ENA is the S/PDIF transmit enable. Transmitter is enabled when this register is set.
SP_TX_CHST2_RS1_RU is a user data bit for the right channel. Default value is ’0’. User data
bits can be used to convey an application specific message to the receiver. Some equipment
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11
categories dictate the message, see IEC 60958-3.
SP_TX_CHST2_RS1_RV is the validity bit of the right channel sample word. If the audio sample word is not a linear PCM, this bit must be set.
SP_TX_CHST2_LS1_LU is a user data bit for the left channel. Default value is ’0’. User data
bits can be used to convey an application specific message to the receiver. Some equipment
categories dictate the message, see IEC 60958-3.
SP_TX_CHST2_LS1_LV is the validity bit of the left channel sample word. If the audio sample
word is not a linear PCM, this bit must be set.
SP_TX_CHST2_CH2_FSO defines the original sampling frequency of the audio stream. “0000”
means the original sampling frequency is not indicated (default).
In SP_TX_CHST2_CH2_WRDL, the sample word length is coded with respect to SP_TX_CHST2_CH2_WRDL
“000” means the word length is not indicated.
SP_TX_CHST2_CH2_WRDLM indicates whether the maximum word length is 24 bits (’1’) or
20 bits (’0’).
IM
S/PDIF TX Configuration SP_TX_CF
Name
Bits Description
SP_TX_CF_CLKDIV
15:2 Clock divider
SP_TX_CF_IE
1 Interrupt enable
SP_TX_CF_SND
0 Send words
SP_TX_CF_CLKDIV contains a clock divider value that is used to generate S/PDIF Transmitter operating frequency. The target is twice the bit rate. Bit rate is sampling frequency of
the transmitted signal multiplied by 64. For example, 48 kHz audio signal requires bit rate of
3.072 MHz and consequent clock frequency for the peripheral is 6.144 MHz. Default value for
SP_TX_CF_CLKDIV is 4, resulting to Fs = 48 kHz when master clock frequency is 24.576 MHz.
Zero is forbidden value.
S/PDIF Transmitter frequencies
bit rate (Fs x 64) Target frequency for clock divider
2.048 MHz
4.096 MHz
2.8224 MHz
5.6448 MHz
3.072 MHz
6.144 MHz
6.144 MHz
12.288 MHz
12.288 MHz
24.576 MHz
EL
Fs
32 kHz
44.1 kHz
48 kHz
96 kHz
192 kHz
Divider = Master clock / Targer frequency, Divider = Master clock / (Fs * 64 * 2).
PR
SP_TX_CF_IE, when ’1’, enables processor interrupt request when new values must be written
for the sample word registers: SP_LDATA and SP_RDATA. Default is ’0’.
SP_TX_CF_SND, when ’1’, S/PDIF Transmitter sends the data in the sample word registers.
Otherwise only empty subframes with zero payload will be sent. This is because the receiver
may use S/PDIF signal as a clock source and hence, the S/PDIF signal must not stop even
though no data is sent.
The S/PDIF Transmitter has one interrupt. Interrupt request is issued when SP_ST_NWRQ is
set, i.e. when new sample words must be written to the sample word registers.
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11.15
UART Peripheral
VS1005G PERIPHERALS AND REGISTERS
IN
AR
Y
11
RS232 UART implements a serial interface using rs232 standard.
Start
bit
D0
D1
D2
D3
D4
D5
D6
Stop
D7 bit
Figure 18: RS232 serial interface protocol
When the line is idling, it stays in logic high state. When a byte is transmitted, the transmission
begins with a start bit (logic zero) and continues with data bits (LSB first) and ends up with a
stop bit (logic high). 10 bits are sent for each 8-bit byte frame.
UART Peripheral Registers
Reg
0xFE00
0xFE01
0xFE02
0xFE03
Type
r
r/w
r/w
r/w
UART Registers
Reset Abbrev
0 UART_STATUS[4:0]
0 UART_DATA[7:0]
0 UART_DATAH[15:8]
0 UART_DIV
IM
11.15.1
Description
Status
Data
Data High
Divider
UART_STATUS register monitors the UART status.
EL
UART_STATUS Bits
Name
Bits Description
UART_ST_FRAMERR
4 Framing Error (stop bit was 0)
UART_ST_RXORUN
3 Receiver overrun
UART_ST_RXFULL
2 Receiver data register full
UART_ST_TXFULL
1 Transmitter data register full
UART_ST_TXRUNNING
0 Transmitter running
UART_ST_FRAMERR is set at the time of stop bit reception. When reception is functioning
normally, stop bit is always “1”. If, however, “0” is detected at the line input at the stop bit
time, UART_ST_FRAMERR is set to “1”. This can be used to detect “break” condition in some
protocols.
PR
UART_ST_RXORUN is set if a received byte overwrites unread data when it is transferred from
the receiver shift register to the data register, otherwise it is cleared.
UART_ST_RXFULL is set if there is unread data in the data register.
UART_ST_TXFULL is set if a write to the data register is not allowed (data register full).
UART_ST_TXRUNNING is set if the transmitter shift register is in operation.
UART_DATA is the uart data register. A read from UART_DATA returns the received byte in bits
7:0, bits 15:8 are returned as ’0’. If there is no more data to be read, the receiver data register
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full indicator will be cleared.
VS1005G PERIPHERALS AND REGISTERS
IN
AR
Y
11
A receive interrupt will be generated when a byte is moved from the receiver shift register to
the receiver data register.
A write to UART_DATA sets a byte for transmission. The data is taken from bits 7:0, other
bits in the written value are ignored. If the transmitter is idle, the byte is immediately moved
to the transmitter shift register, a transmit interrupt request is generated, and transmission is
started. If the transmitter is busy, the UART_ST_TXFULL will be set and the byte remains in the
transmitter data register until the previous byte has been sent and transmission can proceed.
UART_DATAH is the same register as the UART_DATA, except that bits 15:8 are used.
UART_DIV register configures uart tansmission speed.
Name
UART_DIV_D1
UART_DIV_D2
UART_DIV Bits
Bits Description
15:8 Divider 1 (0..255)
7:0 Divider 2 (6..255)
The divider is set to 0x0000 in reset. The ROM boot code must initialize it correctly depending
on the master clock frequency to get the correct bit speed. The second divider (D2 ) must be
from 6 to 255.
fm
(D1 +1)×(D2 )
, where fm is XTALI, and f is the TX/RX speed in
PR
EL
IM
The communication speed f =
bps.
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11.16
Watchdog Peripheral
VS1005G PERIPHERALS AND REGISTERS
IN
AR
Y
11
The watchdog consist of a watchdog counter and some logic. After reset, the watchdog is inactive. The counter reload value can be set by writing to WDOG_CF. The watchdog is activated by
writing 0x4ea9 to register WDOG_KEY. Every time this is done, the watchdog counter is reset.
Every 65536’th clock cycle the counter is decremented by one. If the counter underflows, it will
activate vsdsp’s internal reset sequence.
Thus, after the first 0x4ea9 write to WDOG_KEY, subsequent writes to the same register with
the same value must be made no less than every 65536×WDOG_CF clock cycles.
Once started, the watchdog cannot be turned off. Also, a write to WDOG_CF doesn’t change
the counter reload value.
After watchdog has been activated, any read/write operation from/to WDOG_CF or WDOG_DUMMY
will invalidate the next write operation to WDOG_KEY. This will prevent runaway loops from resetting the counter, even if they do happen to write the correct number. Writing an incorrect
value to WDOG_KEY will also invalidate the next write to WDOG_KEY.
Reads from watchdog registers return undefined values.
Watchdog Registers
Type
w
w
w
Watchdog Registers
Reset Abbrev
0 WDOG_CF
0 WDOG_KEY
0 WDOG_DUMMY[-]
Description
Configuration
Clock configuration
Dummy register
PR
EL
Reg
0xFE20
0xFE21
0xFE22
IM
11.16.1
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11.17
I2S Peripheral
VS1005G PERIPHERALS AND REGISTERS
IN
AR
Y
11
VS1005g has a bi-directional I2S digital interface. I2S is a serial audio interface which uses
serial bit clock (i2s_bck), frame sync (i2s_frm) and serial data line (i2s_dout, i2s_din) to transfer
data. I2S frame consists of left and right data which is transmitted left word first and MSB bit
first. Data is latched out at falling edge of bit clock and latched in at rising edge of bit clock. I2S
data format is shown in Figure 19.
Figure 19: I2S frame format.
I2S Peripheral Registers
Type
r/w
r/w
r/w
r/w
r/w
Reset
0
0
0
0
0
I2S_CF Bits
Description
32-bit mode (1) / 16-bit mode (0) select
I2S peripheral interrupt enable
Receiver right data register full
Receiver left data register full
Receiver over run flag
Transmitter right data register full
Transmitter left data register full
Transmitter under run flag
I2S peripheral mode select (dsp or SRC out)
I2S sample rate selection
I2S peripheral enable
I2S master clock (12 MHz) pad driver enable
I2S master (1) / slave (0) mode select
EL
Reg
0xFE60
0xFE61
0xFE62
0xFE63
0xFE64
I2S Registers
Abbrev
Description
I2S_CF[13:0]
Configuration and status register
I2S_LEFT_LSB
Left data bits[15:0]
I2S_LEFT
Left data bits[32:16]
I2S_RIGHT_LSB Right data bits[15:0]
I2S_RIGHT
Right data bits[32:16]
IM
11.17.1
PR
Name
I2S_CF_32B
I2S_CF_INTENA
I2S_CF_RXRFULL
I2S_CF_RXLFULL
I2S_CF_RXORUN
I2S_CF_TXRFULL
I2S_CF_TXLFULL
I2S_CF_TXURUN
I2S_CF_MODE
I2S_CF_FS[1:0]
I2S_CF_ENA
I2S_CF_ENAMCK
I2S_CF_MASTER
Bits
13
12
11
10
9
8
7
6
5
4:3
2
1
0
I2S_CF_MASTER bit is used to select between master (1) and slave (0) modes. In master
mode the VS1005g generates bit clock and frame sync signals. In slave mode the external I2S
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AR
Y
11
master generates the clock and sync signals.
I2S_CF_ENAMCK is the 12 MHz output clock enable signal. It can be used to clock external
I2S circuitry. This clock is the same clock as the XTALI oscillator clock of VS1005g.
I2S_CF_ENA is the transmitter and receiver enable signal. When set the receiver and transmitter enter the active state.
I2S_CF_FS register is used to set the I2S peripheral sample rate. This register can be modified
only when I2S is in idle state, i.e. I2S_CF_ENA is reset. Next table lists the sample rates when
XTALI = 12.288 MHz is used.
I2S Sample Rates
I2S_CF_FS[1:0] 16-bit mode 32-bit mode
11
48 kHz
24 kHz
10
192 kHz
96 kHz
01
96 kHz
48 kHz
00
48 kHz
24 kHz
I2S_CF_MODE register selects between dsp mode and SRC mode. In dsp mode the data is
transferred from left and right data registers. In SRC mode the data is sampled from DAC’s
SRC filter and I2S is operating in master mode only.
IM
I2S_CF_TXURUN is the transmitter under run flag register. It is set if left or right data buffer
register was empty as it was copied to shifter register.
I2S_CF_TXLFULL and I2S_CF_TXRFULL registers are the transmitter data buffer full flags for
left and right channel. Flags are set when transmitter data buffer registers are modified. The
flags are reset as the left and right data buffer is copied to shifter register.
I2S_CF_RXORUN is the receiver over run flag. It is set when receiver data buffers were full
and new frame was received. The flag is reset by writing it to ’0’.
EL
I2S_CF_RXLFULL and I2S_CF_RXRFULL are the receiver data buffer full flags for left and
right channel. Flags are set when receiver data buffer registers are full. The flags are reset as
the left and right data buffer is read.
I2S_CF_INTENA enables the I2S interrupt when set.
I2S_CF_32B register selects between 32-bit (1) and 16-bit (0) data format. This register can
be modified only in idle state.
PR
I2S_LEFT, I2S_LEFT_LSB, I2S_RIGHT and I2S_RIGHT_LSB are the left and right data registers for receiver and transmitter. Each write to I2S_LEFT and I2S_RIGHT registers sets the
I2S_CF_TXLFULL and I2S_CF_TXRFULL flags. Each read from I2S_LEFT and I2S_RIGHT
registers resets the I2S_CF_RXLFULL and I2S_CF_RXRFULL flags. In 16-bit mode the registers I2S_LEFT_LSB and I2S_RIGHT_LSB are not used. In 32-bit mode they are used to
transfer 16-lsb bits of data.
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11.18
Timer Peripheral
VS1005G PERIPHERALS AND REGISTERS
IN
AR
Y
11
VS1005g has three 32-bit timers that can be initialized and enabled independently of each
other. If enabled, a timer initializes to its user initialized start value, and starts decrementing
every clock cycle. When the value goes past zero, an interrupt request is generated, and the
timer initializes to the value in its start value register, and continues downcounting. A timer
stays in that loop as long as it is enabled. Each timer has its own interrupt request.
A timer has a 32-bit timer register for down counting and a 32-bit TIMER1_LH register for
holding the timer start value written by the processor. Timers have also a 3-bit TIMER_ENA
register. Each timer is enabled (1) or disabled (0) by a corresponding bit of the enable register.
Timer Peripheral Registers
Type
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
r/w
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Timer Registers
Abbrev
TIMER_CF[7:0]
TIMER_ENA[2:0]
TIMER_T0L
TIMER_T0H
TIMER_T0CNTL
TIMER_T0CNTH
TIMER_T1L
TIMER_T1H
TIMER_T1CNTL
TIMER_T1CNTH
TIMER_T2L
TIMER_T2H
TIMER_T2CNTL
TIMER_T2CNTH
Description
Timer configuration
Timer enable
Timer0 startvalue - LSBs
Timer0 startvalue - MSBs
Timer0 counter - LSBs
Timer0 counter - MSBs
Timer1 startvalue - LSBs
Timer1 startvalue - MSBs
Timer1 counter - LSBs
Timer1 counter - MSBs
Timer2 startvalue - LSBs
Timer2 startvalue - MSBs
Timer2 counter - LSBs
Timer2 counter - MSBs
EL
Reg
0xFE80
0xFE81
0xFE84
0xFE85
0xFE86
0xFE87
0xFE88
0xFE89
0xFE8A
0xFE8B
0xFE8C
0xFE8D
0xFE8E
0xFE8F
IM
11.18.1
TIMER_CF Bits
Name
Bits Description
TIMER_CF_CLKDIV
7:0 Master clock divider
PR
TIMER_CF_CLKDIV is the master clock divider for all timer clocks. The generated internal
fm
clock frequency fi = c+1
, where fm is the master clock frequency and c is TIMER_CF_CLKDIV.
Example: With a 12 MHz master clock, TIMER_CF_DIV=3 divides the master clock by 4, and
Hz
the output/sampling clock would thus be fi = 12M
3+1 = 3M Hz.
Name
TIMER_ENA_T2
TIMER_ENA_T1
TIMER_ENA_T0
Version: 0.52, 2012-11-07
TIMER_ENA Bits
Bits Description
2 Enable timer 2
1 Enable timer 1
0 Enable timer 0
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VS1005g Datasheet
VS1005G PERIPHERALS AND REGISTERS
IN
AR
Y
11
TIMER_Tx[L/H] register defines the Timer X Startvalue. The 32-bit start value TIMER_Tx[L/H]
fi
sets the initial counter value when the timer is reset. The timer interrupt frequency ft = c+1
where fi is the master clock obtained with the clock divider and c is TIMER_Tx[L/H].
TIMER_TxCNT[L/H] contains the current counter values. By reading this register pair, the user
may get knowledge of how long it will take before the next timer interrupt. Also, by writing to
this register, a one-shot different length timer interrupt delay may be realized.
PR
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Each timer has its own interrupt, which is asserted when the timer counter underflows.
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VS1005g Datasheet
11.19
Real Time Clock (RTC)
VS1005G PERIPHERALS AND REGISTERS
IN
AR
Y
11
RTC is used for accurate time measurements and storing data when CPU is powered down.
The oscillator input clock frequency is 32768 Hz. Real time clock is a 32-bit time keeping up
counter which has a resolution of 1 second. Additionally the 8-bit clock divider register value is
accessible giving 1/128 seconds resolution. Other functions of VS1005g RTC are time alarm
and 32 word register memory for battery backup. The RTC consists of two parts, the Real Time
Clock module and its dsp interfacing peripheral. The RTC has its own power network which
enables its use when the rest of the system is powered off. The interface between these two is
bit-serial.
11.19.1
RTC Peripheral Registers
Reg
0xFEA0
0xFEA1
0xFEA2
Type
r/w
r/w
r/w
RTC Interface Registers
Reset Abbrev
Description
0 RTC_LOW
RTC data register bits [15:0]
0 RTC_HIGH
RTC data register bits [31:16]
0 RTC_CF[4:0] RTC if control and status register
IM
Name
RTC_CF_GSCK
RTC_CF_EXEC
RTC_CF_RDBUSY
RTC_CF_DBUSY
RTC_CF_IBUSY
RTC_CF Bits
Bits Description
4 Generate serial clock for RTC
3 RTC execute instruction
2 Read cycle init and busy flag
1 Data cycle init and busy flag
0 Instruction cycle init and busy flag
EL
RTC_LOW and RTC_HIGH are the rtc_if data registers. Write to RTC_CF registers busy bits
start a data transfer to/from RTC. When the operation has finished the status bit is reset and
result can be read from RTC_HIGH and RTC_LOW registers or RTC_HIGH and RTC_LOW
registers were transferred to RTC.
RTC_IBUSY is the instruction cycle initialization register. When RTC_IBUSY is set the current content of RTC_HIGH and RTC_LOW registers is transferred to RTC and latched to its
instruction register. When rtc_if is ready it resets the RTC_IBUSY.
PR
RTC_DBUSY is the data cycle initialization register. When RTC_DBUSY is set the current
content of RTC_HIGH and RTC_LOW registers is transferred to RTC data buffer. When rtc_if
is ready it resets the RTC_DBUSY.
RTC_RDBUSY is the data read cycle initialization register. Before reading rtc a valid instruction must be in RTC instruction register (RTC_I_READRTC, RTC_I_RDDIV128). When
RTC_RDBUSY is set the rtc_if first samples the selected rtc register to RTC data buffer. When
the data is read to RTC_HIGH and RTC_LOW registers. When rtc_if is ready it resets the
RTC_RDBUSY.
RTC_EXEC is used to execute current RTC instruction. Before executing an instruction a
valid instruction must be in RTC instruction register (RTC_I_RESET, RTC_I_LOADRTC). For
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VS1005G PERIPHERALS AND REGISTERS
IN
AR
Y
11
RTC_I_RESET, RTC_I_LOADRTC instructions the RTC_EXEC register must be set for 1 second before the instruction is ececuted. The user must reset the RTC_EXEC register after this
time has elapsed.
RTC_GSCK is used to generate RTC memory clock. When RTC_GSCK is set the rtc_if generates one clock pulse for memory store. RTC_EXEC must be set during this operation. Rtc_if
resets this register automatically.
RTC instructions are 8-bit codes which are written to RTC_HIGH[15:8] before setting RTC_IBUSY.
RTC Instruction Codes
Hex code
Delay Description
EB
1/128 s Reset control registers
59
1 s Initialize time counter register
56 1/12 MHz Read time counter register
C7 1/12 MHz Read 8-bit divider register (1/128s)
AC
1/128 s Set RTC alarm time
35 1/12 MHz Write to rtc memory
3A 1/12 MHz Read from RTC memory
PR
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Instruction
RTC_I_RESET
RTC_I_LOADRTC
RTC_I_READRTC
RTC_I_RDDIV128
RTC_I_ALARM
RTC_I_MEM_WR
RTC_I_MEM_RD
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11.20
VS1005G PERIPHERALS AND REGISTERS
IN
AR
Y
11
10-Bit Successive Approximation Register Analog-to-Digital Converter (SAR)
VS1005g has a 10-bit ADC with following features:
• Successive Approximation Register conversion (SAR)
• Up to 5 analog input channels
• Up to 0.1Msps conversion speed
• AVDD voltage as reference
• Continuous or software enabled (once only) operation modes
• input range from 0V to AVDD
Before SAR can be used the following analog control registers must be configured.
Analog configuration for SAR
Register Name Address Value Description
ANA_CF2
0xFED2 0x0008 Analog reference
ANA_CF1
0xFECB 0x0100 SAR power down
SAR operation is controlled with configuration register and the 10-bit data is stored in the data
register. SAR generates an interrupt as the data register is updated.
Type
r
SAR Control/Configuration Register
Type
Reset Abbrev
Description
r/w
0x003F SAR_CF[11:0] SAR control register
SAR_CF Bits
Bits Description
11:8 SAR input selection
7 SAR initialize read cycle
6 SAR operation mode
5:0 SAR Clock divider register
EL
Reg
0xFED6
SAR Data Register
Reset Abbrev
Description
0 SAR_DAT[9:0] 10-bit SAR data register
IM
Reg
0xFECD
Name
SAR_CF_SEL
SAR_CF_ENA
SAR_CF_MODE
SAR_CF_CK[5:0]
PR
SAR_CF_ENA is used to start SAR cycle. When this register is set the SAR measures voltage
from a given channel and stores the 10-bit value to SAR_DAT register. SAR_CF_ENA is reset
when the result is ready and can be read from data register.
SAR_CF_CK[5:0] is used to select the interface clock speed divider. The SAR clock runs at
XT ALI
32×(SAR_CF _CK+1) .
SAR_CF_MODE selects between continuous mode (’1’) and run-once (’0’) modes.
SAR input channel is selected with SAR_CF_SEL[3:0] register. This register is double buffered
against possible conversion time changes. The register is sampled as the SAR is enabled or it
is in idle state. In continuous mode the register is sampled at the end of each conversion.
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VS1005g Datasheet
Decimal
12
10
8
7
6
5
4
2
0
VS1005G PERIPHERALS AND REGISTERS
IN
AR
Y
11
SAR input channel selection
Hex Package Pin
Max Voltage
0xC 67
3.6 V
0xA Internal
3.6 V
0x8 Internal / 78 1
3.6 V
0x7 68
3.6 V
0x6 Internal / 64 2
1.95 V
1
3
0x5 Internal / 15
1.95 V
0x4 71
3.6 V
0x2 70
3.6 V
0x0 69
3.6 V
1
Description
aux0
Divided VHIGH
RCAP 1.2 or 1.6 V reference voltage
aux1
RTC voltage
Core voltage CVDD
aux4
aux3
aux2
Although connected to a pin, this voltage is normally generated by VS1005g. In a typical case
this pin should not be driven externally.
2
Maximum allowed external voltage to this pin is RTCVDD (1.95 V). Failing to follow this limitation may break VS1005g’s internal digital circuitry.
3
Maximum allowed external voltage to this pin is CVDD (1.95 V). Failing to follow this limitation
may break VS1005g’s internal digital circuitry.
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Other pin values than mentioned in the table are not allowed.
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11.21
VS1005G PERIPHERALS AND REGISTERS
IN
AR
Y
11
Pulse Width Modulation Unit
VS1005g has a PWM output which can be programmed to generate any pulse width within 256
XTALI clock periods.
Reg
0xFED4
0xFED5
Type
r/w
r/w
Reset
0
0
PWM Registers
Abbrev
Description
PWM_PULSE[7:0] PWM pulse width, 0 - 255 clock cycles
PWM_FRAME[7:0] PWM frame length, 2 - 255 clock cycles
PWM_FRAME[7:0] defines the pwm frame length. Values 0 and 1 are not allowed and they
place the unit in powerdown (output is zero). With frame values > 1 the pwm output is enabled
with rising edge at start of frame and falling edge at PWM_PULSE[7:0]. If PWM_PULSE is zero
the output is always zero. If PWM_PULSE > PWM_FRAME the output is always at logic high
state.
PWM unit generates interrupt request at the start of each frame.
In VS1005g power-up as the PWRBRTN pin is high the pwm output generates an oscillation
for external powering circuitry. The oscillation reguires that there is an external pull-up resistor
connected to the pwm pin.
Min
PWM start-up oscillator
Typical Max Description
100 kΩ
Value of external pull-up resistor
370 kHz
Start-up oscillation frequency
PR
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Item
Pull-up resistor
Start-up frequency
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11.22
11.22.1
Special Features
Software Protection
VS1005G PERIPHERALS AND REGISTERS
IN
AR
Y
11
PR
EL
IM
VS1005g hardware supports software protection. Two registers control the hardware debugging and serial flash access. To use on-circuit debugging it must first be enabled by a software
register. After power-up the debugger is disabled. The register can be set and reset by software. The access to serial flash can be disabled with a software register after boot-up. When
serial flash is disabled it can not be enabled by software. To re-enable it requires system reset
(SYSRST).
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VS1005g Debugger
VS1005G DEBUGGER
IN
AR
Y
12
VS1005g has a hardware debugger which uses common Joint Test Action Group (JTAG) interface. The JTAG pins are in hardware debug mode when the dbgmode pin is pulled high. This
enables the JTAG pins to access Test Acess Port (TAP) controller and swithes clocks to debug
mode.
VS1005g Hardware Debuger Pins
Package pin Description
31 Test mode select
32 Test data in
33 Test data out
34 Test clock
35 Debug interrupt
61 JTAG debug mode enable
Name
tms
tdi
tdo
tck
dbgreq
dbgmode
PR
EL
IM
Debug functions are controlled with JTAG DR (data) and IR (instruction) registers which can be
written and read in predefined JTAG states. JTAG state machine is shown in Figure 20.
Figure 20: JTAG state machine.
TAP function is selected by writing a special 4-bit instruction to IR register. Additionally to debug
functions, some common JTAG functions are supported.
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VS1005g Datasheet
Instruction
BYPASS
IDCODE
VS1005G DEBUGGER
IN
AR
Y
12
VS1005g JTAG instruction codes
IR register Description
“0000” Places jtag to bypass mode. In bypass mode
there is one clock cycle delay between tdi and
tdo.
“1111” Places jtag’s 32-bit ID code register between tdi
and tdo.
The snooper module supports up to 8 breakpoints which can be programmed to trigger at
data/address events. Snooper’s control and status registers are
• Enable register (SENA)
• 16-bit event count register (ECNT)
• 16-bit instruction address register (BADDR)
SENA register enables the snooper module when set. The register is reset when breakpoint
interrupt is triggered and all snooper logic is halted. ECNT register is a decrementing counter
which is decremented by one at each breakpoint event. When register is zero and a breakpoint event occurs, a breakpoint interrupt is generated. BADDR register stores the instruction
address when the breakpoint interrupt is generated.
IM
Each breakpoint has three configuration registers:
• Configuration register
• Address register
• Data register
Breakpoint configuration register is used to set-up a breakpoint.
Breakpoint Configuration Register Bits
Register Bit Description
7 Breakpoint triggered flag
6:5 X/Y/I bus selection
4:3 Fetch/Read/Write access type selection
2:0 Breakpoint condition selection
EL
Name
Status
Bus Type
Access Type
Condition Type
Breakpoint status bit is set when the breakpoint triggeres an interrupt.
Breakpoint Bus Type Bit Configuration
Bus Description
I
Breakpoint at I-bus
X
Breakpoint at X-bus
Y
Breakpoint at Y-bus
Illegal Don’t use
PR
Value
’00’
’01’
’10’
’11’
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VS1005g Datasheet
Value
’00’
’01’
’10’
’11’
Value
‘000’
‘001’
‘010’
‘011’
‘100’
’101’
’110’
’111’
VS1005G DEBUGGER
IN
AR
Y
12
Breakpoint Access Type Bit Configuration
Register Bit
Description
Disabled
Breakpoint is disabled
Fetch/Read
Breakpoint set to snoop read accesses
Write
Breakpoint set to snoop write accesses
Read or Write Breakpoint set to snoop both the read and write
accesses
Breakpoint Condition Type Bit Configuration
Bus
Description
Disabled Breakpoint disabled
Any
Match only address
=
X/Y-bus data EQUAL to snoop breakpoint data
6=
X/Y-bus data NOT EQUAL to snoop breakpoint data
< signed Signed comparison of X/Y-bus data LESS THAN
snoop breakpoint data
≥ signed Signed comparison of X/Y-bus data GREATER THAN
OR EQUAL to snoop breakpoint data
Illegal
Don’t use
Illegal
Don’t use
PR
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The hardware debugger requires the VLSI JTAG connector and Integrated Development Environment VSIDE for full debug capabilities. For further information about the hardware debugger
connect VLSI technical support.
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13
DOCUMENT VERSION CHANGES
IN
AR
Y
13
Document Version Changes
This chapter describes the most important changes to this document.
Version 0.52, 2012-11-07
• Added new pin types, DIPD and DIOPD, replacing a part of DI and DIO pins in Chapter 6.3, VS1005g Pin Descriptions.
• Clarified documentation in Chapter 11.4, Interrupt Controller.
• Renamed INT_ENABLEH0, INT_ENABLEL0, INT_ENABLEH1, and INT_ENABLEL1, to
INT_ENABLE0_HP, INT_ENABLE0_LP, INT_ENABLE1_HP, and INT_ENABLE1_LP, in
Chapter 11.4.1.
• Some register XP_ST bit names changed in Chapter 11.11, Common Data Interfaces.
• Some ANA_CF1 register bits changed in Chapter 11.6.1, Analog Control Registers.
Version 0.51, 2012-10-16
IM
• Added better instructions on how to connect the center ground plate GPLATE in Chapter 6.3, VS1005g Pin Descriptions.
• Corrected name for bit RS_DN_DNERR in Chapter 11.11.2, Reed-Solomon Codec.
Version 0.50, 2012-10-01
• Added documentation regarding how to use ADC3 to Chapter 11.8, 24-bit Analog to Digital Converters (ADC), including adding configuration bit AD_CF_AD23_FLP to Figure 10.
EL
• Description for FM_CF register bit FM_CF_ENABLE changed in Chapter 11.8.2, Digital
Filter Operation Modes.
• Added new USB_CF bits in Chapter 11.12.1, USB Peripheral Registers.
• Added Chapter 2, Licenses.
• Corrected descriptions for Nand flash register bits, Chapter 11.11.3, Nand Flash Interface.
• Typo corrections.
PR
Versions 0.42 & 0.41, 2012-05-31
• Updated figures in Chapter 6.1, Packages. Package thickness has changed from 0.9 mm
to 0.8 mm.
• Changed function descriptions for pins 67-68 and 70-73 in Chapter 6.3, VS1005g Pin
Descriptions.
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Version 0.4, 2012-05-30
DOCUMENT VERSION CHANGES
IN
AR
Y
13
• Added Chapter 5.10, Power Button Charactestics.
• Renamed Chapter 11.8 from Line and Mic Inputs to 24-bit Analog to Digital Converters
(ADC) and added documentation to it. Among other things, added Chapter 11.8.1, Configuring Signal Paths for ADC1 and ADC2.
• Redrawn Figure 10, VS1005g recording (AD and FM) signal paths, on page 51, and
Figure 9, VS1005g playback (DA) audio paths, on page 46. Also updated accompanying
documentation.
• Some register names still adjusted.
Version 0.3, 2012-04-04
• Checked and corrected register names.
• Modifications to Chapter 10, Firmware Operation.
Version 0.2, 2012-03-16
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• First public release.
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14
CONTACT INFORMATION
Contact Information
AR
VLSI Solution Oy
Entrance G, 2nd floor
Hermiankatu 8
FI-33720 Tampere
FINLAND
Y
14
PR
EL
IM
IN
Fax: 13751145915
QQ:2355355260
Email: [email protected]
URL: http://www.vlsi.fi/
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